RENESAS M301N2M8T

REJ09B0007-0100Z
M16C/1N Group
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/10 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.00
Revision date: Oct 20, 2004
www.renesas.com
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1.
Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corporation product best suited to the customer's application; they do
not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/1N Group of microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7
b6
b5
b4
b3
b2
*1
b1
b0
0 0
Symbol
XXX
Address
XXX
After Reset
0016
Bit Name
Bit Symbol
Function
RW
*2
b1 b0
XXX0
XXX bit
XXX1
(b2)
0 0: XXX
0 1: XXX
1 0: Do not set a value
1 1: XXX
RW
Nothing is assigned.
When write, set to "0". When read, its content is indeterminate.
Reserved bit
(b4 - b3)
Set to "0"
*3
WO
*4
XXX5
XXX bit
Function varies depending on mode
of operation
RW
RW
XXX6
XXX7
RW
XXX bit
0: XXX
1: XXX
RO
*1
Blank:Set to "0" or "1" according to the application
0:
Set to "0"
1:
Set to "1"
X:
Nothing is assigned
*2
RW:
RO:
WO:
–:
Read and write
Read only
Write only
Nothing is assigned
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions,
set to "0" when writing to this bit.
• Do not set a value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
3. M16C Family Documents
The following documents were prepared for the M16C family. (1)
Document
Short Sheet
Data Sheet
Hardware Manual
Software Manual
Application Note
Technical Update
Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts)
Detailed description of assembly instructions and microcomputer performance of each instruction
• Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
Preliminary report about the specification of a product, a document, etc.
NOTES :
1. Before using this material, please visit the our website to confirm that this is the most current document
available.
Table of Contents
Quick Reference to Pages Classified by Address .................................................................. B1
1. Overview .............................................................................................................................. 1
1.1
1.2
1.3
1.4
1.5
1.6
Applications ................................................................................................................................................. 1
Performance Overview ............................................................................................................................... 2
Block Diagram ............................................................................................................................................. 3
Performance Overview ............................................................................................................................... 4
Pin Configuration ........................................................................................................................................ 5
Pin Description ............................................................................................................................................ 6
2. Central Processing Unit (CPU) ............................................................................................ 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Data Registers (R0, R1, R2, and R3) ......................................................................................................... 7
Address Registers (A0 and A1) ................................................................................................................... 7
Frame Base Register (FB) .......................................................................................................................... 8
Interrupt Table Register (INTB) ................................................................................................................... 8
Program Counter (PC) ................................................................................................................................ 8
User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................................................................ 8
Static Base Register (SB) ........................................................................................................................... 8
Flag Register (FLG) .................................................................................................................................... 8
2.8.1 Carry Flag (C Flag) ............................................................................................................................. 8
2.8.2 Debug Flag (D Flag) ........................................................................................................................... 8
2.8.3 Zero Flag (Z Flag) ............................................................................................................................... 8
2.8.4 Sign Flag (S Flag) ............................................................................................................................... 8
2.8.5 Register Bank Select Flag (B Flag) ..................................................................................................... 8
2.8.6 Overflow Flag (O Flag) ........................................................................................................................ 8
2.8.7 Interrupt Enable Flag (I Flag) .............................................................................................................. 8
2.8.8 Stack Pointer Select Flag (U Flag) ...................................................................................................... 8
2.8.9 Processor Interrupt Priority Level (IPL) ............................................................................................... 8
2.8.10 Reserved Area .................................................................................................................................. 8
3. Memory ................................................................................................................................ 9
4. Special Function Registers (SFR) ...................................................................................... 10
5. Reset .................................................................................................................................. 20
5.1 Hardware Reset ........................................................................................................................................ 20
5.2 Software Reset ......................................................................................................................................... 22
6. Clock Generation Circuit .................................................................................................... 23
6.1
6.2
6.3
6.4
6.5
6.6
Main Clock ................................................................................................................................................ 28
Sub-clock .................................................................................................................................................. 29
On-chip Oscillator Clock ........................................................................................................................... 29
CPU Clock and Peripheral Function Clock ............................................................................................... 30
Power Control ........................................................................................................................................... 31
Oscillation Stop Detection Function .......................................................................................................... 36
7. Protection ........................................................................................................................... 40
8. Processor Mode ................................................................................................................. 41
8.1 Types of Processor Mode ......................................................................................................................... 41
A-1
9. Bus Control ........................................................................................................................ 42
10. Interrupt ............................................................................................................................ 44
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Overview of Interrupt ............................................................................................................................... 44
INT Interrupt ............................................................................................................................................ 60
CNTR0 Interrupt ...................................................................................................................................... 62
TCIN Interrupt ......................................................................................................................................... 63
Key Input Interrupt .................................................................................................................................. 64
Address Match Interrupt .......................................................................................................................... 65
Precautions for Interrupts ........................................................................................................................ 66
______
11. Watchdog Timer ............................................................................................................... 68
12. Timers .............................................................................................................................. 70
12.1
12.2
12.3
12.4
12.5
Timer 1 .................................................................................................................................................... 71
Timer X .................................................................................................................................................... 73
Timer Y .................................................................................................................................................... 82
Timer Z .................................................................................................................................................... 90
Timer C ................................................................................................................................................. 105
13. Serial I/O ........................................................................................................................ 108
13.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 113
13.2 Clock Asynchronous Serial I/O (UART) Mode ...................................................................................... 118
14. A/D Converter ................................................................................................................. 122
14.1
14.2
14.3
14.4
14.5
One-shot Mode ..................................................................................................................................... 126
Repeat Mode ........................................................................................................................................ 127
Sample and Hold .................................................................................................................................. 128
Extended Analog Input Pins .................................................................................................................. 128
External Operation Amp Connection Mode ........................................................................................... 128
15. D/A Converter ................................................................................................................. 129
16. CAN Module ................................................................................................................... 131
16.1 CAN Module-Related Registers ............................................................................................................ 132
16.2 CAN0 Message Box .............................................................................................................................. 133
16.3 Acceptance Mask Registers .................................................................................................................. 135
16.4 CAN SFR Registers .............................................................................................................................. 136
16.5 Operational Modes ................................................................................................................................ 144
16.6 Configuration of the CAN Module System Clock .................................................................................. 146
16.7 Acceptance Filtering Function and Masking Function ........................................................................... 148
16.8 Acceptance Filter Support Unit (ASU) ................................................................................................... 149
16.9 Basic CAN Mode ................................................................................................................................... 150
16.10 Return from Bus off Function .............................................................................................................. 150
16.11 Listen-Only Mode ................................................................................................................................ 150
16.12 Reception and Transmission ............................................................................................................... 151
16.13 CAN Interrupts .................................................................................................................................... 154
17. Programmable I/O Ports ................................................................................................ 155
17.1 Description ............................................................................................................................................ 155
17.2 Example connection of unused pins ..................................................................................................... 163
18. Electrical Characteristics ................................................................................................ 164
18.1 Timing requirements ............................................................................................................................. 170
A-2
19. Flash Memory Version ................................................................................................... 173
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
Overview ............................................................................................................................................... 173
Flash Memory ....................................................................................................................................... 174
Functions to Inhibit Rewriting Flash Memory Version ........................................................................... 175
Boot Mode ............................................................................................................................................. 177
CPU Rewrite Mode ............................................................................................................................... 178
Parallel Input/Output Mode ................................................................................................................... 195
Standard Serial Input/Output Mode ...................................................................................................... 196
CAN Input/Output Mode ........................................................................................................................ 201
20. Precautionary Notes in Using the Device ........................................................................ 204
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
Clock ..................................................................................................................................................... 204
Interrupts ............................................................................................................................................... 207
Timer ..................................................................................................................................................... 209
Serial I/O ............................................................................................................................................... 211
A/D Converter ....................................................................................................................................... 212
CAN Module .......................................................................................................................................... 214
Noise ..................................................................................................................................................... 217
Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers .......... 218
Flash Memory Version .......................................................................................................................... 219
Package Dimension .............................................................................................................. 221
Register Index ....................................................................................................................... 222
M16C/1N Group Usage Note Reference Book
For the most current Usage Note Reference Book, please visit our website.
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of
error. Specifications in this manual may be changed for functional or performance improvements. Please
make sure your manual is the latest edition.
A-3
Quick Reference to Pages Classified by Address
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Register
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
Symbol
PM0
PM1
CM0
CM1
Address match interrupt enable register AIER
Protect register
PRCR
Page
22, 41
22, 41, 69
25
25
65
40
Oscillation stop detection register
CM2
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
69
69
Address match interrupt register 0
RMAD0
65
Address match interrupt register 1
RMAD1
65
INT0 input filter select register
INT0F
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
26, 37
60, 94
Note 1: The blank areas are reserved.
B-1
Register
Symbol
Page
CAN0 wake up interrupt control register C01WKIC
CAN0 error interrupt control register
C01ERRIC
51
51
CAN0 successful reception interrupt control register C0RECIC
CAN0 successful transmission interrupt control register C0TRMIC
51
51
Key input interrupt control register
KUPIC
A/D conversion interrupt control register ADIC
51
51
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer 1 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
CNTR0 interrupt control register
TCIN interrupt control register
Timer C interrupt control register
INT3 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
51
S0TIC
S0RIC
S1TIC
S1RIC
T1IC
TXIC
TYIC
TZIC
CNTR0IC
TCINIC
TCIC
INT3IC
INT0IC
INT1IC
INT2IC
Address
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
Register
Timer Y, Z mode register
Prescaler Y
Timer Y secondary
Timer Y Primary
Timer Y, Z waveform output control register
Prescaler Z
Timer Z secondary
Timer Z Primary
Prescaler 1
Timer 1
Timer Y, Z output control register
Timer X mode register
Prescaler X
Timer X
Timer count source setting register
Clock prescaler reset flag
Symbol
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
PRE1
T1
TYZOC
TXMR
PREX
TX
TCSS
CPSRF
Timer C
TC
Page
82, 86, 88, 91, 96, 98, 100, 103
83
84, 86, 88, 93, 96, 98, 100, 103
92
72
83, 94
62, 73, 75-78, 80
74
72, 74, 84, 93
26
106
External input enable register
INTEN
Key input enable register
KIEN
64
Timer C control register 0
Timer C control register 1
TCC0
TCC1
63, 106
Timer measurement register
TM
UART0 transmit/receve mode register U0MR
UART0 bit rate generator
U0BRG
60, 94
106
111, 114, 119
110
UART0 transmit buffer register
U0TB
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
U0C0
U0C1
111
112
UART0 receive buffer register
U0RB
110
UART1 transmit/receive mode register U1MR
UART1 bit rate generator
U1BRG
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
111, 114, 119
110
UART1 transmit buffer register
U1TB
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
U1C0
U1C1
111
112
UART1 receive buffer register
U1RB
110
UART transmit/receive control register 2 UCON
112
Note 1: The blank areas are reserved.
B-2
Register
Symbol
Page
A/D register
AD
125
A/D control register 2
ADCON2
125
A/D control register 0
A/D control register 1
D/A register
ADCON0
ADCON1
DA
D/A control register
DACON
130
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
160
CAN0 I/O pin select register
CIOSR
162
Pull-up control register 0
PUR0
Pull-up control register 1
PUR1
Port P1 drive capacity control register DRR
124, 126, 127
130
161
Address
010016
010116
010216
010316
010416
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
Register
symbol
Page
Flash memory control register 4
FMR4
182
Flash memory control register 1
FMR1
182
Flash memory control register 0
FMR0
181
CAN0 message control register 0
CAN0 message control register 1
CAN0 message control register 2
CAN0 message control register 3
CAN0 message control register 4
CAN0 message control register 5
CAN0 message control register 6
CAN0 message control register 7
CAN0 message control register 8
CAN0 message control register 9
CAN0 message control register 10
CAN0 message control register 11
CAN0 message control register 12
CAN0 message control register 13
CAN0 message control register 14
CAN0 message control register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
CAN0 control register
C0CTLR
137
CAN0 status register
C0STR
138
CAN0 slot status register
C0SSTR
139
CAN0 interrupt control register
C0ICR
140
CAN0 extended ID register
C0IDR
140
CAN0 configuration register
C0CONR
141
CAN0 reception error count register
C0RECR
CAN0 transmission error count register C0TECR
142
Address
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
026116
026216
026316
026416
026516
026616
026716
026816
026916
026A16
026B16
026C16
026D16
026E16
026F16
027016
027116
027216
027316
027416
027516
027616
027716
027816
027916
027A16
027B16
027C16
027D16
027E16
027F16
136
Note 1: The blank areas are reserved.
B-3
Register
Symbol
Page
CAN0 acceptance filer support register
C0AFS
143
CAN0 clock select register
CCLKR
27
CAN0 message box 0: Identifier/DLC
CAN0 message box 0: Data field
CAN0 message box 0: Time stamp
CAN0 message box 1: Identifier/DLC
CAN0 message box 1: Data field
CAN0 message box 1: Time stamp
133
134
Address
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
Register
Symbol
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
Page
CAN0 message box 2: Identifier/DLC
CAN0 message box 2: Data field
CAN0 message box 2: Time stamp
CAN0 message box 3: Identifier/DLC
CAN0 message box 3: Data field
CAN0 message box 3: Time stamp
133
134
CAN0 message box 4: Identifier/DLC
CAN0 message box 4: Data field
CAN0 message box 4: Time stamp
CAN0 message box 5: Identifier/DLC
CAN0 message box 5: Data field
CAN0 message box 5: Time stamp
Note 1: The blank areas are reserved.
B-4
Register
Symbol
Page
CAN0 message box 6: Identifier/DLC
CAN0 message box 6: Data field
CAN0 message box 6: Time stamp
CAN0 message box 7: Identifier/DLC
CAN0 message box 7: Data field
CAN0 message box 7: Time stamp
CAN0 message box 8: Identifier/DLC
CAN0 message box 8: Data field
CAN0 message box 8: Time stamp
CAN0 message box 9: Identifier/DLC
CAN0 message box 9: Data field
CAN0 message box 9: Time stamp
133
134
Address
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Register
Symbol
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
Page
CAN0 message box 10: Identifier/DLC
CAN0 message box 10: Data field
CAN0 message box 10: Time stamp
CAN0 message box 11: Identifier/DLC
CAN0 message box 11: Data field
CAN0 message box 11: Time stamp
133
134
CAN0 message box 12: Identifier/DLC
CAN0 message box 12: Data field
CAN0 message box 12: Time stamp
CAN0 message box 13: Identifier/DLC
03B416
03B516
03B616
03B716
03B816
03B916
CAN0 message box 13: Data field
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
CAN0 message box 13: Time stamp
Note 1: The blank areas are reserved.
B-5
Register
Symbol
Page
CAN0 message box 14: Identifier/DLC
CAN0 message box 14: Data field
CAN0 message box 14: Time stamp
133
134
CAN0 message box 15: Identifier/DLC
CAN0 message box 15: Data field
CAN0 message box 15: Time stamp
CAN0 global mask register
CAN0 local mask A register
CAN0 local mask B register
135
M16C/1N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1. Overview
The M16C/1N group consists of single-chip microcomputers that use high-performance silicon gate CMOS
processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 48-pin plastic
mold QFP package. These single-chip microcomputers have both high function instructions and high instruction efficiency and feature a one-megabyte address space and the capability to execute instructions at
high speed.
1.1 Applications
Automotive and industrial control systems, other automobile, other
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M16C/1N Group
1. Overview
1.2 Performance Overview
Table 1.1 gives an overview of the M16C/1N group performance specification.
Table 1.1 Performance overview
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
size
RAM
I/O port
Multifunction T1
timer
TX, TY, TZ
TC
Serial I/O (UART or clock synchronous)
A/D converter
(maximum resolution: 10 bits)
D/A converter
CAN controller
Watchdog timer
Interrupts
Clock generating circuits
Power supply voltage
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
Rev.1.00 Oct 20, 2004
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Performance
91 instructions
62.5 ns (when f(XIN)=16MHz)
See Table 1.2 Performance overview
See Table 1.2 Performance overview
P0 to P5: 37 lines
8 bits x 1
8 bits x 3
16 bits x 1
x2
x 12 channels
(Expandable up to 14 channels)
8 bits x 1
1 channel, 2.0B active
15 bits x 1 (with prescaler)
15 internal causes, 8 external causes, 4 software causes
3 internal circuits
4.2 V to 5.5V (when f(XIN)=16MHz)
70mW(VCC=5.0V, f(XIN)=16MHz)
5V
5mA (10mA:LED drive port)
CMOS silicon gate
48-pin LQFP
M16C/1N Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows block diagram of the M16C/1N group.
8
I/O ports
Port P0
2
8
8
Port P3
Port P2
Port P1
8
Port P4
Internal peripheral functions
Timer
Timer 1 (8 bits)
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
A/D converter
D/A converter
(10 bits X 12 channels,
(8 bits X 1 channel)
expandable to 14 channels)
System clock generator
XIN-XOUT
XCIN-XCOUT
On-chip oscillation
UART/clock synchronous SI/O
(8 bits X 2 channels)
CAN controller (1 channel)
M16C/60 series 16-bit CPU core
Registers
Watchdog timer
(15 bits)
R0H
R0H
R1H
R0L
R0L
R1L
R2
R3
A0
A1
FB
SB
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1 Block diagram
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Program counter
PC
Stack pointers
ISP
USP
Memory
ROM
(Note 1)
RAM
(Note 2)
Vector table
INTB
Flag register
FLG
Multiplier
3
Port P5
M16C/1N Group
1. Overview
1.4 Performance Overview
Table 1.2 shows performance overview.
Table 1.2 Performance overview
Type No.
M301N2M4T-XXXFP(D)
M301N2M8T-XXXFP(D)
M301N2F8TFP(D)
M301N2F8FP(D)
(D): Under development
Type No.
ROM
32Kbytes
RAM
1Kbytes
64Kbytes
3Kbytes
Package
As of June 2004
Remarks
Mask ROM
48P6Q-A
Flash memory
M30 1N 2 M 4 T - XXX FP
Package type:
FP: Package 48P6Q-A
ROM No.
Omitted for flash memory version
Indicates differences in characteristics and usage etc:
Nothing: Common
T:
Automobiles
ROM size:
4: 32 Kbytes
8: 64 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
Indicates pin count, etc
(The value itself has no specific meaning)
M16C/1N Group
M16C Family
Figure 1.2 Type No., memory size, and package
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M16C/1N Group
1. Overview
1.5 Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
P07/AN0
IVCC
P30/TXOUT
VSS
P31/TZOUT
VCC
P40/ANEX0
P41/ANEX1
P42/INT3
P43/INT1
P32/TYOUT
P33/TCIN
Figure 1.3 shows pin configurations (top view) of the M16C/1N group.
37
38
39
40
41
42
43
44
45
46
47
48
M16C/1N Group
24
23
22
21
20
19
18
17
16
15
14
13
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
NC
P21
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
P36/CLK1
P35/RxD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
RESET
XOUT
VSS
XIN
VCC
P17/CNTR0
1
2
3
4
5
6
7
8
9
10
11
12
P06/AN1
P05/AN2
P04/AN3
VREF
P52
P51(CRx)(Note 1)
P50(CTx)(Note 1)
P03/AN4/CRx(Note 1)
P02/AN5/CTx(Note 1)
P01/AN6
P00/AN7
P37/TxD1/RxD1
Package: 48P6Q-A
Note 1: Either P02, P03 or P50, P51 can be selected as CAN0 I/O ports by software.
Figure 1.3 Pin configuration diagram (top view)
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M16C/1N Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description.
Table 1.3 Pin Description
Pin name
I/O type
Signal name
Function
VCC, VSS
Power supply
input
Input
IVCC
IVCC
Input
Connect a capacitor (0.1 µF) between this pin and VSS.
CNVSS
CNVSS
Input
Connect it to the VSS pin via resistance (about 5 kΩ).
RESET
Reset input
Input
A "L" on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock oscillation circuit.
Connect a ceramic resonator or crystal between the XIN and
XOUT pins. To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open.
VREF
Reference
voltage input
Input
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor. These pins are shared with analog input pins.
P02 and P03 function as CAN0 I/O pins by using software.
P10 to P17
I/O port P1
Input/output
This is an 8-bit I/O port equivalent to P0. P10 to P13 are shared
with analog inputs and key input interrupts. P14 to P16 are
shared with serial I/O pins. P17 is shared with timer input. Can
be used as an LED drive port.
P20 to P21
I/O port P2
Input/output
This is a 2-bit I/O port equivalent to P0.
P30 to P37
I/O port P3
Input/output
This is a 8-bit I/O port equivalent to P0. P30 to P33 are shared
with timer input/output. P34 to P37 are shared with serial I/O.
P34 is shared with analog outputs.
P40 to P47
I/O port P4
Input/output
This is a 8-bit I/O port equivalent to P0. P40 to 41 are shared
with analog inputs. P42 to P45 are shared with interrupt inputs.
P46 to P47 are shared with the I/O pin of the clock oscillation
circuit for the clock.
P50 to P52
I/O port P5
Input/output
This is a 3-bit I/O port equivalent to P0. P50 and P51 function as
CAN0 I/O pins by using software.
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Supply 4.2 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin is a reference voltage input for the A/D converter.
M16C/1N Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R0H (R0's high bits) R0L (R0's low bits)
R3
R1H (R1's high bits) R1L (R1's low bits)
Data registers (Note 1)
R2
R3
A0
Address registers (Note 1)
A1
FB
Frame base registers (Note 1)
b19
b0
INTBH
Interrupt table register
INTBL
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
Flag register
b8 b7
IPL
U
b0
I
O B S
Z
D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M16C/1N Group
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0”; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is set to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
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M16C/1N Group
3. Memory
3. Memory
Figure 3.1 is a memory map. The address space extends the 1M bytes from address 0000016 to FFFFF16.
From FFFFF16 down is ROM. For example, in the M301N2M4T-XXXFP, there is 32K bytes of internal ROM
from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to
FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for
timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts
for details.
From 0040016 up is RAM. For example, in the M301N2M4T-XXXFP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
(For details, refer to
4. SFR)
FFE0016
0040016
Internal RAM area
XXXXX16
Special page
vector table
FFFDC16
YYYYY16
Internal ROM area
FFFFF16
Type No.
M301N2M4T
FFFFF 16
Internal RAM
Size
Address XXXXX16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
UART0 reception
Reset
Internal ROM
Size
Address YYYYY16
1 Kbytes
007FF16
32 Kbytes
F800016
3 Kbytes
00FFF16
64 Kbytes
F000016
M301N2M8T
M301N2F8TFP
M301N2F8FP
Figure 3.1 Memory map
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M16C/1N Group
4. Special Function Registers (SFR)
4. Special Function Registers (SFR)
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Register
Symbol
After reset
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
XXXX0X002
00XXX0X02
4816
2016
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX002
XXXXX0002
Oscillation stop detection register
CM2
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
Address match interrupt register 0
RMAD0
Address match interrupt register 1
RMAD1
000000002
000000002
XXXX00002
INT0 input filter select register
INT0F
XXXXX0002
0416
XX16
000XXXXX2
000000002
000000002
XXXX00002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
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M16C/1N Group
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
4. Special Function Registers (SFR)
Register
Symbol
After reset
CAN0 wakeup interrupt control register
CAN0 state/error interrupt control register
C01WKIC
C01ERRIC
XXXXX0002
XXXXX0002
CAN0 reception successful interrupt control register
CAN0 transmission successful interrupt control register
C0RECIC
C0TRMIC
XXXXX0002
XXXXX0002
Key input interrupt control register
A/D conversion interrupt control register
KUPIC
ADIC
XXXXX0002
XXXXX0002
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer 1 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
CNTR0 interrupt control register
TCIN interrupt control register
Timer C interrupt control register
INT3 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
S0TIC
S0RIC
S1TIC
S1RIC
T1IC
TXIC
TYIC
TZIC
CNTR0IC
TCINIC
TCIC
INT3IC
INT0IC
INT1IC
INT2IC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XX00X0002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
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M16C/1N Group
Address
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
4. Special Function Registers (SFR)
Register
Timer Y, Z mode register
Prescaler Y
Timer Y secondary
Timer Y primary
Timer Y, Z waveform output control register
Prescaler Z
Timer Z secondary
Timer Z primary
Prescaler 1
Timer 1
Timer Y, Z output control register
Timer X mode register
Prescaler X
Timer X
Timer count source set register
Clock prescaler reset flag
Symbol
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
PRE1
T1
TYZOC
TXMR
PREX
TX
TCSS
CPSRF
After reset
000000X02
FF16
FF16
FF16
0016
FF16
FF16
FF16
XX16
XX16
XXXXX0002
000000002
FF16
FF16
0016
0XXXXXXX2
XX16
XX16
Timer C counter
TC
External input enable register
INTEN
0016
Key input enable register
KIEN
0016
Timer C control register 0
Timer C control register 1
TCC0
TCC1
Time measurement register
TM
0XX000002
XXXXXX112
XX16
XX16
UART0 transmit/receive mode register
UART0 bit rate generator
U0MR
U0BRG
UART0 transmit buffer register
U0TB
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
U0C0
U0C1
UART0 receive buffer register
U0RB
UART1 transmit/receive mode register
UART1 bit rate generator
U1MR
U1BRG
UART1 transmit buffer register
U1TB
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
U1C0
U1C1
UART1 receive buffer register
U1RB
UART transmit/receive control register 2
UCON
0016
XX16
XX16
XX16
0816
XXXX00102
XX16
XX16
0016
XX16
XX16
XX16
0816
XXXX00102
XX16
XX16
X00000002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 12 of 222
M16C/1N Group
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
4. Special Function Registers (SFR)
Register
Symbol
After reset
XX16
XX16
A/D register
AD
A/D control register 2
ADCON2
XXXX00002
A/D control register 0
A/D control register 1
D/A register
ADCON0
ADCON1
DA
00000XXX2
0016
XX16
D/A control register
DACON
XXXXX0X02
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
XX16
XX16
0016
0016
XX16
XX16
XXXXXX002
0016
XX16
XX16
0016
XXXXX0002
CAN0 I/O port select register
CIOSR
XXXXXXX02
Pull-up control register 0
Pull-up control register 1
Port P1 drive capacity control register
PUR0
PUR1
DRR
00X000002
XXXXX0002
0016
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
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REJ09B0007-0100Z
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M16C/1N Group
Address
010016
010116
010216
010316
010416
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
4. Special Function Registers (SFR)
Register
Symbol
After reset
Flash memory control register 4 (Note 2)
FMR4
010000002
Flash memory control register 1 (Note 2)
FMR1
0000XX0X2
Flash memory control register 0 (Note 2)
FMR0
XX0000012
CAN0 message control register 0
CAN0 message control register 1
CAN0 message control register 2
CAN0 message control register 3
CAN0 message control register 4
CAN0 message control register 5
CAN0 message control register 6
CAN0 message control register 7
CAN0 message control register 8
CAN0 message control register 9
CAN0 message control register 10
CAN0 message control register 11
CAN0 message control register 12
CAN0 message control register 13
CAN0 message control register 14
CAN0 message control register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
CAN0 control register
C0CTLR
CAN0 status register
C0STR
CAN0 slot status register
C0SSTR
CAN0 interrupt control register
C0ICR
CAN0 extended ID register
C0IDR
CAN0 configuration register
C0CONR
CAN0 receive error count register
CAN0 transmit error count register
C0RECR
C0TECR
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
X00000012
XX0X00002
0016
X00000012
000016
000016
000016
000016
000016
000016
XX16
XX16
0016
0016
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Note 2: These registers are available on flash memory versions only.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 14 of 222
M16C/1N Group
Address
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
026116
026216
026316
026416
026516
026616
026716
026816
026916
026A16
026B16
026C16
026D16
026E16
026F16
027016
027116
027216
027316
027416
027516
027616
027716
027816
027916
027A16
027B16
027C16
027D16
027E16
027F16
4. Special Function Registers (SFR)
Register
Symbol
CAN0 acceptance filter support register
C0AFS
CAN0 clock select register
CCLKR
CAN0 slot 0: Identifier / DLC
CAN0 slot 0: Data Field
CAN0 slot 0: Time Stamp
CAN0 slot 1: Identifier / DLC
CAN0 slot 1: Data Field
CAN0 slot 1: Time Stamp
After reset
XX16
XX16
X000XXXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 15 of 222
M16C/1N Group
Address
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
4. Special Function Registers (SFR)
Register
CAN0 slot 2: Identifier / DLC
CAN0 slot 2: Data Field
CAN0 slot 2: Time Stamp
CAN0 slot 3: Identifier / DLC
CAN0 slot 3: Data Field
CAN0 slot 3: Time Stamp
CAN0 slot 4: Identifier / DLC
CAN0 slot 4: Data Field
CAN0 slot 4: Time Stamp
CAN0 slot 5: Identifier / DLC
CAN0 slot 5: Data Field
CAN0 slot 5: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
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REJ09B0007-0100Z
page 16 of 222
M16C/1N Group
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
4. Special Function Registers (SFR)
Register
CAN0 slot 6: Identifier / DLC
CAN0 slot 6: Data Field
CAN0 slot 6: Time Stamp
CAN0 slot 7: Identifier / DLC
CAN0 slot 7: Data Field
CAN0 slot 7: Time Stamp
CAN0 slot 8: Identifier / DLC
CAN0 slot 8: Data Field
CAN0 slot 8: Time Stamp
CAN0 slot 9: Identifier / DLC
CAN0 slot 9: Data Field
CAN0 slot 9: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 17 of 222
M16C/1N Group
Address
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
4. Special Function Registers (SFR)
Register
CAN0 slot 10: Identifier / DLC
CAN0 slot 10: Data Field
CAN0 slot 10: Time Stamp
CAN0 slot 11: Identifier / DLC
CAN0 slot 11: Data Field
CAN0 slot 11: Time Stamp
CAN0 slot 12: Identifier / DLC
CAN0 slot 12: Data Field
CAN0 slot 12: Time Stamp
CAN0 slot 13: Identifier / DLC
CAN0 slot 13: Data Field
CAN0 slot 13: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 18 of 222
M16C/1N Group
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
4. Special Function Registers (SFR)
Register
Symbol
CAN0 slot 14: Identifier / DLC
CAN0 slot 14: Data Field
CAN0 slot 14: Time Stamp
CAN0 slot 15: Identifier / DLC
CAN0 slot 15: Data Field
CAN0 slot 15: Time Stamp
CAN0 Global mask
CAN0 local mask A
CAN0 local mask B
C0GMR
C0LMAR
C0LMBR
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
03B416
03B516
03B616
03B716
03B816
03B916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 19 of 222
M16C/1N Group
5. Reset
5. Reset
There are two types of resets; hardware and software. In both cases, operation is the same after the reset.
5.1 Hardware Reset
____________
A reset is applied using the RESET pin.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
____________
reset pin level "L" (0.2VCC max.). When the RESET pin level is then returned to the "H" level, the reset
status is cancelled and program execution resumes from the address in the reset vector table. Since the
value of RAM is indeterminate when power is applied, the initial values must be set. Also, if a reset signal
is input during write to RAM, the access to the RAM will be interrupted. Consequently, the value of the
RAM being written may change to an unintended value due to the interruption.
Note 1: M16C/1N group is delayed more than 2ms until the execution of the program after reset clear in
comparison with M16C/10 group products.
Figures 5.1 and 5.2 show the example reset circuit. Figure 5.3 shows the reset sequence.
5.1.1 When the power supply is stable
____________
(1)Apply a "L" signal to the RESET pin for at least 200µs.
____________
(2)Apply a "H" signal to the RESET pin.
5.1.2 Power on
____________
(1)Apply a "L" signal to the RESET pin.
(2)Let the power supply voltage increase until it meets the recommended operating condition.
(3)Wait for td(P-R) + 200µs or more until the internal power supply stabilizes.
____________
(4)Apply a "H" signal to the RESET pin.
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 20 of 222
M16C/1N Group
5. Reset
Example when VCC = 5V.
5V
4.2V
VCC
RESET
0V
5V
VCC
RESET
0.8V
0V
More than td(P-R)+200µs
Figure 5.1 Example reset circuit
Example when VCC = 5V.
5V
4.2V
VCC
RESET
VCC
Supply voltage
detection circuit
0V
5V
RESET
0V
More than td(P-R)+200µs
Figure 5.2 Example reset circuit (example voltage check circuit)
VCC
Internal on-chip
oscillation
td(P-R)
More than 20cycles are needed
RESET
BCLK 28cycles
BCLK
(Internal clock)
Content of reset vector
FFFFC16
Address
(Internal address
signal)
FFFFE16
Figure 5.3 Reset sequence
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 21 of 222
M16C/1N Group
5. Reset
5.2 Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. Set the PM03 bit to "1" after selecting on-chip oscillator for CPU's operating clock source.
A software reset has almost the same effect as a hardware reset. The contents of internal RAM are
preserved.
Figure 5.4 shows the processor mode register 0 and 1.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
0 0
Bit symbol
Address
000416
When reset
XXXX0X002
Bit name
Reserved bit
Function
Set to "0"
RW
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM03
Software reset bit
The device is reset when this bit
is set to "1". The value of this bit
is "0" when read.
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
0
Bit symbol
PM10
Address
000516
When reset
00XXX0X02
Bit name
DATAROM area access
bit (Note 2)
Function
0 : Disabled
1 : Enabled
RW
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 3)
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Reserved bit
PM17
Wait bit
Set to "0"
RW
0 : No wait
1 : Wait
RW
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0".
Note 3: After setting this bit to "1", can not change to "0" by software.
Figure 5.4 Processor mode register 0 and 1
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 22 of 222
M16C/1N Group
6. Clock Generation Circuit
6. Clock Generation Circuit
The clock regeneration circuit contains three circuits as follows:
- Main clock oscillation circuit
- Sub clock oscillation circuit
- On-chip oscillator
Table 6.1 lists Clock Generation Circuit Specifications. Figure 6.1 shows a Clock Generation Circuit. Figure
6.2, 6.3 and 6.5 show clock-associated registers. Figure 6.4 shows fC32 block diagram.
Table 6.1 Main clock, sub-clock, and on-chip oscillator circuits
Main clock oscillation circuit
Sub clock oscillation circuit
On-chip oscillator circuit
Use of clock
• CPU’s operating clock source • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral unit’s • Timer 1/X/Y/Z’s count
• Internal peripheral unit’s
operating clock source
clock source
operating clock source
• Timer Y’s count clock
source
Usable oscillator
• Ceramic oscillator
• Crystal oscillator
–
connectable (Note 1)
• Crystal oscillator
Oscillator connect pins
XIN, XOUT
XCIN, XCOUT
None (has internal pins)
Oscillation stop/restart function Available
Available
Available
Oscillator status immediately Oscillating
Stopped
Oscillating
after reset
Other
Externally generated clock can be input
–
Note 1: When not using the main clock generating circuit, pull up the XIN pin and leave the XOUT pin open.
Also, set the main clock stop bit (bit 5 at address 000616) to "1" (stop).
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 23 of 222
M16C/1N Group
6. Clock Generation Circuit
By CCLK4, 5, 6
Divider
XCOUT
XCIN
1/32
fC32
fCAN0
f1
CM04
fAD
fC
f8
Sub clock
CM10 "1"
Write signal
f32
S Q
XIN
XOUT
fMAIN
R
On-chip
oscillator
oscillation
circuit
RESET
Software reset
Main clock
1/2
b
Main
clock
switching
circuit
a
c
Divider
d CM07=0
fC
fRING
BCLK
CM07=1
CM05
Interrupt request
level judgment output
CM02
Oscillation
stop detection
CM20
CM22
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17, CM16=11
CM06=1
CM06=0
CM17, CM16=10
d
CM06=0
CM17, CM16=01
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
CM2i : Bit i at address 000C16
WDCi : Bit i at address 000F16
CM06=0
CM17, CM16=00
Figure 6.1 Block diagram of clock generating circuit
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 24 of 222
Details of divider
M16C/1N Group
6. Clock Generation Circuit
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
0 0
Bit symbol
Address
000616
When reset
010010002
Bit name
Function
RW
Set to "0"
RW
WAIT peripheral function
clock stop bit
XCIN-XCOUT drive capacity
select bit (Note 3)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 2)
RW
0 : LOW
1 : HIGH
RW
CM04
Port XC select bit
CM05
Main clock (XIN-XOUT)
stop bit (Note 4,5,6)
0 : I/O port
1 : XCIN-XCOUT generation
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
RW
CM07
System clock select bit
(Note 8)
0 : XIN, XOUT
1 : XCIN, XCOUT
RW
Reserved bit
CM02
CM03
RW
RW
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: fc32 is not included. Do not set to "1" when using low-speed, low power dissipation or on-chip oscillator mode.
Note 3: Changes to "1" when shifting to stop mode.
Note 4: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN after
exiting from the stop mode, set this bit to "0". When operating with a self-excited oscillator, set the system clock select bit
(CM07) to "1" before setting this bit to "1".
Note 5: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 6: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being ON, so XIN turns pulled up to XOUT ("H")
via the feedback resistor.
Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from
low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: Set port Xc select bit (CM04) to "1" before setting this bit to "1". Can not write to both bits at the same time.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
0 0 0
Address
000716
Bit symbol
Bit name
CM10
All clock stop control bit
(Note 2)
Reserved bit
When reset
001000002
Function
0 : Clock on
1 : All clocks off (stop mode)
RW
Set to "0"
RW
RW
CM14
On-chip oscillation stop bit 0 : Oscillation enabled
1 : Oscillation stopped (Note 3)
RW
CM15
XIN-XOUT drive capacity
select bit (Note 4)
RW
CM16
Main clock division
select bit 1 (Note 5)
CM17
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
RW
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: The mode of power control cannot be shifted on the stop mode directly from the on-chip oscillator.
If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is ineffective.
Note 3: This bit can be set to "1" only when both the main clock switch bit (CM22) and clock monitor bit (CM23) are set to "0".
Moreover, this bit is automatically set to "0" if the main clock switch bit (CM22) is set to "1".
Note 4: This bit changes to "1" when shifting from high-speed/middle-speed mode to stop mode or at reset. When shifting from lowspeed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 5: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8.
Figure 6.2 System clock control registers 0 and 1
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M16C/1N Group
6. Clock Generation Circuit
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM2
0 0 0 0
Address
000C16
Bit symbol
Bit name
CM20
Oscillation stop
detection bit
When reset
000001002
Function
0 : The function is invalid
1 : The function is valid (Note 2)
RW
RW
CM21
Oscillation stop detection
interrupt enable bit
0 : Disabled
1 : Enabled (Note 3)
RW
CM22
Main clock switch bit
0 : Select XIN clock
1 : Select on-chip oscillator (Note 4)
RW
CM23
Clock monitor bit (Note 5) 0 : XIN oscillating normally
1 : XIN stopping abnormally
Reserved bit
RO
RW
Set to "0"
Note 1: In case of writing to this register, set bit 0 of the protect register (address 000A16) to "1".
Note 2: Set to "0" before stopping the oscillation of the main clock (XIN-XOUT).
(stop mode, low power dissipation mode, on-chip oscillation mode)
An oscillation stop is detected if the oscillation of the main clock (XIN-XOUT) is stopped when the following
two conditions are satisfied: (1) the oscillation stop detection function is valid and (2) CM21=1.
Note 3: Valid when CM20=1.
Note 4: CM22 bit switches to "1" automatically if an oscillation stop is detected when both CM20 bit and CM 21 bit
are "1". CM22 bit cannot be cleared when CM23=1.
Note 5: This bit is valid when both CM20 bit is "1". Use this bit for the purpose of confirming XIN operation for
oscillation stop detection interrupt execution.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Bit symbol
Address
008F16
Bit name
When reset
0XXXXXXX2
Function
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is "0")
Figure 6.3 Oscillation stop detection register and clock prescaler reset flag
Clock prescaler
XCIN
Clock prescaler reset flag (bit 7
at address 008F16) set to "1"
Figure 6.4 fC32 block diagram
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page 26 of 222
1/32
Reset
fC32
RW
M16C/1N Group
6. Clock Generation Circuit
CAN0 clock select register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
0
Bit symbol
Address
025F16
When reset
X000XXXX2
Bit name
Function
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
CCLK4
CCLK5
CCLK6
Reserved bit
CAN0 clock select bit
b6 b5 b4
0 0 0 : No division mode
0 0 1 : Division by 2 mode
0 1 0 : Division by 4 mode
0 1 1 : Division by 8 mode
1 0 0 : Division by 16 mode
1 0 1 : Inhibited
1 1 0 : Inhibited
1 1 1 : Inhibited
RW
Set to "0"
RW
RW
RW
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing in this register.
Note 2: Change the register value only when the CAN module is in Reset/Initialization mode (the bit 0 of the CAN
Control Register (address 023016) is "1").
Figure 6.5 CAN0 clock select register
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M16C/1N Group
6. Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
6.1 Main Clock
The main clock is generated by the main clock oscillation circuit. After reset, oscillation starts. The clock
can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock reduces the
power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit changes to "1" when shifting from highspeed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Figure 6.5 shows the examples of main clock connection circuit.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note 1)
Rd
Externally derived clock
CIN
COUT
External ceramic oscillator
Vcc
Vss
External clock input
Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation
drive capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator
manufacturer’s data sheet specifies that a feedback resistor be added external to the chip, insert a feedback
resistor between XIN and XOUT following the instruction.
Figure 6.6 Examples of main clock connection circuit
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M16C/1N Group
6. Clock Generation Circuit
6.2 Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that
the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to "1" when shifting to
stop mode and at a reset.
Figure 6.7 shows the examples of sub-clock connection circuit.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note 1)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note 1: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation
drive capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 6.7 Examples of sub-clock connection circuit
6.3 On-chip Oscillator Clock
This clock by supplied by a on-chip oscillator. The oscillation of the on-ship oscillator can be used as
BCLK by setting the main clock selected bit (bit 2 at address 000C16. Lower power consumption can be
realized because the oscillating frequency of the on-chip oscillator is much lower compared to that of XIN.
The frequency of the on-chip oscillator depends on the supply voltage and the operation temperature
range. The application products must be designed with sufficient margin to accommodate the frequency
range.
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M16C/1N Group
6. Clock Generation Circuit
6.4 CPU Clock and Peripheral Function Clock
6.4.1 BCLK
The BCLK is the clock that drives the CPU. The clock source for BCLK is as follows: (1) the clock
derived by dividing the main clock by 1, 2, 4, 8, or 16, (2) fc, or (3) the clock derived by dividing the
clock supplied by the on-chip oscillator circuit (fRING) by 1, 2, 4, 8 or 16. After reset, the BCLK is
derived by dividing the fRING by 8.
The main clock division select bit 0 (bit 6 at address 000616) changes to "1" when shifting from highspeed/medium-speed mode to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
6.4.2 Peripheral Function Clock
6.4.2.1 f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction.
6.4.2.2 fAD
This clock has the same frequency as the main clock and is used in A/D conversion.
6.4.2.3 fCAN0
This clock is derived by dividing the main clock by 1, 2, 4, 8, 16 by setting the CAN0 clock select
register.
It is used for the corresponding CAN module.
This clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock
stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction.
6.4.2.4 fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer 1, timer X, timer Y and
timer X counts.
6.4.2.5 fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog
timer.
6.4.3 fRING
This clock is supplied by the on-chip oscillator circuit. In the on-chip oscillator mode, the clock divided
by the division ratio selected with the main clock division select bit 0 and bit 1 (bit 6 at address 000616,
and bit 6 and bit 7 at address 000716) is supplied as BCLK. Immediately after reset, 8 divisions of this
clock is supplied as BCLK. The on-chip oscillator oscillation can be set to BCLK when oscillation stop
is detected or with the main clock switching bit (bit 2 at address 000C16).
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M16C/1N Group
6. Clock Generation Circuit
6.5 Power Control
There are three power control modes. All modes other than wait and stop modes are referred to as
normal operation mode.
6.5.1 Normal Operating Modes
Normal operation mode is further separated into five modes.
In normal operation mode, the CPU clock and the peripheral function clock are supplied to operate the
CPU and the peripheral function.
Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU
clock frequency, the more processing power increases. The lower the CPU clock frequency, the more
power consumption decreased. When unnecessary oscillator circuits stop, power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source after switching
needs to be stabilized and oscillated. If the new clock source is the main clock, allow sufficient wait
time in a program until an oscillation is stabilized. When the clock source for the CPU clock is changed
from the one-chip oscillator to the main clock, change the operation mode to the medium-speed mode
(divided-by-8 mode) after the clock was divided by 8 in on-chip oscillator mode.
6.5.1.1 High-speed Mode
The main clock divided-by-1 (undivided) provides the CPU clock. The peripheral functions operate
on the clocks specified for each respective function.
6.5.1.2 Medium-speed Mode
The main clock divided-by-2, -4, -8 or -16 provides the CPU clock. The peripheral functions operated on the clocks specified for each respective function. The main clock must be oscillating stably
before transferring from the main clock divided-by-8 to divided-by-1, -2 or -4 and the sub-clock
must be oscillating stably before transferring to low-speed or lower power-dissipation mode.
6.5.1.3 Low-speed Mode
The sub-clock provides the CPU clock. The peripheral functions operate on the clocks specified for
each respective function. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are
required after the sub-clock status. Therefore, the program must be written to wait until this clock
has stabilized immediately after powering up and after stop mode is cancelled.
6.5.1.4 Low Power-dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub-clock
provides the CPU clock. Only the peripheral functions for which the sub-clock was selected as the
count source continue to operate.
6.5.1.5 On-chip Oscillator Mode
The on-chip oscillator clock divided-by-1(undivided) -2,-4,-8, or -16 provides the CPU clock. The
on-chip oscillator clock is also the clock source for the peripheral function clocks. The higher division and the main clock is turned off after being placed in on-chip oscillator mode, power consumption is reduced further.
Table 6.2 lists the setting and mode of clock associated bit.
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M16C/1N Group
6. Clock Generation Circuit
Table 6.2 Setting and mode of clock associated bit
CM2 register
CM1 register
CM0 regiser
CM22
CM17, CM16
CM07
CM06
CM05
CM04
0
002
0
0
0
_
Divide-by-2
0
012
0
0
0
_
Divide-by-4
0
102
0
0
0
_
Divide-by-8
0
_
0
1
0
_
Divide-by-16
0
112
0
0
0
_
Low-speed mode
0
_
1
_
0
1
Low power-dissipation mode
0
_
1
_
1
1
Undivided
1
002
0
0
_
_
Divide-by-2
1
012
0
0
_
_
Divide-by-4
1
102
0
0
_
_
Divide-by-8
1
_
0
1
_
_
Divide-by-16
1
112
0
0
_
_
Mode
High-speed mode
Medium-speed
mode
On-chip oscillator
mode
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M16C/1N Group
6. Clock Generation Circuit
6.5.2 Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 6.3 lists the status of the ports in
wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode,
the microcomputer restarts using as BCLK, the clock that had been selected when the WAIT instruction was executed.
Table 6.3 Port status during wait mode
Pin
Port
States
Retains status before wait mode
6.5.3 Stop Mode
Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that
VCC remains above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fc32, fAD and fCAN0 stop in stop mode, peripheral functions such as the A/D converter and watchdog timer do not function. However, timer X operate provided that the event counter mode is set to an external pulse, and UART0 and UART1 function provided an external clock is selected. Table 6.4 lists the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop
mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not
used to cancel must have been changed to 0 before shifting to stop mode. If returning by an interrupt,
that interrupt routine is executed. If only a hardware reset is used to cancel stop mode, change the
priority level of all interrupt to 0, then shift to stop mode.
When shifting from high-speed/medium-speed mode to stop mode or at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Stop mode must not be use while operating in on-chip oscillator mode.
Table 6.4 Port status during stop mode
Pin
Port
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REJ09B0007-0100Z
States
Retains status before stop mode
page 33 of 222
M16C/1N Group
6. Clock Generation Circuit
Figure 6.8 shows the state transition to stop and wait modes. Figure 6.9 shows the state transition in
normal operation mode.
Transition of stop mode, wait mode
Reset
On-chip oscillator mode (Note 1)
(divided-by-8 mode)
All oscillators stopped
CM10 = "1"
Stop mode
All oscillators stopped
Stop mode
Interrupt
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = "1"
High-speed/mediumspeed mode
All oscillators stopped
CM10 = "1"
Stop mode
Interrupt
Low-speed/low power
dissipation mode
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
CPU operation stopped
Wait mode
Normal mode
(See Fig. 6.9 for the State transition in normal operation mode.)
Note 1: The mode cannot be shifted to stop mode directly from on-chip oscillator mode.
Figure 6.8 State transition of stop and wait modes
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M16C/1N Group
6. Clock Generation Circuit
Transition of normal operation mode
Main clock is oscillating
Sub clock is stopped
On-chip oscillator mode (divided-by-8 mode)
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
CM06="1"
BCLK: f(RING)/8
CM07="0" CM06="1"
CM05="0"
CM22="1"
CM22="1"
BCLK: f(XIN)/8
CM22="0"
(Note 1)
CM07="0" CM06="1"
CM22="0"
Main clock is stopped
Sub clock is stopped
CM05 = "0"
On-chip oscillator mode
CM05 = "1"
8-division mode
CM04="0"
CM07="0" (Note 1)
CM06="1"
CM04="0"
CM04="1"
(Notes 1, 3)
BCLK: f(RING)/8
CM07="0"
CM05="1"
CM22="1"
1-division mode (Note 3)
BCLK: f(RING)
CM07="0"
CM05="1"
CM16="0"
CM06="0"
CM22="1"
CM17="0"
4-division mode (Note 3)
BCLK: f(RING)/4
CM07="0"
CM05="1"
CM16="0"
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN)
BCLK : f(XIN)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM06="0"
CM22="1"
CM17="0"
16-division mode (Note 3)
BCLK: f(RING)/16
CM07="0"
CM05="1"
CM16="1"
CM06="0"
CM22="1"
CM17="1"
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = "0"
(Notes 1, 3)
BCLK : f(XIN)/8
CM07 = "0"
CM06 = "1"
BCLK : f(XCIN)
CM07 = "1"
CM06 = "1"
(Note 2, 5)
CM07 = "1"
CM06 = "1"
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
CM04 = "0"
CM05 = "0"
CM04 = "1"
Low power dissipation mode
High-speed mode
Medium-speed mod
(divided-by-2 mode)
BCLK : f(XIN)
BCLK : f(XIN)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
BCLK : f(XIN)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
BCLK : f(XCIN)
CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"
CM07 = "1"
CM06 = "1"
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM17 and CM16 before changing CM06.
Note 4: Transit in accordance with arrow.
Note 5: Before switching BCLK to other from the main clock, divide the main clock by 8 for
safety purposes to switch BCLK to the main clock again.
Figure 6.9 State transition in normal operation mode
page 35 of 222
CM05 = "1"
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
BCLK: f(RING)/2
CM07="0"
CM05="1"
CM16="1"
BCLK : f(XIN)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
CM06 = "0"
(Notes 1, 3)
2-division mode (Note 3)
Main clock is oscillating
Sub clock is oscillating
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM06="0"
CM22="1"
CM17="1"
CM06="1"
M16C/1N Group
6. Clock Generation Circuit
6.6 Oscillation Stop Detection Function
The oscillation stop detection function detects abnormal stopping of the main clock by causes such as
opening and shorting of the XIN oscillation circuit. When oscillation stop is detected, an oscillation stop
detection interrupt is issued. When an oscillation stop detection interrupt is issued, the on-chip oscillator
in the microcomputer operates automatically and is used as the main clock in place of the XIN clock. This
allows interrupt processing.
The oscillation stop detection function can be enabled/disabled with bit 0 and bit 1 of the oscillation stop
detection register. When this bit is set to "112", the function is enabled. After the reset is released, the
oscillation stop detection function becomes disabled because the bit value is "002".
Table 6.5 lists the specification of oscillation stop detection function, Figure 6.10 shows a configuration
diagram of the oscillation stop detection circuit and Figure 6.11 shows the configuration of the oscillation
stop detection register.
Table 6.5 Specification overview of the oscillation stop detection function
Item
Specification
Oscillation stop detectable clock and
XIN ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop When the oscillation stop detection bit (bit 0 at address 000C16)
detection function
Operation at oscillation stop detection
Notes on STOP mode, low power
dissipation mode, and on-chip
oscillator mode
Notes on WAIT mode
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page 36 of 222
and the oscillation stop detection interrupt enable bit (bit 1 at
address 000C16) are set to "1"
• Oscillation stop detection interrupt occurs
Before stopping the main clock (XIN-XOUT), set the
oscillation stop detection enable bit to "0" to disable the
oscillation stop detection function. Enable main clock
(XIN-XOUT) oscillation and after the oscillation stabilizes,
set the bit to "1" again.
If the peripheral function clock is stopped in WAIT mode
with the WAIT mode peripheral function clock stop bit
(bit 2 at address 000616), oscillation stop will be detected.
Do not stop the peripheral function clock in WAIT mode.
M16C/1N Group
6. Clock Generation Circuit
Compulsory discharge when CM20=0
Pulse generation
circuit for clock
edge detection
and charge/
discharge control
fMAIN
(Note 1)
Charge/discharge
circuit
Oscillation stop
detection interrupt
generating circuit
CM21
To the CPU
Watchdog
timer
interrupt
CM22
CM14
Main clock switch control
On-chip oscillator
Main clock
To the main clock
division circuit
#: When XIN is supplied, this repeats charge and discharge with pulses by XIN edge detection.
When XIN is not supplied, this continues charging. When the charge exceeds a certain level,
it regards the oscillation as stopped.
Note 1: As for the fMAIN, see Figure 6.1 clock generating circuit.
Figure 6.10 Oscillation stop detection circuit
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
CM2
0
Bit symbol
CM20
Address
000C16
When reset
0416
RW
Bit name
Oscillation stop
detection bit
Function
0 : The function is invalid
1 : The function is valid (Note 2)
CM21
Oscillation stop detection
interrupt enable bit
0 : Disabled
1 : Enabled (Note 3)
CM22
Main clock switch bit
0 : Select XIN clock
RW
1 : Select on-chip oscillator (Note 4)
CM23
Clock monitor bit (Note 5) 0 : XIN oscillating normally
1 : XIN stopping abnormally
Reserved bit
Set to "0"
RW
RW
RO
RW
Note 1: In case of writing to this register, set bit 0 of the protect register (address 000A16) to "1".
Note 2: Set to "0" before stopping the oscillation of the main clock (XIN-XOUT).
(stop mode, low power dissipation mode, on-chip oscillation mode)
An oscillation stop is detected if the oscillation of the main clock (XIN-XOUT) is stopped when the following
two conditions are satisfied: (1) the oscillation stop detection function is valid and (2) CM21=1.
Note 3: Valid when CM20=1.
Note 4: CM22 bit switches to "1" automatically if an oscillation stop is detected when both CM20 bit and CM 21 bit
are "1". CM22 bit cannot be cleared when CM23=1.
Note 5: This bit is valid when both CM20 bit is "1". Use this bit for the purpose of confirming XIN operation for
oscillation stop detection interrupt execution.
Figure 6.11 Oscillation stop detection register
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6. Clock Generation Circuit
6.6.1 Oscillation Stop Detection Bit (CM20)
You can start the oscillation stop detection by setting this bit to "1" and CM21=1 (oscillation stop
detection interrupt enabled). The detection is not executed when this bit is set to "0" or in reset status.
Be sure to set this bit to "0" before setting for the stop-mode. Set this bit again to "1" after release from
stop-mode. Set this bit to "0" also before setting the main clock stop bit (bit 5 at address 000616) to "1".
Do not set this bit to "1" if the frequency of XIN is lower than 2 MHz.
An oscillation stop is detected if CM02="1" (peripheral function clock has been set for stop in wait
mode) and the mode is shifted to wait.
6.6.2 Oscillation Stop Detection Interrupt Enable Bit (CM21)
When CM20=1 and CM21=1, an oscillation stop detection interrupt is generated if an abnormal stop of
XIN is detected. The on-chip oscillator starts operation instead of the XIN clock which stopped abnormally. The operation goes further with the main clock supplied from the on-chip oscillator. For the
oscillation stop detection interrupt, judgment on the interrupt condition is necessary, because this
interrupt shares the vector table with watchdog timer interrupt. Figure 6.12 shows flow of the judgment
with oscillation stop detection interrupt processing program.
6.6.3 Main Clock Switch Bit (CM22)
When setting this bit to "1", the on-chip oscillator is selected as main clock. At this time, the on-chip
oscillator starts simultaneously if it has been stopped (CM14=1). This bit is cleared only when CM23 is
"0" (when XIN is oscillating).
If an oscillation stop is detected while both CM20 and CM21 are "1", this bit automatically switches to
"1".
When this bit is set to "1", the on-chip oscillation stop bit (bit 4 at address 000716) is automatically set
to "0".
6.6.4 Clock Monitor Bit (CM23)
You can see the operation status of the XIN clock. When this bit is "0", XIN is operating correctly. You
can check the oscillation status of XIN when an oscillation stop detection interrupt is generated or after
reset.
When oscillation stop detection is invalid (CM20="0"), the clock monitor bit is "0".
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6. Clock Generation Circuit
Figure 6.12 shows the flow of interrupt cause determination of oscillation stop detection or watchdog
timer interrupt.
Oscillation stop detection interrupt
or watchdog timer interrupt
is generated
Read oscillation stop
detection register
CM23=1?
NO
YES
CM21=1 and
CM22=1?
NO
YES
Clear CM21 bit (Note 1)
Jump to the execution
program for oscillation stop
detection interrupt
Jump to the execution
program for watchdog timer
interrupt
Note 1: Disables multiple interrupts of oscillation stop detection and let watchdog
timer take priority.
Figure 6.12 Flow of interrupt cause determination
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7. Protection
7. Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 7.1 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P0 direction register
(address 00E216) can only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs can be allocated to port P0.
If, after "1" (write-enabled) has been written to bit "enables writing to port P0 direction register" (bit 2 at
address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited).
Make sure no interrupts will generate between the instruction in which the PRC2 bit to "1" and the next
instruction. The system clock control registers 0 and 1 and oscillation stop detection register write-enable
bit (bit 0 at address 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at address 000A16)
do not automatically return to "0" after a value has been written to an address. The program must therefore
be written to return these bits to "0".
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
0 0 0
Bit symbol
PRC0
PRC1
PRC2
Reserved bit
Address
000A16
When reset
XXXXX0002
Bit name
Function
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716), oscillation stop
detection register (address 000C16)
and CAN0 clock select register
(address 025F16)
0 : Write-inhibited
1 : Write-enabled
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516)
0 : Write-inhibited
1 : Write-enabled
Enables writing to port P0 direction
register (address 00E216) and
CAN0 I/O port select register
(address 00F816) (Note 1)
0 : Write-inhibited
1 : Write-enabled
RW
Set to "0"
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note 1: Writing a value to an address after "1" is written to this bit returns the bit to "0".
Other bits do not automatically return to "0" and they must therefore be reset by the program.
Figure 7.1 Protect register
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RW
RW
RW
RW
M16C/1N Group
8. Processor Mode
8. Processor Mode
8.1 Types of Processor Mode
The processor mode is single-chip mode. Table 8.1 lists features of processor mode.
Figure 8.1 shows the processor mode register 0 and 1.
Table 8.1 Features of processor mode
Processor mode
Access space
Pins to which I/O ports are assigned
Single chip mode SFR, Internal RAM, Internal ROM All pins are I/O ports or peripheral function I/O pins.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
0 0
Bit symbol
Address
000416
When reset
XXXX0X002
Bit name
Reserved bit
Function
Set to "0"
RW
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM03
Software reset bit
The device is reset when this bit
is set to "1". The value of this bit
is "0" when read.
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
0
Bit symbol
PM10
Address
000516
When reset
00XXX0X02
Bit name
DATAROM area access
bit (Note 2)
Function
0 : Disabled
1 : Enabled
RW
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 3)
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Reserved bit
PM17
Wait bit
Set to "0"
RW
0 : No wait
1 : Wait
RW
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0".
Note 3: After setting this bit to "1", can not change to "0" by software.
Figure 8.1 Processor mode register 0 and 1
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9. Bus Control
9. Bus Control
During access, the memory areas (ROM, RAM, FLASH, etc.) and the SFR area have different bus cycles.
The memory areas can be accessed in one cycle of the CPU operation clock BCLK. The SFR area can be
accessed in two cycles of BCLK.
Software wait states can be inserted to the memory areas by using the PM17 bit of the processor mode
register 1 (bit 7 at address 000516) (Note 1). When the PM17 bit is set to "0", the memory areas are
accessed in one cycle of BCLK. When the PM17 bit is set to "1", the memory areas are accessed in two
cycles of BCLK. The PM17 bit is "0" after the reset status is cancelled. The SFR area is not influenced by
the PM17 bit and is always accessed in two cycles of BCLK.
The Table 9.1 lists bus cycle for access areas. Figure 9.1 shows SFR area and memory areas.
Note 1: When rewriting the processor mode register 1, set the PRC1 bit of the protect register (bit 1 at
address 000A16) to "1".
Table 9.1 Bus cycle for access areas
Area
PM17
Bus cycle
SFR
Internal
ROM/RAM
2 BCLK cycles
0
1 BCLK cycle
1
2 BCLK cycles
0000016
SFR area
(For details, refer to
4. SFR)
SFR area
0040016
Internal RAM area
XXXXX16
Memory area
YYYYY16
Internal ROM area
FFFFF16
Figure 9.1 SFR area and memory areas
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9. Bus Control
The memory areas and the SFR area also have different bus widths. The memory areas have a 16-bit bus
width, while the SFR area has an 8-bit bus width. Consequently, different operations are used when the
areas are accessed in word (16 bits) units.
Table 9.2 lists access unit and bus operation.
Table 9.2 Access unit and bus operation
SFR
Space
Even address
byte access
BCLK
BCLK
Address
Data
BCLK
Data
BCLK
Even
Data
Even+1
Data
BCLK
Address
Data
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Data
Odd
Data
Data
BCLK
Data
Odd address
word access
Data
Address
Odd
Data
Address
Even
BCLK
Address
Even address
word access
Address
Even
Data
Odd address
byte access
ROM/RAM (No wait setting)
page 43 of 222
Address
Even/even+1
Word
Data
Data
BCLK
Odd
Data
Odd+1
Data
Address
Data
Odd
Data
Odd+1
Data
M16C/1N Group
10. Interrupt
10. Interrupt
10.1 Overview of Interrupt
10.1.1 Type of Interrupts
Figure 10.1 lists the types of interrupts.










Hardware
Special
(Non-maskable
interrupt)














Interrupt
Software
(Non-maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
______
INT instruction
Reset
UART0 reception
________
DBC
Oscillation stop detection/watchdog timer
Single step
Address matched
Peripheral I/O (Note 1)
Note 1: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer
system.
Figure 10.1 Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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10. Interrupt
10.1.2 Software Interrupts
A software interrupt is generated when an instruction is executed. The software interrupts are nonmaskable interrupts.
10.1.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
10.1.2.2 Overflow Interrupt
The overflow interrupt is generated when the INTO instruction is executed with the overflow flag (O
flag) set to "1". The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
10.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
______
10.1.2.4 INT instruction Interrupt
______
______
______
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction
can select the software interrupt numbers 0 to 63. The software interrupt numbers 0 to 31 are
assigned to the peripheral function interrupt. Therefore, the microcomputer executes the same
______
interrupt routine when the INT instruction interrupt is executed as when a peripheral function interrupt is generated.
______
The stack pointer (SP) used for the INT instruction interrupt is dependent on which software interrupt number is involved.
So far as software interrupt numbers 0 to 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning
from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 to 63 are concerned, the stack pointer does not make
a shift.
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10. Interrupt
10.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
10.1.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an "L" is input to the RESET pin.
• UART0 reception interrupt
UART0 reception interrupt occurs when UART0 is received. This interrupt can be enabled with bit
2 of the INT0 input filter select register (address 001E16).
This interrupt is exclusively for the debugger, do not use it in other circumstances.
_______
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Oscillation stop detection/watchdog timer interrupt
Generated by the oscillation stop detection or watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set
to "1".
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
10.1.3.2 Peripheral I/O Interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector
______
table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses.
Peripheral I/O interrupts are maskable interrupts.
• CAN0 error interrupt
Tis is an interrupt that CAN error generates.
• CAN0 wake up interrupt
CAN0 wake up interrupt occurs if a falling edge is input to the CRx pin.
• CAN0 successful reception interrupt
This is an interrupt that the CAN reception generates.
• CAN0 successful transmission interrupt
This is an interrupt that the CAN transmission generates.
• Key-input interrupt
___
A key-input interrupt occurs if a falling or rising edge is input to the KI pin.
• A/D conversion interrupt
This is an interrupt that the A/D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer 1 interrupt
This is an interrupt that timer 1 generates.
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10. Interrupt
• Timer X interrupt
This is an interrupt that timer X generates.
• Timer Y interrupt
This is an interrupt that timer Y generates.
• Timer Z interrupt
This is an interrupt that timer Z generates.
• Timer C interrupt
This is an interrupt that timer C generates.
• CNTR0 interrupt
This interrupt occurs if either a falling edge or a rising edge is input to the CNTR0 pin.
• TCIN interrupt
This interrupt occurs if any one of a falling edge, a rising edge or both edges is input to the TCIN
pin. This interrupt also occurs with the fRING256.
• INT0 to INT3 interrupt
INT0 to INT2 interrupts occur if any one of a falling edge, a rising edge or both edges is input to the
______
INT pin.
______
INT3 interrupt occurs if either a falling edge or both edges is input to the INT pin.
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10. Interrupt
10.1.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt
vector table. Set the first address of the interrupt routine in each vector table. Figure 10.2 shows
format for specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed
and variable vector table in which addresses can be varied by the setting.
MSB
LSB
Vector address + 0
Low address
Vector address + 1
Mid address
Vector address + 2
0000
High address
Vector address + 3
0000
0000
Figure 10.2 Format for specifying interrupt vector addresses
10.1.4.1 Fixed Vector Tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an
area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first
address of interrupt routine in each vector table. Table 10.1 lists the interrupts assigned to the fixed
vector tables and addresses of vector tables.
Table 10.1 Interrupt and fixed vector address
Interrupt source
Undefined instruction
Overflow
BRK instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Address match
FFFE816 to FFFEB16
Single step (Note 1)
Oscillation stop detection/
Watchdog timer
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Do not use
FFFF416 to FFFF716
Do not use
________
DBC (Note 1)
UART0 reception (Note 1)
FFFF816 to FFFFB16
Do not use
Reset
FFFFC16 to FFFFF16
Note 1: Interrupts used for debugging purposes only.
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10. Interrupt
10.1.4.2 Variable Vector Tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the
address the INTB indicates becomes the area for the variable vector tables. One vector table
comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 10.2
lists the interrupts assigned to the variable vector tables and addresses of vector tables.
Table 10.2 Interrupt causes (variable interrupt vector addresses)
Software interrupt number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
to
63
Vector table address (Note 1)
Address (L) to address (H)
+0
+4
+8
+12
+16
+20
+24
+28
+32
+36
+40
+44
+48
+52
+56
+60
+64
+68
+72
+76
+80
+84
+88
+92
+96
+100
+104
+108
+112
+116
+120
+124
+128
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
+252 to
+3
+7
+11
+15
+19
+23
+27
+31
+35
+39
+43
+47
+51
+55
+59
+63
+67
+71
+75
+79
+83
+87
+91
+95
+99
+103
+107
+111
+115
+119
+123
+127
+131
Interrupt source
BRK instruction
page 49 of 222
Cannot be masked by I flag
CAN0 wake up
CAN0 error
CAN0 successful reception
CAN0 successful transmission
Key input
A/D
UART0 transmission
UART0 reception
UART1 transmission
UART1 reception
Timer 1
Timer X
Timer Y
Timer Z
CNTR0
TCIN
Timer C
INT3
INT0
INT1
INT2
software interrupt
+255
Note 1: Address relative to address in interrupt table register (INTB).
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Remarks
Cannot be masked by I flag
M16C/1N Group
10. Interrupt
10.1.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent
is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I
flag) and the IPL are located in the flag register (FLG).
Figure 10.3 shows the interrupt control registers.
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10. Interrupt
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
C01WKIC
C01ERRIC
C0RECIC
C0TRMIC
KUPIC
ADIC
SiTIC(i=0,1)
SiRIC(i=0,1)
T1IC
TXIC
TYIC
TZIC
CNTR0IC
TCINIC
TCIC
INT3IC
004516
004616
004816
004916
004D16
004E16
005116, 005316
005216, 005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
Interrupt request bit
Function
RW
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
RW
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that
register. For details, see 10.7 the precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0, 1, 2)
Bit symbol
ILVL0
Address
005D16, 005E16,
005F16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00X0002
XX00X0002
Interrupt request bit
Polarity select bit
Reserved bit
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
RW
RW
(Note 1)
0 : Selects falling edge
1 : Selects rising edge
RW
Set to "0"
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read,
turns out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Figure 10.3 Interrupt control register
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10. Interrupt
10.1.5.1 Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts.
This flag is set to "0" after reset.
10.1.5.2 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt
is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software (Do not set this bit to "1").
10.1.5.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority
level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt
is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt.
Table 10.3 lists the settings of interrupt priority levels and Table 10.4 lists the interrupt levels enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
Table 10.3 Settings of interrupt priority levels
Interrupt priority
level select bit
b2 b1 b0
Interrupt priority
level
0 0 0
Level 0
(interrupt disabled)
0 0 1
Level 1
0 1 0
Table 10.4 Interrupt levels enabled according
to the contents of the IPL
Priority
order
IPL
Enabled interrupt priority levels
IPL2 IPL1IPL0
Interrupt levels 1 and above are enabled
0
0
0
0
0
1 Interrupt levels 2 and above are enabled
Level 2
0
1
0 Interrupt levels 3 and above are enabled
0 1 1
Level 3
0
1
1 Interrupt levels 4 and above are enabled
1 0 0
Level 4
1
0
0 Interrupt levels 5 and above are enabled
1 0 1
Level 5
1
0
1 Interrupt levels 6 and above are enabled
1 1 0
Level 6
1
1
0 Interrupt levels 7 and above are enabled
1 1 1
Level 7
1
1
1 All maskable interrupts are disabled
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Low
High
M16C/1N Group
10. Interrupt
10.1.5.4 Rewrite the Interrupt Control Register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request
for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control
register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B
#00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B
#00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B
#00h, 0055h
POPC
FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is
to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to
effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
the interrupt request bit is not set sometimes even if the interrupt request for that register has been
generated. This will depend on the instruction. If this creates problems, use the below instructions
to change the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt
request bit is not cleared sometimes. This will depend on the instruction. If this creates problems,
use the below instructions to change the register.
Instructions : MOV
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10. Interrupt
10.1.5.5 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when
the execution of the instruction is completed, and transfers control to the interrupt sequence from
the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or
RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPUgets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note 1) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U
______
flag) to "0" (the U flag, however, does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed).
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the
first address of the interrupt routine.
Note 1: This register cannot be utilized by the user.
Figure 10.4 shows the time required for executing interrupt sequence.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
BCLK
Address
0000016
Address bus
Interrupt
information
Data bus
R
Indeterminate
Indeterminate
SP-2
SP-2
contents
SP-4
vec
SP-4
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 10.4 Time required for executing interrupt sequence
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vec
contents
vec+2
vec+2
contents
PC
18
M16C/1N Group
10. Interrupt
10.1.5.6 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the
first instruction within the interrupt routine has been executed. This time comprises the period from
the occurrence of an interrupt to the completion of the instruction under execution at that moment
(a) and the time required for executing the interrupt sequence (b). Figure 10.5 shows the interrupt
response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then executing is
completed. The length of this time varies with the instruction being executed. The DIVX instruction
requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that
the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and
single-step interrupts.
Locate an interrupt vector address in an even address, if possible.
Interrupt vector address
Stack pointer (SP) value
Without wait
Even
Even
18 cycles
Even
Odd
19 cycles
Odd
Even
19 cycles
Odd
Odd
20 cycles
Figure 10.5 Interrupt response time
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10. Interrupt
10.1.5.7 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values
shown in Table 10.6 is set in the IPL.
Table 10.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
Watchdog timer
7
Reset
0
Other
Not changed
10.1.5.8 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program
counter (PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8
low-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of
the program counter. Figure 10.6 shows the state of the stack as it was before the acceptance of
the interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m-4
m-4
Program counter (PCL)
m-3
m-3
Program counter (PCM)
m-2
m-2
Flag register (FLGL)
m-1
m-1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Program
Flag register
counter (PCH)
(FLGH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 10.6 State of stack before and after acceptance of interrupt request
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[SP]
New stack
pointer value
M16C/1N Group
10. Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note 1), at the time of acceptance of an interrupt request, is even or
odd. If the content of the stack pointer (Note 1) is even, the content of the flag register (FLG) and
the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are
saved in two steps, 8 bits at a time. Figure 10.7 shows the operation of the saving registers.
Note 1: This is the stack pointer indicated by the U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] - 5 (Odd)
[SP] - 4 (Even)
Program counter (PCL)
[SP] - 3 (Odd)
Program counter (PCM)
[SP] - 2 (Even)
Flag register (FLGL)
[SP] - 1 (Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] - 5 (Even)
[SP] - 4 (Odd)
Program counter (PCL)
(3)
[SP] - 3 (Even)
Program counter (PCM)
(4)
[SP] - 2 (Odd)
Flag register (FLG
(1)
[SP] - 1 (Even)
[SP]
Flag register
Program
(FLGH)
counter (PCH)
Saved simultaneously,
all 8 bits
(2)
(Odd)
Finished saving registers
in four operations.
Note 1: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is
acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of saving registers
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M16C/1N Group
10. Interrupt
10.1.5.9 Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag
register (FLG) as it was immediately before the start of interrupt sequence and the contents of the
program counter (PC), both of which have been saved in the stack area. Then control returns to the
program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
10.1.5.10 Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling
(checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt
priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Figure 10.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
Reset
High
UART0 reception
DBC
Watchdog timer/Oscillation stop detection
Peripheral function
Single step
Address match
Low
Figure 10.8 Hardware interrupts priorities
10.1.5.11 Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are
generated simultaneously.
Figure 10.9 shows the interrupt resolution circuit.
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M16C/1N Group
10. Interrupt
Priority level of each interrupt
Level 0 (initial value)
INT1
INT3
TCIN
High
Timer Z
Timer X
CAN0 error
INT2
INT0
Timer C
CNTR0
Timer Y
CAN0 wake up
Priority of peripheral I/O
interrupts
(if priority levels are same)
UART1 reception
UART0 reception
A/D conversion
CAN0 successful reception
Timer 1
UART1 transmission
UART0 transmission
Key input
CAN0 successful transmission
Low
Processor interrupt priority level (IPL)
Interrupt request level
judgment output signal
Interrupt enable flag (I flag)
Interrupt
request
accepted
Address match
Oscillation stop detection/Watchdog timer
DBC (Note 1)
UART0 reception (Note 1)
Reset
UART0 receive hardware
interrupt enable bit
Note 1: Interrupts used for debugging purposes only.
Figure 10.9 Interrupt resolution circuit
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M16C/1N Group
10. Interrupt
______
10.2 INT Interrupt
________
10.2.1 INT0 Interrupt
INT0 to INT3 are triggered by the edges of external inputs. The edge polarity of INT0 to INT2 is selected
using the polarity select bit (bit 4 at addresses 005D16, 005E16 and 005F16). Input to INT0 is available
via filter with three different sampling frequencies.
As to external interrupt input, an interrupt can be generated both at the rising edge and at the falling
________
edge by setting the INTi (i=0 to 3) input polarity select bit of the external input enable register (address
009616) to "1". To select both edges, set the polarity switching bit of the corresponding interrupt control register to "0" (falling edge). To select one edge, set the polarity switching bit of the corresponding
interrupt control register to either "1" (raising edge) or "0" (falling edge). Please note that when one
edge is selected using INT3, the polarity will be a falling edge.
After setting the external input enable register, clear the interrupt request bit, and then enable the
corresponding input interrupt. Moreover, you should write to the external input enable bit only under
conditions where the corresponding input interrupt is disabled.
Figure 10.10 shows the external input related registers.
External input enable register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
INTEN
Bit symbol
When reset
0016
Address
009616
Bit name
Function
RW
INT0EN
INT0 input enable bit (Note 1)
0 : Disabled
1 : Enabled
RW
INT0PL
INT0 input polarity select bit
(Note 1)
0 : One edge
1 : Two edges
RW
INT1EN
INT1 input enable bit
0 : Disabled
1 : Enabled
RW
INT1PL
INT1 input polarity select bit
0 : One edge
1 : Two edges
RW
INT2EN
INT2 input enable bit
0 : Disabled
1 : Enabled
RW
INT2PL
INT2 input polarity select bit
0 : One edge
1 : Two edges
RW
INT3EN
INT3 input enable bit
0 : Disabled
1 : Enabled
RW
INT3PL
INT3 input polarity select bit
0 : One edge
1 : Two edges
RW
Note 1: This bit must be set in condition of the INT0 pin one-shot trigger control bit (bit 6 at address 008416)="0"
(INT0 pin one-shot trigger invalid).
INT0 input filter select register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
INT0F
Bit symbol
Address
001E16
When reset
XXXXX0002
Bit name
Function
RW
b1 b0
INT0F0
INT0 input filter select bit
INT0F1
INT0F2
UART0 receive hardware
interrupt enable bit (Note 1)
0
0
1
1
0
1
0
1
:
:
:
:
No filter
Filter with f1 sampling
Filter with f8 sampling
Filter with f32 sampling
0 : Disabled
1 : Enabled
Nothing is assigned.
When write, nothing can be written. When read, their contents are indeterminate.
Note 1: Interrupts used for debugging purposes only. Be sure to set "0" to this bit.
Figure 10.10 External input related registers
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RW
RW
RW
M16C/1N Group
10. Interrupt
10.2.2 INT0 Input Filter
The INT0 input has a digital filter which can be sampled by one of three sampling clocks. You select
the sampling clock using the INT0 Input Filter Select bits, bits 1 and 0.
INT0 interrupt request occurs when the sampled input level matches three times.
When selecting "Sampling with filter", the value of the port P45, if read, will be the value after filtering.
Figure 10.11 shows the INT0 input filter.
INT0 input filter
select bit
INT0
Digital filter
(input level
matches 3x)
Port P45
direction
register
Figure 10.11 INT0 input filter
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f1
f8
f32
INT0 input enable bit
INT0 interrupt request
M16C/1N Group
10. Interrupt
10.3 CNTR0 Interrupt
A CNTR0 interrupt is generated from the selected edge polarity, a rising or a falling edge, of the CNTR0
input signal. The edge polarity is selected using the CNTR0 polarity select bit (bit 2 at address 008B16).
When using the CNTR0 interrupt, the port P17 direction register should be set to input.
When the pulse output mode of timer X is selected, the CNTR0 pin functions as a pulse output pin. In this
case, a CNTR0 interrupt occurs by a falling or rising edge output from the CNTR0 pin. The port P17
direction register should else be set to input at this time.
Figure 10.12 shows the timer X mode register.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
Address
008B16
Bit name
When reset
0016
Function
RW
b1 b0
Operation mode
0 0 : Timer mode or
select bit 0, 1
pulse period measurement mode
(Note 2) 0 1 : Pulse output mode (Note 1)
1 0 : Event counter mode
1 1 : Pulse width measurement mode
RW
RW
R0EDG
0 : Rising edge
CNTR0 polarity
switching bit (Note 2) 1 : Falling edge
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
Function varies with each operation mode
TXMOD2
Operation mode
select bit 2
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
TXEDG
Effectual edge
Function varies with each operation mode
reception flag (Note 3)
RW
TXUND
Timer X under flow
flag (Note 3)
RW
Function varies with each operation mode
RW
RW
Note 1: In the pulse output mode, the direction register of port P17 should be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use all interrupt, enable an interrupt after the CNTR0
interrupt request bit is cleared with the MOV instruction.
Note 3: Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB).
Figure 10.12 Timer X mode register
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M16C/1N Group
10. Interrupt
10.4 TCIN Interrupt
A TCIN interrupt is generated from edges of a TCIN input signal or after 256 divisions of fRING.
To use TCIN input signal, set the time measurement input source switching bit (bit 7 at address 009A16)
of timer C control register 0 to "0" (TCIN). The level of input to TCIN pin is sampled by one of three
sampling clocks, f1, f8 or f32, selected with the digital filter clock select bit (bits 0 and 1 at address
009B16). The input level is determined when the sampled input level matches three times. (However, if
the port P33 is read, the value will be the unfiltered value.) The edge polarity of an interrupt can be a rising
edge, a falling edge, or both edges using the time measurement edge trigger select bits (bits 3 and 4 at
address 009A16).
When triggered after 256 divisions of fRING, set the time measurement input source switching bit (bit 7 at
address 009A16) to "1" (fRING256).
Figure 10.13 shows the timer C control registers 0 and 1.
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC0
Bit symbol
TCC00
Address
009A16
When reset
0XX000002
Bit name
Time measurement control bit
Function
0 : Time measurement disabled
1 : Time measurement enabled
RW
RW
b2 b1
TCC01
Timer C clock select bit
(Note 1)
TCC02
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
RW
RW
b4 b3
TCC03
Time measurement input edge
trigger bit
(Note 1)
TCC04
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Inhibited
RW
RW
Nothing is assigned.
When write, set "0". When read, their contents are "0".
TCC07
Time measurement input
0 : TCIN
RW
source switching bit
1 : fRING256
(Note 1 to 3)
Note 1: Change this bit when time measurement is disabled.
Note 2: Set the ring oscillation stop bit (CM14) to "0" before setting this bit to "1".
Note 3: Inhibit an interrupt when changing the time measurement input source switching bit. The TCIN interrupt may be
generated after changing the time measurement input source switching bit. An interrupt should be enabled after
the interrupt request bit is cleared.
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC1
Bit symbol
Address
009B16
When reset
XXXXXX112
Bit name
Function
b1 b0
TCC10
Digital filter clock select bit
(Note 1)
TCC11
0 0 : Inhibited
0 1 : f1
1 0 : f8
1 1 : f32
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: Input edge becomes active when the same value from TCIN pin is sampled three times in succession.
Figure 10.13 Timer C control registers 0 and 1
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RW
RW
RW
M16C/1N Group
10. Interrupt
10.5 Key Input Interrupt
_____
When the direction register of any of P10 to P13 is set for input and the KIi (i=0 to 3) input enable bit of this
port is set for enabled, if a falling or rising edge is input to that port, a key input interrupt is generated. A
key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop
mode.
Figure 10.14 shows the block diagram of the key input interrupts. When the appropriate signal ("L" for a
pin that has falling edge selected and "H" for a pin that has rising edge selected) is input to a pin for the
input inhibit process has not been executed, inputs to the other pins are not detected as interrupts.
_____
_____
You should overwrite the KIi (i=0 to 3) input polarity select bit or the KIi (i =0 to 3) input enable bit only
_____
under conditions where the key input interrupt is disabled. After overwriting the KIi (i=0 to 3) input polarity
_____
select bit or the KIi (i=0 to 3) input enable bit, clear the interrupt request bit, and then enable the key input
interrupt.
Port P10-P13
pull-up select bit
Pull-up
transistor
Key input interrupt control register (address 004D16)
Port P13
direction register
KI3 input enable bit
Port P13
direction register
P13/KI3
KI3 input polarity
select bit
KI2 input enable bit
Pull-up
transistor
Port P12
direction register
Interrupt control
circuit
P12/KI2
KI2 input
polarity
select bit
KI1 input enable bit
Pull-up
transistor
Port P11
direction register
P11/KI1
Pull-up
transistor
Key input interrupt
request
KI1 input
polarity
select bit
KI0 input enable bit
Port P10
direction register
P10/KI0
KI0 input
polarity
select bit
Figure 10.14 Block diagram of key input interrupt
Key input enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIEN
Bit symbol
page 64 of 222
Bit name
When reset
0016
Function
RW
KI0EN
KI0 input enable bit
0 : Disabled
1 : Enabled
RW
KI0PL
KI0 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI1EN
KI1 input enable bit
0 : Disabled
1 : Enabled
RW
KI1PL
KI1 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI2EN
KI2 input enable bit
0 : Disabled
1 : Enabled
RW
KI2PL
KI2 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI3EN
KI3 input enable bit
0 : Disabled
1 : Enabled
RW
KI3PL
KI3 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
Figure 10.15 Key input enable register
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Address
009816
M16C/1N Group
10. Interrupt
10.6 Address Match Interrupt
An address match interrupt is generated immediately before the instruction at the address indicated by
the address match interrupt register is executed. Two address match interrupts can be set, each of which
can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figure 10.16 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
Function
RW
Bit symbol
Bit name
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read,
turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
Address
RMAD0
001216 to 001016
RMAD1
001616 to 001416
When reset
XXXX00002, 000000002, 000000002
Function
Values that can be set
RW
Address setting register for address match interrupt
0000016 to FFFFF16
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read,
turns out to be indeterminate.
Figure 10.16 Address match interrupt-related registers
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M16C/1N Group
10. Interrupt
10.7 Precautions for Interrupts
10.7.1 Reading Address 0000016
When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0".
Even if the address 0000016 is read out by software, "0" is set to the enabled highest priority interrupt
source request bit. Therefore, interrupt can be canceled and unexpected interrupt can occur.
Do not read address 0000016 by software.
10.7.2 Setting the Stack Pointer
The value of the stack pointer immediately after reset is initialized to address 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a
value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately
after reset, generating any interrupts is prohibited.
10.7.3 External Interrupt
________
Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0
_______
to INT3 regardless of the CPU operation clock.
________
_______
When changing a polarity of pins INT0 to INT3 and CNTR0, the interrupt request bit may become "1".
Clear the interrupt request bit after changing the polarity. Figure 10.17 shows the switching condition
of external interrupt request.
Clear the interrupt enable flag to "0"
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7
(Enable the accepting of interrupt request)
Set the interrupt enable flag to "1"
(Enable interrupt)
Figure 10.17 Switching condition of external interrupt request
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M16C/1N Group
10. Interrupt
10.7.4 Changing Interrupt Control Register
See "10.1.5.4 Rewrite the Interrupt Control Register".
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M16C/1N Group
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
or reset is generated when an underflow occurs in the watchdog timer. A watchdog timer interrupt or reset
is selected by bit 2 of the processor mode register 1. When XIN is selected for the BCLK, bit 7 of the
watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128).
When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F16).
When XIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
When XCIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 11.1 shows the block diagram of the watchdog timer. Figure 11.2 shows the watchdog timer-related
registers.
Prescaler
"CM07 = 0"
"WDC7 = 0"
"PM12=0"
"CM07 = 0"
"WDC7 = 1"
"PM12=1"
1/16
Watchdog timer
interrupt request
Reset (Note 1)
1/128
BCLK
Watchdog timer
"CM07 = 1"
1/2
Write to the watchdog timer
start register
(address 000E16)
Set to
"7FFF16"
RESET
Note 1: This bit is set to "1" once, can not be clear to "0" by software.
Figure 11.1 Block diagram of watchdog timer
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M16C/1N Group
11. Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
0 0
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
RO
High-order bit of watchdog timer
Reserved bit
WDC7
RW
Prescaler select bit
Set to "0"
RW
0 : Divided by 16
1 : Divided by 128
RW
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction
to this register. The watchdog timer value is always initialized to "7FFF16"
regardless of whatever value is written.
WO
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
0
Bit symbol
PM10
Address
000516
When reset
00XXX0X02
Bit name
DATAROM area access
bit (Note 2)
Function
0 : Disabled
1 : Enabled
RW
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 3)
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Reserved bit
PM17
Wait bit
Set to "0"
RW
0 : No wait
1 : Wait
RW
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0".
Note 3: After setting this bit to "1", can not change to "0" by software.
Figure 11.2 Watchdog timer control and start registers
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M16C/1N Group
12. Timers
12. Timers
The microcomputer has four 8-bit timers and one 16-bit timer. The four 8-bit timers are Timer 1, Timer X,
Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and has time
measurement function. All these timers function independently. The count source for each timer is the
operating clock that regulates the timing of timer operations such as counting and reloading.
Table 12.1 shows functional comparison.
Table 12.1 Functional comparison
Timer1
8-bit timer
with 8-bit
prescaler
Down
•f1
•f8
•f32
•fc32
TimerX
8-bit timer
with 8-bit
prescaler
Down
•f1
•f8
•f32
•fc32
TimerY
8-bit timer
with 8-bit
prescaler
Down
•f1
•f8
•fRING
•fc32
√
−
−
√
√
√
√
−
−
√
−
−
−
−
−
−
√
−
−
−
−
√
−
−
−
−
−
√
√
−
−
−
−
√
−
−
−
−
√
−
Input pin
−
−
−
−
−
INT0
√
TCIN
Output pin
−
−
CNTR0
CNTR0
TXOUT
TmrX int
CNTR0 int
√
TYOUT
TZOUT
−
TmrY int
TmrZ int
√
√
Configuration
Count
Count source
Function
Timer mode
Pulse output mode
Event counter mode
Pulse width
measurement mode
Pulse period
measurement mode
Programmable waveform
generation mode
Programmable one-shot
generation mode
Programmable wait
one-shot generation mode
Time measurement
Related interrupt
Tmr1 int
Timer stop
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−
page 70 of 222
TimerZ
8-bit timer
with 8-bit
prescaler
Down
•f1
•f8
•TmrY underflow
•fc32
TimerC
16-bit
free-run
timer
Up
•f1
•f8
•f32
TmrC int
TCIN int
√
M16C/1N Group
12. Timers
12.1 Timer 1
Timer 1 is an 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer 1. The timer
constantly counts an internally generated count source (clock source). The count source after reset is set
to f1. The timer cannot stop counting. Table 12.2 shows the specifications of Timer 1 and Figure 12.2
shows Timer 1 related registers.
Peripheral data bus
Clock source
selection
Reload register (8)
f1
f8
fP1
Counter (8)
f32
fC32
Reload register (8)
Prescaler 1 (address 008816)
Counter (8)
Timer 1 interrupt
request bit
Timer 1 (address 008916)
Figure 12.1 Block diagram of Timer 1
Table 12.2 Specifications of Timer 1 (Timer mode)
Item
Count source
Count operation
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
1
(n+1) X (m+1)
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
Read from timer
Write to timer
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Specification
n: Set value of Prescaler 1, m: Set value of Timer 1
After reset
Disable to stop counting
When Timer 1 underflows
Count value can be read out by reading Timer 1 register.
Same applies to Prescaler 1 register.
When a value is written to Timer 1 register, it is written to both reload register and
counter.
Same applies to Prescaler 1 register.
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M16C/1N Group
12. Timers
Prescaler 1
b7
b0
Symbol
PRE1
Address
008816
When reset
Indeterminate
Function
Values that can be set RW
When set value = n, Prescaler 1 divides the internal count
source by n+1
0016 to FF16
RW
Timer 1
b7
b0
Symbol
T1
Address
008916
Function
When reset
Indeterminate
Values that can be set RW
When set value = m, Timer 1 divides the underflow of
Prescaler 1 by m+1
0016 to FF16
RW
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Bit symbol
Bit name
TXCK0
Timer X count source
select bit (Note 1)
TXCK1
TYCK0
Timer Y count source
select bit (Note 1, 2)
TYCK1
TZCK0
Timer Z count source
select bit (Note 1, 4)
TZCK1
T1CK0
T1CK1
When reset
0016
Address
008E16
Timer 1 count source
select bit
Function
RW
b1 b0
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
b3 b2
0 0 : f1
0 1 : f8
1 0 : On-chip oscillator output (Note 3)
1 1 : fC32
RW
RW
b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
RW
RW
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before
switching a count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the
system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source.
Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the
Timer Y underflow for count source.
Figure 12.2 Timer 1-related register
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M16C/1N Group
12. Timers
12.2 Timer X
Timer X is an 8-bit timer with an 8-bit prescaler.
Timer X has the five operation modes listed as follows:
• Timer mode:
The timer counts an internal count source (clock source).
• Pulse output mode:
The timer counts an internal count source and outputs the pulses
whose polarity is inverted at the timer the timer underflows.
• Event counter mode:
The timer counts pulses from an external source.
• Pulse width measurement mode: The timer measures an external pulse's pulse width.
• Pulse period measurement mode: The timer measures an external pulse's period.
Figure 12.3 shows the block diagram of Timer X. Figures 12.4 and 12.5 shows the Timer X-related
registers.
Peripheral data bus
Timer
Pulse period
measurement
Pulse output
Clock source
selection
f1
f8
f32
fC32
Pulse width
measurement
Counter (8)
Reload register (8)
fPX
Prescaler X (address 008C16)
Event counter
CNTR0
Reload register (8)
Counter (8)
Timer X interrupt
request bit
Timer X (address 008D16)
Timer X count
start flag
CNTR0 interrupt
request bit
Polarity
switching
"1"
Pulse output
Q
Toggle flip-flop
Q
"0"
P30/TXOUT select bit
T
R
CNTR0 polarity
switching bit
TXOUT
Timer X latch write
Pulse output mode
Figure 12.3 Block diagram of Timer X
Timer X mode register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
Address
008B16
Bit name
When reset
0016
Function
RW
b1 b0
Operation mode
00
select bit 0, 1
(Note 2) 0 1
10
11
: Timer mode or
pulse period measurement mode
: Pulse output mode (Note 1)
: Event counter mode
: Pulse width measurement mode
RW
RW
R0EDG
CNTR0 polarity
0 : Rising edge
switching bit (Note 2) 1 : Falling edge
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
Function varies with each operation mode
TXMOD2
Operation mode
select bit 2
0 : Except in pulse period measurement mode
1 : Pulse period measurement mode
TXEDG
Effectual edge
Function varies with each operation mode
reception flag (Note 3)
RW
TXUND
Timer X under flow
flag (Note 3)
RW
Function varies with each operation mode
RW
RW
Note 1: In the pulse output mode, the direction register of port P17 should be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use all interrupt, enable an interrupt after the CNTR0
interrupt request bit is cleared with the MOV instruction.
Note 3: Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB).
Figure 12.4 Timer X-related registers (1)
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M16C/1N Group
12. Timers
Prescaler X
b7
b0
Symbol
PREX
Address
008C16
When reset
FF16
Function
Values that can be set RW
Timer mode
Internal count source is counted
0016 to FF16
RW
Pulse output mode
Internal count source is counted
0016 to FF16
RW
Event counter mode
Externally input pulses are counted
0016 to FF16
RW
Pulse width measurement mode
Pulse width of externally input pulses is measured
(Internal count source is counted)
0016 to FF16
RW
Pulse period measurement mode
Pulse period of externally input pulses is measured
(Internal count source is counted)
0016 to FF16
RW
Timer X
b7
b0
Symbol
TX
Address
008D16
When reset
FF16
Function
Values that can be set RW
Timer mode, Pulse output mode, Event counter mode,
Pulse width measurement mode
Underflow of prescaler X is counted
0016 to FF16
RW
Pulse period measurement mode
Underflow of prescaler X is counted
0116 to FF16
RW
Timer count source setting register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
TCSS
Address
008E16
Bit symbol
Bit name
TXCK0
Timer X count source
select bit (Note 1)
TXCK1
TYCK0
Timer Y count source
select bit (Note 1, 2)
TYCK1
TZCK0
Function
0
0
1
1
0
1
0
1
:
:
:
:
f1
f8
f32
fC32
RW
:
:
:
:
f1
f8
On-chip oscillator output (Note 3)
fC32
RW
RW
b3 b2
0
0
1
1
0
1
0
1
b5 b4
Timer 1 count source
select bit
b7 b6
T1CK1
RW
b1 b0
Timer Z count source
select bit (Note 1, 4)
TZCK1
T1CK0
When reset
0016
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RW
: f1
: f8
: Timer Y underflow
: fC32
RW
:
:
:
:
RW
f1
f8
f32
fC32
RW
RW
Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before
switching a count source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the
system clock control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source.
Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the
Timer Y underflow for count source.
Figure 12.5 Timer X-related registers (2)
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M16C/1N Group
12. Timers
12.2.1 Timer Mode
In this mode, the timer counts an internally generated count source.
(See Table 12.3) Figure 12.6 shows the Timer X mode register in timer mode.
Table 12.3 Specifications of timer mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
1
(n+1) X (m+1)
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
CNTR0 pin function
TXOUT pin function
Read from timer
Write to timer
n: Set value of Prescaler X, m: Set value of Timer X
Count start flag is set (=1)
Count start flag is reset (=0)
When Timer X underflows [Timer X interruption]
Programmable I/O port or CNTR0 interrupt input pin
Programmable I/O port
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Timer X mode register
b7
b6
b5 b4
b3
b2
0 0
b1
b0
Symbol
TXMR
0 0
Bit symbol
TXMOD0
TXMOD1
Address
008B16
Bit name
When reset
0016
Function
b1 b0
Operation mode
0 0 : Timer mode
select bit 0, 1
(Note 1)
RW
RW
RW
R0EDG
CNTR0 polarity
switching bit (Note 1)
0 : Rising edge
1 : Falling edge
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
0 : In timer mode, set to "0"
RW
TXMOD2
Operation mode
select bit 2
0 : In timer mode, set to "0"
RW
TXEDG
Effectual edge
reception flag
Invalid in timer mode.
When write, set "0". When read, this contents
is indeterminate.
RW
Timer X under
flow flag
Invalid in timer mode.
When write, set "0". When read, this contents
is indeterminate.
RW
TXUND
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Figure 12.6 Timer X mode register in timer mode
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M16C/1N Group
12. Timers
12.2.2 Pulse Output Mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows.
(See Table 12.4) Figure 12.7 shows Timer X mode register in pulse output mode.
Table 12.4 Specifications of pulse output mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
1
(n+1) X (m+1)
Divide ratio
n: Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [CNTR0 interruption]
CNTR0 pin function
Pulse output
TXOUT pin function
Programmable I/O port or pulse output (Inverted waveform of the pulse output from the
CNTR0 pin)
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
• Pulse output function
Each time the timer underflows, the TXOUT pin’s polarity is reversed
• CNTR0 polarity switching function
The polarity level at starting of pulse output can be selected to be "High" or "Low" with software.
Timer X mode register
b7
b6
b5 b4
b3
b2
0
b1
b0
Symbol
TXMR
0 1
Bit symbol
TXMOD0
TXMOD1
Address
008B16
Bit name
When reset
0016
Function
b1 b0
Operation mode
0 1 : Pulse output mode (Note 1)
select bit 0, 1
(Note 2)
RW
RW
R0EDG
CNTR0 polarity
0 : Output starts at "H" (Interrupt at rising edge)
switching bit (Note 2) 1 : Output starts at "L" (Interrupt at falling edge)
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
0 : Port P30
1 : TXOUT output (Note 3)
RW
TXMOD2
Operation mode
select bit 2
0 : Set to "0" in pulse output mode
RW
TXEDG
Effectual edge
reception flag
Invalid in pulse output mode.
When write, set "0". When read, this contents
is indeterminate.
RW
Timer X under
flow flag
Invalid in pulse output mode.
When write, set "0". When read, this contents
is indeterminate.
RW
TXUND
Note 1: In the pulse output mode, the direction register of port P17 must be set to input.
Note 2: This bit should rewrite with inhibiting the CNTR0 interrupt. To use this interrupt, enable an interrupt after the
CNTR0 interrupt request bit is cleared with the MOV instruction.
Note 3: Output is set regardless of the setting of the direction register of port P30.
Figure 12.7 Timer X mode register in pulse output mode
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
RW
page 76 of 222
M16C/1N Group
12. Timers
12.2.3 Event Counter Mode
In this mode, the timer counts an external signal fed to CNTR0 pin. (See Table 12.5) Figure 12.8
shows Timer X mode register in event counter mode.
Table 12.5 Specifications of event counter mode
Item
Specification
Count source
Count operation
External signals fed to CNTR0 pin (Active edge is selected by software)
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1
(n+1) X (m+1)
n: Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
CNTR0 pin function
Count source input
TXOUT pin function
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
• CNTR0 polarity switching function
The active edge of count source can be selected to be the rising or the falling edge with
software.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Address
008B16
Symbol
TXMR
1 0
Bit symbol
TXMOD0
TXMOD1
Bit name
When reset
0016
Function
b1 b0
Operation mode
1 0 : Event counter mode
select bit 0, 1
(Note 1)
RW
RW
RW
R0EDG
CNTR0 polarity
0 : Counts at rising edge (Interrupt at rising edge)
switching bit (Note 1) 1 : Counts at falling edge (Interrupt at falling edge)
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
0 : Set to "0" in event counter mode
RW
TXMOD2
Operation mode
select bit 2
0 : Set to "0" in event counter mode
RW
TXEDG
Effectual edge
reception flag
Invalid in event counter mode.
When write, set "0". When read, this contents
is indeterminate.
RW
Timer X under
flow flag
Invalid in event counter mode.
When write, set "0". When read, this contents
is indeterminate.
RW
TXUND
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Figure 12.8 Timer X mode register in event counter mode
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M16C/1N Group
12. Timers
12.2.4 Pulse Width Measurement Mode
In this mode, the timer measures the pulse width of an external signal fed to CNTR0 pin.
(See Table 12.6) Figure 12.9 shows the Timer X mode register in pulse width measurement mode.
Figure 12.10 shows an operation example in pulse width measurement mode.
Table 12.6 Specifications of pulse width measurement mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• Down count
• Continuously counts the selected signal only when the measurement pulse is "H" level,
or conversely only "L" level.
• When the timer underflows, it reloads the reload register contents before continuing
counting
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
CNTR0 pin function
Measurement pulse input
TXOUT pin function
Read from timer
Programmable I/O port
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
• CNTR0 polarity switching function
The measurement pulse input can be selected to be "H" level width or "L" level width by
software.
Write to timer
Select function
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TXMR
1 1
Bit symbol
TXMOD0
TXMOD1
Address
008B16
When reset
0016
Bit name
Function
Operation mode
b1 b0
1 1 : Pulse width measurement mode
select bit 0, 1
(Note 1)
RW
RW
RW
R0EDG
CNTR0 polarity
0 : Measures "L" level width (Interrupt at rising edge)
switching bit (Note 1) 1 : Measures "H" level width (Interrupt at falling edge)
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT
P30/TXOUT
select bit
0 : Set to "0" in pulse width measurement mode
RW
TXMOD2
Operation mode
select bit 2
0 : Set to "0" in pulse width measurement mode
RW
TXEDG
Effectual edge
reception flag
Invalid in pulse width measurement mode.
When write, set "0". When read, this contents
is indeterminate.
RW
Timer X under
flow flag
Invalid in pulse width measurement mode.
When write, set "0". When read, this contents
is indeterminate.
RW
TXUND
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Figure 12.9 Timer X mode register in pulse width measurement mode
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12. Timers
Conditions: "H" level width of measurement pulse is measured. (R0EDG=1)
n = high-level: the contents of Timer X reload register, low-level: the contents of Prescaler X reload register
FFFF16
Count start
Underflow
Counter contents
n
Count stop
Count stop
Count restart
000016
Time
Set to "1" by software
Count start flag "1"
"0"
Measurement pulse "H"
(CNTR0 pin input) "L"
Cleared to "0" when interrupt request is accepted, or cleared by software
CNTR0 interrupt
request bit
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Timer X interrupt "1"
request bit "0"
Figure 12.10 Operation example in pulse width measurement mode
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12. Timers
12.2.5 Pulse Period Measurement Mode
In this mode, the timer measures the pulse period of an external signal fed to CNTR0 pin.
Table 12.7 lists specifications of pulse period measurement mode. Figure 12.11 shows the Timer X
mode register in pulse period measurement mode. Figure 12.12 shows the operation example.
Table 12.7 Specifications of pulse period measurement mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• Down count
• After valid edge of measurement pulse is input, the timer X reloads contents in the
reload register and continues counting in underflow of the second prescaler X.
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing • When Timer X underflows [Timer X interruption]
• Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption or timer X interrupt]
CNTR0 pin function
Measurement pulse input (Note 1)
TXOUT pin function
Programmable I/O port
Read from timer
When reading Timer X register, the count value of buffer for read purpose can be read
out. The buffer of read purpose retains the content of Timer X register upon an active
edge of measurement pulse, and starts to read the content of Timer X register by reading
Timer X.
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
• CNTR0 polarity switching function
The measurement period of pulse input can be selected to be a period from one rising
edge to the next rising edge or from one falling edge to the next falling edge by software.
Write to timer
Select function
Note 1: Avoid a shorter period pulse input than double prescaler X period. Longer pulse for H width and L width than the
prescaler X period should be input to the CNTR0 pin. If shorter pulse than the period is input to the CNTR0 pin,
the input may be disabled.
Timer X mode register
b7
b6
b5 b4
1
b3
0
b2
b1
b0
0
0
Symbol
TXMR
Bit symbol
TXMOD0
TXMOD1
R0EDG
TXS
TXOCNT
TXMOD2
Address
008B16
When reset
0016
Bit name
Function
Operation mode
b1 b0
0 0 : Pulse period measurement mode
select bit 0, 1
(Note 1)
CNTR0 polarity
0 : Measures a measurement pulse from one
rising edge to the next rising edge
switching bit
(Interrupt at rising edge)
(Note 1)
1 : Measures a measurement pulse from one
falling edge to the next falling edge
(Interrupt at falling edge)
Timer X count
0 : Stops counting
start flag (Note 3)
1 : Starts counting
P30/TXOUT
0 : In pulse period measurement mode, set to "0"
select bit
Operation mode
1 : Pulse period measurement mode
select bit 2 (Note 1)
RW
RW
RW
RW
RW
RW
RW
TXEDG
Effectual edge
0 : No effectual edge
reception flag (Note 2) 1 : Effectual edge found
RW
TXUND
Timer X under
flow flag (Note 2)
RW
0 : No under flow
1 : Under flow found
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Note 2: These bits are set to "0" by writing a "0" in a program. (Writing a "1" has no effect.)
Nothing is assigned to the pod probe for M16C/1N group (M301N2T-PRB).
Note 3: Execute the MOV instruction when stopping the timer X while pulse period measurement mode.
Figure 12.11 Timer X mode register in pulse period measurement mode
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12. Timers
Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured. (R0EDG=0)
Timer X=0F16
fPX
Set to "1" by software (Note 7)
Count start flag
"1"
"0"
Count start
Measurement pulse "1"
(CNTR0 pin input) "0"
Hold
Timer X
reloads
Timer X
reloads
Timer X contents
0F16
Timer X
reloads
0E16 0D16 0F16 0E16 0D16 0C16 0B16 0A16 0916 0F16 0E16
Contents of read
purpose buffer
(Note 1)
0B16 0A16
XX16
(Note 2)
0916
Timer X
Dummy read (Note 3)
(Note 2)
0116 0016 0F16 0E16
0D16
0116 0016 0F16 0E16
Timer X
Read by software
(Note 3)
Effectual edge "1"
reception flag
"0"
Cleared to "0" by software (Note 4)
(Note 6)
Timer X "1"
underflow flag "0"
Cleared to "0" by software (Note 5)
Timer X interrupt "1"
request bit
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
CNTR0 interrupt "1"
request bit "0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Note 1: If timer X is read out in pulse period measurement mode, the contents of the read purpose buffer can be read.
Note 2: After an active edge of measurement pulse is input, effectual edge reception flag (TXEDG) is set to "1" when the prescaler
X underflows for the second time.
Note 3: The timer X should be read out before the next active edge is input after TXEDG is set to "1". If the timer X is not read
before the next active edge is input, the value in the read purpose buffer remains unchanged and therefore is not updated
on an active edge.
Note 4: When set to "0" by software, use a MOV instruction to write "0" to the bit 6 (TXEDG) in the timer X mode register (008B16).
At the same time, write "1" to the bit 7 (TXUND).
Note 5: When set to "0" by software, use a MOV instruction to write "0" to the bit 7 (TXUND) in the timer X more register (008B16).
At the same time, write "1" to the bit 6 (TXEDG).
Note 6: If the timer X underflow flag (TXUND) and TXEDG are both set to "1". In this case, the validity of TXUND should be judged
by the contents of the read purpose buffer.
Note 7: When setting the timer X count start flag to "1", the timer X interrupt request bit and the effectual edge reception flag may
become "1".
Thus, the timer X interrupt must be enabled after setting the timer X count flag to "1" and clearing the timer X interrupt
request bit and the effectual edge reception flag to "0" with inhibiting the timer X interrupt.
Figure 12.12 Operation example in pulse width measurement mode
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12. Timers
12.3 Timer Y
Timer Y is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Y Primary and Timer
Y Secondary.
Timer Y has the two operation modes listed as follows:
• Timer mode: The timer counts an internal count source (clock source).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
Figure 12.13 shows the block diagram of Timer Y. Figures 12.14 to 12.16 show the Timer Y-related
registers.
Peripheral data bus
Timer Y primary
(address 008316)
Clock source
selection
Reload register (8)
f1
f8
fRING
fC32
Timer Y secondary
(address 008216)
Reload register (8)
Reload register (8)
Counter (8)
Counter (8)
fPY
Prescaler Y (address 008116)
Timer Y interrupt
request bit
Timer Y (address 008316)
Timer Y count
start flag
Programmable waveform
generation mode
"1"
Q
"0"
Toggle flip-flop
TYOUT
T
Q
Port P32 register
"0"
"1"
Timer Y output
level latch
Timer Y programmable
waveform output
switching bit
Figure 12.13 Block diagram of Timer Y
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
Bit symbol
TYMOD0
Address
008016
Function
RW
0 : Timer mode
1 : Programmable waveform generation mode
(Note 1)
RW
Bit name
Timer Y operation
mode bit
When reset
000000X02
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y write
control bit
Function varies depending on
the operation mode
RW
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
TZMOD0
Timer Z operation
mode bit (Note 3)
b5 b4
TZWC
Timer Z write
control bit
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on
the operation mode
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
TZMOD1
RW
RW
RW
RW
Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the value of the direction
register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output regardless of the value of
the direction register.
Figure 12.14 Timer Y-related registers (1)
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12. Timers
Prescaler Y
b7
b0
Symbol
PREY
Address
008116
When reset
FF16
Values that can be set
RW
Timer mode
Internal count source is counted
Function
0016 to FF16
RW
Programmable waveform generation mode
Internal count source is counted
0016 to FF16
RW
(Note 1)
Note 1: When using the waveform extend function, set the value "0016" for the Prescaler Y.
Timer Y Secondary
b7
b0
Symbol
TYSC
Address
008216
When reset
FF16
Function
Values that can be set
RW
Timer mode
Invalid
Programmable waveform generation mode
Underflow of Prescaler Y is counted (Note 1)
0016 to FF16
WO
(Note 2)
Note 1: The values of Timer Y Primary and Timer Y Secondary are reloaded to the Timer Y alternately for counting.
Note 2: The count value can be read out by reading the Timer Y Primary even when the secondary period is being
counted.
Timer Y Primary
b7
b0
Symbol
TYPR
Address
008316
When reset
FF16
Function
Values that can be set
RW
Timer mode
Underflow of Prescaler Y is counted
0016 to FF16
RW
Programmable waveform generation mode
Underflow of Prescaler Y is counted (Note 1)
0016 to FF16
RW
Note 1: The values of Timer Y Primary and Timer Y Secondary are reloaded to the Timer Y alternately for counting.
Timer Y, Z output control register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
TYZOC
Bit symbol
When reset
XXXXX0002
Address
008A16
Bit name
Function
RW
TZOS
Timer Z one-shot
start bit (Note 1)
0 : Stops one-shot
1 : Starts one-shot
RW
TYOCNT
Timer Y programmable
waveform generation
output switching bit (Note 2)
0 : Outputs programmable waveform
1 : Outputs the value of P32 port register
RW
Timer Z programmable
waveform generation
output switching bit (Note 2)
0 : Outputs programmable waveform
1 : Outputs the value of P31 port register
RW
TZOCNT
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: This bit is automatically cleared to "0" when the output of one-shot waveform is completed. This bit should be set to
"0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the
waveform output.
Note 2: This bit is valid only when operating in programmable waveform generation mode.
Figure 12.15 Timer Y-related registers (2)
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12. Timers
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
TZPUM1
Address
008416
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
Timer Z primary
waveform extension
control bit
Timer Z secondary
waveform extension
control bit
When reset
0016
Function
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 2)
RW
0 : No waveform extension
1 : Waveform extension (Note 2)
RW
TYOPL
Timer Y output level
latch
Function varies depending on the operation mode
TZOPL
Timer Z output level
latch
Function varies depending on the operation mode
INOSTG
INT0 pin one-shot
trigger control bit
(Timer Z)
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid (Note 3)
INOSEG
RW
0 : Edge trigger at falling edge
INT0 pin one-shot
trigger polarity select bit 1 : Edge trigger at rising edge
(Note 4)
(Timer Z)
RW
RW
RW
RW
Note 1: When setting this bit to "1", the prescaler Y register must be set to "0016".
Note 2: When setting this bit to "1", the prescaler Z register must be set to "0016".
Note 3: When setting this bit to "1", this bit must be set to "1" after setting the INT0 input enable bit (bit 0 at address 009616), the
INT0 input polarity select bit (bit 1 at address 009616), the INT0 input filter select bits (bits 0 and 1 at address 001E16)
and the INT0 pin one-shot trigger polarity select bit.
Note 4: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge).
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Bit symbol
TXCK0
Address
008E16
Bit name
b1 b0
Timer Y count source
select bit (Note 1, 2)
b3 b2
TYCK1
TZCK0
Timer Z count source
select bit (Note 1, 4)
TZCK1
T1CK0
Function
Timer X count source
select bit (Note 1)
TXCK1
TYCK0
When reset
0016
Timer 1 count source
select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
0 0 : f1
0 1 : f8
1 0 : On-chip oscillator output (Note 3)
1 1 : fC32
RW
RW
RW
RW
RW
b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer Y underflow
1 1 : fC32
RW
RW
b7 b6
0 0 : f1
RW
0 1 : f8
1 0 : f32
T1CK1
RW
1 1 : fC32
Note 1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a
counter source.
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Note 3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock
control register (address 000716) for oscillation enabled.
Note 4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source.
Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y
underflow for count source.
Figure 12.16 Timer Y-related registers (3)
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12. Timers
12.3.1 Timer Mode
In this mode, the timer counts an internally generated count source.
(See Table 12.8) The Timer Y secondary is unused in this mode. Figure 12.17 shows the Timer Y, Z
mode register and Timer Y, Z waveform output control register in timer mode.
Table 12.8 Specifications of timer mode
Item
Specification
Count source
Count operation
f1, f8, on-chip oscillator output, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Y underflows, the contents of the Timer Y primary reload
register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before it
stops.
1
(n+1) X (m+1)
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TYOUT pin function
Read from timer
n: Set value of Prescaler Y, m: Set value of Timer Y primary
Count start flag is set (=1)
Count start flag is reset (=0) (Note 1)
When Timer Y underflows
Programmable I/O port
Count value can be read out by reading Timer Y primary register.
Same applies to Prescaler Y register.
Write to timer
When a value is written to Timer Y Primary register, it is written to both reload register
and counter or written to only reload register. Selected by software.
Same applies to Prescaler Y register.
Select function
• Timer Y write control function (Note 2)
When a value is written to Timer Y Primary register, it can be selected that the value is
written to both reload register and counter or written to only reload register.
Same applies to Prescaler Z register.
Note 1: When the count is stopped, the Timer Y interrupt request bit becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request bit to "0"
before starting counting again.
Note 2: If writing to the Timer Y or prescaler Y under the following conditions being filled at the same time the Timer Y
interrupt request bit becomes "1" and an interrupt occurs.
<Conditions>
• Timer Y write control bit (bit 2 at address 008016) is "0" (write to timer and reload register simultaneously)
• Timer Y count start flag (bit 3 at address 008016) is "1" (count start)
To write to the Timer Y or prescaler Y in the above state, disable interrupts before writing.
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12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
0
Bit symbol
TYMOD0
Address
008016
Bit name
When reset
000000X02
Function
Timer Y operation
mode bit
0 : Timer mode
RW
RW
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Timer Y write
control bit
0 : Write to timer and reload register
simultaneously (Note 1)
1 : Write to reload register
RW
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
TZMOD0
Timer Z-related bit
TYWC
RW
TZMOD1
RW
TZWC
RW
TZS
RW
Note 1: When this bit is "0", when you write in the prescaler Y while the timer Y is counting, the timer Y reloads the content
of the timer Y reload register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
Address
008416
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
When reset
0016
Function
Invalid in timer mode
RW
RW
Invalid in timer mode
RW
Timer Z-related bits
RW
RW
TZPUM1
TYOPL
Timer Y output level
latch
TZOPL
Timer Z-related bits
Invalid in timer mode
RW
RW
INOSTG
RW
INOSEG
RW
Figure 12.17 Timer Y, Z mode register in timer mode and Timer Y, Z waveform output control
register
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12. Timers
12.3.2 Programmable Waveform Generation Mode
In this mode, the microcontroller, while counting the set values of Timer Y primary and Timer Y secondary alternately, outputs from the TYOUT pin a waveform whose polarity is inverted each time Timer
Y secondary underflows.
(See Table 12.9) A counting starts by counting the set value in the Timer Y primary. Figure 12.18
shows Timer Y, Z mode register in programmable waveform generation mode. Figure 12.19 shows
the operation example.
Table 12.9 Specifications of programmable waveform generation mode
Item
Specification
Count source
Count operation
f1, f8, on-chip oscillator output, fC32
• Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it
stops.
fi
(n+1) X ((m+1)+(l+1))
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TYOUT pin function
Read from timer
Write to timer
Select function
n: Set value of Prescaler Y, m: Set value of Timer Y primary, l: Set value of Timer Y secondary
Count start flag is set (=1)
Count start flag is reset (=0) (Note 1)
When Timer Y underflows during secondary period
Pulse output (Note 2)
Count value can be read out by reading Timer Y primary register.
Same applies to Prescaler Y register. (Note 3)
When a value is written to Timer Y primary register, it is written to only reload register.
Same applies to Timer Y secondary register and Prescaler Y register. (Note 4)
• Output level latch select function
The output level of a waveform being counted during primary and secondary periods is
selectable.
• Programmable waveform generation output switching function (Note 5)
Can select either programmable waveform or the value of port P32 register for output.
• Waveform extend function (Note 6)
The waveform output primary period and secondary period can each be extended 0.5
cycles of the count source.
Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TYPUM0+TYPUM1)
Duty: (2x(m+1)+TYPUM0)/((2x(m+1)+TYPUM0)+(2x(l+1)+TYPUM1))
m: set value of Timer Y primary, l: set value of Timer Y secondary
TYPUM0: Timer Y primary waveform extension control bit
TYPUM1: Timer Y secondary waveform extension control bit
Note 1: When the count is stopped, the Timer Y interrupt request bit becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Y interrupt request bit to "0"
before starting counting again.
Note 2: When the counting stopped, the pin is the secondary period output level.
Note 3: Even when counting the secondary period, read out the Timer Y primary register.
Note 4: The set value of Timer Y secondary register and waveform extension control bits as well as Timer Y primary
register are made effective by writing a value to the Timer Y primary register. The written values are reflected to
the waveform output from the next primary period after writing to the Timer Y primary register.
Note 5: The output is switched in sync with Timer Y secondary underflow.
Note 6: When using the waveform extend function, the Prescaler Y register must be set to "0016".
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12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
TYZMR
1
Bit symbol
TYMOD0
When reset
000000X02
Address
008016
Bit name
Timer Y operation
mode bit
Function
RW
1 : Programmable waveform generation mode
(Note 1)
RW
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
TYWC
Timer Y write
control bit
1 : Set to "1" in programmable waveform
generation mode
RW
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
TZMOD0
Timer Z-related bit
RW
TZMOD1
RW
TZWC
RW
TZS
RW
Note 1: Output is set for Port P32 regardless of the value of the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
Address
008416
When reset
0016
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
Function
RW
0 : No waveform extension
1 : Waveform extension (Note 1, 2)
RW
Timer Z-related bits
RW
RW
TZPUM1
TYOPL
TZOPL
RW
0 : No waveform extension
1 : Waveform extension (Note 1, 2)
Timer Y output level
latch
0 : Outputs "H" for the period set by Timer Y primary and
"L" for the period set by Timer Y secondary.
"L" is outputted when the timer is stopped.
1 : Outputs "L" for the period set by Timer Y primary and
"H" for the period set by Timer Y secondary.
"H" is outputted when the timer is stopped.
Timer Z-related bits
RW
RW
INOSTG
RW
INOSEG
RW
Note 1: When setting this bit to "1", the Prescaler Y Register must be set to "0016".
Note 2: The waveform extend function cannot be used when selecting f1 for count source.
Figure 12.18 Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable waveform generation mode
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12. Timers
Conditions: Timer Y primary=0316, Timer Y primary waveform not extended,
Timer Y secondary=0216, Timer Y secondary waveform extended,
Timer Y output level latch [TYOPL]=0
fPY
Set to "1" by
software
Count start flag
"1"
"0"
Timer Y
secondary
reload
Timer Y
primary
reload
Timer Y
secondary
reload
Count start
0316
The contents of Timer Y
0216
0116
0016
0216
0116
0016
0316
0216
0116
0016 0216
0116
Cleared to "0" when interrupt
request is accepted,
or cleared by software
Timer Y interrupt "1"
request bit
"0"
Cleared to "0"
by software
Timer Y output "1"
level latch
"0"
Waveform
output started
Waveform
output inverted
Waveform
output inverted
(Note 1)
Waveform
output inverted
"H"
TYOUT pin output
"L"
Initialized to "L"
Secondary waveform
extended
Note 1: The waveform output in the secondary period is inverted after 0.5 clock (1 clock when
secondary waveform extended) of fPY from occurrence of Timer Y interrupt request.
Figure 12.19 Timer Y operation example in programmable waveform generation mode
Programmable waveform generation output switching function
When the Timer Y programmable waveform generation output switching bit (bit 1 at address 008A16)
is set to 0, the output from TYOUT is inverted synchronously when the Timer Y secondary underflows.
And when set to 1, the Port P32 register value is output from TYOUT synchronously when the Timer Y
secondary underflows.
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12. Timers
12.4 Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers - Timer Z Primary and Timer
Z Secondary.
Timer Z has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source (clock source) or Timer Y underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Figure 12.20 shows the block diagram of Timer Z. Figures 12.21 to 12.24 show the Timer Z-related
registers.
Peripheral data bus
Timer Z primary
(address 008716)
Reload register (8)
Clock source
selection
f1
f8
Timer Y underflow
Counter (8)
Timer Z count
start flag
Digital
filter
INT0
Reload register (8)
Reload register (8)
fPZ
Counter (8)
Timer Z (address 008716)
Prescaler Z (address 008516)
fC32
One edge/ both edges
input polarity select
INT0 input polarity select bit
Programmable waveform generation mode
INT0 input enable bit
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Timer Z one-shot start bit
Polarity
select
INT0 one-shot trigger
polarity select bit
"1"
Q
"0"
Toggle flip-flop
TZOUT
Port P31 register
"1"
Timer Z programmable
waveform output
switching bit
Figure 12.20 Block diagram of Timer Z
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Timer Z secondary
(address 008616)
page 90 of 222
"0"
Timer Z output
level latch
Q
T
Timer Z interrupt
request bit
M16C/1N Group
12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
Bit symbol
TYMOD0
Address
008016
Function
RW
0 : Timer mode
1 : Programmable waveform generation mode
(Note 1)
RW
Bit name
Timer Y operation
mode bit
When reset
000000X02
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y write
control bit
Function varies depending on
the operation mode
RW
TYS
Timer Y count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
TZMOD0
Timer Z operation
mode bit (Note 3)
b5 b4
TZWC
Timer Z write
control bit
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
Function varies depending on
the operation mode
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
TZMOD1
RW
RW
RW
RW
Note 1: In programmable waveform generation mode, port P32 is set for output regardless of the value of the direction
register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Note 3: When timer Z operation mode bit is set for "01", "10" or "11", port P31 is set for output regardless of the value of
the direction register.
Figure 12.21 Timer Z-related registers (1)
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12. Timers
Prescaler Z
b7
b0
Symbol
PREZ
Address
008516
Function
When reset
FF16
Values that can be set RW
Timer mode
Internal count source or Timer Y underflow is counted
0016 to FF16
Programmable waveform generation mode
Internal count source or Timer Y underflow is counted
RW
0016 to FF16
(Note 1)
Programmable one-shot generation mode
Internal count source or Timer Y underflow is counted
0016 to FF16
RW
(Note 1)
Programmable wait one-shot generation mode
Internal count source or Timer Y underflow is counted
RW
0016 to FF16
(Note 1)
RW
Note 1: When using the waveform extend function, set the value "0016" for the Prescaler Z.
Timer Z Secondary
b7
b0
Symbol
TZSC
Address
008616
Function
When reset
FF16
Values that can be set RW
Timer mode
Invalid
Programmable waveform generation mode
Underflow of Prescaler Z is counted (Note 1)
0016 to FF16
WO
(Note 2)
Programmable one-shot generation mode
Invalid
Programmable wait one-shot generation mode
Underflow of Prescaler Z is counted
0016 to FF16
WO
(One-shot width is counted)
Note 1: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the Timer Z alternately for counting.
Note 2: The count value can be read out by reading the Timer Z Primary even when the secondary period is being
counted.
Timer Z Primary
b7
b0
Symbol
TZPR
Address
008716
Function
When reset
FF16
Values that can be set RW
Timer mode
Underflow of Prescaler Z is counted
0016 to FF16
RW
Programmable waveform generation mode
Underflow of Prescaler Z is counted (Note 1)
0016 to FF16
RW
Programmable one-shot generation mode
Underflow of Prescaler Z is counted
(One-shot width is counted)
0016 to FF16
RW
Programmable wait one-shot generation mode
Underflow of Prescaler Z is counted
(Wait period is counted)
0016 to FF16
RW
Note 1: Each value of Timer Z Primary and Timer Z Secondary is reloaded to the Timer Z alternately for counting.
Figure 12.22 Timer Z-related registers (2)
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12. Timers
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
TYPUM1
TZPUM0
TZPUM1
Address
008416
Bit name
Timer Y primary
waveform extension
control bit
Timer Y secondary
waveform extension
control bit
Timer Z primary
waveform extension
control bit
Timer Z secondary
waveform extension
control bit
When reset
0016
Function
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 2)
RW
0 : No waveform extension
1 : Waveform extension (Note 2)
RW
TYOPL
Timer Y output level
latch
Function varies depending on the operation mode
TZOPL
Timer Z output level
latch
Function varies depending on the operation mode
INOSTG
INT0 pin one-shot
trigger control bit
(Timer Z)
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid (Note 3)
INOSEG
RW
0 : Edge trigger at falling edge
INT0 pin one-shot
trigger polarity select bit 1 : Edge trigger at rising edge
(Note 4)
(Timer Z)
RW
RW
RW
RW
Note 1: When setting this bit to "1", the prescaler Y register must be set to "0016".
Note 2: When setting this bit to "1", the prescaler Z register must be set to "0016".
Note 3: When setting this bit to "1", this bit must be set to "1" after setting the INT0 input enable bit (bit 0 at address 009616), the
INT0 input polarity select bit (bit 1 at address 009616), the INT0 input filter select bits (bits 0 and 1 at address 001E16)
and the INT0 pin one-shot trigger polarity select bit.
Note 4: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge).
Timer count source setting register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
TCSS
Bit symbol
TXCK0
Bit name
Timer X count source
select bit (Note 1)
TXCK1
TYCK0
Timer Y count source
select bit (Note 1, 2)
TYCK1
TZCK0
Note
Note
Note
Note
Function
RW
b1 b0
0
0
1
1
0
1
0
1
:
:
:
:
f1
f8
f32
fC32
RW
:
:
:
:
f1
f8
On-chip oscillator output (Note 3)
fC32
RW
RW
b3 b2
0
0
1
1
0
1
0
1
Timer Z count source
select bit (Note 1, 4)
b5 b4
Timer 1 count source
select bit
b7 b6
TZCK1
T1CK0
When reset
0016
Address
008E16
0
0
1
1
0
1
0
1
: f1
: f8
: Timer Y underflow
: fC32
RW
RW
RW
0 0 : f1
RW
0 1 : f8
1 0 : f32
T1CK1
RW
1 1 : fC32
1: Avoid switching a count source, while a counter is in progress. Timer counter should be stopped before switching a
counter source.
2: The waveform extend function cannot be used when selecting f1 for count source.
3: When attempting to select on-chip oscillator output, set the on-chip oscillation enable bit (CM14) of the system clock
control register (address 000716) for oscillation enabled.
4: The waveform extend function cannot be used when selecting Timer Y underflow and f1 for count source.
Both the Timer Y primary underflow and the Timer Y secondary underflow are counted when selecting the Timer Y
underflow for count source.
Figure 12.23 Timer Z-related registers (3)
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12. Timers
Timer Y, Z output control register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
TYZOC
Bit symbol
When reset
XXXXX0002
Address
008A16
Bit name
Function
RW
TZOS
Timer Z one-shot
start bit (Note 1)
0 : Stops one-shot
1 : Starts one-shot
RW
TYOCNT
Timer Y programmable
waveform generation
output switching bit (Note 2)
0 : Outputs programmable waveform
1 : Outputs the value of P32 port register
RW
Timer Z programmable
waveform generation
output switching bit (Note 2)
0 : Outputs programmable waveform
1 : Outputs the value of P31 port register
RW
TZOCNT
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: This bit is automatically cleared to "0" when the output of one-shot waveform is completed. This bit should be set to
"0" by program when the one-shot waveform output is terminated by setting the count start flag to "0" during the
waveform output.
Note 2: This bit is valid only when operating in programmable waveform generation mode.
External input enable register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
INTEN
Bit symbol
When reset
0016
Address
009616
Bit name
Function
RW
INT0EN
INT0 input enable bit (Note 1)
0 : Disabled
1 : Enabled
RW
INT0PL
INT0 input polarity select bit
(Note 1)
0 : One edge
1 : Two edges
RW
INT1EN
INT1 input enable bit
0 : Disabled
1 : Enabled
RW
INT1PL
INT1 input polarity select bit
0 : One edge
1 : Two edges
RW
INT2EN
INT2 input enable bit
0 : Disabled
1 : Enabled
RW
INT2PL
INT2 input polarity select bit
0 : One edge
1 : Two edges
RW
INT3EN
INT3 input enable bit
0 : Disabled
1 : Enabled
RW
INT3PL
INT3 input polarity select bit
0 : One edge
1 : Two edges
RW
Note 1: This bit must be set in condition of the INT0 pin one-shot trigger control bit (bit 6 at address 008416)="0"
(INT0 pin one-shot trigger invalid).
INT0 input filter select register
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
INT0F
Bit symbol
Address
001E16
When reset
XXXXX0002
Bit name
Function
RW
b1 b0
INT0F0
INT0 input filter select bit
INT0F1
INT0F2
UART0 receive hardware
interrupt enable bit (Note 1)
0
0
1
1
0
1
0
1
:
:
:
:
No filter
Filter with f1 sampling
Filter with f8 sampling
Filter with f32 sampling
0 : Disabled
1 : Enabled
Nothing is assigned.
When write, nothing can be written. When read, their contents are indeterminate.
Note 1: Interrupts used for debugging purposes only. Be sure to set "0" to this bit.
Figure 12.24 Timer Z-related registers (4)
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RW
RW
RW
M16C/1N Group
12. Timers
12.4.1 Timer Mode
In this mode, the timer counts an internally generated count source or Timer Y underflow. (See Table
12.10) The Timer Z secondary is unused in this mode. Figure 12.25 shows the Timer Y, Z mode
register and Timer Y, Z waveform output control register in timer mode.
Table 12.10 Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, Timer Y underflow, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting (When the Timer Z underflows, the contents of the Timer Z primary reload
register is reloaded.)
• When a counting stops, the timer reloads the content of the reload register before
stopping counting.
1
(n+1) X (m+1)
Divide ratio
n: Set value of Prescaler Z, m: Set value of Timer Z primary
Count start condition
Count stop condition
Count start flag is set (=1)
Count start flag is reset (=0) (Note 1)
Interrupt request generation timing
TYOUT pin function
INT0 pin function
Read from timer
When Timer Z underflows
Programmable I/O port
Programmable I/O port, or external interrupt input pin
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register.
When a value is written to Timer Z Primary register, it is written to both reload register
and counter or written to only reload register. Selected by software.
Same applies to Prescaler Z register.
• Timer Z write control function (Note 2)
When a value is written to Timer Z Primary register, it can be selected that the value is
written to both reload register and counter or written to only reload register.
Same applies to Prescaler Z register.
Write to timer
Select function
Note 1: When the count is stopped, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0"
before starting counting again.
Note 2: If writing to the Timer Z or prescaler Z under the following conditions being filled at the same time the Timer Z
interrupt request bit becomes "1" and an interrupt occurs.
<Conditions>
• Timer Z write control bit (bit 6 at address 008016) is "0" (write to timer and reload register simultaneously)
• Timer Z count start flag (bit 7 at address 008016) is "1" (count start)
To write to the Timer Z or prescaler Z in the above state, disable interrupts before writing.
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M16C/1N Group
12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
0 0
Bit symbol
TYMOD0
Address
008016
When reset
000000X02
Bit name
Function
Timer Y-related bit
RW
RW
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
RW
RW
TYS
b5 b4
TZMOD0
Timer Z operation
mode bit
0 0 : Timer mode
RW
RW
TZMOD1
TZWC
TZS
Timer Z write
control bit
0 : Write to timer and reload register
simultaneously (Note 1)
1 : Write to reload register
RW
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
Note 1: At this bit is "0", when you write in the prescaler Z while the timer Z is counting, the timer Z reloads content of the
timer Z reload register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
Function
RW
Timer Y-related bits
RW
TYPUM1
TZPUM0
TZPUM1
RW
Timer Z primary
waveform extension
control bit
Invalid in timer mode
Timer Z secondary
waveform extension
control bit
Invalid in timer mode
RW
RW
RW
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
Invalid in timer mode
INOSTG
INT0 pin one-shot
trigger control bit
Invalid in timer mode
INOSEG
Invalid in timer mode
INT0 pin one-shot
trigger polarity select bit
RW
RW
RW
Figure 12.25 Timer Y, Z mode register and Timer Y, Z waveform output control register in timer
mode
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M16C/1N Group
12. Timers
12.4.2 Programmable Waveform Generation Mode
In this mode, the microcontroller, while counting the set values of Timer Z primary and Timer Z secondary alternately, outputs from the TZOUT pin a waveform whose polarity is inverted each time Timer
Z secondary underflows. (See Table 12.11) A counting starts by counting the value set in the Timer Z
primary. Figure 12.26 shows Timer Y, Z mode register and Timer Y, Z waveform output control register in this mode. The Timer Z operates in the same way as the Timer Y in this mode. See Figure 12.19
shown the Timer Y operating example in programmable waveform generation mode.
Table 12.11 Specifications of programmable waveform generating mode
Item
Specification
Count source
Count operation
f1, f8, Timer Y underflow, fC32
• Down count
• When the timer underflows, it reloads the contents of primary reload register and secondary reload register alternately before continuing counting.
• When a counting stops, the timer reloads the content of the reload register before it
stops.
fi
(n+1) X ((m+1)+(l+1))
Divide ratio
n: Set value of Prescaler Z, m: Set value of Timer Z primary, l: Set value of Timer Z secondary
Count start flag is set (=1)
Count start flag is reset (=0) (Note 1)
When Timer Z underflows during secondary period
Pulse output (Note 2)
Programmable I/O port, or external interrupt input pin
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register. (Note 3)
Write to timer
When a value is written to Timer Z primary register, it is written to only reload register.
Same applies to Timer Z secondary register and Prescaler Z register. (Note 4)
Select function
• Output level latch select function
The output level of an waveform being counted during primary and secondary periods
is selectable.
• Programmable waveform generation output switching function (Note 5)
Can select either programmable waveform or the value of port P31 register for output.
• Waveform extend function (Note 6)
The waveform output primary and secondary periods can each be extended 0.5 cycles
of the count source.
Frequency when waveform extended: 2xfi/((2x(m+1))+(2x(l+1))+TZPUM0+TZPUM1)
Duty: (2x(m+1)+TZPUM0)/((2x(m+1)+TZPUM0)+(2x(l+1)+TZPUM1))
m: set value of Timer Z primary, l: set value of Timer Z secondary
TZPUM0: Timer Z primary waveform extension control bit
TZPUM1: Timer Z secondary waveform extension control bit
Note 1: When the count is stopped, the Timer Z interrupt request bit becomes "1" and an interrupt may occur. Thus,
interrupts must be disabled before the count is stopped. Furthermore, set the Timer Z interrupt request bit to "0"
before starting counting again.
Note 2: When the counting stopped, the pin is the secondary period output level.
Note 3: Even when counting the secondary period, read out the Timer Z primary register.
Note 4: The set value of Timer Z secondary register and waveform extension control bits as well as Timer Z primary
register are made effective by writing a value to the Timer Z primary register. The written values are reflected to
the waveform output from the next primary period after writing to the Timer Z primary register.
Note 5: The output is switched in sync with Timer Z secondary underflow.
Note 6: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
Count start condition
Count stop condition
Interrupt request generation timing
TZOUT pin function
INT0 pin function
Read from timer
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M16C/1N Group
12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
1 0 1
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
RW
RW
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
RW
Timer Y-related bits
RW
TYS
b5 b4
TZMOD0
Timer Z operation
mode bit
0 1 : Programmable waveform generation mode
(Note 1)
TZMOD1
RW
RW
TZWC
Timer Z write
control bit
1 : Set to "1" in programmable waveform
generation mode
RW
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
Note 1: When selecting programmable waveform generation mode, output is set for Port P31 regardless of the value of the
direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
When reset
0016
Bit name
Function
Timer Y-related bits
RW
TYPUM1
TZPUM0
TZPUM1
RW
Timer Z primary
waveform extension
control bit
Timer Z secondary
waveform extension
control bit
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
RW
0 : Outputs "H" for the period set by Timer Z primary and
"L" for the period set by Timer Z secondary.
"L" is outputted when the timer is stopped.
1 : Outputs "L" for the period set by Timer Z primary and
"H" for the period set by Timer Z secondary.
"H" is outputted when the timer is stopped.
RW
INOSTG
INT0 pin one-shot
trigger control bit
Invalid in programmable waveform generation
mode
RW
INOSEG
INT0 pin one-shot
trigger polarity select bit
Invalid in programmable waveform generation
mode
RW
Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Figure 12.26 Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable waveform generation mode
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M16C/1N Group
12. Timers
12.4.3 Programmable One-shot Generation Mode
In this mode, upon software command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin. (See Table 12.12) When a trigger occurs, the
timer starts operating from the point only once for a given period equal to the set value of the Timer Z
primary. Timer Z secondary is unused in this mode.
Table 12.12 lists specifications of programmable one-shot generating mode. Figure 12.27 shows the
Timer Y, Z mode register and Timer Y, Z waveform output control register in this mode. Figure 12.28
shows the Timer Z operation example in this mode.
Table 12.12 Specifications of programmable one-shot generating mode
Item
Count source
Count operation
Specification
f1, f8, Timer Y underflow, fC32
• Down counts the set value of Timer Z primary
• When the timer underflows, it reloads the contents of reload register before stopping
counting.
• When a counting stops, the timer reloads the contents of the reload register before it
stops.
1
Divide ratio
(n+1) X (m+1)
n: Set value of Prescaler Z, m: Set value of Timer Z primary
Count start condition
• Timer Z one-shot start bit is set (=1) (Note 1)
• Valid trigger is input to INT0 pin (Note 2)
Count stop condition
• When reloading is completed after count value was set to "0016"
• When Count start flag is reset (=0)
• Timer Z one-shot start bit is reset (=0) (Note 3)
Interrupt request generation timing When count value becomes "0016"
TZOUT pin function
Pulse output
INT0 pin function
Programmable I/O port, external interrupt input pin, or external trigger input pin
Read from timer
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register.
Write to timer
When a value is written to Timer Z primary register, it is written to only reload register.
Same applies to Prescaler Z register. (Note 4)
Select function
• Output level latch select function
The output level of one-shot pulse waveform is selectable.
• INT0 pin one-shot trigger control function and polarity select function
The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's
polarity can be chosen to be the rising edge, falling edge, or rising and falling both
edges.
• Waveform extend function (Note 5)
The one-shot pulse waveform can be extended 0.5 cycles of the count source.
Frequency when waveform extended: 2xfi/(n+1)/(2x(m+1)+TZPUM0)
n: set value of Prescaler Z, m: set value of Timer Z primary
TZPUM0: Timer Z primary waveform extension control bit
Note 1: Count start flag must have been set to "1". _______
_______
Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 pin one-shot trigger
control bit to "1".
Note 3: When the count is stopped by writing "0" to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt
request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is
stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again.
Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected
collectively beginning with the next one-shot pulse after writing to the Timer Z primary.
Note 5: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
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M16C/1N Group
12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
1 1 0
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
RW
RW
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
RW
TYS
RW
b5 b4
TZMOD0
Timer Z operation
mode bit
1 0 : Programmable one-shot generation mode
(Note 1)
TZMOD1
TZWC
TZS
RW
RW
Timer Z write
control bit
1 : Set to "1" in programmable one-shot
generation mode
RW
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
Note 1: When selecting programmable one-shot generation mode, output is set for Port P31 regardless of the value of the
direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
Function
Timer Y-related bits
RW
TYPUM1
TZPUM0
TZPUM1
RW
RW
Timer Z primary
waveform extension
control bit
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
Invalid in programmable one-shot generation
mode
RW
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
0 : Outputs "H" level one-shot pulse.
"L" is outputted when the timer is stopped.
1 : Outputs "L" level one-shot pulse
"H" is outputted when the timer is stopped.
RW
INT0 pin one-shot
trigger control bit
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid (Note 2)
RW
INOSTG
RW
INOSEG
INT0 pin one-shot
0 : Edge trigger at falling edge
RW
1 : Edge trigger at rising edge
trigger polarity select
bit (Note 3)
Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 2: When changing this bit to "1", set the INT0 input filter select bit (bit 0 at address 009616), the INT0 input polarity select bit (
bit 1 at address 009616), the INT0 input filter select bit (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger
polarity select bit.
Note 3: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge).
Figure 12.27 Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable one-shot generation mode
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M16C/1N Group
12. Timers
Conditions: Timer Z primary=0316, Timer Z primary waveform extended,
Timer Z output level latch [TZOPL]=0,
INT0 one-shot trigger is valid at rising edge,
INT0 input filter select bit [INT0F0, INT0F1]=002 (No filter)
fPZ
Set to "1" by
software
Count start flag "1"
"0"
Set to "1" by
software
Cleared to "0"
when counting
completed
Set to "1" by
INT0 pin input
trigger
One-shot "1"
start bit
"0"
INT0 pin "1"
input "0"
Timer Z Count
primary start
reload
Count
start
The contents of
Timer Z
0316
0216 0116 0016
0316
Timer Z
primary
reload
0216 0116 0016
Cleared to "0" when interrupt
request is accepted,
or cleared by software
Timer Z interrupt "1"
request bit "0"
Timer Z output "1"
level latch "0"
Cleared to "0"
by software
Waveform
output starts
Waveform Waveform
output ends output starts
Waveform
output ends
"H"
TZOUT pin output
"L"
Initialized to "L"
Primary waveform
extended
Figure 12.28 Operation example in programmable one-shot generation mode
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Primary waveform
extended
M16C/1N Group
12. Timers
12.4.4 Programmable Wait One-shot Generation Mode
In this mode, upon software command or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZOUT pin after waiting for a given length of time. (See Table
12.13) When a trigger occurs, from this point, the timer starts outputting pulses only once for a given
length of time equal to the Timer Z primary set value after waiting for a given length of time equal to the
Timer Z primary set value. Figure 16.29 shows the Timer Y, Z mode register and Timer Y, Z waveform
output control register in this mode. Figure 12.30 shows the Timer Z operation example in this mode.
Table 12.13 Specifications of programmable wait one-shot generating mode
Item
Specification
Count source
Count operation
Wait time
f1, f8, Timer Y underflow, fC32
• Down counts the set value of Timer Z primary
• When Timer Z primary underflows, the contents of Timer Z secondary is reloaded before continuing counting.
• When Timer Z secondary underflows, the contents of Timer Z primary is reloaded before stopping counting.
• When a counting stops, the timer reloads the contents of the reload register before it stops.
(n+1) x (m+1)/fi, n: Set value of Prescaler Z, m: Set value of Timer Z primary
One-shot pulse output time (n+1) x (l+1))/fi, n: Set value of Prescaler Z, l: Set value of Timer Z secondary
Count start condition
• Timer Z one-shot start bit is set (=1) (Note 1)
• Valid trigger is input to INT0 pin (Note 2)
Count stop condition
• When reloading is completed after count value at counting Timer Z secondary was set to "0016"
• When Count start flag is reset (=0)
• Timer Z one-shot start bit is reset (=0) (Note 3)
Interrupt request generation timing When count value at counting Timer Z secondary becomes "0016"
TZOUT pin function
Pulse output
INT0 pin function
Programmable I/O port, external interrupt input pin, or external trigger input pin
Read from timer
Count value can be read out by reading Timer Z primary register.
Same applies to Prescaler Z register.
Write to timer
When a value is written to Timer Z primary register, it is written to only reload register.
Same applies to Prescaler Z register. (Note 4)
Select function
• Output level latch select function
The output level of one-shot pulse waveform is selectable.
• INT0 pin one-shot trigger control function and polarity select function
The trigger input from the INT0 pin can be set to valid or invalid. Also, the valid trigger's
polarity is selectable: rising edge, falling edge, or rising and falling both edges.
• Waveform extend function (Note 5)
Waiting time and one-shot pulse waveform can each be extended 0.5 cycles of the
count source.
Waiting time when waveform extended: (n+1) x (2x(m+1)+TZPUM0)/2fi
One-shot pulse output time when waveform extended: (n+1) x (2x(l+1)+TZPUM1)/2fi
n: set value of Prescaler Z, m: set value of Timer Z primary, l: set value of Timer Z secondary
TZPUM0: Timer Z primary waveform extension control bit, TZPUM1: Timer Z secondary waveform extension control bit
Note 1: Count start flag must have been set to "1". _______
_______
Note 2: Count start flag must have been set to "1", INT0 input enable bit [INT0EN] to "1", and INT0 pin one-shot trigger
control bit to "1".
Note 3: When the count is stopped by writing "0" to the count start flag or Timer Z one-shot start bit, the Timer Z interrupt
request bit becomes "1" and an interrupt may occur. Thus, interrupts must be disabled before the count is
stopped. Furthermore, set the Timer Z interrupt request bit to "0" before starting counting again.
Note 4: Each set value becomes effective by writing to the Timer Z primary register. And the set values are reflected
collectively beginning with the next one-shot pulse after writing to the Timer Z primary.
Note 5: When using the waveform extend function, the Prescaler Z register must be set to "0016".
When selecting Timer Y underflow and f1 for the count source, the waveform extend function cannot be used.
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M16C/1N Group
12. Timers
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
1 1 1
Address
008016
Bit symbol
Bit name
TYMOD0
Timer Y-related bit
When reset
000000X02
Function
RW
RW
Nothing is assigned.
When write, set "0". When read, the content is "0".
TYWC
Timer Y-related bits
RW
TYS
RW
b5 b4
TZMOD0
Timer Z operation
mode bit
1 1 : Programmable wait one-shot generation
mode
(Note 1)
TZMOD1
RW
RW
TZWC
Timer Z write
control bit
1 : Set to "1" in programmable wait one-shot
generation mode
RW
TZS
Timer Z count
start flag
0 : Stops counting (Note 2)
1 : Starts counting
RW
Note 1: When selecting programmable wait one-shot generation mode, output is set for Port P31 regardless of the value of
the direction register.
Note 2: When this bit is cleared to "0", the timer reloads the content of the reload register before it stops. Read out the
count value before you stop the timer.
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Bit symbol
TYPUM0
Address
008416
Bit name
When reset
0016
Function
Timer Y-related bits
RW
TYPUM1
TZPUM0
TZPUM1
RW
RW
Timer Z primary
waveform extension
control bit
Timer Z secondary
waveform extension
control bit
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
0 : No waveform extension
1 : Waveform extension (Note 1)
RW
TYOPL
Timer Y-related bit
TZOPL
Timer Z output level
latch
0 : Outputs "H" level one-shot pulse.
"L" is outputted when the timer is stopped.
1 : Outputs "L" level one-shot pulse.
"H" is outputted when the timer is stopped.
RW
INOSTG
INT0 pin one-shot
trigger control bit
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid (Note 2)
RW
INOSEG
INT0 pin one-shot
0 : Edge trigger at falling edge
trigger polarity select bit 1 : Edge trigger at rising edge
(Note 3)
RW
RW
Note 1: When setting this bit to "1", the Prescaler Z Register must be set to "0016".
Note 2: When changing this bit to "1", set the INT0 input filter select bit (bit 0 at address 009616), the INT0 input polarity select bit
(bit 1 at address 009616), the INT0 input filter select bit (bits 0 and 1 at address 001E16) and the INT0 pin one-shot trigger
polarity select bit.
Note 3: This bit is valid only when the INT0 input polarity select bit (bit 1 at address 009616) is "0" (one-edge).
Figure 12.29 Timer Y, Z mode register and Timer Y, Z waveform output control register in
programmable wait one-shot generation mode
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M16C/1N Group
12. Timers
Conditions: Timer Z primary=0316, Timer Z primary waveform not extended,
Timer Z primary=0416, Timer Z secondary waveform not extended,
Timer Z output level latch [TZOPL]=0,
INT0 one-shot trigger is valid at rising edge
fPZ
Set to "1" by
software
Count start flag
"1"
"0"
Set to "1" by software, or set
to "1" by INT0 pin input
trigger
Cleared to "0"
when counting
completed
One-shot "1"
start bit "0"
INT0 pin "1"
input "0"
Count
start
The contents of
Timer Z
0316
Timer Z secondary
reload
0216 0116 0016
0416
Timer Z primary
reload
0316 0216 0116 0016
0316
Cleared to "0" when interrupt
request is accepted,
or cleared by software
Timer Z interrupt "1"
request bit "0"
Timer Z output "1"
level latch
"0"
Cleared to "0"
by software
Wait starts
Waveform
output starts
Waveform
output ends (Note 1)
"H"
TZOUT pin output
"L"
Initialized to "L"
Note 1: The waveform output of one-shot pulse is completed after 0.5 clock (1 clock when
primary waveform extended) of fPZ from occurrence of Timer Z interrupt request.
Figure 12.30 Operation example in programmable wait one-shot generation mode
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M16C/1N Group
12. Timers
12.5 Timer C
Timer C is a 16-bit free-running timer. The Timer C uses an edge input to TCIN pin or the output of 256
fRING divisions as trigger to latch the timer count value and generates an interrupt request. The TCIN
input has a digital filter and this prevents an error caused by noise or so on from occurring.
Figure 12.31 shows the block diagram of Timer C. Table 12.14 shows Timer C specifications. Figure
12.32 shows Timer C-related registers. Figure 12.33 shows an operation example of Timer C and timer
measurement register.
Data bus
Address 009C16
Address 009D16
Lower 8 bits
Upper 8 bits
Time measurement register (16)
Timer C clock
select bit
f1
f8
Upper 8 bits
Lower 8 bits
Timer C counter (16)
Address 009116
Address 009016
f32
Digital
filter
TCIN
f1
f8
f32
Digital filter clock
select bit
On-chip oscillation
"0"
Timer C overflow interrupt
Reload signal
TCIN interrupt
Edge detection
"1"
Time measurement
input source
switching bit
1/256
Figure 12.31 Block diagram of Timer C
Table 12.14 Specifications of Timer C
Item
Count source
Count operation
Specification
f1, f8, f32
• Up count
• Transfer counter value to time measurement register at active edge of
measurement pulse
• When timer C stops counting, the value of timer C is reset to "000016".
Count start condition
• Time measurement control bit is set (=1)
Counter stop condition
• Time measurement control bit is reset (=0)
Interrupt request generation timing • When active edge of measurement pulse is input [TCIN interrupt]
• When the time underflows [Timer C interrput]
TCIN pin function
Measurement pulse input
Count value reset timing
When time measurement control bit is reset (=0)
Read from timer (Note 1)
• Count value can be read out by reading Timer C.
• Count value at measurement pulse active edge input can be read out by reading time
measurement register.
Write to timer
Cannot write to Timer C and time measurement register
Select function
• Measurement pulse active edge: selectable (rising edge/falling edge/both edges)
• Measurement pulse: selectable (input from TCIN pin/256 divisions of fRING)
• Digital filter sampling frequency: selectable (f1/f8/f32)
Note 1: The Timer C and the timer measurement register must be read in word-size.
Rev.1.00 Oct 20, 2004
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M16C/1N Group
12. Timers
Timer C
(b15)
b7
(b8)
b0 b7
b0
Symbol
TC
Address
009116, 009016
When reset
Indeterminate
Function
RW
RO
Internal count source is counted
Time measurement register
(b15)
b7
(b8)
b0 b7
b0
Symbol
TM
Address
009C16, 009D16
When reset
Indeterminate
Function
RW
When active edge of measurement pulse is input, the count value of Timer C
is stored (Note 1)
RO
Note 1: When time measurement is disabled, the value is indeterminate. After enabling time measurement, the
value is indeterminate until the first trigger is generated.
Timer C control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC0
Bit symbol
Address
009A16
When reset
0XX000002
Bit name
TCC00
Time measurement control bit
TCC01
Timer C clock select bit
(Note 1)
Function
0 : Time measurement disabled
1 : Time measurement enabled
RW
RW
b2 b1
TCC02
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
RW
RW
b4 b3
TCC03
Time measurement input edge
trigger bit
(Note 1)
TCC04
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Inhibited
RW
RW
Nothing is assigned.
When write, set "0". When read, their contents are "0".
TCC07
Time measurement input
0 : TCIN
source switching bit
1 : fRING256
RW
(Note 1 to 3)
Note 1: Change this bit when time measurement is disabled.
Note 2: Set the on-chip oscillation stop bit (CM14) to "0" before setting this bit to "1".
Note 3: Change this bit when the interrupt is disabled. When switching the timer measurement input source, the TCIN
interrupt may be requested. Therefore, enable the interrupt after setting the interrupt request bit to "0".
Timer C control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCC1
Bit symbol
Address
009B16
When reset
XXXXXX112
Bit name
Function
b1 b0
TCC10
TCC11
Digital filter clock select bit
(Note 1)
0 0 : Inhibited
0 1 : f1
1 0 : f8
1 1 : f32
Nothing is assigned.
When write, set "0". When read, their contents are "0".
Note 1: Input edge becomes active when the same value from TCIN pin is sampled three times in succession.
Figure 12.32 Timer C-related register
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 106 of 222
RW
RW
RW
M16C/1N Group
12. Timers
Conditions: Time measurement input edge trigger is set for falling edge (TCC03="1", TCC04="0")
Overflow
Counter contents (hex)
FFFF16
Count start
Measurement value 2
Measurement
value 3
Measurement value 1
000016
Time
Cleared to "0"
by software
Set to "1" by software
Time measurement "1"
control bit "0"
The delay caused
by digital filter
Measurement pulse "H"
(TCIN pin input) "L"
Transmit
Transmit
(Measurement (Measurement
value 1)
value 2)
Transmit
(Measurement
value 3)
Transmit timing from
Timer C counter to
time measurement register
Indeterminate
Indeterminate
Time measurement register
Measurement value 2
Measurement
value 1
Measurement
value 3
Cleared to "0" when interrupt request is accepted, or cleared by software
TCIN interrupt "1"
request bit "0"
Cleared to "0" when interrupt
request is accepted, or
cleared by software
Timer C interrupt "1"
request bit "0"
Figure 12.33 Operation example of Timer C and time measurement register
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M16C/1N Group
13. Serial I/O
13. Serial I/O
Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive
timer to generate a transfer clock, so they operate independently of each other.
Figure 13.1 shows the block diagram of UARTi (i=0,1). Figure 13.2 shows the block diagram of the transmit/
receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 00A016 and
00A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART. Although a few
functions are different, UART0 and UART1 have almost the same functions.
Figures 13.3 through 13.5 show the registers related to UARTi.
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection
Bit rate generator Clock synchronous type
f1
f8
Reception
control circuit
Receive
clock
Internal (Address 00A116)
f32
fc
1 / (n0+1)
1/16
UART transmission
Clock synchronous type
External
Transmission
control circuit
Transmit
clock
Transmit/
receive
unit
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
CLK
polarity
reversing
circuit
CLK0
(UART1)
RxD1
TxD1
UART reception
1/16
Clock source selection
Bit rate generator Clock synchronous type
f1
f8
Reception
control circuit
Receive
clock
Internal (Address 00A916)
1 / (n1+1)
f32
fc
External
1/16
UART transmission
Clock synchronous type
Transmission
control circuit
Transmit
clock
Transmit/
receive
unit
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
CLK1
CLK
polarity
reversing
circuit
CLKS1
n0: Values set to UART0 bit rate generator (BRG0)
n1: Values set to UART1 bit rate generator (BRG1)
Clock output pin
select switch
Figure 13.1 Block diagram of UARTi (i= 0, 1)
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REJ09B0007-0100Z
Clock synchronous type
(when external clock is selected)
page 108 of 222
M16C/1N Group
13. Serial I/O
Clock
synchronous
type
Clock
synchronous
PAR
type
disabled
1SP
RxDi
SP
SP
UART (7 bits)
UART (8 bits)
UARTi receive register
UART (7 bits)
PAR
UART
PAR
enabled
2SP
UART (9 bits) Clock
synchronous
type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
D1
D0
UARTi transmit
buffer register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
UART (8 bits)
UART (9 bits)
UART (9 bits)
PAR
enabled
2SP
SP
SP
UART
TxDi
PAR
1SP
Clock
PAR
disabled synchronous
type
"0"
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
Figure 13.2 Block diagram of transmit/receive unit
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
Clock
synchronous
type
page 109 of 222
UART (7 bits)
UARTi transmit register
SP: Stop bit
PAR: Parity bit
M16C/1N Group
13. Serial I/O
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
Address
00A316, 00A216
00AB16, 00AA16
When reset
Indeterminate
Indeterminate
Function
RW
WO
Transmit data (Note 1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note 1: When transfer data length is 9-bit long, write high-byte first then low-byte with byte-size.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0RB
U1RB
Bit
symbol
Bit name
Address
00A716, 00A616
00AF16, 00AE16
When reset
Indeterminate
Indeterminate
Function
(During clock synchronous serial I/O mode)
Receive data
Function
(During UART mode)
Receive data
RW
RO
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
OER
Overrun error flag
(Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
RO
FER
Framing error flag
(Note 1)
Invalid
0 : No framing error
1 : Framing error found
RO
PER
Parity error flag
(Note 1)
Invalid
0 : No parity error
1 : Parity error found
RO
SUM
Error sum flag
(Note 1)
Invalid
0 : No error
1 : Error found
RO
Note 1: Bits 15 to 12 are set to "0" when the serial I/O mode select bits (bit 2 to 0 at addresses 00A016 and 00A816) are set to "0002" or
receive enable bit to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower
byte of the UARTi receive buffer register (addresses 00A616, and 00AE16) is read out or when this register is read out in word-size.
When reading data from the UARTi receive buffer, data should be read high-byte first then low-byte using byte-size.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
00A116
00A916
Function
Assuming that set value = n, BRGi divides the
count source by n + 1
Figure 13.3 Serial I/O-related registers (1)
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 110 of 222
When reset
Indeterminate
Indeterminate
Values that can be set
RW
0016 to FF16
WO
M16C/1N Group
13. Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
0
Bit
symbol
Address
00A016, 00A816
When reset
0016
Function
(During clock synchronous serial I/O mode)
Bit name
Must be fixed to 001
SMD0 Serial I/O mode select bit
RW
b2 b1 b0
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
Function
(During UART mode)
SMD2
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
RW
RW
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
0 : Internal clock
1 : External clock
RW
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
RW
PRY
Odd/even parity select bit Invalid
Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity
RW
0 : Parity disabled
1 : Parity enabled
RW
PRYE
Parity enable bit
Invalid
Reserved bit
RW
Set to "0"
Note 1: Set the corresponding port direction register to "0".
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
0
Bit
symbol
Address
00A416, 00AC16
Bit name
Function
(During UART mode)
Function
(During clock synchronous serial I/O mode)
RW
b1 b0
b1 b0
CLK1
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
Reserved bit
Set to "0"
RW
TXEPT Transmit register empty
flag
0 : Data present in transmit
0 : Data present in transmit register
register (during transmission)
(during transmission)
1 : No data present in transmit 1 : No data present in transmit
register (transmission
register (transmission completed)
completed)
RO
Nothing is assigned
In an attempt to write to this bit, write "0".
The value, if read, turn out to be "0".
CLK0
NCH
BRG count source
select bit
Data output select bit
CKPOL CLK polarity select bit
Figure 13.4 Serial I/O-related registers (2)
page 111 of 222
RW
RW
0 : TXDi pin is CMOS output 0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
1 : TXDi pin is N-channel openopen-drain output
drain output
RW
Set to "0"
0 : Transmit data is output
at falling edge of transfer
clock and receive data is
input at rising edge
1 : Transmit data is output
at rising edge of transfer
clock and receive data is
input at falling edge
RW
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
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When reset
0816
Set to "0"
RW
M16C/1N Group
13. Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Bit
symbol
Address
00A516, 00AD16
When reset
XXXX00102
Function
(During clock synchronous serial I/O mode)
Bit name
Function
(During UART mode)
RW
0 : Transmission disabled
1 : Transmission enabled
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in transmit 0 : Data present in transmit
buffer register
buffer register
1 : No data present in
1 : No data present in
transmit buffer register
transmit buffer register
RO
RE
Receive enable bit
(Note 1)
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in receive
buffer register
0 : No data present in
receive buffer register
1 : Data present in receive
buffer register
RO
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: As for the UART1, set the RXD1 input port select bit before setting this bit to reception enabled.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Bit
symbol
U0IRS
U1IRS
U0RRM
U1RRM
Address
00B016
Bit name
When reset
0016
Function
(During clock synchronous serial I/O mode)
Function
(During UART mode)
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty
0 : Transmit buffer empty
(Tl = 1)
(Tl = 1)
1 : Transmission completed 1 : Transmission completed
(TXEPT = 1)
(TXEPT = 1)
RW
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty
0 : Transmit buffer empty
(Tl = 1)
(Tl = 1)
1 : Transmission completed 1 : Transmission completed
(TXEPT = 1)
(TXEPT = 1)
RW
UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
RW
UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
Valid when bit 5 = "1"
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD0 CLK/CLKS select bit 0
RW
RW
CLKMD1 CLK/CLKS select
bit 1 (Note 1)
0 : Normal mode
Set to "0"
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
RW
RXD1EN RXD1 input port
select bit (Note 2)
0 : P37
1 : P35
RW
0 : P37
1 : P35
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: When using multiple pins to output the transfer clock, the following requirements must be met:
UART1 internal/external clock select bit (bit 3 at address 00A816) = "0".
Note 2: For P37, select "0" for data receive, and "1" for data transfer.
And set the direction register of port P37 to input ("0") when receiving.
Figure 13.5 Serial I/O-related registers (3)
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RW
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M16C/1N Group
13. Serial I/O
13.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.
Table 13.1 lists specifications of clock synchronous sperial I/O mode. Figure 13.6 shows the UARTi
transmit/receive mode register.
Table 13.1 Specifications of clock synchronous serial I/O mode
Item
Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock
• When internal clock is selected (bit 3 at address 00A016,00A816 = "0"): fi/ 2(n+1) (Note 1)
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 00A016,00A816 = "1"): Input from CLKi pin
Transmission start
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = "1"
condition
_ Transmit buffer empty flag (bit 1 at addresses 00A516,00AD16) = "0"
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H"
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"
Reception start
• To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 00A516,00AD16) = "1"
conditio
_ Transmit enable bit (bit 0 at address 00A516,00AD16) = "1"
_ Transmit buffer empty flag (bit 1 at address 00A516,00AD16) = "0"
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "0": CLKi input level = "H"
_ CLKi polarity select bit (bit 6 at address 00A416,00AC16) = "1": CLKi input level = "L"
Interrupt request
• When transmitting
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = "0": Intergeneration timing
rupts requested when data transfer from UARTi transfer buffer register to UARTi
transmit register is completed
_ Transmit interrupt cause select bit (bit 0 and bit 1 at address 00B016) = "1": Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
Error detection
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading
UARTi receive buffer register and received the 7th bit of the next data
Select function
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be chosen by software to be output from one of the two pins set
• RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Note 1: "n" denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi
receive interrupt request bit does not change.
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13. Serial I/O
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 1
Symbol
UiMR (i=0,1)
Bit symbol
SMD0
When reset
0016
Address
00A016, 00A816
Bit name
Function
Serial I/O mode select bit
SMD1
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
SMD2
CKDIR
STPS
RW
RW
RW
RW
Internal/external clock
0 : Internal clock
select bit
1 : External clock (Note 1)
Invalid in clock synchronous serial I/O mode
RW
RW
PRY
RW
PRYE
RW
Reserved bit
RW
Set to "0"
Note 1: Set the corresponding port direction register to "0".
Figure 13.6 UARTi transmit/receive mode register in clock synchronous serial I/O mode
Table 13.2 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table
shows the pin functions when the transfer clock output from multiple pins is not selected. Note that for a
period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an
"H". (If the N-channel open-drain is selected, this pin is in floating state.)
Table 13.2 Input/output pin functions in clock synchronous serial I/O mode
Function
Serial data output
Serial data input
Pin name
Method of selection
Remarks
Port P14 cannot be used as an I/O port even when
performing only serial data input but not serial data output.
TxD0 (P14)
TxD1 (P37)
RxD1 input pin select bit
(bit 6 at address 00B016)="1"
Port P37 cannot be used as an I/O port even when
performing only serial data input but not serial data output.
RxD0 (P15)
Port P15 direction register
(bit 5 at address 00E316)="0"
Port P15 can be used as an I/O port when performing only
serial data output but not serial data input.
RxD1 (P35)
Port P35 direction register
(bit 5 at address 00E716)="0"
RxD1 input pin select bit
(bit 6 at address 00B016)="1"
Port P35 can be used as an I/O port when performing only
serial data output but not serial data input.
RxD1 (P37)
Port P37 direction register
(bit 7 at address 00E716)="0"
RxD1 input pin select bit
(bit 6 at address 00B016)="0"
When setting Port P37 as RxD1, serial data output cannot
be performed.
Port P35 can be used as an I/O port.
Transfer clock output CLKi (P16, P36) Internal/external clock select bit
(bit 3 at addresses 00A016 and
00A816)="0"
Transfer clock input CLKi (P16, P36) Internal/external clock select bit
(bit 3 at address 00A016 and
00A816)="1"
Ports P16 and P36 direction
register (bit 6 at address 00E316
and 00E716)="0"
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13. Serial I/O
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1"
Transmit enable
bit (TE)
"0"
Data is set in UARTi transmit buffer
register
"1"
Transmit buffer
empty flag (Tl)
"0"
Transferred from UARTi transmit buffer register to UARTi transmit
register
TCLK
Stopped pulsing because transfer enable bit = "0"
CLKi
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
TxDi
Transmit
register empty
flag (TXEPT)
D7
D0 D1 D2 D3 D4 D5 D6
D7
"1"
"0"
Transmit interrupt "1"
"0"
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = 0.
Transmit interrupt cause select bit = 0.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32, fc)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
"1"
"0"
"1"
"0"
Dummy data is set in UARTi transmit buffer register
"1"
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6
RxDi
Receive complete
flag (Rl)
"1"
Receive interrupt
request bit (IR)
"1"
Transferred from UARTi receive register
to UARTi receive buffer register
D7
D0 D1 D2 D3 D4 D5
Read out from UARTi receive buffer register
"0"
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = 0.
Meet the following conditions when the CLKi input level
before data reception = "H"
Transmit enable bit "1"
Receive enable bit "1"
Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 13.7 Typical transmit/receive timings in clock synchronous serial I/O mode
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13. Serial I/O
13.1.1 Polarity Select Function
As shown in Figure 13.8, the CLK polarity select bit (bit 6 at addresses 00A416 and 00AC16) allows
selection of the polarity of the transfer clock.
When CLK polarity select bit = "0"
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLKi pin level when not
transferring data is "H".
When CLK polarity select bit = "1"
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLKi pin level when not
transferring data is "L".
Figure 13.8 Polarity of transfer clock
13.1.2 LSB First/MSB First Select Function
As shown in Figure 13.9, when the transfer format select bit (bit 7 at addresses 00A416 and 00AC16)
= "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
When transfer format select bit = "0"
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
LSB first
When transfer format select bit = "1"
CLKi
TXDi
D7
D6
D5
D4
D3
MSB first
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note 1: This applies when the CLK polarity select bit = "0".
Figure 13.9 Transfer format
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13. Serial I/O
13.1.3 Transfer Clock Output from Multiple Pins Function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 00B016). The multiple pins
function is valid only when the internal clock is selected for UART1.
Figure 13.10 shows the transfer clock output from the multiple pins function usage.
Microcomputer
TXD1 (P37)
CLKS (P34)
CLK1 (P36)
IN
IN
CLK
CLK
Note 1: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 13.10 The transfer clock output from the multiple pins function usage
13.1.4 Continuous Receive Mode
If the continuous receive mode enable bit (bits 2 and 3 at address 00B016) is set to "1", the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
13.1.5 RxD1 Input Pin Selection Function (UART1)
This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by
using the RxD1 input pin select bit (bits 6 at address 00B016).
When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When selecting "0" (P37), serial data output cannot be performed. However, P35 can be used as an input/output
port.
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13. Serial I/O
13.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format.
Table 13.3 lists the specifications of UART mode. Figure 13.11 shows the UARTi transmit/receive mode register.
Table 13.3 Specifications of UART Mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start condition
Interrupt request generation timing
Error detection
Select function
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 00A016, 00A816 = "0"):
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
• When external clock is selected (bit 3 at addresses 00A016 = "1"):
fEXT/16(n+1) (Note 1) (Note 2)
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 00A516, 00AD16) = "1"
- Transmit buffer empty flag (bit 1 at addresses 00A516, 00AD16) = "0"
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 00A516, 00AD16) = "1"
- Start bit detection
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 00B016) = "0":
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 00B016) = "1":
Interrupts requested when data transmission from UARTi transfer register is
completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs if the serial I/O started receiving the next data before reading the UARTi receive buffer register and the bit one before the last stop bit
of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
• RxD1 input pin selection
UART1 RxD1 can be chosen by software to be input to one of the two pins set
Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi
receive interrupt request bit does not change.
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13. Serial I/O
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiMR (i=0,1)
Bit symbol
SMD0
Address
00A016, 00A816
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
STPS
PRY
Internal / external clock
select bit
Stop bit length select bit
Odd / even parity
select bit
PRYE
Parity enable bit
Reserved bit
When reset
0016
Function
RW
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
RW
b2 b1 b0
0 : Internal clock
1 : External clock (Note 1)
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity
RW
RW
RW
RW
RW
0 : Parity disabled
1 : Parity enabled
RW
Set to "0"
RW
Note 1: Set the corresponding port direction register to "0".
Figure 13.11 UARTi transmit/receive mode register in UART mode
Table 13.4 lists the functions of the input/output pins during UART mode. Note that for a period from when
the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the Nchannel open-drain is selected, this pin is in floating state.)
Table 13.4 Input/output pin functions in UART mode
Function
Serial data output
Serial data input
Pin name
Method of selection
Remarks
Port P14 cannot be used as an I/O port even when
performing only serial data input but not serial data output.
TxD0 (P14)
TxD1 (P37)
RxD1 input pin select bit
(bit 6 at address 00B016)="1"
Port P37 cannot be used as an I/O port even when
performing only serial data input but not serial data output.
RxD0 (P15)
Port P15 direction register
(bit 5 at address 00E316)="0"
Port P15 can be used as an I/O port when performing only
serial data output but not serial data input.
RxD1 (P35)
Port P35 direction register
(bit 5 at address 00E716)="0"
RxD1 input pin select bit
(bit 6 at address 00B016)="1"
Port P35 can be used as an I/O port when performing only
serial data output but not serial data input.
RxD1 (P37)
Port P37 direction register
(bit 7 at address 00E716)="0"
RxD1 input pin select bit
(bit 6 at address 00B016)="0"
When setting Port P37 as RxD1, serial data output cannot
be performed.
Port P35 can be used as an I/O port.
Transfer clock input CLKi (P16, P36) Internal/external clock select bit Ports P16 and P36 can be used as an I/O port when not
(bit 3 at address 00A016 and
performing transfer clock input. In this case, set the
00A816)="1"
internal/external clock select bit to "0".
Ports P16 and P36 direction
register (bit 6 at address 00E316
and 00E716)="0"
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13. Serial I/O
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
bit (TE)
"1"
Transmit buffer
empty flag (TI)
"1"
"0"
Data is set in UARTi transmit buffer register.
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit register
empty flag
(TXEPT)
P
Stopped pulsing because transmit enable bit = "0"
Stop
bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
"1"
"0"
Transmit interrupt "1"
request bit (IR)
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = 1.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit (TE)
"1"
Transmit buffer
empty flag (TI)
"1"
"0"
Data is set in UARTi transmit buffer register
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit register
empty flag
(TXEPT)
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
"1"
"0"
Transmit interrupt "1"
request bit (IR)
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = 0.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 13.12 Typical transmit timings in UART mode
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13. Serial I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
"1"
"0"
Stop bit
D0
Start bit
RxDi
D1
D7
Sampled "L"
Receive data taken in
Transfer clock
Receive
complete flag
Reception triggered when transfer clock
"1" is generated by falling edge of start bit
"0"
Receive interrupt
request bit
"1"
"0"
Transferred from UARTi receive register to
UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software
The above timing applies to the following settings:
Parity is disabled.
One stop bit.
Figure 13.13 Typical receive timing in UART mode
13.2.1 RxD1 Input pin Selection Function (UART1)
This function allows the setting two RxD1 input pins and choosing one of the two to input serial data by
using the RxD1 input pin select bit (bits 6 at address 00B016).
When selecting "1" (P35) for RxD1 input pin select bit, P37 functions as TxD1 output pin. When selecting "0" (P37), serial data output cannot be performed. However, P35 can be used as an input/output
port.
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M16C/1N Group
14. A/D Converter
14. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive
coupling amplifier. Pins P00 to P07, P10 to P13, P40 and P41 also function as the analog signal input pins.
The direction registers of these pins for A/D conversion must therefore be set to input. The Vref connect bit
(bit 5 at address 00D716) can be used to isolate the resistance ladder of the A/D converter from the reference voltage input pin (VREF) when the A/D converter is not used. Doing so stops any current flowing into
the resistance ladder from VREF, reducing the power dissipation. When using the A/D converter, start A/D
conversion only after connecting to VREF.
The result of A/D conversion is stored in the A/D registers. When set to 10-bit precision, the low 8 bits are
stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 14.1 shows the performance of the A/D converter. Figure 14.1 shows the block diagram of the A/D
converter, and Figures 14.2 and 14.3 show the A/D converter-related registers.
Table 14.1 Performance of A/D converter
Item
Performance
Method of A/D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
Operating clock ØAD (Note 2)
Resolution
Absolute precision
0V to VCC
VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
8-bit or 10-bit (selectable)
VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN11 input: ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected): ±7LSB
Operating modes
One-shot mode and repeat mode (Note 3)
Analog input pins
12 pins (AN0 to AN11) + 2 pins (ANEX0 to ANEX1)
A/D conversion start condition • Software trigger
A/D conversion starts when the A/D conversion start flag changes to "1"
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 ØAD cycles, 10-bit resolution: 59 ØAD cycles
• With sample and hold function
8-bit resolution: 28 ØAD cycles, 10-bit resolution: 33 ØAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide fAD if (XIN) exceeds 10MHz, and make ØAD equal to or lower than 10MHz. Also if Vcc is less
than 4.2V, divide fAD and make ØAD equal to or lower than fAD/2.
Without sample and hold function, set the ØAD frequency to 250kHz min.
With the sample and hold function, set the ØAD frequency to 1MHz min.
Note 3: In repeat mode, only 8-bit mode can be used.
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M16C/1N Group
14. A/D Converter
CKS1=1
CKS0=1
fAD
1/2
1/2
CKS0=0
flAD
CKS1=0
A/D conversion rate
selection
VCUT=0
VSS
VREF
Resistor ladder
VCUT=1
Successive conversion register
A/D control register 1 (address 00D716)
A/D control register 0 (address 00D616)
Addresses
(00C116, 00C016)
A/D register (16)
Vref
Decoder
Data bus low-order
VIN
Port P0 group
CH2,CH1,CH0=000
P07/AN0
CH2,CH1,CH0=001
P06/AN1
P05/AN2
CH2,CH1,CH0=010
ADGSEL0=0
CH2,CH1,CH0=011
P04/AN3
P03/AN4
P02/AN5
P01/AN6
P00/AN7
OPA1, OPA0=0, 0
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Port P1 group
P10/AN8
P11/AN9
CH2,CH1,CH0=100
P12/AN10
P13/AN11
CH2,CH1,CH0=110
ADGSEL0=1
CH2,CH1,CH0=101
CH2,CH1,CH0=111
OPA1,OPA0=1,1
OPA0=1
P40/ANEX0
P41/ANEX1
OPA1=1
Figure 14.1 Block diagram of A/D converter
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OPA1,OPA0=0,1
Comparator
M16C/1N Group
14. A/D Converter
A/D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
0
Bit symbol
CH0
Address
00D616
When reset
00000XXX2
Bit name
Analog input pin select bit
CH1
CH2
Function
RW
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4, AN8 are selected
1 0 1 : AN5, AN9 are selected
1 1 0 : AN6, AN10 are selected
1 1 1 : AN7, AN11 are selected (Note 2, 3)
RW
b2 b1 b0
RW
RW
MD
A/D operation mode
select bit 0
0 : One-shot mode
1 : Repeat mode (Note 2)
RW
ADGSEL0
A/D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
RW
Set to "0"
RW
Reserved bit
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
RW
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When changing A/D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit.
A/D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
0 0 0
Bit symbol
Address
00D716
When reset
0016
Bit name
Function
RW
Reserved bit
Set to "0"
RW
BITS
8/10-bit mode select bit
(Note 2)
0 : 8-bit mode
1 : 10-bit mode
RW
CKS1
Frequency select bit 1
(Note 3)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
RW
VCUT
VREF connect bit
0 : VREF not connected
1 : VREF connected
RW
OPA0
External op-amp
connection mode bit
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: In repeat mode, only 8-bit mode can be used.
Note 3: When f(XIN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing.
Figure 14.2 A/D converter-related registers (1)
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RW
RW
M16C/1N Group
14. A/D Converter
A/D control register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
0 0 0
Bit symbol
SMP
Address
00D416
When reset
XXXX00002
Bit name
Function
A/D conversion method
select bit
Reserved bit
RW
0 : Without sample and hold
1 : With sample and hold
RW
Set to "0"
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out
to be "0".
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
A/D register
(b15)
b7
(b8)
b0 b7
b0
Symbol
AD
Address
00C016
00C116
Function
Eight low-order bits of A/D conversion result
During 10-bit mode
Two high-order bits of A/D conversion result
During 8-bit mode
The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if
read, turns out to be "0".
Figure 14.3 A/D converter-related registers (2)
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When reset
Indeterminate
Indeterminate
RW
RO
RO
M16C/1N Group
14. A/D Converter
14.1 One-shot Mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A/D conversion.
(See Table 14.2.) Figure 14.4 shows the A/D control register in one-shot mode.
Table 14.2 One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A/D conversion
Start condition
Writing "1" to A/D conversion start flag
Stop condition
• End of A/D conversion (A/D conversion start flag changes to "0")
• Writing "0" to A/D conversion start flag
Interrupt request generation timing End of A/D conversion
Input pin
One of AN0 to AN11, as selected
Reading of result of A/D converter Read A/D register
A/D control register 0 (Note 1)
b7
b6
b5 b4
b3
b2
b1
b0
Symbol
ADCON0
0
Bit symbol
When reset
00000XXX2
Address
00D616
Bit name
Function
RW
b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
: AN0 is selected
: AN1 is selected
: AN2 is selected
: AN3 is selected
: AN4, AN8 are selected
: AN5, AN9 are selected
: AN6, AN10 are selected
: AN7, AN11 are selected (Note 2, 3)
RW
RW
RW
MD0
A/D operation mode
select bit 0
0 : One-shot mode (Note 2)
ADGSEL0
A/D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
RW
RW
Set to "0"
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
RW
Reserved bit
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When changing A/D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit.
A/D control register 1 (Note 1)
b7
b6
b5 b4
1
b3
b2
b1
b0
Symbol
ADCON1
0 0 0
Bit symbol
Address
00D716
Bit name
Reserved bit
When reset
0016
Function
Set to "0"
RW
RW
BITS
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
(Note 2)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
RW
VCUT
VREF connect bit
1 : VREF connected
RW
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
OPA1
1 1 : External op-amp connection mode
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When f(XIN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing.
OPA0
External op-amp
connection mode bit
Figure 14.4 A/D conversion register in one-shot mode
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RW
RW
M16C/1N Group
14. A/D Converter
14.2 Repeat Mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A/D conversion.
(See Table 14.3.) Figure 14.5 shows the A/D control register in repeat mode.
Table 14.3 Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A/D conversion
Start condition
Writing "1" to A/D conversion start flag
Stop condition
Writing "0" to A/D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN11, as selected (Note 1)
Reading of result of A/D converter Read A/D register (at any time)
Note 1: AN4 to AN7 can be used in the same way as for AN8 to AN11.
A/D control register 0 (Note 1)
b7
b6
b5 b4
b3
0
1
b2
b1
b0
Symbol
ADCON0
Bit symbol
Address
00D616
When reset
00000XXX2
Bit name
Function
RW
b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
: AN0 is selected
: AN1 is selected
: AN2 is selected
: AN3 is selected
: AN4, AN8 are selected
: AN5, AN9 are selected
: AN6, AN10 are selected
: AN7, AN11 are selected (Note 2, 3)
RW
RW
RW
MD
A/D operation mode
select bit 0
1 : Repeat mode (Note 2)
ADGSEL0
A/D input group select bit
0 : Port P0 group is selected
1 : Port P1 group is selected
RW
Set to "0"
RW
Reserved bit
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
RW
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: When changing A/D operation mode, set analog input pin again.
Note 3: AN4 to AN7 and AN8 to AN11 are selected by the A/D input group select bit.
A/D control register 1 (Note 1)
b7
b6
b5 b4
b3
1
0 0 0 0
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
00D716
When reset
0016
Bit name
Reserved bit
Function
Set to "0"
RW
RW
BITS
8/10-bit mode select bit 0 : 8-bit mode
(Note 2)
RW
CKS1
Frequency select bit 1
(Note 3)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
RW
VCUT
VREF connect bit
1 : VREF connected
RW
b7 b6
OPA0
External op-amp
connection mode bit
OPA1
0
0
1
1
0
1
0
1
: ANEX0 and ANEX1 are not used
: ANEX0 input is A/D converted
: ANEX1 input is A/D converted
: External op-amp connection mode
Note 1: If the A/D control register is rewritten during A/D conversion, the conversion result is indeterminate.
Note 2: In repeat mode, only 8-bit mode can be used.
Note 3: When f(XIN) is over 10 MHz, the flAD frequency must be under 10 MHz by dividing.
Figure 14.5 A/D conversion register in repeat mode
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RW
RW
M16C/1N Group
14. A/D Converter
14.3 Sample and Hold
Sample and hold is selected by setting bit 0 of the A/D control register 2 (address 00D416) to "1". When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 ØAD cycle is
achieved with 8-bit resolution and 33 ØAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A/D conversion whether sample and
hold is to be used.
14.4 Extended Analog Input Pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A/D control register 1 (address 00D716) is "1" and bit 7 is "0", input via ANEX0 is
converted from analog to digital.
When bit 6 of the A/D control register 1 (address 00D716) is "0" and bit 7 is "1", input via ANEX1 is
converted from analog to digital.
14.5 External Operation Amp Connection Mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A/D conversion.
When bit 6 of the A/D control register 1 (address 00D716) is "1" and bit 7 is "1", input via AN0 to AN11 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
A/D register. The speed of A/D conversion depends on the response of the external operation amp. Do
not connect the ANEX0 and ANEX1 pins directly.
Figure 14.6 is an example of how to connect the pins in external operation amp mode.
Resistance ladder
Successive conversion register
Analog
input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
ADGSEL0=0
ADGSEL0=1
ANEX0
ANEX1
Comparator
External op-amp
Figure 14.6 Example of external op-amp connection mode
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M16C/1N Group
15. D/A Converter
15. D/A Converter
This is an 8-bit, R-2R type D/A converter. The microcomputer contains one independent D/A converter of
this type.
D/A conversion is performed when a value is written to the corresponding D/A register. Bit 0 (D/A output
enable bit) of the D/A control register decide if the result of conversion is to be output. Do not set the target
port to output mode if D/A conversion is to be performed. When D/A output is set for enabled, the corresponding port is inhibited to be pulled up.
Output analog voltage (V) is determined by a set value (n: decimal) in the D/A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF: reference voltage
Table 15.1 lists the performance of the D/A converter. Figure 15.1 shows the block diagram of the D/A
converter, Figure 15.2 shows the D/A control register and Figure 15.3 shows D/A converter equivalent
circuit.
Table 15.1 Performance of D/A converter
Item
Performance
Conversion method
R-2R method
Resolution
8 bits
Analog output pin
1 channel
D/A register (8)
(Address 00D816)
D/A output enable bit
R-2R resistance ladder
Figure 15.1 Block diagram of D/A converter
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P34 / CLKS1 / DA
M16C/1N Group
15. D/A Converter
D/A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
0
Bit symbol
DAE
When reset
0016
Address
00DC16
Bit name
RW
Function
D/A output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
When write, set "0". When read, the value of this bit is "0".
Reserved bit
Set to "0"
RW
Nothing is assigned.
When write, set "0". When read, the value of these bits are "0".
D/A register
b7
b0
Symbol
DA
When reset
Indeterminate
Address
00D816
Function
RW
Output value of D/A conversion
RW
Figure 15.2 D/A control register
D/A output enable bit
"0"
R
R
R
R
R
R
R
2R
DA
"1"
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D/A register 0
"0"
"1"
VSS
VREF
Note 1: In the above figure, the D/A register value is "2A16".
Note 2: To save power when not using the D/A converter, set the D/A output enable bit to "0"
and the D/A register to "0016", and prevent current flowing to the R-2R resistance.
Figure 15.3 D/A converter equivalent circuit
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M16C/1N Group
16. CAN Module
16. CAN Module
The CAN (Controller Area Network) module for the M16C/1N group of microcomputers is a communication
controller implementing the CAN 2.0B protocol. The M16C/1N group contains one Full CAN module which
can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats.
Figure 16.1 shows a block diagram of the CAN module.
External CAN bus driver and receiver are required.
Data Bus
CAN0 Configuration
Register
CAN0 Control
Register
CAN0 Global
Mask Register
CAN0 Mailbox
Control
Register 15
CAN0
Mailbox
CAN0
Control Mailbox
Register 1
Control Register 0
CTX
CAN0 Extended
ID Register
CAN0 Local
Mask A Register
CAN0 Local
Mask B Register
Mailboxes
Mailbox 0
Mailbox 1
Protocol
Controller
Mailbox 2
Acceptance Filter
16-bit
Timer
Mailbox 14
CRX
Mailbox 15
Wakeup
Logic
Interrupt
Control Logic
CAN0 REC
Register
CAN0 TEC
Register
CAN0 Mailbox
Status Register
CAN0 Status
Register
CAN0 Interrupt
Control Register
CAN0 receptionsuccessful interrupt
CAN0 transmissionsuccessful interrupt
CAN0 error interrupt
CAN0 wakeup interrupt
Data Bus
Figure 16.1 Block Diagram of CAN Module
CTx/CRx:
CAN I/O pins. Either P02, P03 or P50, P51 can be selected as CAN I/O pins by a
program.
Protocol controller:
This controller handles the bus arbitration and the CAN protocol services, i.e. bit
timing, stuffing, error status etc.
Message box:
This memory block consists of 16 slots that can be configured either as transmitter
or receiver. Each slot contains an individual ID, data length code, a data field (8
bytes) and a time stamp.
Acceptance filter:
This block performs filtering operation for received messages. For the filtering operation, the C0GMR register, the C0LMAR register, or the C0LMBR register is
used.
16 bit timer:
Used for the time stamp function. When the received message is stored in the
message memory, the timer value is stored as a time stamp.
Wake up function:
CAN0 wake up interrupt is generated by a message from the CAN bus.
Interrupt generation function: The interrupt events are provided by the CAN module. CAN0 successful reception
interrupt, CAN0 successful transmission interrupt, CAN0 error interrupt, and
CAN0 wake up interrupt.
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M16C/1N Group
16. CAN Module
16.1 CAN Module-Related Registers
The CAN0 module has the following registers.
(1) CAN Message Box
A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as
Basic CAN.
• Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission
and reception.
• A program can define whether a slot is defined as transmitter or receiver.
(2) Acceptance Mask Registers
A CAN module is equipped with 3 masks for the acceptance filter.
• CAN0 global mask register (C0GMR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slots 0 to 13
• CAN0 local mask A register (C0LMAR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 14
• CAN0 local mask B register (C0LMBR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 15
(3) CAN SFR Registers
• CAN0 message control register i (C0MCTLi register: 8 bits X 16) (i = 0 to 15)
Control of transmission and reception of a corresponding slot
• CAN0 control register (C0CTLR register: 16 bits)
Control of the CAN protocol
• CAN0 status register (C0STR register: 16 bits)
Indication of the protocol status
• CAN0 slot status register (C0SSTR register: 16 bits)
Indication of the status of contents of each slot
• CAN0 interrupt control register (C0ICR register: 16 bits)
Selection of interrupt enabled or disabled for each slot
• CAN0 extended ID register (C0IDR register: 16 bits)
Selection of ID format (standard or extended) for each slot
• CAN0 configuration register (C0CONR register: 16 bits)
Configuration of the bus timing
• CAN0 receive error count register (C0RECR register: 8 bits)
Indication of the error status of the CAN module in reception: the counter value is incremented or
decremented according to the error occurrence.
• CAN0 transmit error count register (C0TECR register: 8 bits)
Indication of the error status of the CAN module in transmission: the counter value is incremented
or decremented according to the error occurrence.
• CAN0 acceptance filter support register (C0AFS register: 16 bits)
Decoding the received ID for use by the acceptance filter support unit
Explanation of each register is given below.
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M16C/1N Group
16. CAN Module
16.2 CAN0 Message Box
Table 16.1 shows the memory mapping of the CAN0 message box.
It is possible to access to the message box in byte or word.
Mapping of the message contents differs from byte access to word access. Byte access or word access
can be selected by the MsgOrder bit of the C0CTLR register.
Table 16.1 Memory Mapping of CAN0 Message Box (n = 0 to 15: the number of the slot)
Message content (Memory mapping)
Address
Byte access (8 bits)
Word access (16 bits)
026016 + n • 16 + 0
SID10 to SID6
SID5 to SID0
026016 + n • 16 + 1
SID5 to SID0
SID10 to SID6
026016 + n • 16 + 2
EID17 to EID14
EID13 to EID6
026016 + n • 16 + 3
EID13 to EID6
EID17 to EID 14
026016 + n • 16 + 4
EID5 to EID0
Data Length Code (DLC)
026016 + n • 16 + 5
Data Length Code (DLC)
EID5 to EID0
026016 + n • 16 + 6
Data byte 0
Data byte 1
026016 + n • 16 + 7
Data byte 1
Data byte 0
•
•
•
026016 + n • 16 + 13
026016 + n • 16 + 14
026016 + n • 16 + 15
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•
•
•
•
•
•
Data byte 7
Data byte 6
Time stamp high-order byte Time stamp low-order byte
Time stamp low-order byte Time stamp high-order byte
M16C/1N Group
16. CAN Module
Figures 16.2 and 16.3 show the bit mapping in each slot in byte access and word access. The content of
each slot remains unchanged unless transmission or reception of a new message is performed.
Bit 7
Bit 0
SID 5
EID13
EID12
SID10
SID 9
SID8
SID 7
SID 6
SID 4
SID3
SID2
SID 1
SID0
EID17
EID16
EID15
EID14
EID11
EID10
EID 9
EID8
EID 7
EID6
EID 5
EID 4
EID 3
EID2
EID1
EID0
DLC3
DLC2
DLC1
DLC0
Data Byte 0
Data Byte 1
Data Byte 7
Time Stamp high-order byte
Time Stamp low-order byte
CAN Data Frame:
SID10 to 6
SID5 to 0
EID17 to 14
EID13 to 6
EID5 to 0
DLC3 to 0
Data Byte 0
Data Byte 1
Data Byte 7
is read, the value is the one written upon the transmission slot configuration.
Note 1: When
The value is "0" when read on the reception slot configuration.
Figure 16.2 Bit Mapping in Byte Access
Bit 15
Bit 8 Bit 7
Bit 0
SID10 SID9 SID8 SID7 SID6
SID5 SID4 SID3 SID2 SID1 SID0
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
EID5 EID4 EID3 EID2 EID1 EID0
DLC3 DLC 2 DLC1 DLC0
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Time Stamp high-order byte
Time Stamp low-order byte
CAN Data Frame:
SID10 to 6
SID5 to 0
Note 1: When
EID17 to 14
EID13 to 6
EID5 to 0
DLC3 to 0
Data Byte 0
is read, the value is the one written upon the transmission slot configuration.
The value is "0" when read on the reception slot configuration.
Figure 16.3 Bit Mapping in Word Access
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Data Byte 1
page 134 of 222
Data Byte 7
M16C/1N Group
16. CAN Module
16.3 Acceptance Mask Registers
Figures 16.4 and 16.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in
which bit mapping in byte access and word access are shown.
Bit 7
Bit 0
SID5
EID13
EID12
EID12
EID12
SID9
SID8
SID7
SID6
036016
SID4
SID3
SID2
SID1
SID0
036116
EID17
EID16
EID15
EID14
036216
EID10
EID9
EID8
EID7
EID6
036316
EID5
EID4
EID3
EID2
EID1
EID0
036416
SID10
SID9
SID8
SID7
SID6
036616
SID4
SID3
SID2
SID1
SID0
036716
EID17
EID16
EID15
EID14
036816
EID11
EID10
EID9
EID8
EID7
EID6
036916
EID5
EID4
EID3
EID2
EID1
EID0
036A16
SID10
SID9
SID8
SID7
SID6
036C16
SID4
SID3
SID2
SID1
SID0
036D16
EID17
EID16
EID15
EID14
036E16
SID5
EID13
SID10
EID11
SID5
EID13
Addresses
CAN0
EID11
EID10
EID9
EID8
EID7
EID6
036F16
EID5
EID4
EID3
EID2
EID1
EID0
037016
C0GMR register
C0LMAR register
C0LMBR register
Note 1:
is indeterminate.
Note 2: These registers can be written in CAN reset/initialization mode of the CAN module.
Figure 16.4 Bit Mapping of Mask Registers in Byte Access
Bit 15
Bit 8 Bit 7
Bit 0
Addresses
CAN0
SID5 SID4 SID3 SID2 SID1 SID0
036016
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
036216
SID10 SID9 SID8 SID7 SID6
EID5 EID4 EID3 EID2 EID1 EID0
SID10 SID9 SID8 SID7 SID6
036416
SID5 SID4 SID3 SID2 SID1 SID0
036616
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
036816
EID5 EID4 EID3 EID2 EID1 EID0
SID10 SID9 SID8 SID7 SID6
SID5 SID4 SID3 SID2 SID1 SID0
036C16
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
036E16
Note 1:
is indeterminate.
Note 2: These registers can be written in CAN reset/initialization mode of the CAN module.
Figure 16.5 Bit Mapping of Mask Registers in Word Access
page 135 of 222
C0LMAR register
036A16
EID5 EID4 EID3 EID2 EID1 EID0
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REJ09B0007-0100Z
C0GMR register
037016
C0LMBR register
M16C/1N Group
16. CAN Module
16.4 CAN SFR Registers
16.4.1 C0MCTLi Register (i = 0 to 15)
Figure 16.6 shows the C0MCTLi register.
CAN0 message control register i (i = 0 to 15) (Note 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0MCTL0 to C0MCTL15
Bit symbol
Address
After reset
0016
022016 to 022F16
Bit name
Function
RW
NewData
Successful
reception flag
When set to reception slot
0 : The content of the slot is read or still under
RO
(Note 1)
processing by the CPU.
1 : The CAN module has stored new data in the slot.
SentData
Successful
transmission flag
When set to transmission slot
0 : Transmission is not started or completed yet.
1 : Transmission is successfully completed.
InvalData
"Under reception" When set to reception slot
flag
0 : The message is valid.
1 : The message is invalid.
(The message is being updated.)
RO
"Under
When set to transmission slot
transmission" flag 0 : Waiting for bus idle or completion of arbitration.
1 : Transmitting
RO
TrmActive
RO
(Note 1)
MsgLost
Overwrite flag
When set to reception slot
RO
0 : No message has been overwritten in this slot.
1 : This slot already contained a message, but it has (Note 1)
been overwritten by a new one.
RemActive
Remote frame
transmission/
reception status
flag (Note 2)
0 : Data frame transmission/reception status
1 : Remote frame automatic transfer status
Transmission/
reception auto
response lock
mode select bit
When set to reception remote frame slot
0 : After a remote frame is received, it will be
answered automatically.
1 : After a remote frame is received, no transmission
will be started as long as this bit is set to "1".
(Not responding)
Remote frame
corresponding
slot select bit
0 : Slot not corresponding to remote frame
1 : Slot corresponding to remote frame
RW
Reception slot
request bit
(Note 3)
0 : Not reception slot
1 : Reception slot
RW
Transmission
slot request bit
(Note 3)
0 : Not transmission slot
1 : Transmission slot
RW
RspLock
Remote
RecReq
TrmReq
RW
RW
Note 1: As for write, only writing "0" is possible. The value of each bit is written when the CAN module enters the respective state.
Note 2: In Basic CAN mode, this bit serves as data format identification flag. When receiving a data frame, this bit is set to "0" and
when receiving a remote frame, this bit is set to "1".
Note 3: One slot cannot be defined as reception slot and transmission slot at the same time.
Note 4: This register can not be set in CAN reset/initialization mode of the CAN module.
Figure 16.6 C0MCTLi Register
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M16C/1N Group
16. CAN Module
16.4.2 C0CTLR Register
Figures 16.7 shows the C0CTLR register.
CAN0 control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0CTLR
Bit symbol
Address
023016
After reset
X00000012
Bit name
Function
RW
Reset
CAN module
0 : Operation mode
reset bit
(Note 2) 1 : Reset/initialization mode
RW
LoopBack
Loop back mode
0 : Normal operation mode
select bit (Note 3) 1 : Loop back mode
RW
MsgOrder
Message order
0 : Word access
select bit (Note 3) 1 : Byte access
RW
BasicCAN
Basic CAN mode
0 : Normal operation mode
select bit (Note 3) 1 : Basic CAN mode
RW
BusErrEn
Bus error interrupt
0 : Bus error interrupt disabled
enable bit (Note 3) 1 : Bus error interrupt enabled
RW
Sleep
Sleep mode
0 : Sleep mode disabled
select bit (Note 3, 4) 1 : Sleep mode enabled; clock supply stopped
RW
PortEn
CAN port enable bit
-
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7)
0 : I/O port function
1 : CTx/CRx function (Note 1)
RW
-
Note 1: Irrespective of setting of PD0 and PD5 registers.
Note 2: When the Reset bit is set to "1" (CAN reset/initialization mode), check that the State_Reset bit of the C0STR register is set to "1" (Reset
mode).
Note 3: Set these bits only in CAN reset/initialization mode.
Note 4: When using CAN0 wake up interrupt, set this bit to "1" (Sleep mode disabled).
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
Symbol
C0CTLR
Bit symbol
Address
023116
After reset
XX0X00002
Bit name
Function
RW
b1 b0
Time stamp
prescaler (Note 3) 0 0 : Period of 1 bit time
0 1 : Period of 1/2 bit time
1 0 : Period of 1/4 bit time
1 1 : Period of 1/8 bit time
RW
TSReset
Time stamp counter 0 : Normal operation mode
reset bit (Note 1) 1 : Force reset of the time stamp counter
RW
RetBusOff
Return from bus off 0 : Normal operation mode
command bit
1 : Force return from bus off
(Note 2)
RW
Bit1, Bit0
(b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
RXOnly
Listen-only mode
select bit (Note 3)
-
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7-b6)
0 : Normal operation mode
1 : Listen-only mode (Note 4)
RW
-
Note 1: When the TSReset bit = 1, the C0TSR register is set to "000016". After this, the bit is automatically set to "0".
Note 2: When the RetBusOff bit = 1, the C0RECR register and the C0TECR register are set to "0016". After this, the bit is automatically set to "0".
Note 3: Set these bits only in CAN reset/initialization mode.
Note 4: When listen-only mode is selected, do not request a transmission.
Figure 16.7 C0CTLR Register
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M16C/1N Group
16. CAN Module
16.4.3 C0STR Register
Figure 16.8 shows the C0STR register.
CAN0 status register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0STR
Bit symbol
MBox
Address
023216
After reset
0016
Bit name
Active slot bits
(Note 2)
Function
RW
b3 b2 b1 b0
0 0 0 0 : Slot 0
0 0 0 1 : Slot 1
0 0. 1 0 : Slot 2
..
1 1 1 0 : Slot 14
1 1 1 1 : Slot 15
RO
Successful
transmission flag
0 : No [successful] transmission
1 : The CAN module has transmitted a message
successfully.
RO
RecSucc
Successful
reception flag
0 : No [successful] reception
1 : CAN module received a message successfully.
RO
TrmState
Transmission flag
(Transmitter)
0 : CAN module is idle or receiver.
1 : CAN module is transmitter.
RO
RecState
Reception flag
(Receiver)
0 : CAN module is idle or transmitter.
1 : CAN module is receiver.
RO
TrmSucc
Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.
Note 2: These bits change when a slot enabled interrupt has transmitted or received successfully.
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
Symbol
C0STR
Bit symbol
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After reset
X00000012
Bit name
Function
RW
State_Reset
Reset state flag
0 : Operation mode
1 : Reset mode
RO
State_
LoopBack
Loop back state flag
0 : Normal operation mode
1 : Loop back mode
RO
State_
MsgOrder
Message order
state flag
0 : Word access
1 : Byte access
RO
State_
BasicCAN
Basic CAN mode
state flag
0 : Normal operation mode
1 : Basic CAN mode
RO
State_
BusError
Bus error
state flag
0 : No error has occurred.
1 : A CAN bus error has occurred.
RO
State_
ErrPass
Error passive
state flag
0 : The CAN module is not in error passive state.
1 : The CAN module is in error passive state.
RO
State_
BusOff
Error bus off
state flag
0 : The CAN module is not in error bus off state.
1 : The CAN module is in error bus off state.
RO
-
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7)
Figure 16.8 C0STR Register
Address
023316
-
M16C/1N Group
16. CAN Module
16.4.4 C0SSTR Register
Figure 16.9 shows the C0SSTR register.
CAN0 slot status register
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0SSTR
Address
023516, 023416
Function
Slot status bits
Each bit corresponds to the slot with the
same number.
Figure 16.9 C0SSTR Register
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page 139 of 222
After reset
000016
Setting values
RW
0 : Reception slot
The message has been read.
Transmission slot
Transmission is not completed.
1 : Reception slot
The message has not been read.
Transmission slot
Transmission is completed.
RO
M16C/1N Group
16. CAN Module
16.4.5 C0ICR Register
Figure 16.10 shows the C0ICR register.
CAN0 interrupt control register (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0ICR
Address
023716, 023616
After reset
000016
Function
Setting values
0 : Interrupt disabled
Interrupt enable bits:
1 : Interrupt enabled
Each bit corresponds with a slot with the same
number.
Enabled/disabled of successful transmission interrupt or successful reception interrupt can be selected.
RW
RW
Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.
Figure 16.10 C0ICR Register
16.4.6 C0IDR Register
Figure 16.11 shows the C0IDR register.
CAN0 extended ID register (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0IDR
Address
023916, 023816
After reset
000016
Function
Extended ID bits:
Each bit corresponds with a slot with the same
number.
Selection of the ID format that each slot handles.
Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.
Figure 16.11 C0IDR Register
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REJ09B0007-0100Z
page 140 of 222
Setting values
0 : Standard ID
1 : Extended ID
RW
RW
M16C/1N Group
16. CAN Module
16.4.7 C0CONR Register
Figure 16.12 shows the C0CONR register.
CAN0 configuration register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0CONR
Bit symbol
BRP
Address
023A16
After reset
Indeterminate
Bit name
Prescaler division
ratio select bits
Function
RW
b3 b2 b1 b0
.....
0 0 0 0 : Divide-by-1 of fCAN
0 0 0 1 : Divide-by-2 of fCAN
0 0 1 0 : Divide-by-3 of fCAN
RW
(Note 1)
1 1 1 0 : Divide-by-15 of fCAN
1 1 1 1 : Divide-by-16 of fCAN
SAM
Sampling control
bit
0 : One time sampling
1 : Three times sampling
PTS
Propagation time
segment control bits
b7 b6 b5
0 0 0 : 1Tq
0 0 1 : 2Tq
0 1 0 : 2Tq
RW
.....
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
Note 1: fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 4 to 6).
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
Symbol
C0CONR
Bit symbol
PBS1
Address
023B16
After reset
Indeterminate
Bit name
Phase buffer
segment 1
control bits
Function
RW
b2 b1b0
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
RW
.....
1 1 0 : 7Tq
1 1 1 : 8Tq
PBS2
Phase buffer
segment 2
control bits
b5 b4 b3
.....
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
SJW
Figure 16.12 C0CONR Register
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page 141 of 222
Re synchronization
jump width
control bits
b7 b6
0
0
1
1
0 : 1Tq
1 : 2Tq
0 : 3Tq
1 : 4Tq
RW
M16C/1N Group
16. CAN Module
16.4.8 C0RECR Register
Figure 16.13 shows the C0RECR register.
CAN0 receive error count register (Note 2)
b7
b0
Symbol
C0RECR
Address
023C16
After reset
0016
Counter value
Function
Reception error counting function
The value is incremented or decremented
according to the CAN module’s error status.
0016 to FF16 (Note 1)
RW
RO
Note 1: The value is indeterminate in bus off state.
Note 2: These bits can not be set in CAN reset/initialization mode of the CAN module.
Figure 16.13 C0RECR Register
16.4.9 C0TECR Register
Figure 16.14 shows the C0TECR register.
CAN0 transmit error count register (Note 1)
b7
b0
Symbol
C0TECR
Address
023D16
After reset
0016
Function
Transmission error counting function
The value is incremented or decremented
according to the CAN module’s error status.
Note 1: These bits can not be set in CAN reset/initialization mode of the CAN module.
Figure 16.14 C0TECR Register
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REJ09B0007-0100Z
page 142 of 222
Counter value
0016 to FF16
RW
RO
M16C/1N Group
16. CAN Module
16.4.10 C0AFS Register
Figure 16.15 shows the C0AFS register.
CAN0 acceptance filter support register
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0AFS
Address
024516 , 024416
Function
Write the content equivalent to the standard frame
ID of the received message.
The value is "converted standard frame ID" when
read.
Figure 16.15 C0AFS Register
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REJ09B0007-0100Z
page 143 of 222
After reset
Indeterminate
Setting values
Standard frame ID
RW
RW
M16C/1N Group
16. CAN Module
16.5 Operational Modes
The CAN module has the following three operational modes.
• CAN Reset/Initialization Mode
• CAN Sleep Mode
• CAN Operation Mode
Figure 16.16 shows transition between operational modes.
MCU Reset
CAN
Reset/initialization
mode
(State_Reset = 1)
Sleep = 0
and
Reset = 1
Reset = 1
Sleep = 1
and
Reset = 0
CAN Sleep mode
CAN
Operation mode
(State_Reset = 0)
Reset = 0
TEC > 255
Reset = 1
When 11 consecutive
recessive bits are monitored
128 times on the bus or
RetBusOff = 1
Bus off state
(State_Bus off = 1)
Reset, Sleep, RetBusOff : C0CTLR register’s bits
State_Reset, State_BusOFF : C0STR register’s bits
Figure 16.16 Transition Between Operational Modes
16.5.1 CAN Reset/Initialization Mode
CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit of the C0CTLR
register. When setting the Reset bit to "1", check that the State_Reset bit of C0STR register is set to
"1". Entering CAN reset/initialization mode, the module initiates the following functions:
• Suspend all communication functions. When the CAN reset/initialization mode is activated during
an ongoing transmission in operation mode, the module suspends the mode transition until
completion of the transmission (successful, arbitration loss, or error detection) and then sets the
State_Reset bit.
• The C0IDR, C0MCTLi (i = 0 to 15), C0ICR, C0STR, C0RECR and C0TECR registers are initialized. All these registers are locked to prevent CPU modification.
• The C0CTLR, C0CONR, C0GMR, C0LMAR and C0LMBR registers and the CAN0 message box
retain their contents and are available for CPU access.
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M16C/1N Group
16. CAN Module
16.5.2 CAN Operation Mode
CAN operation mode is activated by setting the Reset bit of the C0CTLR register to “0”. When setting
the Reset bit to "0", check that the State_reset bit of C0STR register is set to "0". In CAN operation
mode, the CAN module becomes the following status after having detected 11 consecutive recessive
bits on the bus.
• The module's communication functions are released and it becomes an active node on the network and may transmit and receive CAN messages.
• Release the internal fault confinement logic including receive and transmit error counters. The
module may leave CAN operation mode depending on the error counts.
Within CAN operation mode, the module may be in three different sub modes, depending on which
type of communication functions are performed:
• Module idle: The modules receive and transmit sections are inactive.
• Module receives: The module receives a CAN message sent by another node.
• Module transmits: The module transmits a CAN message. The module may receive its own
message simultaneously when the looback function is enabled.
Figure 16.17 shows sub modes of CAN operation mode.
Module idle
TrmState = 0
RecState = 0
A SOF
detected
Transmission
start
Transmission
finished
Reception
finished
Module transmits
TrmState = 1
RecState = 0
Module receives
Lost in arbitration
TrmState = 0
RecState = 1
TrmState, RecState : C0STR register’s bit
Figure 16.17 Sub Modes of CAN Operation Mode
16.5.3 CAN Sleep Mode
CAN sleep mode is activated by setting the Sleep bit of the C0CTLR register to “1” and Reset bit to “0”.
It should never be activated from CAN operation mode but only via CAN reset/initialization mode.
Entering CAN sleep mode instantly stops the modules clock supply and thereby reduces power dissipation.
16.5.4 Bus Off State
The bus off sate is entered according to the fault confinement rules of the CAN specification. When
returning to CAN operation mode from the bus off state, the module has the following two cases.
In this time, the value of any CAN registers, except C0STR, C0RECR and C0TECR registers, does
not change.
(1) When 11 consecutive recessive bits are monitored 128 times
The module enters instantly into error active state and the CAN communication becomes possible
immediately.
(2) When the RetBus Off bit in the CiCTLR register = 1 (Force return form buss off)
The module enters instantly into error active state, and the CAN communication becomes possible again after 11 consecutive recessive bits are monitored.
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M16C/1N Group
16. CAN Module
16.6 Configuration of the CAN Module System Clock
The M16C/1N group has a CAN module system clock select circuit.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register
and the BRP bit of the C0CONR register.
For the CCLKR register, refer to clock generation circuit.
Figure 16.18 shows a block diagram of the clock generation circuit of the CAN module system.
f1
Divider
Value: 1, 2, 4, 8, 16
Divide-by-1 of XIN (undivided)
Divide-by-2 of XIN
Divide-by-4 of XIN
Divide-by-8 of XIN
Divide-by-16 of XIN
Prescaler
fCAN
1/2
Prescaler
for baud rate
fCANCLK
Division by (P + 1)
CCLKR register
CAN module
fCAN:
CAN module system clock
P:
The value written in the BRP bit of the C0CONR register. P = 0 to 15
fCANCLK: CAN communication clock fCANCLK = fCAN/2(P + 1)
Figure 16.18 Block Diagram of CAN Module System Clock Generation Circuit
16.6.1 Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum
of delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than
expected, the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the
bit falls earlier than expected, the segment can become shorter by the maximum of the value
defined in SJW.
Figure 16.19 shows the bit timing.
Bit time
SS
PTS
PBS2
PBS1
SJW
SJW
Sampling point
The range of each segment: Bit time = 8 to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
Figure 16.19 Bit Timing
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Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
PBS1 ≥ SJW
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
M16C/1N Group
16. CAN Module
16.6.2 Baud Rate
Baud rate depends on XIN, the division value of the CAN module system clock, the division value of
the prescaler for baud rate, and the number of Tq of one bit.
Table 16.2 shows the examples of baud rate.
Table 16.2 Examples of Baud Rate
Baud rate
1 Mbps
500 kbps
16 MHz
10 MHz
8 MHz
8Tq (1)
8Tq (2)
10Tq (1)
8Tq (1)
16Tq (1)
125 kbps
8Tq (8)
10Tq (4)
8Tq (4)
16Tq (4)
20Tq (2)
16Tq (2)
83.3 kbps
8Tq (12)
10Tq (6)
8Tq (6)
16Tq (6)
20Tq (3)
16Tq (3)
33.3 kbps
8Tq (30)
10Tq (15)
8Tq (15)
16Tq (15)
Note 1: The number in ( ) indicates a value of fCAN division value multiplied by division value of the prescaler
for baud rate.
Calculation of Baud Rate
XIN
2 X fCAN division value (Note 1) X division value of prescaler for baud rate (Note 2) X number of Tq of one bit
Note 1: fCAN division value = 1, 2, 4, 8, 16
fCAN division value: a value selected in the CCLKR register
Note 2: Division value of prescaler for baud rate = P + 1 (P: 0 to 15)
P: a value selected in the BRP bit of the C0CONR register
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M16C/1N Group
16. CAN Module
16.7 Acceptance Filtering Function and Masking Function
These functions serve the users to select and receive a facultative message. The C0GMR register, the
C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID
of 29 bits. The C0GMR register corresponds to slots 0 to 13, the C0LMAR register corresponds to slot 14,
and the C0LMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits
of a received ID according to the value in the corresponding slot of the C0IDR register upon acceptance
filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs.
Figure 16.20 shows correspondence of the mask registers and slots, Figure 16.21 shows the acceptance
function.
C0GMR register
Slot #0
Slot #1
Slot #2
Slot #3
Slot #4
Slot #5
Slot #6
Slot #7
Slot #8
Slot #9
Slot #10
Slot #11
Slot #12
Slot #13
C0LMAR register
C0LMBR register
Slot #14
Slot #15
Figure 16.20 Correspondence of Mask Registers to Slots
ID of the
ID stored in
received message the slot
The value of the
mask register
Mask Bit Values
0: ID (to which the received message
corresponds) match is handled as
"Don’t care".
1: ID (to which the received message
corresponds) match is checked.
Acceptance Signal
Acceptance judge signal
0: The CAN module ignores the
current incoming message.
(Not stored in any slot)
1: The CAN module stores the
current incoming message in
a slot of which ID matches.
Figure 16.21 Acceptance Function
When using the acceptance function, note the following points.
(1) When one ID is defined in two slots, the one with a smaller number alone is valid.
(2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15
receive all IDs which are not stored into slots 0 to 13.
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M16C/1N Group
16. CAN Module
16.8 Acceptance Filter Support Unit (ASU)
The acceptance filter support unit has a function to judge valid/invalid of a received ID through table
search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register,
and table search is performed with a decoded received ID. The acceptance filter support unit can be used
for the IDs of the standard frame only.
The acceptance filter support unit is valid in the following cases.
• When the ID to receive cannot be masked by the acceptance filter.
(Example) IDs to receive: 07816, 08716, 11116
• When there are too many IDs to receive; it would take too much time to filter them by software.
Figure 16.22 shows the write and read of C0AFS register in word access.
Address
Bit 15
When write
Bit 8 Bit 7
SID10 SID9 SID8 SID7 SID6
Bit 0
SID5 SID4 SID3 SID2 SID1 SID0
024516,
024416
3/8 Decoder
Bit 15
Bit 8 Bit 7
When read
Figure 16.22 Write/read of CiAFS Register in Word Access
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Bit 0
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
page 149 of 222
024516,
024416
M16C/1N Group
16. CAN Module
16.9 Basic CAN Mode
When the BasicCAN bit in the C0CTLR register is set to "1", slots 14 and 15 correspond to Basic CAN
mode. In normal operation mode, each slot can handle only one type message at a time, either a data
frame or a remote frame by setting C0MCTLi register (i = 0 to 15). However, in Basic CAN mode, slots 14
and 15 can receive both types of message at the same time.
When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored
in slots 14 and 15 alternately.
Which type of message has been received can be checked by the RemActive bit in the C0MCTLi register.
Figure 16.23 shows the operation of slots 14 and 15 in Basic CAN mode.
Slot 14
Empty
Msg. n
Locked (Msg. n)
Msg. n+2 (Msg. n lost)
Slot 15
Locked (empty)
Locked (empty)
Msg. n + 1
Locked (Msg. n+1)
Msg. n
Msg. n+1
Msg. n+2
Figure 16.23 Operation of Slots 14 and 15 in Basic CAN Mode
When using Basic CAN mode, note the following points.
(1) Setting of Basic CAN mode has to be done in CAN reset/initialization mode.
(2) Select the same ID for slots 14 and 15. Also, setting of the C0LMAR and C0LMBR registers has to
be the same.
(3) Define slots 14 and 15 as reception slot only.
(4) There is no protection available against message overwrite. A message can be overwritten by a
new message.
(5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode.
16.10 Return from Bus off Function
When the protocol controller enters bus off state, it is possible to make it forced return from bus off state
by the return from bus off function of the C0CTLR register. At this time, the error state changes from bus
off state to error active state. Implementation of this function initializes the protocol controller. However,
registers of the CAN module such as C0CONR register and the content of each slot are not initialized.
16.11 Listen-Only Mode
When the RXOnly bit of the C0CTLR register is set to "1", the module enters listen-only mode.
Listen-only mode is not allowed to have any influence on the bus. It shall not send any frames nor send
acknowledgement, error frames, overload frames. When setting the CAN module to Listen-only mode, do
not request a transmission.
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M16C/1N Group
16. CAN Module
16.12 Reception and Transmission
Configuration of CAN Reception and Transmission Mode
Table 16.3 shows configuration of CAN reception and transmission mode.
Table 16.3 Configuration of CAN Reception and Transmission Mode
TrmReq
RecReq
0
0
0
1
0
0
Configured as a reception slot for a data frame.
1
0
1
0
Configured as a transmission slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of transmission, this functions as a reception slot for a
data frame. (At this time the RemActive bit is "0".)
However, when an ID that matches on the CAN bus is detected before
remote frame transmission, this immediately functions as a reception
slot for a data frame.
1
0
0
0
Configured as a transmission slot for a data frame.
0
1
1
1/0
Remote
RspLock
Communication mode of the slot
Communication environment configuration mode: configure the communication mode of the slot.
Configured as a reception slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of reception, this functions as a transmission slot for a
data frame. (At this time the RemActive bit is "0".)
However, transmission does not start as long as RspLock bit remains "1";
thus no automatic remote frame response.
Response (transmission) starts when RspLock bit is set to "0".
TrmReq, RecReq, Remote, RspLock, RemActive, RspLock: C0MCTLi register’s bit
When configuring a slot as a reception slot, note the following points.
(1) Before configuring a slot as a reception slot, be sure to set the C0MCTLi registers (i = 0 to 15) to
"0016".
(2) A received message is stored in a slot that matches the condition first according to the result of
reception mode configuration and acceptance filtering operation. Upon deciding in which slot to
store, the smaller the number of the slot is, the higher priority it has.
(3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches,
the CAN module never receives the transmitted data. In loop back mode, however, the CAN module receives back the transmitted data. In this case, the module does not return ACK.
When configuring a slot as a transmission slot, note the following points.
(1) Before configuring a slot as a transmission slot, be sure to set the C0MCTLi registers to "0016".
(2) Set the TrmReq bit to "0" (not transmission slot) before rewriting a transmission slot.
(3) A transmission slot should not be rewritten when the TrmActive bit is "1" (transmitting). If it is
rewritten, an indeterminate data will be transmitted.
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M16C/1N Group
16. CAN Module
16.12.1 Reception
Figure 16.24 shows the behavior of the module when receiving two consecutive CAN messages.
SOF
ACK
EOF
IFS
SOF
ACK
EOF
IFS
RecReq
(2)
NewData
(2)
(5)
(4)
(5)
MsgLost
RecState
(5)
(3)
Succ.Rec Int.
(1)
RecSucc
MBOX
Receive slot No.
CAN0 status register
InvalData
CAN0 message control register
CANbus
Figure 16.24 Timing of Receive Data Frame Sequence
(1) On monitoring a SOF on the bus the RecState bit becomes active immediately, given the module
has no transmission pending (see section "16.12.2 Transmission" below).
(2) After successful reception of the message the NewData bit of the receiving slot becomes active.
The InvalData bit becomes active at the same time and becomes inactive again after the complete
message was transferred to the slot.
(3) When the bit in the C0ICR register of the receiving slot is active the receive successful interrupt is
requested and the C0STR register changes. It shows the slot number where the message was
stored and the RecSucc bit is active.
(4) Read the message out of the slot after setting the New Data bit to “0” by a program.
(5) If the NewData bit is set to "0" by a program or the next CAN message is received successfully
before the reception request for the slot is canceled, the MsgLost bit is set to "1". The new received
message is transferred to the slot. The interrupt request and the C0STR register change like (3).
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M16C/1N Group
16. CAN Module
16.12.2 Transmission
Figure 16.25 shows the timing of the transmit sequence.
EOF
IFS
SOF
CANbus
TrmReq
(1)
B(4)
TrmActive
(1)
(2)
(3)
SentData
(3)
Succ. Xmit Int.
(3)
TrmState
(1)
(2)
TrmSucc
MBOX
Transmission slot No.
CAN0 message control register
ACK
CAN0 status register
SOF
i=0 to15
Figure 16.25 Timing of Transmit Sequence
(1) If the TrmReq bit of the C0MCTLi register (i=0 to 15) is set to "1" (Transmission slot) in bus idle
state, the TrmActive bit of the C0MCTLi register and the TrmState bit of the C0STR register are set
to "1" (Transmitting/Transmitter), and the CAN module starts transmitting.
(2) If the arbitration is lost after the CAN module starts transmitting, the TrmActive and TrmState bits
are set to "0".
(3) If the transmission is successful without lost arbitration, the SentData bit of the C0MCTLi register is
set to "1" (Transmission is successfully completed) and TrmActive bit of the C0MCTLj register is
set to "0" (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits of
the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is generated and the MBOX (the slot number which transmitted the message) and TrmSucc bits of the
C0STR register are changed.
(4) When starting the next transmission, set the SentData and TrmReq bits to "0", then set the TrmReq
bit to "1" after checking that the SentData and TrmReq bits are set to "0".
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M16C/1N Group
16. CAN Module
16.13 CAN Interrupts
The CAN module provides the following CAN interrupts.
• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN0 Error Interrupt
Error Passive State
Error BusOff State
Bus Error (this feature can be disabled separately)
• CAN0 Wake Up Interrupt
When the CPU detects a successful reception/transmission interrupt, the C0STR register must be read to
determine which slot has issued the interrupt.
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M16C/1N Group
17. Programmable I/O Ports
17. Programmable I/O Ports
17.1 Description
There are 37 programmable I/O ports: P0 to P5. Each port can be set independently for input or output
using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows
the drive capacity of its N-channel output transistor to be set as necessary. The port P1 can be used as
LED drive port if the drive capacity is set to "HIGH".
Figures 17.1 to 17.4 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to
input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D/A
converter), they function as outputs regardless of the contents of the direction registers. When a pin is to
be used as the output for the D/A converter, do not set the direction register to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
17.1.1 Direction registers
Figure 17.5 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these
registers corresponds one for one to each I/O pin.
17.1.2 Port registers
Figure 17.6 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
17.1.3 Pull-up control registers
Figure 17.7 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When
ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction
register is set for input.
17.1.4 Port P1 drive capacity control register
Figure 17.7 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit
in this register corresponds one for one to the port pins.
17.1.5 CAN0 I/O port selected register
Figure 17.8 shows the CAN0 I/O port selected register.
This register is used to select I/O port for CAN0.
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M16C/1N Group
17. Programmable I/O Ports
P00 to P07, P40, P41
Pull-up selection
Direction register
Port latch
Data bus
(Note 1)
A/D input
Input to respective peripheral functions
P10 to P13
P03 only
Pull-up selection
Direction register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
P1X driving capacity
A/D input
Pull-up selection
P14
Direction register
"1"
output
Port latch
Data bus
(Note 1)
P14 driving capacity
P15
Pull-up selection
Direction register
Data bus
Port latch
(Note 1)
P15 driving capacity
Input to respective peripheral functions
Note 1: Do not apply a voltage higher than Vcc to each port.
Figure 17.1 Programmable I/O ports (1)
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M16C/1N Group
17. Programmable I/O Ports
Pull-up selection
P16, P17
Direction register
"1"
output
Data bus
Port latch
(Note 1)
P1x driving capacity
Input to respective peripheral functions
Pull-up selection
P20, P21
P52
Direction register
Port latch
Data bus
(Note 1)
D/A output enable
P34
Pull-up selection
Direction register
"1"
output
Data bus
Port latch
(Note 1)
Analog input
D/A output enable
Note 1: Do not apply a voltage higher than Vcc to each port.
Figure 17.2 Programmable I/O ports (2)
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M16C/1N Group
17. Programmable I/O Ports
Pull-up selection
P36, P37
Direction register
"1"
output
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Pull-up selection
P30, P31, P32
P50
Direction register
"1"
output
Port latch
Data bus
(Note 1)
Pull-up selection
P33, P35, P42 to P44
P51
Direction register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 1: Do not apply a voltage higher than Vcc to each port.
Figure 17.3 Programmable I/O ports (3)
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M16C/1N Group
17. Programmable I/O Ports
Pull-up selection
P45
Direction register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Digital
filter
Pull-up selection
P47
Direction register
Data bus
Port latch
(Note 1)
fc
Rf
Pull-up selection
P46
Rd
Direction register
"1"
output
Data bus
Port latch
(Note 1)
Note 1:
Figure 17.4 Programmable I/O ports (4)
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page 159 of 222
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
M16C/1N Group
17. Programmable I/O Ports
Port Pi direction register (Note 1, 2, 3)
Symbol
PDi (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Address
00E216, 00E316
00E616
00E716, 00EA16
00EB16
When reset
0016
XXXXXX002
0016
XXXXX0002
Function
Bit name
RW
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
Port Pi3 direction register
PDi_4
Port Pi4 direction register
RW
PDi_5
Port Pi5 direction register
RW
PDi_6
Port Pi6 direction register
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 5)
RW
RW
RW
RW
RW
PDi_7
Port Pi7 direction register
Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P0 direction register.
Note 2: Nothing is assigned in bit 2 to bit 7 of port P2 direction register. When write, set "0". When read, their
contents are "0".
Note 3: Nothing is assigned in bit 3 to bit 7 of port P5 direction register.
When write, set "0".
When read, their contents are "0".
Figure 17.5 Port Pi direction register
Port Pi register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Pi (i = 0 to 5)
Bit symbol
Address
00E016, 00E116, 00E416,
00E516, 00E816, 00E916
Bit name
Function
RW
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : "L" level data
1 : "H" level data
(i = 0 to 5)
RW
Pi_0
Port Pi0 register
Pi_1
Port Pi1 register
Pi_2
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
RW
Pi_6
Port Pi6 register
RW
Pi_7
Port Pi7 register
RW
Note 1: Nothing is assigned in bit 2 to bit 7 of port P2 register.
When write, set "0".
When read, their contents are "0".
Note 2: Nothing is assigned in bit 3 to bit 7 of port P5 register.
When write, set "0".
When read, their contents are "0".
Figure 17.6 Port Pi register
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When reset
Indeterminate
Indeterminate
page 160 of 222
RW
RW
RW
RW
M16C/1N Group
17. Programmable I/O Ports
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Bit symbol
Address
00FC16
Bit name
When reset
00X000002
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
RW
RW
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
RW
PU04
P20 to P21 pull-up
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminate.
The corresponding port is pulled
PU06
P30 to P33 pull-up
high with a pull-up resistor
0 : Not pulled high
PU07
P34 to P37 pull-up
1 : Pulled high
RW
RW
RW
RW
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Bit symbol
Address
00FD16
Bit name
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P52 pull-up
When reset
XXXXX0002
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
RW
RW
RW
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminate.
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRR
Bit symbol
Address
00FE16
Bit name
When reset
0016
Function
RW
DRR0
Port P10 drive capacity
DRR1
Port P11 drive capacity
DRR2
Port P12 drive capacity
DRR3
Port P13 drive capacity
RW
DRR4
Port P14 drive capacity
RW
DRR5
Port P15 drive capacity
RW
DRR6
Port P16 drive capacity
RW
DRR7
Port P17 drive capacity
RW
Set P1 N-channel output
transistor drive capacity
0 : LOW
1 : HIGH
RW
RW
RW
Figure 17.7 Pull-up control register 0, Pull-up control register 1 and Port P1 drive capacity control
register
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M16C/1N Group
17. Programmable I/O Ports
CAN0 I/O pin select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CIOSR
Bit symbol
CIO0C
Address
00F816
Bit name
CAN0 I/O pin
When reset
XXXXXXX02
Function
0 : CTx = P02 pin
CRx = P03 pin
1 : CTx = P50 pin
CRx = P51 pin
Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to this register.
Figure 17.8 CAN0 I/O pin select register
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RW
RW
M16C/1N Group
17. Programmable I/O Ports
17.2 Example connection of unused pins
Table 17.1 shows example connection of unused pins.
Table 17.1 Example connection of unused pins
Pin name
Connection
Ports P0 to P5 (Note 1)
After setting for input mode, connect every pin to VSS (pull-down); or
after setting for output mode, leave these pins open.
XOUT (Note 2)
Open
VREF
Connect to VSS
XIN (Note 3)
Connect to VCC (pull-up) via a resistor
Note 1: Connect unused pins as described above. If connected otherwise, power supply current may
increase due to flow-through current on Schmitt circuit in the port.
Note 2: With external clock input to XIN pin.
Note 3: When the main clock oscillation circuit isn’t used, connect XIN pin to VCC (pull-up), leave XOUT pin
open and set the main clock stop bit (bit 5 at address 000616) to "1" (STOP).
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M16C/1N Group
18. Electrical Characteristics
18. Electrical Characteristics
Table 18.1 Absolute maximum ratings
Symbol
Parameter
Vcc
Supply voltage
VI
Input voltage
Rated value
Unit
- 0.3 to 6.5
V
RESET, VREF, XIN
P00 to P07, P10 to P17, P20, P21,
P30 to P37, P40 to P47, P50 to P52, CNVss (Note 1)
- 0.3 to Vcc + 0.3
V
P00 to P07, P10 to P17, P20, P21, P30 to P37,
P40 to P47, P50 to P52, XOUT
- 0.3 to Vcc + 0.3
V
VO
Output voltage
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Condition
IVCC
Topr = 25 ˚C
Note 1: CNVSS pin of flash memory version: -0.3 to 6.5 V
Note 2: When flash memory version is program/erase mode: 0 to 60 °C
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 164 of 222
- 0.3 to 2.8V
V
300
mW
- 40 to 85 (Note 2)
˚C
- 65 to 150
˚C
M16C/1N Group
18. Electrical Characteristics
Table 18.2 Recommended operating conditions
(Unless otherwise noted: VCC = 4.2V to 5.5V, Topr = -40 to 85oC)
Symbol
Standard
Parameter
Min
Typ.
Max.
4.2
5.0
5.5
Unit
Vcc
Supply voltage
Vss
Supply voltage
VIH
HIGH input
voltage
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52, XIN, RESET, CNVSS
0.8Vcc
Vcc
V
VIL
LOW input
voltage
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52, XIN, RESET, CNVSS
0
0.2Vcc
V
IOH (peak)
HIGH peak
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52
- 10.0
mA
IOH
HIGH average
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52
- 5.0
mA
LOW peak
output current
P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52
10.0
mA
P10 to P17
HIGH POWER
20.0
LOW POWER
10.0
(avg)
IOL (peak)
IOL (avg)
LOW average
output current
0
P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52
P10 to P17
f (XIN)
Main clock input oscillation frequency (Note 3)
f (XcIN)
Subclock oscillation frequency
5.0
HIGH POWER
10.0
LOW POWER
5.0
Vcc=4.2V to 5.5V
0
32.768
V
V
mA
mA
mA
16
MHz
50
kHz
Highest operation frequency [MHz]
Note 1: The average output current is an average value measured over 100ms.
Note 2: Keep output current as follows:
The sum of port P00 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOL (peak) is under 60
mA. The sum of port P00 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOH (peak) is
under 60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOL (peak) is under
60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOH (peak) is under 60
mA.
Note 3: Relationship between main clock oscillation frequency and supply voltage is shown as below.
Main clock input oscillation frequency
16.0
0.0
4.2
Power supply voltage [V]
(Main clock: no division)
Rev.1.00 Oct 20, 2004
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page 165 of 222
5.5
M16C/1N Group
18. Electrical Characteristics
Table 18.3 Electrical characteristics (1)
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC, f(XIN) = 16MHz)
Parameter
Symbol
VOH
VOH
VOH
VOL
VOL
VOL
VOL
VT+ -VT-
Measuring condition
HIGH output P00 to P07,P10 to P17,P20 to P21, IOH = - 5 mA
P30 to P37,P40 to P47,P50 to P52
voltage
IOH = - 200 µA
Min.
Standard
Typ. Max.
3.0
V
4.7
HIGH output XOUT
voltage
HIGH POWER
IOH = - 1 mA
3.0
LOW POWER
IOH = - 0.5 mA
3.0
HIGH output XCOUT
voltage
HIGH POWER
No load
2.5
LOW POWER
No load
1.6
LOW output P00 to P07,P20,P21,P30 to P37,
voltage
P40 to P47,P50 to P52
V
IOL = 5 mA
V
2.0
IOL = 200 µA
0.45
LOW output P10 to P17
voltage
HIGH POWER
IOL = 10 mA
2.0
LOW POWER
IOL = 5 mA
2.0
LOW output XOUT
voltage
HIGH POWER
IOH = 1 mA
2.0
LOW POWER
IOH = 0.5 mA
2.0
LOW output XCOUT
voltage
HIGH POWER
No load
0
LOW POWER
No load
0
Hysteresis
Unit
V
V
V
V
CNTR0,TCIN,
INT0 to INT3,CLK0,CLK1,P45
RxD0,RxD1,KI0 to KI3,CRX0
0.2
0.8
V
0.2
1.8
V
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P20,P21,
VI = 5V
P30 to P37,P40 to P47,P50 to P52,
XIN,RESET,CNVss
5.0
µA
LOW input
current
P00 to P07,P10 to P17,P20,P21,
VI = 0V
P30 to P37,P40 to P47,P50 to P52,
XIN,RESET,CNVss
-5.0
µA
167.0
kΩ
IIL
RPULLUP Pull-up
resistor
P00 to P07,P10 to P17,P20,P21,
VI = 0V
P30 to P37,P40 to P47,P50 to P52
RfXIN
Feedback
resistor
XIN
RfXCIN
Feedback
resistor
XCIN
VRAM
RAM retention voltage
ROSC
Oscillation frequency of
On-chip oscillator
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
When clock is stopped
30.0
50.0
1.0
MΩ
15.0
MΩ
2.0
V
Mask ROM
Flash memory
page 166 of 222
300
600
1200
kHz
M16C/1N Group
18. Electrical Characteristics
Table 18.4 Electrical characteristics (2)
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Parameter
Symbol
Icc
Measuring condition
I/O pin Mask ROM
has no
load
Flash memory
Power supply current
Mask ROM
Min.
f(XIN) = 16 MHz
Square wave, no division
On-chip oscillator mode
No division
Flash memory
Mask ROM
On-chip oscillator mode
When a WAIT instruction
is executed
Flash memory
Mask ROM
f(XCIN) = 32 kHz
Square wave
Flash memory
Mask ROM
Flash memory
Mask ROM
f(XCIN) = 32 kHz
When a WAIT instruction
is executed
f(XCIN) = 32 kHz
When a WAIT instruction
is executed
Topr = 25 ˚C when clock
is stopped
Flash memory
Standard
Typ. Max.
Unit
12.0
22.0
mA
14.0
24.0
mA
300
µA
800
µA
60
µA
100
µA
20
µA
450
µA
2
µA
2
µA
0.8
3
µA
0.8
3
µA
Table 18.5 Power supply timing circuit characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
td(M-L)
Parameter
Timer for internal power supply stabilization during powering-on
Stop release time
Wait release time during low power dissipation mode
Timer for internal power supply stabilization when main clock oscillation starts
Measuring condition
VCC = 4.2 to 5.5 V
Interrupt for
stop or wait mode
release
CPU clock
td(R-S)
td(W-S)
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Min.
Standard
Typ. Max.
Unit
2
ms
150
µs
150
µs
150
µs
M16C/1N Group
18. Electrical Characteristics
Table 18.6 Flash memory version electrical characteristics
(Unless otherwise noted: Vcc = 4.2 to 5.5 V, Topr= 0 to 60oC)
Symbol
Parameter
Erase/write cycle (Note 2)
Word programming time
Block erasing time
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
td(SR-ES) Transition time from erasure operation
to erase-suspend
Data retention
-
Min.
100 (Note 3)
Standard
Typ. (Note 1)
75
0.2
0.4
0.7
1.2
10
Max.
Unit
600
9
9
9
9
cycle
µs
s
s
s
s
20
ms
year
Note1: Vcc=5.0V, Topr=25˚C
Note2: Definition of Programming and erasure times
The Programming and erasure times are defined to be per-block erasure times. For example a case where a 2Kbyte block is programmed in 1,024 operations by writing one word at a time and erased thereafter. Performing
multiple programs to the same address before an erase operation is prohibited.
Note 3: Minimum number of programming/erasure for which operation is guaranteed.
Erasure-suspend
request
(Interrupt request)
FMR46
td(SR-ES)
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REJ09B0007-0100Z
page 168 of 222
M16C/1N Group
18. Electrical Characteristics
Table 18.7 A/D conversion characteristics
(Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Symbol
Parameter
Measuring condition
Min.
Resolution
VREF =VCC
Absolute Sample & hold function not available
VREF =VCC = 5V
accuracy Sample & hold function available(10bit) VREF =VCC = 5V AN0 to AN11 input
ANEX0, ANEX1 input,
external op-amp
connected mode
Sample & hold function available(8bit) VREF =VCC = 5V
Standard
Typ. Max.
10
Unit
±3
±3
Bits
LSB
LSB
±7
LSB
±2
LSB
RLADDER
Ladder resistance
VREF =VCC
10
tCONV
Conversion time(10bit)
f(XIN)=10MHz, ØAD=fAD=10MHz
3.3
µs
tCONV
tSAMP
VREF
Conversion time(8bit)
Sampling time
Reference voltage
f(XIN)=10MHz, ØAD=fAD=10MHz
f(XIN)=10MHz, ØAD=fAD=10MHz
2.8
0.3
µs
µs
f(XIN)=10MHz, ØAD=fAD=10MHz
2
VCC
V
VIA
Analog input voltage
f(XIN)=10MHz, ØAD=fAD=10MHz
0
VREF
V
40
k
Note 1: Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (ØAD) equal to or
lower than 10MHz.
Table 18.8 D/A conversion characteristics
(Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note 1)
Standard
Typ. Max.
8
1.0
3
10
20
1.5
Unit
Bits
%
µs
k
mA
Note 1: The A/D converter's ladder resistance is not included.
When D/A register contents are not "0016", the current IVREF always flows even though VREF may
have been set to be unconnected by the A/D control register.
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 169 of 222
M16C/1N Group
18. Electrical Characteristics
18.1 Timing requirements
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC)
Table 18.9 XIN input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(XIN)
XIN input cycle time
62.5
ns
twH(XIN)
twL(XIN)
XIN input HIGH pulse width
30
ns
XIN input LOW pulse width
30
ns
Table 18.10 CNTR0 input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
100
40
ns
twH(CNTR0)
twL(CNTR0)
CNTR0 input LOW pulse width
40
ns
ns
Table 18.11 TCIN input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TCIN)
TCIN input cycle time
TCIN input HIGH pulse width
400(Note 1)
200(Note 2)
ns
twH(TCIN)
twL(TCIN)
TCIN input LOW pulse width
200(Note 2)
ns
ns
Note 1: Use the greater value, either (1/digital filter clock frequency X 6) or min. value.
Note 2: Use the greater value, either (1/digital filter clock frequency X 3) or min. value.
Table 18.12 Serial I/O
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
200
100
ns
tw(CKH)
tw(CKL)
CLKi input LOW pulse width
100
ns
td(C-Q)
th(C-Q)
TxDi output delay time
tsu(D-C)
th(C-D)
ns
80
ns
0
ns
RxDi input setup time
30
ns
RxDi input hold time
90
ns
TxDi hold time
_______
Table 18.13 External interrupt INTi input
Symbol
tw(INH)
tw(INL)
Standard
Min.
Max.
Parameter
250(Note 1)
250(Note 2)
INTi input HIGH pulse width
INTi input LOW pulse width
_______
Unit
ns
ns
_______
Note 1: When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width
to the greater value, either (1/digital filter clock frequency X 3) or min. value.
_______
_______
Note 2: When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pulse width to
the greater value, either (1/digital filter clock frequency X 3) or min. value.
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 170 of 222
M16C/1N Group
18. Electrical Characteristics
P0
30pF
P1
P2
P3
P4
P5
Figure 18.1 Port P0 to P5 measurement circuit
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 171 of 222
M16C/1N Group
18. Electrical Characteristics
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
tsu(D-C)
td(C-Q)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 18.2 Vcc=5V timing diagram
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 172 of 222
th(C-D)
M16C/1N Group
19. Flash Memory Version
19. Flash Memory Version
19.1 Overview
The flash memory version has four modes—CPU rewrite, standard serial input/output (hereinafter referred to as standard serial I/O), parallel input/output (hereinafter referred to as parallel I/O), and CAN
input/output (hereinafter referred to as CAN I/O) modes—in which its internal flash memory can be operated on.
Table 19.1 shows the outline performance of flash memory version and Table 19.2 shows the outline of
flash memory rewrite mode. (see Table 1.1 Performance outline for the items not listed in Table 19.1).
Table 19.1 Outline performance of flash memory version
Item
Performance
Flash memory operation mode
Four modes (CPU rewrite, parallel I/O, standard serial I/O and CAN I/O)
Erase block division
See Figure 19.1 Outline performance of flash memory version
Program method
In units of word, in units of byte (Note 1)
Erase method
Block erase
Program, erase control method Program and erase controlled by software command
Protect method
Block 0 and 1 are protected by register rewrite (FMR02)
Block 0 to 3 are protected by register rewrite enable bit (FMR16)
Number of commands
5 commands
100 times
Block 0 to 3
Program, erase
Block A and B
count
100 times
(Data area)
Data retention
10 years
ROM code protect
Parallel I/O, standard serial I/O and CAN I/O modes are supported
Note 1: Can be programmed in byte units in only parallel I/O mode.
Table 19.2 Outline of flash memory rewrite mode
Flash memory
rewrite mode
Function
Standard serial I/O
mode
CPU rewrite mode
Parallel I/O mode
The user ROM area is
rewritten by executing
software commands
from the CPU.
EW0 mode:
Can be rewritten in
any area other than
the flash memory
EW1 mode:
Can be rewritten in
the flash memory
User ROM area
The user ROM area is
rewritten by using a
dedicated parallel programmer.
The user ROM area is
rewritten by using a
dedicated serial programmer.
Standard serial I/O mode 1:
Clock sync. serial I/O
Standard serial I/O mode 2
(Note 1): UART
The user ROM area is
rewritten by using a
dedicated CAN programmer.
User ROM area,
Boot ROM area
Parallel I/O mode
User ROM area
User ROM area
Boot mode
Boot mode
Parallel programmer
Serial programmer
CAN programmer
Areas which
can be rewritten
Operation
Single chip mode
mode
ROM
None
programmer
CAN I/O mode
Note 1: When using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is
set to 10 or 16 MHz.
Rev.1.00 Oct 20, 2004
REJ09B0007-0100Z
page 173 of 222
M16C/1N Group
19. Flash Memory Version
19.2 Flash Memory
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 19.1 shows the block diagram of flash memory. The user ROM area has 2K-byte block A and B, in
addition to the area that stores a program for microcomputer operation during singe-chip mode.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in all of CPU
rewrite, standard serial I/O, parallel I/O and CAN I/O modes. Block 0 and 1 can be rewritten by setting
FMR0 register's FMR02 bit to "1" and the FMR1 register's FMR16 bit to "1" in CPU rewrite mode only.
Block 2 and 3 can be rewriting by setting the FMR 1 register's FMR 16 bit to "1". Block A and B are
enabled for use by setting the PM1 register's PM10 bit to "1".
The boot ROM area is reserved area. A rewrite control program for standard serial I/O and CAN I/O
modes is written into the boot ROM area when the device is shipped from the factory. The boot ROM area
can be rewritten in parallel I/O mode.
00F00016
Block A : 2K bytes (Note 2)
Block B : 2K bytes (Note 2)
00FFFF16
Data ROM area
0F000016
Block 3 : 32K bytes (Note 5)
0F7FFF16
0F800016
Block 2 : 16K bytes (Note 5)
0FBFFF16
0FC00016
Note 1: To specify a block, use an even address in that block.
Note 2: Block A and B can be mode usable by setting the PM1 register’s PM10 bit to "1".
Note 3: Block 0 and 1 can be rewritten by setting FMR0 register’s FMR02 bit to "1" and the FMR
1 register’s FMR16 bit to "1" in CPU rewrite mode only. Block 2 and 3 can be rewriting
by setting the FMR1 register’s FMR16 bit to "1".
Note 4: The boot ROM area is reserved area. This area can be rewritten in parallel I/O mode.
Note 5: Block 2 and 3 can be rewriting by setting the FMR1 register’s FMR16 bit to "1" (in CPU
rewrite mode only).
Block 1 : 8K bytes (Note 3)
0FDFFF16
0FE00016
Block 0 : 8K bytes (Note 3)
0FF00016
4K bytes (Note 4)
0FFFFF16
0FFFFF16
User ROM area (Note 1)
Figure 19.1 Block diagram of flash memory
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REJ09B0007-0100Z
page 174 of 222
Boot ROM area (Reserved area)
M16C/1N Group
19. Flash Memory Version
19.3 Functions to Inhibit Rewriting Flash Memory Version
To prevent the flash memory from being read or rewritten easily, parallel I/O mode has a ROM code
protect and standard serial I/O and CAN I/O modes have an ID code check function.
19.3.1 ROM code protect function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
I/O mode. Figure 19.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM
code protect function is enabled by clearing one or both of two ROMCP1 bits to "0" when the ROMCR
bits are not '002,' with the flash memory thereby protected against reading or rewriting. Conversely,
when the ROMCR bits are '002' (ROM code protect removed), the flash memory can be read or
rewritten. Once the ROM code protect function is enabled, the ROMCR bits cannot be changed during
parallel I/O mode. Therefore, use standard serial I/O or other modes to rewrite the flash memory.
19.3.2 ID code check function
Use this function in standard serial I/O and CAN I/O modes. Unless the flash memory is blank, the ID
codes sent from the programmer and the ID codes written in the flash memory are compared to see if
they match. If the ID codes do not match, the commands sent from the programmer are not accepted.
The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16,
0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which
the ID codes are preset at these addresses and write it in the flash memory.
Figure 19.3 shows ID code store addresses.
Rev.1.00 Oct 20, 2004
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M16C/1N Group
19. Flash Memory Version
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ROMCP
1 1 1 1
Address
0FFFFF16
Bit name
Bit symbol
(b3-b0)
ROMCR
ROMCP1
Value when shipped
FF16 (Note 1)
Function
Reserved bit
Set this bit to "1"
ROM code protect reset bit
(Note 1, 2)
ROM code protect level
1 set bit (Note 1, 3, 4)
RW
RW
b5 b4
0 0 : Removes protect
01:
1 0 : Enables ROMCP1 bit
11:
}
RW
RW
b7 b6
00:
Protect enabled
01:
10:
1 1 : Protect disabled
}
RW
RW
Note 1: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that contains the
ROMCP register is erased, the ROMCP register is set to ’FF16’.
Note 2: If the ROMCR bits are set to ’002’ when the ROMCR bits are other than ’002’ and the ROMCP1 bits are other than ’112’, ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified
during parallel I/O mode, they need to be modified in standard serial I/O or other modes.
Note 3: If the ROMCR bits are set to other than ’002’ and the ROMCP1 bits are set to other than ’112’ (ROM code
protect enabled), the flash memory is disabled against reading and rewriting in parallel I/O mode.
Note 4: The ROMCP1 bits are effective when the ROMCR bits are ’012’, ’102’, or ’112’.
Figure 19.2 ROMCP register
Address
0FFFDC16 to 0FFFDF16
ID1 Undefined instruction vector
0FFFE016 to 0FFFE316
ID2 Overflow vector
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16
ID3 Address match vector
0FFFEC16 to 0FFFEF16
ID4 Single step vector
0FFFF016 to 0FFFF316
ID5 Watchdog timer vector
0FFFF416 to 0FFFF716
ID6 DBC vector
0FFFF816 to 0FFFFB16
ID7 UART0 receive vector
0FFFFC16 to 0FFFFF16
Reset vector
4 bytes
Figure 19.3 ID code store addresses
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M16C/1N Group
19. Flash Memory Version
19.4 Boot Mode
_____
When the microcomputer is reset by applying a high-level signal to the CNVSS and CE pins, it is placed in
boot mode, thereby executing the program in the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR0 register's FMR05
bit.
Rev.1.00 Oct 20, 2004
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M16C/1N Group
19. Flash Memory Version
19.5 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the
CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted onboard without having to use a ROM programmer, etc.
Make sure the program and the block erase commands are executed only on each block in the user ROM area.
When generating an interrupt request during erasure operation in CPU mode, the M16C/1N Group flash
memory can offer the erasure-suspend feature which allows erasure operation to be suspended and to
process the interrupt. User ROM area can be read in a program during erasure-suspend.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or
Erase Write 1 (EW1) mode. Table 19.3 lists the differences between Erase Write 0 (EW0) and Erase
Write 1 (EW1) modes.
Table 19.3 Differences between EW0 mode and EW1 mode
Item
Operation mode
Areas in which a
rewrite control
program can be located
Areas in which a
rewrite control
program can be executed
Areas which can be
rewritten
Software command
limitations
Modes after Program or
Erase
CPU status during Auto
Write and Auto Erase
EW0 mode
• Single chip mode
• User ROM area
EW1 mode
Single chip mode
User ROM area
Must be transferred to any area other Can be executed directly in the user
than the flash memory (e.g., RAM)
ROM area
before being executed
User ROM area (Note 1)
User ROM area (Note 1)
However, this does not include the area
in which a rewrite control program
exists
None
• Program, Block Erase command
Cannot be executed on any block in
which a rewrite control program exists
• Read Status Register command
Cannot be executed
Read Status Register mode
Read Array mode
Operating
Flash memory status
detection
Hold state (I/O ports retain the state in
which they were before the command
was executed)(Note 2)
Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a program
• Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
The shift conditions to
Set the FMR4 register's FMR40 and The FMR register's FMR40 bit is "1" and
erasure-suspend (Note 3) RMR41 bits to "1" by program.
generated the interrupt request of
enabled interrupt.
Note 1: Can be rewritten block 0 and 1 when setting the FMR0 register's FMR02 bit to "1" and the FMR1 register's
FMR16 bit to "1". Block 2 and 3 can be rewriting by setting the FMR1 register's FMR16 bit to "1".
Note 2: Make sure no interrupts will occur.
Note 3: The conditions are met and it takes a maximum of td(SR-ES) time until a flash memory can be
read after shifting to erasure-suspend.
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19. Flash Memory Version
19.5.1 EW0 mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register's FMR01 bit to "1"
(CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's
FMR11 bit = 0, EW0 mode is selected. The FMR01 bit can be set to "1" by writing "0" and then "1" in
succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
When shifting to erasure-suspend during auto erasing, set the FMR40 bit to "1" (Suspend enable) and
the FMR41 bit to "1" (Suspend request).
After waiting for td (SR-ES) time, access user ROM area after confirming that the FMR46bit has been
set to "1" (Erase inactive).
Setting the FMR41 bit to "0" (Erase restart), the erasure operation is resumed.
19.5.2 EW1 mode
EW1 mode is selected by setting FMR11 bit to "1" (by writing "0" and then "1" in succession) after
setting the FMR01 bit to "1" (by writing "0" and then "1" in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.
When enabling the erasure-suspend feature, execute the block erase command after setting the
FMR40 bit to "1" (Suspend enable).
In addition, the interrupt for shifting to erasure suspend has to have been enabled beforehand.
When shifting to erasure-suspend after td (SR-ES) time from interrupt request, the interrupt request is
accepted.
When the interrupt request occurs, the FMR41bit is set to "1" (Suspend request) automatically and
erasure operation is suspended.
After processing the interrupt, when the FM00 bit is "0" (Busy (being erased)), set the FMR41 bit to "0"
and re-execute the block erase command.
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19. Flash Memory Version
Figure 19.4 shows the FMR0 register and Figure 19.5 shows the FMR1 and FMR4 registers.
(1) FMR00 bit
This bit indicates the operating status of the flash memory. The bit is "0" when the program or erase
program is running; otherwise, the bit is "1".
(2) FMR01 bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to "1" (CPU rewrite mode).
During boot mode, make sure the FMR05 bit also is "1" (user ROM area access).
(3) FMR02 bit
Block 0 and 1 do not accept the program or erase command while the FMR02 bit is set to "0" (inhibit
rewriting).
(4) FMSTP bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount
of current consumed in the flash memory. The internal flash memory cannot be accessed by setting
the FMSTP bit to "1". Therefore, the FMSTP bit must be written to by a program in a memory area
other than the flash memory.
In the following cases, set the FMSTP bit to "1":
• When flash memory access resulted in an error while erasing or programming in EW0 mode
(FMR00 bit not reset to "1" (ready))
• When entering low power mode or on-chip oscillator low power mode
Figure 19.7 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the
power for the internal flash memory is automatically turned off and is turned back on again after
returning from stop or wait mode.
(5) FMR05 bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to "0"
when accessing the boot ROM area (for read) or "1" (user ROM access) when accessing the user
ROM area (for read, write or erase).
(6) FMR06 bit
This is a read-only bit indicating the status of auto program operation. The bit is set to "1" when a
program error occurs; otherwise, it is cleared to "0". For details, refer to the description of 19.5.6 Full
Status Check.
(7) FMR07 bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to "1" when an erase error
occurs; otherwise, it is cleared to "0". For details, refer to the description of 19.5.6 Full Status Check.
(8) FMR11 bit
Setting this bit to "1" places the microcomputer in EW1 mode. This bit is relevant if the FMR01 bit is set.
(9) FMR16 bit
When the FMR16bit is "0" (Rewrite disable), the block 0-3 don't accept the program and the block
erase commands. This bit is relevant if the FMR01 bit is set.
(10) FMR 40bit
When setting the FMR40 bit to "1", the erasure-suspend feature is enabled.
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19. Flash Memory Version
(11) FMR 41bit
In EW0 mode, when setting the FMR41 bit to "1" by software during auto erasing, the microcomputer
shifts to the erasure-suspend mode.
In EW1 mode, when occurring the enabled interrupt request, the FMR 41bit changes to "1" (Suspendrequest) automatically and the microcomputer shifts to the erasure-suspend mode.
Setting the FMR41 bit to "0" (Erase restart), auto erasing is resumed.
(12) FMR46bit
The FMR46 bit is "0" during auto erasing and is "1" during the erasure-suspend mode.
The internal flash memory is banned to access while the FMR41 bit is "0".
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
0 0
Bit symbol
Address
01B716
After reset
XX0000012
Bit name
Function
RW
FMR00
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
RO
FMR01
CPU rewrite mode select bit
(Note 1)
0 : Disables CPU rewrite mode
1 : Enables CPU rewrite mode
RW
FMR02
Block 0, 1
rewrite-enable bit (Note 2)
0 : Disables rewriting
1 : Enables rewriting
RW
FMSTP
Flash memory stop bit
(Note 3, 4)
0 : Enables flash memory operation
1 : Stops flash memory operation
(placed in low power mode,
flash memory initialized)
RW
(b4)
Reserved bit
Set to "0"
RW
FMR05
User ROM area select bit
(Effective in only boot mode)
(Note 3)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
RW
FMR06
Program status flag (Note 5)
0 : Terminated normally
1 : Terminated in error
RO
FMR07
Erase status flag (Note 5)
0 : Terminated normally
1 : Terminated in error
RO
Note 1: When setting this bit to "1", write a "0" and then a "1" in to it in succession. Make sure no interrupts will occur
before completion of these two write operations.
In EW0 mode, write this bit by a program placed to an area other than internal flash memory.
Set this bit to "0" after placing in read array mode.
Note 2: When setting this bit to "1", write a "0" and then a "1" in to it in succession while the FMR01 bit is "1". Make sure
no interrupts will occur before completion of these two write operations.
Note 3: Write this bit by a program placed to an area other than internal flash memory.
Note 4: This bit is valid when the FMR01 bit is "1" (CPU rewrite mode). When the FMR01 bit is "0", although the FMSTP
bit can be set to "1" by writing "1" in a program, the flash memory is not initialized.
Note 5: This bit is cleared to "0" by executing the clear status command.
Figure 19.4 FMR0 Register
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19. Flash Memory Version
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR1
0 0
Bit symbol
Address
01B516
Bit name
Reserved bit
(b0)
FMR11
After reset
0000XX0X2
EW1 mode select bit
(Note 1)
Function
The value in this bit when read is
indeterminate.
0 : EW0 mode
1 : EW1 mode
RW
RO
RW
Reserved bit
The value in this bit when read is
indeterminate.
RO
(b5-b4)
Reserved bit
Set to "0"
RW
FMR16
Block 0-3 rewrite enable bit
(Note 2)
0 : Disables rewriting
1 : Enables rewriting
RW
(b7)
Reserved bit
Set to "0"
RW
(b3-b2)
Note 1: When setting this bit to "1", write a "0" and then a "1" in succession while the FMR01 bit is "1". Make sure no
interrupts will occur before completion of these two write operations.
The FMR01 and FMR11 bits both are cleared to "0" by setting the FMR01 bit to "0".
Note 2: When setting this bit to "1", write a "0" and then a "1" to it in succession while the FMR01 bit is "1". Make sure
no interrupts will occur before completion of these two write operations.
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR4
0 0 0 0
Bit symbol
Address
01B316
After reset
010000002
Bit name
Function
Suspend enable bit (Note 1)
FMR41
Suspend request bit (Note 2)
(b5-b2)
Reserved bits
Set to "0"
RO
FMR46
Suspend status
0 : Erase active
1 : Erase inactive
(erasure-suspend)
RO
Set to "0"
RW
(b7)
Reserved bit
0 : Invalid
1 : Valid
0 : Erase restart
1 : Suspend request
RW
FMR40
RW
RW
Note 1: When setting this bit to "1", write a "0" and then a "1" to it in succession. Make sure no interrupts will occur
before completion of these two write operations.
Note 2: This bit is valid only when the FMR40 bit is "1" and can be written in only the period from issuing an erase
command until completion of erasing.
• In EW0 mode, this bit can be set to "0" or "1" by program.
• In EW1 mode, this bit is automatically set to "1" when a maskable interrupt occurs during erasure execution
while the FMR40 bit is "1". It can not be set to "1" by program. (Writing "0" is available.)
Figure 19.5 FMR1 Register, FMR4 Register
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19. Flash Memory Version
Figure 19.6 and 19.7 show the setting and resetting of EW0 mode and EW1 mode, respectively. Figure
19.8 shows the processing before and after low power dissipation mode.
EW0 mode operation procedure
Rewrite control program
Single-chip mode
Set CM0, CM1, and PM1 registers (Note 1)
Transfer a CPU rewrite mode based rewrite control
program to any area other than the flash memory
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory)
For only boot mode
Set the FMR05 bit to "1"
(User ROM area access)
Set the FMR01 bit by writing "0" and then "1"
(CPU rewrite mode enabled) (Note 2)
Execute software commands
Execute the read array command (Note 3)
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write "0" to the FMR05 bit
(Boot ROM area accessed) (Note 4)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits.
Also, set the PM1 register’s PM17 bit to "1" (with wait state).
Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no interrupts will occur before
writing "1" after writing "0".
Write to the FMR01 bit by a program in a memory area other than the flash memory.
Note 3: Disables the CPU rewrite mode after executing the read array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to "1".
Figure 19.6 Setting and resetting of EW0 mode
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19. Flash Memory Version
EW1 mode operation procedure
Program in ROM
Single-chip mode
Set CM0, CM1, and PM1 registers (Note 1)
Set the FMR01 bit by writing "0" and then "1" (CPU
rewrite mode enabled)
Set the FMR11 bit by writing "0" and then "1" (EW1
mode) (Note 2)
Execute software commands
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to "1" (with wait
state).
Note 2: To set the FMR01 bit to "1", write "0" and then "1" in succession. Make sure no
interrupts will occur before writing "1" after writing "0".
Figure 19.7 Setting and resetting of EW1 mode
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19. Flash Memory Version
Low power dissipation
mode program
Transfer a low power dissipation mode program
to any area other than the flash memory
Set the FMR01 bit by writing "0" and then "1"
(CPU rewrite mode enabled)
Jump to the low power dissipation mode program
which has been transferred to any area other than
the flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.)
Set FMSTP bit to "1"
(flash memory stopped. Low power state) (Note 1)
Switch the clock source for CPU clock.
Turn XIN off. (Note 2)
Process of low power dissipation mode or
on-chip oscillator low power dissipation mode
Turn XIN on
wait until oscillation stabilizes
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to "0" (flash memory operation)
Write "0" to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes
(10 µs) (Note 3)
Jump to a specified address in the flash memory
Note 1: Set the FMSTP bit to "1" after setting the FMR01 bit to "1".
Note 2: Before the clock source for CPU clock can be changed, the clock to which to be changed must be stable.
Note 3: Insert a 10 µs wait time in a program. The flash memory cannot be accessed during this wait time.
Figure 19.8 Processing before and after low power dissipation mode
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19. Flash Memory Version
19.5.3 Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM0 register's CM06 bit and CM1 register's CM17–6 bits. Also, set the PM1 register's PM17 bit to "1"
(with wait state).
(2) Instructions inhibited against use
In EW0 mode, the following instructions cannot be used because the flash memory's internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts
EW0 mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
• The watchdog timer interrupt can be used because the FMR0 register and FMR1 register are
initialized when one of those interrupts occurs. However, it is necessary that the jump addresses
for those interrupts are set in the fixed vector table, and that interrupt service routines are available
for those interrupts.
Because the rewrite operation is halted when a watchdog timer interrupt occurs, the FMR01 bit
must be set back to "1" again in order to enable erase or programming operation after exiting the
interrupt service routine.
• The address match interrupt cannot be used because the flash memory's internal data is referenced.
EW1 mode
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
(4) How to access
To set the FMR01, FMR02, or FMR11 bit to "1", write "0" and then "1" in succession. This is necessary
to ensure that no interrupts will occur before writing "1" after writing "0".
(5) Writing in the user ROM area
If the power supply voltage drops while rewriting in EW0 mode any block in which the rewrite control
program is stored, a problem may occur that the rewrite control program is not correctly rewritten and,
consequently, the flash memory becomes unable to be rewritten thereafter. It is recommended that
such a block be rewritten using standard serial I/O, CAN I/O or parallel I/O mode.
(6) Writing command and data
Write the command code and data at even addresses.
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19. Flash Memory Version
(7) Wait mode
When shifting to wait mode, set the FMR01 bit to "0" (CPU rewrite mode disabled) before executing
the WAIT instruction.
(8) Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to "0" (CPU rewrite mode disabled) and setting the CM10 bit to "1" (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to "1" (stop
mode)
Example program
BSET
0, CM1
; Stop mode
JMP.B
L1
L1:
Program after returning from stop mode
(9) Low power dissipation mode, on-chip oscillator low power dissipation mode
If the CM05 bit is set to "1" (main clock stop), the following commands must not be executed.
• Program
• Block erase
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19. Flash Memory Version
19.5.4 Software Commands
Software commands are described below. The command code and data must be read and written in
16 bit units, to and from even addresses in the user ROM area. When writing command code, the 8
high-order bits (D15-D8) are ignored.
Table 19.4 shows the list of software commands.
Table 19.4 List of software commands
First bus cycle
Software Command
Second bus cycle
Mode
Address
Data
(D15-D0)
Mode
Address
Data
(D15-D0)
Read array
Write
X
xxFF16
Read status register
Write
X
xx7016
Read
X
SRD
Clear status register
Write
X
xx5016
Program
Write
WA
xx4016
Write
WA
WD
Block erase
Write
X
xx2016
Write
BA
xxD016
SRD: Status register data (D7-D0)
WA: Write address (even address, however)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
x: High-order 8 bits of command code (ignored)
(1) Read array
This command reads the flash memory.
Writing 'xxFF16' in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16 bit units.
Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession.
(2) Read status register
This command reads the status register.
Write 'xx7016' in the first bus cycle, and the status register can be read in the second bus cycle (refer
to 19.5.5 Status Register). When reading the status register too, specify an even address in the user
ROM area.
Do not execute this command in EW1 mode.
(3) Clear status register
This command clears the status register to "0".
Write 'xx5016' in the first bus cycle, and the FMR0 register's FMR06 to FMR07 bits and the status
register's SR4 to SR5 will be cleared to "0".
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19. Flash Memory Version
(4) Program
This command writes data to the flash memory in 1 word (2 byte) units.
Write 'xx4016' in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR0 register's FMR00 bit to see if auto programming has finished. The FMR00 bit is "0"
during auto programming and set to "1" when auto programming is completed.
Check the FMR0 register's FMR06 bit after auto programming has finished, and the result of auto
programming can be known (refer to 19.5.6 Full Status Check).
Figure 19.9 shows an example of program flowchart.
Writing over already programmed addresses is inhibited.
Also, block 0 to 3 do not accept the program command while the FMR 1 register's FMR 16 bit is "0"
and the FMR0 register's FMR02 bit is "0" (Inhibit rewriting.)
To execute another command immediately after the program command, use the same write address
that was specified in the second bus cycle of the program command for the address value to be
specified in the first bus cycle of the next command.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to
"0" at the same time auto programming starts, and set back to "1" when auto programming finishes. In
this case, the microcomputer remains in read status register mode until a read command is written
next. The result of auto programming can be known by reading the status register after auto programming has finished.
Start
Write the command code ’xx4016’
to the write address (Note 1)
Write data to the write address
(Note 1)
FMR00=1?
NO
YES
Full status check (Note 2)
Program
completed
Note 1: Write the command code and data at even number.
Note 2: See Figure 19.12 Full status check flowchart, handling each error generated.
Figure 19.9 Program flowchart
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19. Flash Memory Version
(5) Block erase
Write 'xx2016' in the first bus cycle and write 'xxD016' to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register's FMR00 bit to see if auto erasing has finished.
The FMR00 bit is "0" during auto erasing and set to "1" when auto erasing is completed.
In EW0 mode, when using the erasure suspend feature, confirm the FMR4 register's FMR46 bit
whether it has shifted to erasure suspend.
The FMR46 bit is "0" during auto erasing and is set to "1" when auto erasing is suspended (shift to
erasure suspend).
Check the FMR0 register's FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known (refer to 19.5.6 Full Status Check).
Also, block 0 and 1 do not accept the block erase command while the FMR0 register's FMR02 bit is set
to "0" (Inhibit rewriting.)
Figure 19.10 shows an example of a block erase flowchart when not using the erasure suspend
feature and Figure 19.11 shows an example of a block erase flowchart when using the erasure suspend feature.
In EW1 mode, do not execute this command on any address at which the rewrite control program is located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to "0" at
the same time auto erasing starts, and set back to "1" when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the read array command is written next. In
addition, when the erase error occurred, repeat the operation executing the clear status register command and then the block erase command in succession at least 3 times until the error is eliminated.
Start
Write the command code ’xx2016’
(Note 1)
Write ’xxD016’ to the uppermost
block address (Note 1)
FMR00=1?
NO
YES
Full status check (Note 2, 3)
Block erase completed
Note 1: Write the command code and data at even number.
Note 2: See Figure 19.12 Full status check flowchart, handling each error generated.
Note 3: When the erase error occurred, repeat the operation executing the clear status register command
and then the block erase command in succession at least 3 times until the error is eliminated.
Figure 19.10 Block erase flowchart (when not using the erasure suspend feature)
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19. Flash Memory Version
(EW0 mode)
Start
Interrupt (Note 4)
FMR40=1
FMR41=1
Write the command code ’xx2016’
(Note 1)
Write ’xxD016’ to uppermost block
address (Note1)
FMR46=1?
NO
YES
Access to flash memory
FMR00=1?
NO
FMR41=0
YES
Full status check (Note 2, 3)
REIT
Block erase completed
(EW1 mode)
Start
Interrupt (Note 4)
FMR40=1
Access to flash memory
Write the command code ’xx2016’
(Note 1)
REIT
Write ’xxD016’ to the uppermost
block address (Note 1)
FMR41=0
FMR00=1?
NO
YES
Full status check (Note 2, 3)
Block erase completed
Note 1: Write the command code and data at even number.
Note 2: See Figure 19.12 Full status check flowchart, handling each error generated.
Note 3: When the erase error occurred, repeat the operation executing the clear status register
command and then the block erase command in succession at least 3 times until the error is
eliminated.
Note 4: In EW0 mode, allocate the interrupt vector table of used interrupt to the internal RAM.
Figure 19.11 Block erase flowchart (when using the erasure suspend feature)
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19. Flash Memory Version
19.5.5 Status Register
The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by
reading the FMR0 register's FMR00, FMR06, and FMR07 bits.
Table 19.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
• When a given even address in the user ROM area is read after writing the Read Status Register
command
• When a given even address in the user ROM area is read after executing the program, or block erase
command but before executing the read array command.
(1) Sequencer status (SR7 and FMR00 bits )
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming and auto erase is set to "1" (ready) at the same time the operation finishes.
(2) Erase status (SR5 and FMR07 bits)
Refer to 19.5.6 Full status check.
(3) Program status (SR4 and FMR06 bits)
Refer to 19.5.6 Full status check.
Table 19.5 Status register
Status
register
bit
SR7 (D7)
FMR0
register
bit
FMR00
SR6 (D6)
Contents
Status name
Sequencer status
Reserved
"0"
"1"
Busy
Ready
-
-
Value
after
reset
1
SR5 (D5)
FMR07
Erase status
Terminated normally
Terminated in error
0
SR4 (D4)
FMR06
Program status
Terminated normally
Terminated in error
0
SR3 (D3)
Reserved
-
-
SR2 (D2)
Reserved
-
-
SR1 (D1)
Reserved
-
-
SR0 (D0)
Reserved
-
-
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to "0" by executing the clear status register
command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the program, block and erase commands are not
accepted.
• D0-D7: Indicates the data bus which is read out when the read status register command is executed.
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M16C/1N Group
19. Flash Memory Version
19.5.6 Full Status Check
When an error occurs, the FMR0 register's FMR06 to FMR07 bits are set to "1", indicating occurrence
of each specific error. Therefore, execution results can be verified by checking these status bits (full
status check).
Table 19.6 lists errors and FMR0 register status. Figure 19.12 shows a full status check flowchart and
the action to be taken when each error occurs.
Table 19.6 Errors and FMR0 register status
FRM00 register
(status register)
status
Error
Error occurrence condition
FMR07
FMR06
(SR5)
(SR4)
1
1
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be written in the second bus cycle of the block erase command (i.e.,
other than 'xxD016' or 'xxFF16') (Note 1)
1
0
Erase error
• When the block erase command was executed on locked blocks
but the blocks were not automatically erased correctly.
0
1
Program error • When the program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
Note 1: Writing 'xxFF16' in the first bus cycle places the microcomputer in read array mode.
Simultaneously, the command code written in the first cycle becomes invalid.
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M16C/1N Group
19. Flash Memory Version
Full status check
FMR06 =1
and
FMR07=1?
YES
Command
sequence error
(1) Execute the clear status register command to clear
these status flags to "0".
(2) Reexecute the command after checking that it is
entered correctly.
NO
FMR07=0?
NO
Erase error
YES
FMR06=0?
NO
YES
Program error
(1) Execute the clear status register command to clear
the erase status flag to "0".
(2) Reexecute the block erase command.
(3) Repeat the operation executing (1) and (2) at least
3 times until the error is eliminated.
Note 1: If the error still occurs, the block in error
cannot be used.
[During programming]
(1) Execute the clear status register command to clear
the erase status flag to "0".
(2) Reexecute the program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Full status check completed
Note 3: If FMR06 or FMR07 = 1, the program, or block erase command is not accepted.
Execute the clear status register command before executing those commands.
Figure 19.12 Full status check flowchart, handling each error generated
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M16C/1N Group
19. Flash Memory Version
19.6 Parallel Input/Output Mode
In parallel I/O mode, the user ROM area can be rewritten by using a parallel programmer suitable for the
M16C/1N group. For more information about parallel programmers, contact the manufacturer of your
parallel programmer. For details on how to use, refer to the user's manual included with your parallel
programmer.
19.6.1 ROM code protect function
The ROM code protect function inhibits the flash memory from being read or rewritten. (refer to the
description of 19.3 Functions to Inhibit Rewriting Flash Memory Version).
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M16C/1N Group
19. Flash Memory Version
19.7 Standard Serial Input/Output Mode
In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted onboard by using a serial programmer suitable for the M16C/1N group. For more information about serial
programmers, contact the manufacturer of your serial programmer. For details on how to use, refer to the
user's manual included with your serial programmer.
There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2,
which is asynchronized.
Table 19.7 lists pin functions (flash memory standard serial I/O mode). Figure 19.13 shows pin connections for standard serial I/O mode.
19.7.1 ID code check function
This function determines whether the ID codes sent from the serial programmer and those written in
the flash memory match (refer to the description of 19.3 Functions to Inhibit Rewriting Flash
Memory Version).
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M16C/1N Group
19. Flash Memory Version
Table 19.7 Pin functions (Flash memory standard serial I/O mode)
Pin
VCC, VSS
Name
Power input
I/O
Description
I
Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to
Vss pin.
Connect a capacitor (0.1µF) to VSS pin.
IVCC
IVCC input
CNVSS
RESET
CNVSS input
I
I
Connect to VCC pin
Reset input
I
Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock
XIN
Clock input
I
Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.
XOUT
Clock output
VREF
P00 to P07
Reference voltage input
O
I
To input an externally generated clock, input it to XIN pin and open XOUT pin.
Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin.
Input port P0
I
Input "H" or "L" level signal or open.
P10 to P13
Input port P1
I
P14
TXD output
P15
P16
RXD input
SCLK input
O
I
I
P17
BUSY output
O
P20, P21
P30
P31
Input port P2
SEL input
CE input
Input port P3
Input port P4
Input port P5
I
I
I
I
I
I
Input "H" or "L" level signal or open.
Serial data output pin (Note 1)
Serial data input pin
Standard serial I/O mode 1: Serial clock input pin.
Standard serial I/O mode 2: Input "L" level signal.
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation check signal
output pin.
Input "H" or "L" level signal or open.
SEL signal input pin. Input "L" level signal.
CE signal input pin. Input "H" level signal.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
to XIN pin.
P32 to P37
P40 to P47
P50 to P52
___________
Note 1: When using standard serial I/O mode 1, the TxD pin must be held high while the RESET pin is low.
Therefore, connect this pin to VCC via a resistor. Because this pin is directed for data output after
reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.
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M16C/1N Group
19. Flash Memory Version
36
35
34
33
32
31
30
29
28
27
26
25
P07/AN0
IVCC
P30/TXOUT
VSS
P31/TZOUT
VCC
P40/ANEX0
P41/ANEX1
P42/INT3
P43/INT1
P32/TYOUT
P33/TCIN
CE
SEL
Mode setup method
Signal
Value
Vcc
CNVss
Vss Vcc
RESET
Vcc
CE
Vss
SEL
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
M16C/1N Group
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
NC
P21
P13/KI3/AN11
P14/TXD0
P15/RXD0
P16/CLK0
TxD
RxD
SCLK
P36/CLK1
P35/RXD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
RESET
XOUT
VSS
XIN
VCC
P17/CNTR0
1
2
3
4
5
6
7
8
9
10
11
12
P06/AN1
P05/AN2
P04/AN3
VREF
P52
P51/CRx
P50/CTx
P03/AN4/CRx
P02/AN5/CTx
P01/AN6
P00/AN7
P37/TXD1/RXD1
Figure 19.13 Pin connections for standard serial I/O mode
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Vcc
Vss
RESET
CNVss
BUSY
Package 48P6Q-A
M16C/1N Group
19. Flash Memory Version
(1) Example for Processing Pins when Using Standard Serial Input/Output Mode
Figure 19.14 and 19.15 show example for processing pins when using standard serial I/O mode 1 and
mode 2, respectively. Control pins will vary according to programmer, therefore refer to the programmer manual for more information.
Note that when using standard serial I/O mode 2, make sure a main clock input oscillation frequency
is set to 10 or 16 MHz.
Microcomputer
(P16)SCLK
Clock input
CE(P31)
(P14)TXD
Data output
(P17)BUSY
BUSY output
CNVss
(P15)RxD
Data input
SEL(P30)
Reset input
RESET
User reset
signal
CRx
CTx
CAN transceiver
CAN H CAN H
CAN L
CAN L
(1) Control pins and external circuitry will vary according to programmer.
For more information, refer to the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
I/O mode by controlling the CNVss input with a switch.
(3) If in standard serial I/O mode 1 there is a possibility that the user reset signal will go
low during serial I/O mode, break the connection between the user reset signal and
RESET pin by using, for example, a jumper switch.
Figure 19.14 Example for processing pins when using standard serial I/O mode 1
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M16C/1N Group
19. Flash Memory Version
Microcomputer
(P16)SCLK
CE(P31)
(P14)TXD
Data output
(P17)BUSY
Monitor output
CNVss
(P15)RxD
Data input
SEL(P30)
Reset input
RESET
User reset
signal
CRx
CTx
CAN transceiver
CAN H
CAN L
(1) In this example, modes are switched between single-chip mode and standard serial
I/O mode by controlling the CNVss input with a switch.
(2) Make sure a main clock input oscillation frequency is set to 10 or 16MHz.
Figure 19.15 Example for processing pins when using standard serial I/O mode 2
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CAN H
CAN L
M16C/1N Group
19. Flash Memory Version
19.8 CAN Input/Output Mode
In CAN I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by
using a CAN programmer suitable for the M16C/1N group. For more information about CAN programmers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user's
manual included with your CAN programmer.
Table 19.8 lists pin functions (flash memory CAN I/O mode). Figure 19.16 shows pin connections for CAN
I/O mode.
19.8.1 ID code check function
This function determines whether the ID codes sent from the CAN programmer and those written in
the flash memory match (refer to the description of 19.3 Functions to Inhibit Rewriting Flash
Memory Version)
Table 19.8 Pin functions (Flash memory CAN I/O mode)
Pin
Name
I/O
VCC, VSS
Power input
I
IVCC
CNVSS
RESET
IVCC input
CNVSS input
Reset input
I
XIN
XOUT
VREF
P00, P01
P04 to P07
P02
P03
P10 to P15,
P17
Clock input
Clock output
Reference voltage input
I
O
I
I
CTX output
CRX input
Input port P1
O
P16
P20, P21
P30
P31
P32 to P37
P40 to P47
P50 to P52
SCLK input
Input port P2
SEL input
CE input
Input port P3
Input port P4
I
I
Input port P0
Input port P5
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I
I
I
I
I
I
I
I
I
Description
Apply the voltage guaranteed for program and erase to Vcc pin and 0 V to
Vss pin.
Connect a capacitor (0.1µF) to VSS pin.
Connect to VCC pin
Reset input pin. While RESET pin is "L" level, input a 20 cycle or longer clock
to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins.
To input an externally generated clock, input it to XIN pin and open XOUT pin.
Enter the reference voltage for AD from this pin. Connect to VCC or VSS pin.
Input "H" or "L" level signal or open.
CAN output pin. Connect this pin to CAN transceiver.
CAN input pin. Connect this pin to CAN transceiver.
Input "H" or "L" level signal or open.
SCLK signal input pin. Input "L" level signal.
Input "H" or "L" level signal or open.
SEL signal input pin. Input "H" level signal.
CE signal input pin. Input "H" level signal.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
M16C/1N Group
19. Flash Memory Version
36
35
34
33
32
31
30
29
28
27
26
25
P07/AN0
IVCC
P30/TXOUT
VSS
P31/TZOUT
VCC
P40/ANEX0
P41/ANEX1
P42/INT3
P43/INT1
P32/TYOUT
P33/TCIN
CE
SEL
Mode setup method
Signal
Value
CNVss
Vcc
Vss Vcc
RESET
Vcc
CE
Vcc
SEL
Vss
SCLK
CRx
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
M16C/1N Group
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
NC
P21
P13/KI3/AN11
P14/TXD0
P15/RXD0
P16/CLK0
SCLK
P36/CLK1
P35/RXD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
RESET
XOUT
VSS
XIN
VCC
P17/CNTR0
1
2
3
4
5
6
7
8
9
10
11
12
CTx
P06/AN1
P05/AN2
P04/AN3
VREF
P52
P51/CRx
P50/CTx
P03/AN4/CRx
P02/AN5/CTx
P01/AN6
P00/AN7
P37/TXD1/RXD1
Figure 19.16 Pin connections for CAN I/O mode
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REJ09B0007-0100Z
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Vcc
Vss
RESET
CNVss
Package 48P6Q-A
M16C/1N Group
19. Flash Memory Version
(1) Example for Processing Pins when Using CAN Input/Output Mode
Figure 19.17 shows example for processing pins when using CAN I/O. Control pins will vary according
to programmer, therefore refer to the programmer manual for more information.
Microcomputer
(P16)SCLK
CE(P31)
CNVss
SEL(P30)
Reset input
RESET
User reset
signal
CRx
CAN transceiver
CAN H
CTx
CAN L
(1) Control pins and external circuitry well vary according to programmer.
For more information, refer to the programmer manual.
(2) In this example, modes are switched between single-chip mode and CAN I/O mode
by controlling the CNVSS input with a switch.
Figure 19.17 Example for processing pins when using CAN I/O mode
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CAN H
CAN L
M16C/1N Group
20. Precautionary Notes in Using the Device
20. Precautionary Notes in Using the Device
20.1 Clock
20.1.1 External Clock
Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the
CPU clock.
20.1.2 Power Control
____________
1. When exiting stop mode by hardware reset, set RESET pin to "L" for at least 200 µs or longer.
2. Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit
of the CM1 register to "1". When shifting to wait mode or stop mode, an instruction queue reads
ahead to the next instruction to halt a program by an WAIT instruction and an instruction to set the
CM10 bit to "1" (all clocks stopped). The next instruction may be executed before entering wait
mode or stop mode, depending on a combination of instruction and an execution timing.
3. In the main clock oscillation or low power dissipation mode, set the CM02 bit of the CM0 register to
"0" (do not stop peripheral function clock in wait mode).
4. Wait until the td(M-L) elapses or main clock oscillation stabilization time, whichever is longer, before switching the clock source for CPU clock to the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock
to the sub clock.
5. Suggestions to reduce power consumption
• Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop
mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize
the potential.
• A/D converter
When A/D conversion is not performed, set the VCUT bit of the ADCON1 register to "0" (VREF
not connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or
longer after setting the VCUT bit to "1" (VREF connection).
• D/A converter
When not performing D/A conversion, set the DAE bit of the DACON register to "0" (input
inhibited) and DA register to "0016".
• Switching the oscillation-driving capacity
Set the driving capacity to "LOW" when oscillation is stable.
• External clock
When using an external clock input for the CPU clock, set the CM05 bit of the CM0 register to
"1" (stop). Setting the CM05 bit to "1" disables the XOUT pin from functioning, which helps to
reduce the amount of current drawn in the chip. (When using an external clock input, note that
the clock remains fed into the chip regardless of how the CM05 bit is set.)
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.1.3 Stop and Wait Modes
____________
1. When returning from a stop mode by hardware reset, RESET pin must be "L" level until the mainclock has stabilized.
2. When switching to a stop or wait mode, 4 instructions are prefetched after the stop or wait instruction. And so, ensure that at least 4 NOPs follow the stop (the all-clock stop bit to "1") or wait
instruction.
3. A Stop or wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to
cancel a stop or wait mode, that interrupt must first have been enabled, and the priority level of the
interrupt which is not used to cancel must have been changed to 0 before shifting to either mode.
If only a hardware reset is used to cancel a stop or wait mode, change the priority level of all
interrupt to 0, then shift to either mode.
Example 1. When an interrupt is used to cancel wait mode
When canceling wait mode by a hardware reset and an INT0 interrupt.
Set the interrupt enable flag (I flag) to "0"
; Disable interrupt
Change the INT0 interrupt priority level to 1 or higher ; Enable INT0 interrupt
In case of processor interrupt priority level = 0
Change all other interrupt priority level to 0 ; Disable all other interrupts
Insert 4 NOPs instructions
Set the interrupt enable flag (I flag) to "1"
; Prevent irregular interrupt occurring
; Enable interrupts
WAIT instruction
Insert 4 NOPs instructions
; Put at least 4 NOPs after a wait instruction because
when switching to a wait mode, 4 instructions are
prefetched after the wait instruction.
Example 2. When only hardware reset is used to cancel wait mode
Set the interrupt enable flag (I flag) to "0"
Change all interrupt priority level to 0
; Disable interrupt
; Disable maskable interrupt
WAIT instruction
Insert 4 NOPs instructions
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; Put at least 4 NOPs after a wait instruction because
when switching to a wait mode, 4 instructions are
prefetched after the wait instruction.
M16C/1N Group
20. Precautionary Notes in Using the Device
4. After returning from stop mode, an unexpected operation may occur (for example, undefined instruction interrupt, BRK instruction interrupt, etc.).
Execute a JMP.B instruction after an instruction to write data to the all clock stop control bit. A
program example is described as follows:
Code examples are shown below.
Example 1:
BSET 0,
JMP.B
L1:
NOP
NOP
NOP
NOP
Example 2:
MOV.B:S
JMP.B
L1:
NOP
NOP
NOP
NOP
Rev.1.00 Oct 20, 2004
REJ090007-0100Z
CM1
L1
; writing to the all clock stop control bit to "1" (stop mode)
#21h, CM1 ; writing to the all clock stop control bit to "1" (stop mode)
L1
page 206 of 222
M16C/1N Group
20. Precautionary Notes in Using the Device
20.2 Interrupts
20.2.1 Reading Address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted,
the CPU reads interrupt information (interrupt number and interrupt request priority level) from the
address 0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is
cleared to "0". If the address 0000016 is read in a program, the IR bit for the interrupt which has the
highest priority among the enabled interrupts is cleared to "0". This causes a problem that the
interrupt is canceled, or an unexpected interrupt is generated.
20.2.2 Stack Pointer
Set the value of the stack pointer before accepting interrupts. Immediately after a reset, the value
of the stack pointer is 000016. Accepting an interrupt before setting a value of the stack pointer
may produce unpredictable results (runaway program, etc.) Make sure that you set the value of
the stack pointer before accepting interrupts.
20.2.3 External interrupts
________
________
Clear the interrupt request bit to "0" when the INT0 to INT3 pins and CNTR0 pin polarity are
changed. The reason being is that an interrupt request may be generated when the polarity is
changed.
20.2.4 Rewriting the Interrupt Control Register
When rewriting the Interrupt Control Register, do it at a point where it does not generate an interrupt request for that register. If there is a possibility that an interrupt may occur, disable the interrupt before rewriting. Examples are shown below.
Example 1:
INT_SWITCH1:
FCLR
I
AND.B
#00H, 0055H
NOP
NOP
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
;
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B
#00H, 0055H
MOV.W
MEM, R0
FSET
I
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC
FLG
FCLR
I
AND.B
#00H, 0055H
POPC
FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
; Enable interrupts.
Note 1: The reason why two NOP instructions or dummy read were inserted before the FSET I for
ex. 1 & 2 is to prevent interrupt enable flag from being set, due to the effects of instruction
queue, before the rewritten value of the interrupt control register takes effect.
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M16C/1N Group
20. Precautionary Notes in Using the Device
When an instruction to rewrite the interrupt control register is executed while the interrupt is disabled, depending on the instruction used for rewriting, there are times the interrupt request bit is
not set even if an interrupt request for that register has been generated. If this creates a problem,
please use any of the instructions below to rewrite the register.
Instructions : AND, OR, BCLR, BSET
20.2.5 Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt
request bit is not cleared sometimes. This will depend on the instruction. If this creates problems,
use the below instructions to change the register.
Instructions : MOV
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.3 Timer
20.3.1 Timer 1
1. Even if the prescaler 1 and Timer 1 are read out simultaneously in word-size, these registers are
read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the
period these two registers are being read.
20.3.2 Timers X, Y and Z
1. These timers stop counting after reset. Therefore, set values to Timer (X, Y, Z) and prescaler (X, Y,
Z) before starting counting.
2. Even if prescaler (X, Y, Z) and Timer (X, Y, Z) are read out simultaneously in word-size, these
registers are read byte-by-byte in the microcomputer. Consequently, the timer value may be updated during the period these two registers are being read.
20.3.3 Timer X
1. Using in the timer X pulse period measurement mode, the effectual edge reception flag and the
timer X under flow flag are set to "0" by writing a "0" in a program. Writing a "1" has no effect. Write
"1" in the other flag by using the MOV instruction when you make the flag of either one side "0" by
program. (The clearance of the flag which isn't intend can be prevented.)
Example:
MOV.B
#10XXXXXXB,008BH
2. When changing to the timer X pulse period measurement mode from other mode, the contents of
the effectual edge reception flag and the timer X under flow flag are indetermind. Write "0" in the
effectual edge reception flag and the timer X under flow flag before starting the timer.
3. In the timer X pulse period measurement mode, use the MOV instruction to stop the timer.
Example:
MOV.B
#1100X00B,008BH
20.3.4 Timer Y
1. When count is stopped by writing "0" to the timer Y count start flag, the timer reloads the value of
reload register and stops. Therefore, the timer count value should be read out before the timer
stops.
2. When count is stopped by writing "0" to the timer Y count start flag, the timer Y interrupt request bit
becomes "1" and an interrupt may occur. Thus, disable interrupts before the timer stops. Furthermore, set the Timer Y interrupt request bit to "0" before starting counting again.
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.3.5 Timer Z
1. When count is stopped by writing "0" to the timer Z count start flag, the timer reloads the value of
reload register and stops. Therefore, the timer count value should be read out before the timer
stops.
2. When count is stopped by writing "0" to the timer Z count start flag (all modes) or by writing "0" to
the one-shot start bit (programmable one-shot generation mode/programmable wait one-shot generation mode), the timer Z interrupt request flag becomes "1" and an interrupt occurs. Thus, disable
interrupts before the timer stops. Furthermore, set the Timer Z interrupt request bit to "0" before
starting counting again.
20.3.6 Timer C
1. Read out the timer C or timer measurement register using in word-size.
Even if the Timer C is read out in word-size, the timer value is not updated during the period the
high-byte and low-byte are being read.
Example:
MOV.W
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0091H,R0
page 210 of 222
;Read out timer C
M16C/1N Group
20. Precautionary Notes in Using the Device
20.4 Serial I/O
1. When reading data from the UARTi receive buffer in the clock asynchronous serial I/O mode, data
should be read high-byte first then low-byte using a byte-size. If data is read as low-byte then highbyte or in word-size the framing error and parity error flags are cleared.
A code example is shown below.
MOV.B
MOV.B
00A7H. R0H
00A6H. R0L
; Read the high-byte of UART0 receive buffer register
; Read the low-byte of UART0 receive buffer register
2. When writing data to the UARTi transmit buffer register in the clock asynchronous serial I/O mode
with 9-bit transfer data length, data should be written high-byte first then low-byte using a byte-size.
A code example is shown below.
MOV.B
MOV.B
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REJ090007-0100Z
#XXH, 00A3H
#XXH, 00A2H
page 211 of 222
; Write the high-byte of UART0 transmit buffer register
; Write the low-byte of UART0 transmit buffer register
M16C/1N Group
20. Precautionary Notes in Using the Device
20.5 A/D Converter
1. Only write to each bit (except bit 6) of the AD Control Register 0, or each bit of the AD Control
Register 1, or bit 0 of the AD Control Register 2 when AD conversion is stopped (before a trigger
occurs). When the VREF connection bit is changed from "0" to "1", wait 1 µs or longer before
starting AD conversion.
2. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors,
insert capacitors between the VCC, VREF, and analog input pins (ANi) each and the VSS pin. Figure
20.1 shows an example connection of each pin.
Microcomputer
VCC
VREF
C1
C2
VSS
C3
ANi
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF (reference).
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 20.1 Example connection of each pin
3. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input
mode).
____
4. When setting the KIi input enable bit to "1" (Enabled) to use key input interrupt and using AN8 to
AN11 as analog input pins, be careful about the following points.
• A key input interrupt request is generated when the A/D input voltage goes "LOW".
• If the A/D input voltage approaches 1/2 VCC, power supply current may increase due to pass
____
current on schmitt circuit of key input interrupt. (When setting the KIi input enable bit to "0"
(Disabled), pass current doesn't flow.)
5. The ØAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the ØAD
frequency to 250 kHz or more. With the sample and hold function, limit the ØAD frequency to 1 MHz
or more.
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M16C/1N Group
20. Precautionary Notes in Using the Device
6. When changing AD operation mode, select an analog pin again.
7. One Shot Mode
Read the AD register only after confirming AD conversion is completed, which can be determined
by using the AD conversion interrupt.
8. Repeat Mode
Use the undivided main clock as the internal CPU clock when using this mode. The main clock can
be divided by an internal divider circuit but make sure that you use main clock when using this
mode.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit of ADCON0
register to "0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate.
If the ADST bit is cleared to "0" in a program, ignore the value of A/D register.
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.6 CAN Module
20.6.1 Reading C0STR Register
The CAN module on the M16C/1N group updates the status of the C0STR register in a certain
period. When the CPU and the CAN module access to the C0STR register at the same time, the
CPU has the access priority; the access from the CAN module is disabled. Consequently, when
the updating period of the CAN module matches the access period from the CPU, the status of the
CAN module cannot be updated. (See Figure 20.2)
Accordingly, be careful about the following points so that the access period from the CPU should
not match the updating period of the CAN module:
1. There should be a wait time of 3fCAN or longer (see Table 20.1) before the CPU reads the C0STR
register. (See Figure 20.3)
2. When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure
20.4)
Table 20.1 CAN Module Status Updating Period
3fCAN period = 3 X XIN (Original oscillation period) X Division value of the CAN clock (CCLK)
(Example 1) Condition XIN 16MHz CCLK: Divided by 1
3fCAN period = 3 X 62.5 ns X 1= 187.5 ns
(Example 2) Condition XIN 16MHz CCLK: Divided by 2
3fCAN period = 3 X 62.5 ns X 2= 375 ns
(Example 3) Condition XIN 16MHz CCLK: Divided by 4
3fCAN period = 3 X 62.5 ns X 4= 750 ns
(Example 4) Condition XIN 16MHz CCLK: Divided by 8
3fCAN period = 3 X 62.5 ns X 8= 1.5 µs
(Example 5) Condition XIN 16MHz CCLK: Divided by 16
3fCAN period = 3 X 62.5 ns X 16= 3 µs
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M16C/1N Group
20. Precautionary Notes in Using the Device
fCAN
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initialization mode
: When the CAN module’s State_Reset bit updating period matches the CPU’s
read period, it does not enter reset mode, for the CPU read has the higher
priority.
Figure 20.2 When Updating Period of CAN Module Matches Access Period from CPU
Wait time
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initialization mode
: Updated without fail in period of 3fCAN
Figure 20.3 With a Wait Time of 3fCAN Before CPU Read
CPU read signal
4fCAN
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initialization mode
: When the CAN module’s State_Reset bit updating period matches the CPU’s
read period, it does not enter reset mode, for the CPU read has the higher
priority.
: Updated without fail in period of 4fCAN
Figure 20.4 When Polling Period of CPU is 3fCAN or Longer
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.6.2 CAN Transceiver in Boot Mode
When programming the flash memory in boot mode via CAN bus, the operation mode of CAN
transceiver should be set to "high-speed mode" or "normal operation mode". If the operation mode
is controlled by the microcomputer, CAN transceiver must be set the operation mode to "highspeed mode" or "normal operation mode" before programming the flash memory by changing the
switch etc. Figure 20.5 shows pin connections of CAN transceiver.
In case of PCA82C250 (Philips product)
Standby mode
high-speed mode
Rs pin (Note 1)
"H"
"L"
CAN communication
impossible
possible
M16C/1N
connection
PCA82C250
CTX P02
CRX P03
TXD CANH
RXD CANL
Port (Note 2)
RS
M16C/1N
PCA82C250
CTX P02
CRX P03
TXD CANH
RXD CANL
Port (Note 2)
Switch OFF
RS
Switch ON
In case of PCA82C252 (Philips product)
sleep mode
normal operation mode
STB pin (Note 1)
EN pin (Note 1)
"L"
"L"
"H"
"H"
CAN communication
impossible
possible
MCU
connection
PCA82C252
CTX P02
CRX P03
TXD CANH
RXD CANL
MCU
CTX P02
CRX P03
Port (Note 2)
STB
Port (Note 2)
Port (Note 2)
EN
Port (Note 2)
Switch OFF
Note 1: The pin which controls the operation mode of CAN transceiver.
Note 2: Connect to enabled port to control CAN transceiver.
Figure 20.5 CAN Transceiver Connection
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REJ090007-0100Z
PCA82C252
page 216 of 222
Switch ON
TXD CANH
RXD CANL
STB
EN
M16C/1N Group
20. Precautionary Notes in Using the Device
20.7 Noise
1. Bypass Capacitor between VCC and VSS Pins
Insert a bypass capacitor (at least 0.1 µF) between VCC and VSS pins as noise and latch-up
countermeasures. In addition, make sure that connecting lines are the shortest and widest possible.
2. Port Control Registers Data Read Error
During severe noise testing, mainly power supply system noise, and introduction of external noise,
the data of port related registers may changed. As a firmware countermeasure, it is recommended
to periodically re-set the port registers, port direction registers and pull-up control registers. However, you should fully examine before introducing the re-set routine as conflicts may be created
between this re-set routine and interrupt routines (i. e. ports are switched during interrupts).
3. CNVss pin wiring
CNVSS pin functions as a pin to change to shipment examination mode or flash memory rewrite
mode in the flash memory version.
In order to improve the pin tolerance to noise, insert a pull down resistance (about 5 kΩ) between
CNVss and Vss, and placed as close as possible to the CNVss pin.
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.8 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin,
noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout
pattern, etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation
tests conducted in the flash memory version.
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.9 Flash Memory Version
20.9.1 Functions to Prevent Flash Memory from Rewriting
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316,
0FFFF716, and 0FFFFB16. If wrong data are written to these addresses, the flash memory cannot
be read or written in standard serial I/O mode and CAN I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the
flash memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of fixed vectors.
20.9.2 Stop Mode
When entering stop mode, the following settings are required:
• Set the CM10 bit to "1" (stop mode) after setting FMR01 bit to "0" (CPU rewrite mode disable).
• Execute the instruction to set the CM10 bit to "1" (stop mode) and then the JMP.B instruction.
Example program
BSET
0, CM1
; Stop mode
JMP.B
L1
L1:
Program after exiting from stop mode
20.9.3 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to "0" (CPU rewrite mode disabled) before executing the WAIT instruction.
20.9.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode
If the CM05 bit is set to "1" (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program
20.9.5 Writing Command and Data
Write commands and data to even addresses in the user ROM area.
20.9.6 Program Command
By writing "xx4016" in the first bus cycle and data to the write address in the second bus cycle, an
auto program operation (data program and verify) will start. The address value specified in the first
bus cycle must be the same even address as the write address specified in the second bus cycle.
20.9.7 Operation Speed
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock
frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the
PM17 bit in the PM1 register to "1" (with wait state).
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M16C/1N Group
20. Precautionary Notes in Using the Device
20.9.8 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in
flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK
instruction
20.9.9 Interrupt
EW0 Mode
To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to
the RAM area.
• The watchdog timer interrupt is available since the FMR0 and FMR1 registers are forcibly reset
when either interrupt request is generated. Allocate the jump addresses for each interrupt service routines to the fixed vector table. Flash memory rewrite operation is aborted when the
watchdog timer interrupt request is generated. Execute the rewrite program again after exiting
the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash
memory.
EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match
interrupt during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
20.9.10 How to Access
To set the FMR01, FMR02 or FMR11 bit to "1", write "1" after first setting the bit to "0". Do not
generate an interrupt between the instruction to set the bit to "0" and the instruction to set the bit to
"1".
20.9.11 Rewriting in User ROM Area
EW0 Mode
The supply voltage drops while rewriting the block where the rewrite control program is stored,
the flash memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error occurs, rewrite the user ROM area while in standard serial I/O mode, parallel I/
O mode, or CAN I/O mode.
EW1 Mode
Avoid rewriting any block in which the rewrite control program is stored.
Rev.1.00 Oct 20, 2004
REJ090007-0100Z
page 220 of 222
M16C/1N Group
Package Dimension
Package Dimension
Recommended
48P6Q-A
EIAJ Package Code
LQFP48-P-77-0.50
Plastic 48pin 7✕7mm body LQFP
Weight(g)
–
Lead Material
Cu Alloy
MD
ME
e
JEDEC Code
–
b2
HD
D
48
37
1
I2
Recommended Mount Pad
36
E
HE
Symbol
25
12
13
24
A
F
L1
A3
A2
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
y
b
x
Detail F
M
Rev.1.00 Oct 20, 2004
REJ090007-0100Z
L
page 221 of 222
Lp
c
A1
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.17
0.22
0.27
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
–
0.5
–
8.8
9.0
9.2
8.8
9.0
9.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
–
–
0.1
–
0°
8°
–
–
0.225
1.0
–
–
–
–
7.4
–
–
7.4
M16C/1N Group
Register Index
Register Index
A
AD ................................................. 125
ADCON0 ......................... 124,126,127
ADCON1 ......................... 124,126,127
ADCON2 ....................................... 125
ADIC ................................................ 51
AIER ................................................ 65
CNTR0IC ......................................... 51
CPSRF ............................................ 26
RMAD1 ............................................ 65
ROMCP ......................................... 176
D
S
DA ................................................. 130
DACON ......................................... 130
DRR .............................................. 161
F
C
C01ERRIC ...................................... 51
C01WKIC ........................................ 51
C0AFS ........................................... 143
C0CONR ....................................... 141
C0CTLR ........................................ 137
C0GMR ......................................... 135
C0ICR ........................................... 140
C0IDR ........................................... 140
C0LMAR ........................................ 135
C0LMBR ........................................ 135
C0MCTL0 ...................................... 136
C0MCTL1 ...................................... 136
C0MCTL2 ...................................... 136
C0MCTL3 ...................................... 136
C0MCTL4 ...................................... 136
C0MCTL5 ...................................... 136
C0MCTL6 ...................................... 136
C0MCTL7 ...................................... 136
C0MCTL8 ...................................... 136
C0MCTL9 ...................................... 136
C0MCTL10 .................................... 136
C0MCTL11 .................................... 136
C0MCTL12 .................................... 136
C0MCTL13 .................................... 136
C0MCTL14 .................................... 136
C0MCTL15 .................................... 136
C0RECIC ........................................ 51
C0RECR ....................................... 142
C0SSTR ........................................ 139
C0STR .......................................... 138
C0TECR ........................................ 142
C0TRMIC ........................................ 51
CAN0/1 SLOT 0 to 15
: Time Stamp ..................... 133,134
: Data Field ........................ 133,134
: Message Box .................. 133,134
CCLKR ............................................ 27
CIOSR ........................................... 162
CM0 ................................................. 25
CM1 ................................................. 25
CM2 ............................................ 26,37
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REJ090007-0100Z
FMR0 ............................................ 181
FMR1 ............................................ 182
FMR4 ............................................ 182
I
INT0F ......................................... 60,94
INT0IC ............................................. 51
INT1IC ............................................. 51
INT2IC ............................................. 51
INT3IC ............................................. 51
INTEN ........................................ 60,94
K
KIEN ................................................ 64
KUPIC ............................................. 51
P
P0 .................................................. 160
P1 .................................................. 160
P2 .................................................. 160
P3 .................................................. 160
P4 .................................................. 160
P5 .................................................. 160
PD0 ............................................... 160
PD1 ............................................... 160
PD2 ............................................... 160
PD3 ............................................... 160
PD4 ............................................... 160
PD5 ............................................... 160
PM0 ............................................ 22,41
PM1 ....................................... 22,41,69
PRCR .............................................. 40
PRE1 ............................................... 72
PREX .............................................. 74
PREY .............................................. 83
PREZ ............................................... 92
PUM ......... 84,86,88,93,96,98,100,103
PUR0 ............................................. 161
PUR1 ............................................. 161
R
RMAD0 ............................................ 65
page 222 of 222
S0RIC ..............................................
S0TIC ..............................................
S1RIC ..............................................
S1TIC ..............................................
51
51
51
51
T
T1 .................................................... 72
T1IC ................................................ 51
TC ................................................. 106
TCC0 ........................................ 63,106
TCC1 ........................................ 63,106
TCIC ................................................ 51
TCINIC ............................................ 51
TCSS ................................ 72,74,84,93
TM ................................................. 106
TX .................................................... 74
TXIC ................................................ 51
TXMR .......................... 62,73,75-78,80
TYIC ................................................ 51
TYPR ............................................... 83
TYSC ............................................... 83
TYZMR ..... 82,86,88,91,96,98,100,103
TYZOC ....................................... 83,94
TZIC ................................................ 51
TZPR ............................................... 92
TZSC ............................................... 92
U
U0BRG ........................................... 110
U0C0 .............................................. 111
U0C1 .............................................. 112
U0MR ............................... 111,114,119
U0RB .............................................. 110
U0TB .............................................. 110
U1BRG ........................................... 110
U1C0 .............................................. 111
U1C1 .............................................. 112
U1MR ............................... 111,114,119
U1RB .............................................. 110
U1TB .............................................. 110
UCON ............................................. 112
W
WDC ................................................ 69
WDTS .............................................. 69
M16C/1N Group Hardware Manual
REVISION HISTORY
Rev.
Description
Summary
Date
Page
1.00 Oct 20, 2004
–
First edition issued (Renesas Technology version)
C-1
Blank page
M16C/1N Group Hardware Manual
Publication Data :
Rev.1.00 Oct 20, 2004
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/1N Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan