RENESAS M306V8FJFP

M306V8FJFP
REJ03B0082-0131
Rev.1.31
Apr 18, 2005
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M306V8FJFP are single-chip microcomputers using the high-performance silicon gate CMOS process
using a M16C/60 Series CPU core and are packaged in a 116-pin plastic molded QFP. These single-chip
microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency.
With 1M bytes of address space, they are capable of executing instructions at high speed. They also
feature a built-in OSD display function and data slicer, making them ideal for closed caption and ID1 for TV
control.
Applications
TV
------Table of Contents-----DESCRIPTION .................................................. 1
Central Processing Unit (CPU) .......................... 9
Reset ................................................................ 22
Processor Mode ............................................... 28
Clock Generating Circuit .................................. 50
Protection ......................................................... 67
Interrupts .......................................................... 68
Watchdog Timer ............................................... 89
DMAC .............................................................. 91
Timer .............................................................. 101
Serial I/O ........................................................ 123
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A/D Converter ................................................ 156
Multi-master I2C-BUS Interface ..................... 170
Data Slicer ..................................................... 190
HSYNC Counter ............................................. 203
OSD Functions ............................................... 204
Programmable I/O Ports ................................ 260
ELECTRICAL CHARACTERISTICS .............. 295
Flash Memory Version ................................... 316
Usage Precaution .......................................... 348
PACKAGE OUTLINE ..................................... 363
M306V8FJFP
Performance Outline
Table 1.1. Performance outline of M306V8FJFP
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
62.5 ns (f(BCLK)= 16MHZ
Memory
ROM
(See the product list)
capacity
RAM
(See the product list)
I/O port
P0 to P10
75
Multifunction TA0, TA1, TA2, TA3, TA4
16 bits output x 5 channels
timer
TB0, TB1, TB2, TB3, TB4,
16 bits input x 6 channels
TB5
Serial I/O
UART0, UART1, UART2
(UART, clock sync. serial I/O, IEBus (Note 2)) x 3
A/D converter
8 bits x 13 channels
Data slicer
2 circuits
Hsync counter
1 circuit 2 lines
OSD function
1 circuit
Multi-master I2Cbus interface (Note 1)
3 circuits 4 lines
DMAC
2 channels (trigger: 29 sources)
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
31 internal and 5 external sources, 4 software sources, 7 levels
Clock generation circuit
3 circuits
• Main clock
• Sub-clock  (These circuits contain a built-in feedback

• OSD clock  resistor and external ceramic/quartz oscillator)
Power supply voltage
3.15 to 3.45V
Flash memory Program/erase voltage
3.15 to 3.45V
Number of program/erase
100 times
Power consumption
500mW
I/O
I/O withstand voltage
3.3V
characteristics Output current
5mA
Memory expansion
Available (to 4M bytes)
Operating ambient temperature
-20 to 70°C
Device configuration
CMOS high performance silicon gate
Package
116-pin plastic mold QFP
Notes:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
When you use option function, please specify that.
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M306V8FJFP
Block Diagram
Figure 1.1 is a block diagram of the M306V8FJFP.
8
8
8
Port P0
Port P1
8
Port P2
Port P3
Internal peripheral functions
8
Port P4
Port P5
Port P6
8
System clock generator
XIN-XOUT
XCIN-XCOUT
A/D converter
(8 bits X 13 channels)
Output (timer A): 5
Input (timer B): 6
8
Port P7
Timer (16-bit)
8
UART or
clock synchronous serial I/O
(15 bits)
4
Port P8
(8 bits X 3 channels)
Watchdog timer
DMAC
(2 channels)
Multi-master
I2C-BUS
interface 1
R0L
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
ROM
(Note 1)
RAM
(Note 2)
PC
FLG
Multiplier
Notes 1: ROM size depends on microcomputer type.
2: RAM size depends on microcomputer type.
Figure 1.1. Block Diagram
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5
Multi-master
I2C-BUS
interface 2
R0H
R1H
Memory
Port P10
HSYNC counter
M16C/60 series16-bit CPU core
2
Data slicer 2
Data slicer 1
Multi-master
I2C-BUS
interface 0
Port P9
OSD
M306V8FJFP
Product List
Product list is show in Table 1.2 type No., memory size and package type are show in Figure 1.2.
Table 1.2. Product List
Type No.
ROM capacity
512K bytes
M306V8FJFP
Type No.
M306V 8 F J
RAM capacity
16K bytes
Package type
116P6A-A
Remarks
Flash memory version
FP
Package type:
FP : Package
116P6A-A
ROM capacity:
J: 512K bytes
Memory type:
F: Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6V Group
M16C Family
Figure 1.2. Type No., Memory Size, and Package
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M306V8FJFP
Pin Configuration
Figures 1.3 show the pin configuration.
P10/D8
P11/D9
P12/D10
P13/D11
P14/D12
P15/D13/ INT3
P16/D14
P17/D15
P20/ A0(/D0/-)
P21/ A1(/D1/D0)
P22/ A2(/D2/D1)
P23/ A3(/D3/D2)
P24/AN24/A4(/D4/D3)
P25/AN25/A5(/D5/D4)
P26/AN26/A6(/D6/D5)
P27/AN27/A7(/D7/D6)
VSS
P30/A8(/-/D7)
VCC2
P31/A9
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
PIN CONFIGURATION (top view)
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
P07/AN07/D7
P06/AN06/D6
P05/AN05/D5
P04/AN04/D4
P03 / D3
P02/ D2
P01/ D1
P00/ D0
P107/AN7 /KI3
P106/AN6 /KI2
P105/AN5 /KI1
P104/AN4 /KI0
CAP/ P103/AN3
R/DIGR0
G/DIGG0
V SS
B/DIGB0
CNVss2
VCC3
OSCOUT
DIGR1
DIGG1
DIGB1
DIGR2
DIGG2
DIGB2
HSYNC
CVIN1
VHOLD1
88
89
90
91
92
93
94
95
96
97
98
VCC2 system
VCC1 system
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
M306V8 Group
VCC3 system
VCC1 system
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
P43/A19
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0/SCL3
P61/CLK0/SDA3
P62/RxD0
P63/TXD0
P64/CTS1/RTS1/CLKS1/CTS0
P65/CLK1
P66/RxD1 /SCL1
P67/TXD1 /SDA1
SCL6 (Note 1)
SDA6 (Note 1)
SCL5 (Note 1)
NC
SDA5 (Note 1)
SCL4 (Note 1)
SDA4 (Note 1)
Vss
HLF1
CVIN2
VHOLD2
HLF2
P91/TB1IN
P90/TB0IN
BYTE
CNVss1
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VCC1
OSC1/OSCHLF
OSC2/VSYNC1/INT2
VSYNC2/P83/INT1
P82/INT0
OUT1
OUT2
P77/TA3IN/HC1
P76/TA3OUT
P75/TA2IN//HC0
P74/TA2OUT
P73/CTS2/RTS2/TA1IN
P72/CLK2/TA1OUT
P71/RxD2/SCL2/TA0IN/TB5IN (Note 1)
P70/TXD2/SDA2/TA0OUT (Note 1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Package: 116P6A-A
Notes 1: N channel open-drain output pins.
2: Use this MCU (microcomputer) with Vcc1 = Vcc2 = Vcc3 = 3.3V.
Figure 1.3. Pin Configuration (Top View)
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M306V8FJFP
Pin Description
Table 1.3. Pin Description (1)
Pin name
Signal name
I/O type
VCC1, V CC2, Power supply
VCC3, V SS input
CNVSS1,
CNVSS2
CNVSS1/
CNVSS2
Function
Power supply
Apply 3.3 V to the VCC1, VCC2 and VCC3 pins and 0 V to the VSSpin. (Note 1)
Insert a bypass capacitor between power supply and GND. (Note 2)
Input
VCC
CNVSS1 pin switches between processor modes. Connect this pin
to V SS pin when after a reset you want to start operation in singlechip mode (memory expansion mode) or the V CC1 pin when
starting operation in microprocessor mode. Always connect
CNVSS2 pin to V SS.
RESET
Reset input
Input
VCC
“L” on this input resets the microcomputer.
XIN
Clock input
Input
VCC
XOUT
Clock output
Output
These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the X IN
and the XOUT pins. T o use an externally derived clock, input it to
the XIN pin and leave the X OUT pin open.
BYTE
External data Input
bus width
select input
VCC
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. Connect
this pin to the V SS pin when operating in single-chip mode.
P00 to P07
I/O port P0
VCC
This is an 8-bit CMOS I/O port. This port has an I/O select direction
register, allowing each pin in that port to be directed for input or
output individually.
If any port is set for input, selection can be made for it in a program
whether or not to have a pull-up resistor in 4 bit units. This selection
is unavailable in memory extension and microprocessor modes.
This port can function as input pins for the A/D converter when so
selected in a program.
D0 to D7
P10 to P17
I/O
I/O
I/O port P1
D8 to D15
I/O
When set as a separate bus, these pins input and output data (D 0
–D7).
VCC
I/O
This is an 8-bit I/O port equivalent to P0. P1 5 also function as INT
interrupt input pins as selected by a program.
When set as a separate bus, these pins input and output data (D8
–D15).
P20 to P27
I/O port P2
I/O
A0 to A7
Output
A0/D0 to
A7/D7
I/O
A0
A1/D0 to
A7/D6
P30 to P37
Output
I/O
I/O port P3
I/O
A8 to A15
A8/D7,
A9 to A15
Output
I/O
Output
P40 to P47 I/O port P4
A16 to A19,
CS0 to CS3
I/O
Output
Output
VCC
VCC
VCC
Notes 1: In this manual, hereafter, VCC
refers to VCC1 unless otherwise
noted.
2: Insert capacitors between each
power supply pin and GND to
prevent errors or latch-up by
noise.
Also, use thick and shortest
possible wiring to connect capacitors.
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This is an 8-bit I/O port equivalent to P0. This port can function as
input pins for the A/D converter when so selected in a program.
These pins output 8 low-order address bits (A0 to A7).
If the external bus is set as an 8-bit wide multiplexed bus, these
pins input and output data (D0 to D7) and output 8 low-order
address bits (A0 to A7) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these
pins input and output data (D0 to D6) and output address (A1 to A7)
separated in time by multiplexing. They also output address (A 0).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A8 to A15).
If the external bus is set as a 16-bit wide multiplexed bus, these
pins input and output data (D7) and output address (A8)
separated in time by multiplexing. They also output address (A 9
to A15).
This is an 8-bit I/O port equivalent to P0.
These pins output A16 to A19 and CS0 to CS3 signals. A 16 to A19
are 4 high- order address bits. CS 0 to CS3 are chip select signals
used to specify an access space.
VCC1
C1
VCC2
C2
C3
VCC3
VSS
C1 =>0.1µF, C2 =>0.1µF, C3 =>0.1µF (reference value)
M306V8FJFP
Table 1.4. Pin Description (2)
Pin name
Signal name
P50 to P57
I/O port P5
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
I/O type
I/O
Power supply
F
VCC
Output
Output
Output
Output
Output
Input
Output
Input
unction
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57
in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program.
Output WRL/WRH, (BHE/WR), RD, BCLK, HLDA, and ALE signals.
WRL/WRH and BHE/WR are switch able in a program. Note that
WRL and WRH are always used as a pair, so as WR and BHE.
WRL, WRH, and RD selected
If the external data bus is 16 bits wide, data are written to even
addresses when the WRL signal is low, and written to odd
addresses when the WRH signal is low. Data are read out when the
RD signal is low.
WR, BHE, and RD selected
Data are written when the WR signal is low, or read out when the
RD signal is low. Odd addresses are accessed when the BHE
signal is low. Use this mode when the external data bus is 8 bits
wide.
The microcomputer goes to a hold state when input to the HOLD
pin is held low. While in the hold state, HLDA outputs a low
level. ALE is used to latch the address. While the input level of the
RDY pin is low, the bus of the microcomputer goes to a wait state.
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as UART0, UART1 and multi-master I2C bus I/O pins as
selected by program.
P60 to P67
I/O port P6
I/O
VCC
P70 to P77
I/O port P7
I/O
VCC
This is an 8-bit I/O port equivalent to P0. (However, P70 and P71
are the pins of N-channel opendrain output) This port can function
as I/O pins for timers A0 to A3 and B5 by selecting in a program.
And, UART2, I2C bus I/O pin, P75 and P77 can also function as
input pin for Hsync conter.
P82, P84,
P86,
P87,
I/O port P8
I/O
VCC
P90, P91
I/O port P9
I/O
VCC
They are I/O ports with the same functions as P0. When so
selected in a program, they can function as I/O pins for INT
interrupt, Vsync input pins and the sub clock oscillator circuit. In that
case, connect a crystal resonator between P86 (XCOUT pin) and P87
(XCIN pin).
This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as timer B0 and B1 input pins as selected by program.
P103 to
P107
I/O port P10
I/O
VCC
SCL4 to 6,
SDA4 to 6
Multi-master I/O
I2C-bus
interface
Hsync
Hsync input
Input
VCC
OSD function Hsync input pins.
R/DIGR0,
B/DIGB0,
G/DIGG0,
OUT1,
OUT2,
DIGR1,
DIGB1,
DIGG1,
DIGR2,
DIGG2,
DIGB2,
OSCOUT
OSD
function
output pin
Output
VCC
These are exclusive pins for OSD functions.
CVin1,
VHOLD1,
HLF1,
CVin2,
VHOLD2,
HLF2
Data slicer
function I/O
pin
I/O
VCC
These are exclusive pins for data slicer function.
OSC1/
OSDHLF,
OSC2
Oscillation
pin for OSD
function
I/O
VCC
These are oscillation pins for OSD function.
Using the same pins as external interrupt and Vsync input pin.
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This is an I/O port equivalent to P0. Pins in this port also function as
A/D converter input pins and the capacitor connection pin for analog
RGB operation.
These are exclusive pins for multi-master I2C-bus interface (Nchannel open drain output.)
M306V8FJFP
Memory
Figure 1.4 is a memory map of the M306V8FJFP. The address space extends the 1M bytes from address
0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,
a 64 Kbytes internal ROM is allocated to the addresses from F000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 10 Kbytes internal RAM is allocated to the addresses from 0040016 to 02BFF16. In addition to storing
data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
0000016
SFR
0040016
Internal RAM
043FF16
0440016
Reserved area
0800016
OSDRAM area
0900016
Reserved area
(Note 1)
(Note 1)
0F00016
FFE0016
Internal ROM
(Data area) (Note 2)
1000016
External area
Special page
vector table
2700016
Reserved area
2800016
3000016
External area
OSDROM area
FFFDC16
5000016
BRK instruction
Address match
Single step
Watchdog timer
DBC
8000016
Internal ROM
Internal RAM
Size
Address
16K bytes
0040016 to 043FF16
Size
Address
Internal ROM
512K bytes 8000016 to FFFFF16
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: There is 4K bytes area (Block A) in flash memory version.
Note 3: Shown here is a memory map for the case where the PM10 bit in the PM1
register is “1” and the PM13 bit in the PM1 register is “1”.
Figure 1.4. Memory Map
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Undefined instruction
Overflow
External area
FFFFF16
Reset
M306V8FJFP
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R0H(R0's high bits) R0L(R0's low bits)
R3
R1H(R1's high bits)R1L(R1's low bits)
R2
Data registers (Note)
R3
A0
b19
A1
Address registers (Note)
FB
Frame base registers (Note)
b15
b0
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. CPU registers
(1) Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
(2) Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M306V8FJFP
(3) Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
(4) Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
(5) Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
(6) User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
(7) Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
(8) Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
• Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
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M306V8FJFP
SFR
Register
Address
Symbol
After reset
000016
000116
000216
000316
000416
Processor mode register 0
(Note 2)
PM0
000000002(CNVSS1 pin is “L”)
000000112(CNVSS1 pin is “H”)
000516
000616
000716
000816
000916
000A16
000B16
000C16
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
Data bank register
System clock control register 2
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
000010002
010010002
001000002
000000012
XXXXXX002
XX0000002
0016
0000X0002
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
??16
00??????2
0016
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
Reserved register
Reserved register
Chip select expansion control register 2
Reserved register
RSVREG0019
RSVREG001A
CSE
RSVREG001C
000010002
0016
0016
0001X0102
Reserved register
Reserved register
DMA0 source pointer
RSVREG001E
RSVREG001F
SAR0
XXX000002
0016
??16
??16
X?16
001D16
001E16
001F16
002016
002116
002216
002316
002416
DMA0 destination pointer
DAR0
??16
??16
X?16
DMA0 transfer counter
TCR0
??16
??16
DMA0 control register
DM0CON
00000?002
DMA1 source pointer
SAR1
??16
??16
X?16
DMA1 destination pointer
DAR1
??16
??16
X?16
DMA1 transfer counter
TCR1
??16
??16
DMA1 control register
DM1CON
00000?002
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 11 of 363
M306V8FJFP
Register
Address
Symbol
After reset
INT3IC
TB5IC
TB4IC
TB3IC
DSC1IC
DSC2I C
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00?0002
XXXX?0002
XXXX?0002
XXXX?0002
XX00?0002
XX00?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XXXX?0002
XX00?0002
XX00?0002
XX00?0002
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
Slicer 1 interrupt control register
Slicer 2 interrupt control register
Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note :The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 12 of 363
M306V8FJFP
Register
Address
Symbol
After reset
008016
008116
008216
008316
008416
008516
008616
~
~
01B016
01B116
01B216
01B316
01B416
01B516
Flash identification register
Flash memory control register 1
(Note 2)
(Note 2)
FIDR
FMR1
XXXXXX002
0?00??0?2
Flash memory control register 0
Address match interrupt register 2
(Note 2)
FMR0
RMAD2
??0000012
0016
0016
X016
XXXXXX002
0016
0016
X016
01B616
01B716
01B816
01B916
01BA16
01BB16
Address match interrupt enable register 2
01BC16
Address match interrupt register 3
01BD16
01BE16
AIER2
RMAD3
01BF16
01C016
01C116
01C216
~
~
01E016
01E116
01E216
01E316
01E416
01E516
01E616
01E716
01E816
01E916
01EA16
01EB16
01EC16
01ED16
01EE16
01EF16
01F016
01F116
01F216
01F316
01F416
01F516
01F616
01F716
01F816
01F916
01FA16
01FB16
01FC16
01FD16
01FE16
01FF16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 13 of 363
M306V8FJFP
Register
Address
Symbol
After reset
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
Sprite OSD control register
OSD control register 1
OSD control register 2
Horizontal position register
Clock control register 1
I/O polarity control register
OSD control register 3
SC
OC1
OC2
HP
CS
PC
OC3
Raster color register
RSC
OSD reserved register 5
Clock control register 2
OR5
CG
XXX000002
0016
0016
0016
0016
100000002
0016
0016
0016
0016
0016
Top border control register
TBR
??16
Bottom border control register
BBR
??16
Block control register 1
Block control register 2
Block control register 3
Block control register 4
Block control register 5
Block control register 6
Block control register 7
Block control register 8
Block control register 9
Block control register 10
Block control register 11
Block control register 12
Block control register 13
Block control register 14
Block control register 15
Block control register 16
BC1
BC2
BC3
BC4
BC5
BC6
BC7
BC8
BC9
BC10
BC11
BC12
BC13
BC14
BC15
BC16
Vertical position register 1
VP1
Vertical position register 2
VP2
Vertical position register 3
VP3
Vertical position register 4
VP4
Vertical position register 5
VP5
Vertical position register 6
VP6
Vertical position register 7
VP7
Vertical position register 8
VP8
Vertical position register 9
VP9
Vertical position register 10
VP10
Vertical position register 11
VP11
Vertical position register 12
VP12
Vertical position register 13
VP13
Vertical position register 14
VP14
Vertical position register 15
VP15
Vertical position register 16
VP16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 14 of 363
M306V8FJFP
Register
Address
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
Symbol
Color palette register 1
CR1
Color palette register 2
CR2
Color palette register 3
CR3
Color palette register 4
CR4
Color palette register 5
CR5
Color palette register 6
CR6
Color palette register 7
CR7
Color palette register 9
CR9
Color palette register 10
CR10
Color palette register 11
CR11
Color palette register 12
CR12
Color palette register 13
CR13
Color palette register 14
CR14
Color palette register 15
CR15
OSD reserved register 1
Peripheral clock selection register
OSD control register 4
Data slicer 0 control register 1
Data slicer 0 control register 2
OR1
PCLKR
OC4
DSC01
DSC02
Caption data register 01
CD01
Caption data register 02
CD02
After reset
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
025C16
025D16
025E16
025F16
026016
026116
026216
026316
026416
026516
026616
026716
026816
026916
026A16
026B16
026C16
026D16
026E16
026F16
027016
027116
027216
027316
027416
027516
027616
027716
027816
027916
027A16
027B16
027C16
027D16
027E16
027F16
Caption position register 0
Slice standard voltage selection register
Data slicer 0 reserved register 1
Clock run-in detection register 0
Data clock position register 0
ID1 control register 0
Standard clock detection register 0
CRCC data register 0
Test reservation register 0
Reserved register
CPS0
SBV0
DR01
CRD0
DPS0
IDC0
BCD0
CRC0
IDT0
RSVREG026F
Left border control register
LBR
Right border control register
RBR
Sprite vertical position register 1
VS1
Sprite vertical position register 2
VS2
Sprite horizontal position register
HS
OSD reserved register 4
OSD reserved register 3
OSD reserved register 2
Peripheral mode register
HSYNC counter register
HSYNC counter latch
OR4
OR3
OR2
PM
HC
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 15 of 363
0016
0316
XXXXXX002
0016
?0?0??0?2
????????2
????????2
????????2
????????2
00?000002
0016
0016
0016
X00000002
0016
XX??????2
XX0000002
0016
XXXXXXX02
XXXXX0002
0016
0016
XXXXX0002
??16
??16
??16
??16
??16
XXXXX0002
X00000002
0016
0016
000XXXXX2
XXX00X002
??16
M306V8FJFP
Address
028016
028116
028216
Register
Internal oscillation control register 1
Internal oscillation control register 2
Internal oscillation control register 3
Symbol
DIV0
DIV1
VCO
After reset
0016
0016
0016
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
Flash memory (USER/OSD) change register
FMSEL
0016
Flash memory OSD1 control register 4
FMOSA4
X0XXXX002
Flash memory OSD1 control register 1
FMOSA1
XXXXXX0X2
Flash memory OSD1 control register 0
FMOSA0
XX0000012
Flash memory OSD2 control register 4
FMOSB4
X0XXXX002
Flash memory OSD2 control register 1
FMOSB1
XXXXXX0X2
Flash memory OSD2 control register 0
FMOSB0
XX0000012
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 16 of 363
M306V8FJFP
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
Register
Extended register 00
Extended register 01
Extended register 02
Extended register 03
Extended register 04
Extended register 05
Extended register 06
Extended register 07
Extended register 08
Extended register 09
Extended register 0A
Extended register 0B
Extended register 0C
Extended register 0D
Extended register 0E
Extended register 0F
Extended register 10
Extended register 11
Extended register 12
Extended register 13
Extended register 14
Extended register 15
Extended register 16
Extended register 17
Extended register 18
Extended register 19
Extended register 1A
Extended register 1B
Extended register 1C
Extended register 1D
Extended register 1E
Extended register 1F
I2C0 data shift register
I2C0 address register
I2C0 status register
I2C0 control register
I2C0 clock control register
Reserved register
I2C0 transmitting buffer register
Symbol
EXTREG02C0
EXTREG02C1
EXTREG02C2
EXTREG02C3
EXTREG02C4
EXTREG02C5
EXTREG02C6
EXTREG02C7
EXTREG02C8
EXTREG02C9
EXTREG02CA
EXTREG02CB
EXTREG02CC
EXTREG02CD
EXTREG02CE
EXTREG02CF
EXTREG02D0
EXTREG02D1
EXTREG02D2
EXTREG02D3
EXTREG02D4
EXTREG02D5
EXTREG02D6
EXTREG02D7
EXTREG02D8
EXTREG02D9
EXTREG02DA
EXTREG02DB
EXTREG02DC
EXTREG02DD
EXTREG02DE
EXTREG02DF
IIC0S0
IIC0S0D
IIC0S1
IIC0S1D
IIC0S2
RSVREG02E5
IIC0S0S
After reset
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
??16
0016
0001000?2
0016
0016
00?000002
??16
I2C1 data shift register
I2C1 address register
I2C1 status register
I2C1 control register
I2C1 clock control register
Reserved register
I2C1 transmitting buffer register
IIC1S0
IIC1S0D
IIC1S1
IIC1S1D
IIC1S2
RSVREG02ED
IIC1S0S
??16
0016
0001000?2
0016
0016
00?000002
??16
I2C2 data shift register
I2C2 address register
I2C2 status register
I2C2 control register
I2C2 clock control register
Reserved register
I2C2 transmitting buffer register
IIC2S0
IIC2S0D
IIC2S1
IIC2S1D
IIC2S2
RSVREG02F5
IIC2S0S
??16
0016
0001000?2
0016
0016
00?000002
??16
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 17 of 363
M306V8FJFP
Address
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
Register
Data slicer 1 control register 1
Data slicer 1 control register 2
CPS1
SBV1
DR11
CRD1
DPS1
IDC1
BCD1
CRC1
IDT1
RSVREG030F
After reset
0016
?0?0??0?2
????????2
????????2
????????2
????????2
00?000002
0016
0016
0016
X00000002
0016
XX??????2
XX0000002
0016
XXXXXXX02
IRSV0
IRSV1
00??????2
00??????2
Symbol
DSC11
DSC12
Caption data register 11
CD11
Caption data register 12
CD12
Caption position register 1
Slice standard voltage selection register
Data slicer 1 reserved register 1
Clock run-in detection register 1
Data clock position register 1
ID1 control register 1
Standard clock detection register 1
CRCC data register 1
Test reservation register 1
Reserved register
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
ID1 reserved register 0
ID1 reserved register 1
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
? : This bit is indeterminate.
page 18 of 363
M306V8FJFP
Address
034016
Register
Symbol
After reset
Timer B3, 4, 5 count start flag
TBSR
000XXXXX2
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
RSVREG0342
RSVREG0343
RSVREG0344
RSVREG0345
RSVREG0346
RSVREG0347
RSVREG0348
RSVREG0349
RSVREG034A
RSVREG034B
RSVREG034C
RSVREG034D
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
??16
??16
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
Timer B3 register
TB3
Timer B4 register
TB4
Timer B5 register
TB5
035116
035216
035316
035416
035516
??16
??16
??16
??16
??16
??16
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 2
Interrupt cause select register
Reserved register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
RSVREG0360
00??00002
00?X00002
00?X00002
00XXXXXX2
0016
??16
Reserved register
Reserved register
Reserved register
RSVREG0362
RSVREG0363
RSVREG0364
010000002
??16
??16
Reserved register
Reserved register
RSVREG0366
RSVREG0367
010000002
??16
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
??16
????????2
XXXXXXX?2
000010002
000000102
????????2
?????XX?2
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
? : This bit is indeterminate.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 19 of 363
M306V8FJFP
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After reset
0016
0XXXXXXX2
0016
0016
0016
Timer A0 register
TA0
Timer A1 register
TA1
Timer A2 register
TA2
Timer A3 register
TA3
Timer A4 register
TA4
Timer B0 register
TB0
Timer B1 register
TB1
Timer B2 register
TB2
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
00??00002
00?X00002
00?X00002
XXXXXX002
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Reserved register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
RSVREG039E
039F16
03A016
UART0 transmit/receive mode register
03A116
UART0 bit rate generator
UART0 transmit buffer register
03AD16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
03AE16
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
0016
??16
????????2
XXXXXXX?2
000010002
000000102
????????2
?????XX?2
0016
??16
????????2
XXXXXXX?2
000010002
000000102
????????2
?????XX?2
X00000002
DMA0 request cause select register
DM0SL
0016
DMA1 request cause select register
DM1SL
0016
03A216
U0MR
U0BRG
U0TB
03A316
03A416
03A516
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
03A616
UART0 receive buffer register
U0C0
U0C1
U0RB
03A716
03A816
UART1 transmit/receive mode register
03A916
UART1 bit rate generator
UART1 transmit buffer register
03AA16
U1MR
U1BRG
U1TB
03AB16
03AC16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
Reserved register
Reserved register
Reserved register
RSVREG03BC
RSVREG03BD
RSVREG03BE
03BF16
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
? : This bit is indeterminate.
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page 20 of 363
??16
??16
??16
M306V8FJFP
Address
03C016
03C116
03C216
03C316
03C416
03C516
03C616
Register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
A/D register 3
Symbol
RSVREG03C0
RSVREG03C1
RSVREG03C2
RSVREG03C3
RSVREG03C4
RSVREG03C5
AD3
03C716
03C816
A/D register 4
AD4
A/D register 5
AD5
A/D register 6
AD6
A/D register 7
AD7
A/D control register 2
ADCON2
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
After reset
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
????????2
XXXXXX??2
03D016
03D116
03D216
03D316
03D416
0016
03D516
03D616
03D716
03D816
A/D control register 0
A/D control register 1
Reserved register
ADCON0
ADCON1
RSVREG03D8
00000???2
0016
??16
Reserved register
RSVREG03DA
??16
Reserved register
RSVREG03DC
0016
Reserved register
Reserved register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
Rserved register
Port P10 direction register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Pull-up control register 0
Pull-up control register 1
RSVREG03DE
RSVREG03DF
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
RSVREG03F5
PD10
RSVREG03F7
RSVREG03F8
RSVREG03F9
RSVREG03FA
RSVREG03FB
PUR0
PUR1
XX00XXXX2
0016
??16
??16
0016
0016
?? 16
?? 16
0016
0016
?? 16
??16
0016
0016
??16
??16
0016
0016
?? 16
?? 16
00X000002
0016
??16
??16
0016
0016
??16
??16
0016
0016
0016
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Pull-up control register 2
Port control register
PUR2
PCR
000000002
000000102
0016
0016
Notes 1: The blank areas are reserved and cannot be accessed by users.
2: At hardware reset 1 or hardware reset 2, the register is as follows
:
• “000000002” where “L” is inputted to the CNVSS1 pin
• “000000102” where “H” is inputted to the CNVSS1 pin
At software reset, watchdog timer reset, the register is as follows:
• “000000002” where the PM01 to PM00 bits in the PM0 register are “002” (single-chip mode)
• “000000102” where the PM01 to PM00 bits in the PM0 register are “002” (memory expansion mode) or
“112” (microprocessor mode)
X : Nothing is mapped to this bit
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? : This bit is indeterminate.
page 21 of 363
(Note 2)
M306V8FJFP
Reset
There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset.
Hardware Reset
____________
_____________
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power
supply voltage is within the recommended operating condition, the pins are initialized (see Table 3.1. Pin
____________
Status When RESET Pin Level is “L”). The oscillation circuit is initialized and the main clock starts oscil____________
lating. When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized,
and the program is executed starting from the address indicated by the reset vector. The internal RAM is
____________
not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM becomes
indeterminate.
Figure 3.1 shows the example reset circuit. Figure 3.2 shows the reset sequence. Table 3.1 shows the
____________
status of the other pins while the RESET pin is “L”. Figure 3.3 shows the CPU register status after reset.
Refer to “SFR” for SFR status after reset.
1. When the power supply is stable
____________
(1) Apply an “L” signal to the RESET pin.
(2) Supply a clock for 20 cycles or more to the XIN pin.
(3) Apply an “H” signal to the RESET pin.
2. Power on
____________
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply stabilizes.
(4) Supply a clock for 20 cycles or more to the XIN pin.
____________
(5) Apply an “H” signal to the RESET pin.
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M306V8FJFP
Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset
vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.
Recommended
operating
voltage
VCC
RESET
VCC1
VCC2
VCC3
0V
RESET
Equal to or less
than 0.2VCC1
0V
Equal to or less
than 0.2VCC1
More than 20 cycles of XIN + td(P-R)
are needed.
Note: When starting the power or turning it off, prevent the Vcc2 voltage from exceeding Vcc1 voltage.
Figure 3.1 shows the example reset circuit
Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed
starting from the address indicated by the reset vector.
At watchdog timer reset, some SFR ’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00
bits in the PM0 register are not initialized, the processor mode remains unchanged.
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M306V8FJFP
VCC1, VCC2,
VCC3
XIN
td(P-R)
More than
20 cycles
are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
28cycles
BCLK
Content of reset vector
FFFFC16
Address
FFFFD16
FFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
Address
FFFFE16
RD
WR
CS0
Single chip
mode
FFFFC16
FFFFE16
Address
Figure 3.2. Reset sequence
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Content of reset vector
page 24 of 363
M306V8FJFP
____________
Table 3.1. Pin Status When RESET Pin Level is “L”
Status
CNVSS1 = VCC1
Pin name
CNVSS1 = VSS
BYTE = VSS
BYTE = VCC
P0
Input port
Data input
Data input
P1
Input port
Data input
Input port
P2, P3, P40 to P43
Input port
Address output (undefined)
Address output (undefined)
P44
Input port
CS0 output (“H” is output)
CS0 output (“H” is output)
P45 to P47
Input port
Input port (Pulled high)
Input port (Pulled high)
P50
Input port
WR output (“H” is output)
WR output (“H” is output)
P51
Input port
BHE output (indeterminate)
BHE output (indeterminate)
P52
Input port
RD output (“H” is output)
RD output (“H” is output)
P53
Input port
BCLK output
BCLK output
P54
Input port
HLDA output (The output value HLDA output (The output value
depends on the input to the
depends on the input to the
HOLD pin)
HOLD pin)
P55
Input port
HOLD input
HOLD input
P56
Input port
ALE output (“L” is output)
ALE output (“L” is output)
P57
Input port
RDY input
RDY input
Input port
Input port
P6, P7, P8, P9, P10 Input port
OSC2/VSYNC1,
OSCOUT, DIGR1,
HSYNC
SCL4, SDA4, SCL5
SDA5, SCL6, SDA6
Output state
DIGR1, DIGG1
DIGB1,
DIGR2, DIGG2
DIGB2
Output state (undefined)
R/DIGR0, G/DIGG0,
B/DIGB0, OUT1,
OUT2,
OSC1/OSCHLF,
CVIN1
VHOLD1, HLF1,
CVIN2, VHOLD2,
HLF2
Input state
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M306V8FJFP
b15
b0
000016
Data register(R0)
000016
Data register(R1)
000016
Data register(R2)
000016
Data register(R3)
000016
000016
Address register(A0)
Address register(A1)
000016
Frame base register(FB)
b19
b0
0000016
Interrupt table register(INTB)
Content of addresses FFFFE16 to FFFFC16
b15
Program counter(PC)
b0
000016
User stack pointer(USP)
000016
Interrupt stack pointer(ISP)
000016
Static base register(SB)
b15
b0
Flag register(FLG)
000016
b15
b8
IPL
b7
U I
b0
O B S Z D C
Figure 3.3. CPU Register Status After Reset
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Bit symbol
(b4-b0)
(b5, b6)
WDC7
Figure 3.4. WDC Register
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Address
000F16
After reset
00XXXXXX2
Bit name
Function
RW
High-order bit of watchdog timer
RO
Reserved bit
Must set to “0”
RW
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
M306V8FJFP
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
0 0 0 0
Symbol
RSVREG0019
Bit symbol
Address
001916
After reset
000010002
Bit name
(b 2- b0)
Reserved bit
(b 3)
Reserved bit
(b 7- b4)
Reserved bit
Function
Must set to “0”
RW
RW
RO
Must set to “0”
RW
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbol
RSVREG001A
Bit symbol
(b 7- b0)
Address
001A16
After reset
0016
Bit name
Reserved bit
Function
Must set to “0”
RW
RW
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbol
RSVREG001F
Bit symbol
Bit name
After reset
0016
Function
Must set to “0”
(b 5- b0)
Reserved bit
(b 7- b6)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Figure 3.5. Reserved register
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Address
001F16
page 27 of 363
RW
RW
M306V8FJFP
Processor Mode
(1) Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 4.1 shows the features of these processor modes.
Table 4.1. Features of Processor Modes
Access space
Processor modes
Single-chip mode
Memory expansion mode
SFR, internal RAM, internal ROM,
OSDRAM, OSDROM
SFR, internal RAM, internal ROM,
external area (Note),
OSDRAM, OSDROM
Pins which are assigned I/O ports
All pins are I/O ports or peripheral
function I/O pins
Some pins serve as bus control pins (Note)
SFR, internal RAM, external area (Note), Some pins serve as bus control pins (Note)
OSDRAM, OSDROM
Microprocessor mode
Note : Refer to “Bus”.
(2) Setting Processor Modes
Processor mode is set by using the CNVSS1 pin and the PM01 to PM00 bits in the PM0 register.
Table 4.2 shows the processor mode after hardware reset. Table 4.3 shows the PM01 to PM00 bit set
values and processor modes.
Table 4.2. Processor Mode After Hardware Reset
CNVSS1 pin input level
VSS
VCC1 (Note 1, Note 2)
Processor mode
Single-chip mode
Microprocessor mode
Note 1: If the microcomputer is reset in hardware by applying VCC1 to the CNVSS1 pin (hardware reset 1
or hardware reset 2), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Note 2: The multiplexed bus cannot be assigned to the entire CS space.
Table 4.3. PM01 to PM00 Bits Set Values and Processor Modes
PM01 to PM00 bits
Processor modes
002
Single-chip mode
012
Memory expansion mode
102
Must not be set
112
Microprocessor mode
Rewriting the PM01 to PM00 bits places the microcomputer in the corresponding processor mode regardless of whether the input level on the CNVSS1 pin is “H” or “L”. Note, however, that the PM01 to PM00 bits
cannot be rewritten to “012” (memory expansion mode) or “112” (microprocessor mode) at the same time
the PM07 to PM02 bits are rewritten. Note also that these bits cannot be rewritten to enter microprocessor
mode in the internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the
internal ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS1 pin (hardware reset 1 or
hardware reset 2), the internal ROM cannot be accessed regardless of PM01 to PM00 bits.
Figures 4.1 and 4.2 show the registers associated with processor modes. Figure 4.3 show the memory
map in single chip mode.
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M306V8FJFP
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PM0
Bit symbol
PM00
Address
000416
After reset (Note 4)
000000002 (CNVSS1 pin = “L”)
000000112 (CNVSS1 pin = “H”)
Bit name
Processor mode bit
(Note 4)
PM01
PM02
R/W mode select bit
(Note 2)
PM03
Software reset bit
PM04
Multiplexed bus space
select bit (Note 2)
PM05
PM06
PM07
Function
b1 b0
RW
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
RW
0 : RD,BHE,WR
1 : RD,WRH,WRL
RW
Setting this bit to “1” resets the
microcomputer. When read, its content
is “0”.
RW
RW
b5 b4
0 0 : Multiplexed bus is unused
(Separate bus in the entire CS
space)
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to the entire CS space
(Note 3)
RW
RW
Port P40 to P43 function
select bit (Note 2)
0 : Address output
1 : Port function
(Address is not output)
RW
BCLK output disable bit
(Note 2)
0 : BCLK is output
1 : BCLK is not output
(Pin is left high-impedance)
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Note 2: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Note 3: To set the PM01 to PM00 bits are “012” and the PM05 to PM04 bits are “112” (multiplexed bus assigned to
the entire CS space), apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the
CNVSS1 pin is held “H” (= VCC1), do not rewrite the PM05 to PM04 bits to “112” after reset.
If the PM05 to PM04 bits are set to “112” during memory expansion mode, P31 to P37 and P40 to P43
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 4: The PM01 to PM00 bits do not change at software reset and watchdog timer reset.
Figure 4.1. PM0 Register
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M306V8FJFP
Processor mode register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
PM1
Bit symbol
Address
000516
After reset
0X0010002
Bit name
Function
RW
0: 0900016 to 26FFF16
(block A disable)
1: 1000016 to 26FFF16
(block A enable)
RW
PM10
CS2 area switch bit
(data block enable bit)
(Note 2)
PM11
0 : Address output
Port P37 to P34
function select bit (Note 3) 1 : Port function
PM12
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 4)
RW
PM13
Internal reserved area
expansion bit
See Note 6
RW
Memory area
expansion bit (Note 3)
b5 b4
PM14
PM15
(b6)
PM17
0 0 : 1 Mbyte mode
(Do not expand)
0 1 : Must not be set
1 0 : Must not be set
1 1 : 4 Mbyte mode
Reserved bit
Should be set to “0”.
Wait bit (Note 5)
0 : No wait state
1 : With wait state (1 wait)
RW
RW
RW
RW
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: For the mask ROM version, this bit must be set to “0” . For the flash memory version, the PM10 bit also
controls block A by enabling or disabling it. However, the PM10 bit is automatically set to “1” when the FMR0
1 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 3: Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Note 4: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 5: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing the internal RAM,
internal ROM, or an external area. If the CSiW bit (i = 0 to 3) in the CSR register is “0” (with wait state), the
CSi area is always accessed with one or more wait states regardless of whether the PM17 bit is set or not.
Where the RDY signal is used or multiplex bus is used, set the CSiW bit to “0” (with wait state).
Note 6: The PM13 bit is automatically set to “1” when the FMR01 bit in the FMR0 register is “1” (CPU rewrite mode).
Note 7: The access area is changed by the PM13 bit as listed in the table below.
Access area
PM13=0
Internal RAM Up to addresses 0040016 to 03FFF16 (15 Kbytes)
PM13=1
The entire area is usable
ROM Up to addresses D000016 to FFFFF16 (192 Kbytes) The entire area is usable
External
Addresses 0400016 to 07FFF16 are usable
Addresses 0400016 to 07FFF16 are reserved
Addresses 8000016 to CFFFF16 are usable
Addresses 8000016 to CFFFF16 are reserved
Figure 4.2. PM1 Register
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M306V8FJFP
Single-chip mode
0000016
SFR
0040016
Internal RAM
XXXXX16
0800016
08FFF16
Can not use
OSD RAM area
PM13=0
Can not
use
15K bytes
3000016
4FFFF16
YYYYY16
Internal RAM
Capacity Address XXXXX16
03FFF16(Note 2)
Internal ROM
Capacity
Address YYYYY16
192K bytes
D000016(Note 2)
OSD ROM area
Can not use
Internal ROM
PM13=1
Internal RAM
Capacity Address XXXXX16
16K bytes
043FF16
Internal ROM
Capacity
Address YYYYY16
512K bytes
8000016
FFFFF16
Note 1: For the mask ROM version, set the PM10 bit to “0” (0800016 to 26FFF16 for CS2 area).
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
Figure 4.3. Memory Map in Single Chip Mode
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M306V8FJFP
Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
_______
data input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to
_______ _____ ________ ______ ________ ________
________ __________ _________
CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
Bus Mode
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0
register.
Separate Bus
In this bus mode, data and address are separate.
Multiplexed Bus
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.
External buses connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd addresses cannot be accessed.
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M306V8FJFP
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software
wait.
(1) Address Bus
The address bus consists of 20 lines, A0 to A19. The address bus width can be chosen to be 12, 16 or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 4.4
shows the PM06 and PM11 bit set values and address bus widths.
Table 4.4. PM06 and PM11 Bits Set Value and Address Bus Width
Set value(Note)
PM11=1
PM06=1
Pin function
P34 to P37
P40 to P43
PM11=0
A12 to A15
PM06=1
P40 to P43
PM11=0
A12 to A15
PM06=0
A16 to A19
Address bus wide
12 bits
16 bits
20 bits
Note 1: No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory extension mode, the address
bus is indeterminate until any external area is accessed.
(2) Data Bus
16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
(3) Chip Select Signal
_____
______
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These
_____
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.
Figure 4.4 shows the CSR register.
______
During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
______
______
______
from the CSi pin. During 4 Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to
______
“Memory space expansion function”. Figure 4.5 shows the example of address bus and CSi signal
output in 1 Mbyte mode.
Chip select control register
b7
b6
b5
b4
b3
b2
b1
Symbol
CSR
b0
Bit symbol
CS0
Address
000816
Bit name
CS1
CS0 output enable bit
CS1 output enable bit
CS2
CS2 output enable bit
CS3
CS3 output enable bit
CS0W
CS0 wait bit
CS1W
CS1 wait bit
CS2W
CS2 wait bit
CS3W
CS3 wait bit
After reset
0116
Function
0 : Chip select output disabled
(functions as I/O port)
1 : Chip select output enabled
RW
RW
RW
RW
RW
0 : With wait state
1 : Without wait state
(Note 1, Note 2, Note 3)
RW
RW
RW
RW
Notes 1: Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set
the CSiW bit to “0” (Wait state).
2: When the PM17 bit in the PM1 register is set to “1” (wait), set the CSiW bit to “1” (wait).
3: When the CSiW bit = “0” (with wait state), the number of wait states (interms of clock cycles) can be
selected using the CSEi1W to CSEi0W bits in the CSE register.
Figure 4.4. CSR Register
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Example 2
Example 1
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The address bus and the chip select signal both change state between
these two cycles.
The chip select signal changes state but the address bus does not
change state
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data bus
Address Address
Address bus
Data
Access to the internal
ROM or internal RAM
Data
Address
CSi
CSi
CSj
Example 3
Example 4
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
The address bus changes state but the chip select signal does not
change state
Neither the address bus nor the chip select signal changes state between
these two cycles
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Access to the same
external area
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data bus
Data
Address Address
Address bus
CSi
No access
Data
Address
CSi
Note : These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle
may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3
(not including i, however)
______
Figure 4.5. Example of Address Bus and CSi Signal Output in 1 Mbyte Mode
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(4) Read and Write Signals
_____
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
________
______
_____ ________
________
BHE and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When
_____ ______
________
the data bus is 8 bits wide, use a combination of RD, WR and BHE.
_____ ________
_________
Table 4.5 shows the operation of RD, WRL, and WRH signals. Table 4.6 shows the operation of operation
_____ ______
________
of RD, WR, and BHE signals.
_____
________
_________
Table 4.5. Operation of RD, WRL and WRH Signals
Data bus width
RD
L
H
H
H
16-bit
( BYTE pin input
= “L”)
WRL
H
L
H
L
_____
______
WRH
H
H
L
L
Status of external data bus
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
________
Table 4.6. Operation of RD, WR and BHE Signals
Data bus width
16-bit
(BYTE pin input
= “L”)
RD
H
L
H
L
H
L
WR
L
H
L
H
L
H
BHE
L
L
H
H
L
L
A0
H
H
L
L
L
L
Status of external data bus
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
(5) ALE Signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
ALE
Address
A0
A1/D0 to A8/D7
A9 to A19
Address
Data
Address
Note : If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 4.6. ALE Signal, Address Bus, Data Bus
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________
(6) The RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
________
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
________
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
______
______
______ ________
________
______
________
__________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
________
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 4.7 shows example in which the wait state was inserted into the read cycle by the
________
________
RDY signal. To use the RDY signal, set the corresponding bit (CS3W to CS0W bits) in the CSR register
________
________
to “0” (with wait state). When not using the RDY signal, process the RDY pin as an unused pin.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
: Wait using RDY signal
Accept timing of RDY signal
: Wait using software
tsu(RDY-BCLK) : RDY input setup time
Shown above is the case where CSEiW to CSEi1W (i = 0 to 3) bits in the CSE register are “002” (one wait state).
________
Figure 4.7. Example in which Wait State was Inserted into Read Cycle by RDY Signal
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__________
(7) HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
__________
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
__________
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
__________
which time the HLDA pin outputs a low-level signal.
Table 4.7 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.
__________
HOLD > DMAC > CPU
Figure 4.8. Bus-using Priorities
Table 4.7. Microcomputer Status in Hold State
Item
Status
BCLK
Output
_______
_______
_____
________
_________ _______ _______
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE
I/O ports
P0, P1, P3, P4(Note 1)
P6 to P10
High-impedance
High-impedance
Maintains status when hold signal is received
__________
HLDA
Internal peripheral circuits
ALE signal
Output “L”
ON (but watchdog timer stops)
Indeterminate
Note 1: When I/O port function is selected.
(8) BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as
that of the CPU clock is output as BCLK from the BCLK pin.
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Table 4.8. Pin Functions for Each Processor Mode
Processor mode
Memory expansion mode or microprocessor mode
002(separate bus)
PM05–PM04 bits
Data bus width
16 bits
“L”
BYTE pin
P00 to P07
012(CS2 is for multiplexed bus and
others are for separate bus)
102(CS1 is for multiplexed bus and
others are for separate bus)
D0 to D7
16 bits
“L”
D0 to D7(Note)
P10 to P17
D8 to D15
D8 to D15(Note)
P20
A0
A0
P21 to P27
A1 to A7
A1 to A7/D0 to D6
(Note 2)
P30
A8
A8/D7(Note 2)
P31 to P33
A9 to A11
P34 to P37
PM11=0
A12 to A15
PM11=1
I/O ports
P40 to P43
PM06=0
A16 to A19
PM06=1
I/O ports
P44
CS0=0
I/O ports
CS0=1
CS0
CS1=0
I/O ports
CS1=1
CS1
CS2=0
I/O ports
CS2=1
CS2
CS3=0
I/O ports
CS3=1
CS3
P45
P46
P47
P50
P51
PM02=0
WR
PM02=1
WRL
PM02=0
BHE
PM02=1
WRH
P52
RD
P53
BCLK
P54
HLDA
P55
P56
HOLD
ALE
P57
RDY
WRL
WRH
I/O ports: Function as I/O ports or peripheral function I/O pins.
Note 1: When VCC1 is inputted into CNVSS1 pin, do not set bits PM05 and PM04 to “112” after reset.
Since P31 to P37, and P40 to P43 become I/O ports when bits PM05 snd PM04 are set to “112” in memory extension mode,
the area which can be accessed is 256 bytes per CS.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3: When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.
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(9) External Bus Status When Internal Area Accessed
Table 4.9 shows the external bus status when the internal area is accessed.
Table 4.9. External Bus Status When Internal Area Accessed
Item
SFR accessed
Internal ROM, RAM accessed
A0 to A19
Address output
Maintain status before accessed
address of external area or SFR
D0 to D15
When read
High-impedance
High-impedance
When write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output “H”
BHE
BHE output
Maintain status before accessed
status of external area or SFR
CS0 to CS3
Output “H”
Output “H”
ALE
Output “L”
Output “L”
(10) Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK.
________
To use the RDY signal, set the corresponding CS0W to CS3W bit to “0”(with wait state). Figure 4.9 shows
the CSE register. Table 4.10 shows the software wait related bits and bus cycles. Figure 4.10 and 4.11
show the typical bus timings using software wait.
Chip select expansion control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CSE
Bit symbol
CSE00W
CSE01W
CSE10W
CSE11W
CSE20W
CSE21W
CSE30W
CSE31W
Address
001B16
Bit name
After reset
0016
Function
b1 b0
CS0 wait expansion bit
(Note) 0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
RW
RW
b3 b2
CS1 wait expansion bit
(Note) 0 0: 1 wait
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
b5 b4
CS2 wait expansion bit
0 0: 1 wait
(Note) 0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
b7 b6
CS3 wait expansion bit
0 0: 1 wait
(Note)
0 1: 2 waits
1 0: 3 waits
1 1: Must not be set
RW
RW
RW
RW
Note: Set the CSiW bit (i = 0 to 3) in the CSR register to “0” (with wait state) before writing to the CSEi1W to
CSEi0W bits. If the CSiW bit needs to be set to “1” (without wait state), set the CSEi1W to CSEi0W bits to “
002” before setting it.
Figure 4.9. CSE Register
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Table 4.10. Bit and Bus Cycle Related to Software Wait
Area
Bus mode
PM1 register
PM17 bit
CSR register
CS3W bit (Note 1)
CS2W bit (Note 1)
CS1W bit (Note 1)
CS0W bit (Note 1)
CSE register
CSE31W to CSE30W bit
CSE21W to CSE20W bit
CSE11W to CSE10W bit
CSE01W to CSE00W bit
Software wait
SFR
Bus cycle
2 BCLK cycle
Internal
RAM, ROM
0
No wait
1
1 wait
1 BCLK cycle (Note 3)
2 BCLK cycles
1 BCLK cycle (read)
0
1
002
No wait
2 BCLK cycles (write)
Separate bus
External
area
1
Multiplexed
bus (Note 2)
1
0
002
1 wait
2 BCLK cycles (Note 3)
0
012
2 waits
3 BCLK cycles
0
102
3 waits
4 BCLK cycles
1
002
1 wait
2 BCLK cycles
0
002
1 wait
3 BCLK cycles
0
012
2 waits
3 BCLK cycles
0
102
3 waits
4 BCLK cycles
0
002
1 wait
3 BCLK cycles
Notes 1: To use the RDY signal, set this bit to “0”.
2: To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
3: After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0” (with wait state), and the CSE register is set to
“0016” (one wait state for CS0 to CS3). Therefore, the internal RAM and internal ROM are accessed with no wait states, and all external areas are
accessed with one wait state.
4: When the PM17 bit is set to “1” and accessing external area, set the CSiW bit (0 to 3) in the CSR register to “0” (wait).
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(1) Separate bus, No wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
CS
(2) Separate bus, 1-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Input
Address
Address
CS
(3) Separate bus, 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 4.10. Typical Bus Timings Using Software Wait (1)
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(1) Separate bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Input
Output
Address
Address bus
Address
CS
(2)Multiplexed bus, 1- or 2-wait setting
Bus cycle (Note)
Bus cycle (Note)
Address
Address
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Data output
Address
Input
CS
(3)Multiplexed bus, 3-wait setting
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Address
Address
Data output
Address
Input
CS
Note : These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 4.11. Typical Bus Timings Using Software Wait (2)
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Memory Space Expansion Function
The following describes a memory space extension function.
During memory expansion or microprocessor mode, the memory space expansion function allows the
access space to be expanded using the appropriate register bits.
Table 4.11 shows the way of setting memory space expansion function, memory spaces.
Table 4.11. The Way of Setting Memory Space Expansion Function, Memory Space
Memory space expansion function
How to set (PM15 to PM14)
Memory space
1 Mbytes mode
4 Mbytes mode
002
112
1 Mbytes (no expansion)
4 Mbytes
(1) 1 Mbyte Mode
In this mode, the memory space is 1 Mbytes. In 1 Mbyte mode, the external area to be accessed is
______
______
specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 4.13 to 4.14
_____
show the memory mapping and CS area in 1 Mbyte mode.
(2) 4 Mbyte Mode
In this mode, the memory space is 4 Mbytes. Figure 4.12 shows the DBR register. The BSR2 to BSR0
bits in the DBR register select a bank number which is to be accessed to read or write data. Setting the
OFS bit to “1” (with offset) allows the accessed address to be offset by 4000016.
______
In 4 Mbyte mode, the CSi (i=0 to 3) pin functions differently for each area to be accessed.
Addresses 0400016 to 3FFFF16, C000016 to FFFFF16
______
______
• The CSi signal is output from the CSi pin (same operation as 1 Mbyte mode. However the last address
_______
of CS1 area is 3FFFF16)
Addresses 4000016 to BFFFF16
______
• The CS0 pin outputs “L”
______
______
• The CS1 to CS3 pins output the value of setting as the BSR2 to BSR0 bits (bank number)
______
Figures 4.15 to 4.16 show the memory mapping and CS area in 4 Mbyte mode. Note that banks 0 to 6 are
______
data-only areas. Locate the program in bank 7 or the CSi area.
Data bank register (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DBR
Address
000B16
Bit symbol
(b1-b0)
Bit name
Offset bit
BSR0
Bank selection bits
BSR2
(b7-b6)
Description
RW
Nothing is assigned. When write, set to “0”. When read, its content is
“0”.
OFS
BSR1
After reset
0016
0: Not offset
1: Offset
b5 b4 b3
0 0 0: Bank 0
0 0 1: Bank 1
0 1 0: Bank 2
0 1 1: Bank 3
RW
b5 b4 b3
1 0 0: Bank 4
1 0 1: Bank 5
1 1 0: Bank 6
1 1 1: Bank 7
RW
RW
RW
Nothing is assigned. When write, set to “0”. When read, its content is
“0”.
Note : Effective when the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor
mode).
Figure 4.12. DBR Register
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Microprocessor mode
Memory expansion mode
0000016
0040016
SFR
SFR
Internal RAM
03FFF16
0400016
0800016
0900016
Internal RAM
OSD RAM area
External area
1000016
2700016
2800016
3000016
5000016
External area
Reserved area
CS2(PM10=0: 120 Kbytes)
CS2 (PM10=1: 92 Kbytes)
Reserved area
OSD ROM area
CS1(32 Kbytes)
OSD ROM area
CS0(Memory expansion mode:512 Kbytes )
External area
External area
D000016
CS3(16 Kbytes)
OSD RAM area
Internal ROM
FFFFF16
PM13=0
Internal RAM (Note 1)
Address
Capacity
Internal ROM (Note 1)
Address
Capacity
15 Kbytes 0040016 to
03FFF16
192 Kbytes D000016 to
FFFFF16
CS0(Microprocessor mode:704 Kbytes)
External area
CS0
Memory expansion mode
5000016–CFFFF16
CS1
2800016–
2FFFF16
Microprocessor mode
5000016–FFFFF16
CS2
When PM10=0
0900016–26FFF16
CS3
0400016–
07FFF16
When PM10=1
1000016–26FFF16
Note : If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
______
Figure 4.13. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=0)
Microprocessor mode
Memory expansion mode
0000016
SFR
SFR
Internal RAM
Internal RAM
0040016
043FF16
0440016
0800016
0900016
OSD RAM area
External area
1000016
2700016
Reserved area
2800016
3000016
5000016
OSD ROM area
External area
8000016
Internal ROM
FFFFF16
PM13=1
OSD RAM area
External area
CS2(PM10=0: 120 Kbytes)
CS2 (PM10=1: 92 Kbytes)
Reserved area
CS1(32 Kbytes)
OSD ROM area
CS0(Memory expansion mode:192 Kbytes )
External area
Internal RAM
Capacity
Address
Internal ROM
Address
Capacity
16 Kbytes 0040016 to
043FF16
512 Kbytes 8000016 to
FFFFF16
CS0(Microprocessor mode:704 Kbytes)
CS0
Memory expansion mode
5000016–7FFFF16
External area
CS1
2800016–
2FFFF16
Microprocessor mode
5000016–FFFFF16
______
Figure 4.14. Memory Mapping and CS Area in 1 Mbyte Mode (PM13=1)
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CS2
When PM10=0
0900016–26FFF16
When PM10=1
1000016–26FFF16
CS3
No area
M306V8FJFP
Microprocessor mode
Memory expansion mode
0000016
SFR
SFR
Internal RAM
Internal RAM
0040016
03FFF16
0400016
0800016
0900016
OSD ROM area
External area
External area
1000016
2700016
2800016
3000016
5000016
CS3(16 Kbytes)
OSD ROM area
Reserved area
CS2(PM10=0: 120 Kbytes)
CS2 (PM10=1: 92 Kbytes)
Reserved area
OSD ROM area
CS1(32 Kbytes)
OSD ROM area
External area
External area
C000016
D000016
Internal ROM
FFFFF16
CS0(Memory expansion mode:448 Kbytes )
CS2(PM10=1: 64 Kbytes)
CS0(Microprocessor mode:256 Kbytes)
PM13=0
Internal RAM (Note 2)
Capacity
Address
Internal ROM (Note 2)
Address
Capacity
15 Kbytes 0040016 to
03FFF16
192 Kbytes D000016 to
FFFFF16
CS0
Memory expansion mode
C000016–CFFFF16
External area
CS1
CS2
2800016–
When PM10=0
2FFFF16
0900016–26FFF16
Microprocessor mode
C000016–FFFFF16
CS3
0400016–
07FFF16
Other than the CS area (Note 1)
5000016–BFFFF16
When PM10=1
1000016–26FFF16
Note 1: The CS0 pin outputs a low signal, and the CS1 - CS3 pins output a bank number.
Note 2: If PM13 bit is set to “0”, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
______
Figure 4.15. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=0)
Microprocessor mode
Memory expansion mode
0000016
SFR
SFR
Internal RAM
Internal RAM
0040016
043FF16
0440016
0800016
0900016
OSD ROM area
External area
1000016
2700016
2800016
Reserved area
3000016
5000016
OSD ROM area
External area
8000016
C000016
Internal ROM
FFFFF16
PM13=1
Internal RAM
Capacity
Address
Internal ROM
Address
Capacity
16 Kbytes 0040016 to
043FF16
512 Kbytes 8000016 to
FFFFF16
OSD ROM area
External area
CS2(PM10=0: 120 Kbytes)
CS2(PM10=1: 92 Kbytes)
Reserved area
CS1(32 Kbytes)
OSD ROM area
External area
Other than the CS area (Memory expansion mode:192 Kbytes X 8 banks)*
*Two 192 Kbytes X 8 banks can be used by changing the offset.
Other than the CS area(Microprocessor mode:448 Kbytes X 8 banks)
CS0(Microprocessor mode:256 Kbytes)
External area
CS0
Microprocessor mode
C000016–FFFFF16
CS1
2800016–
2FFFF16
CS2
When PM10=0
0900016–26FFF16
When PM10=1
1000016–26FFF16
Note 1: The CS0 pin outputs a low signal, and the CS1 - CS3 pins output a bank number.
______
Figure 4.16. Memory Mapping and CS Area in 4 Mbyte Mode (PM13=1)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
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CS3
No area
Other than the CS area (Note 1)
Memory expansion mode
5000016–7FFFF16
Microprocessor mode
5000016–BFFFF16
M306V8FJFP
Figure 4.17 shows the external memory connect example in 4 Mbyte mode.
_____
_______
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte
_______ _______
_______
ROM address input AD21, AD20 and AD19 pins are connected to the CS3, CS2 and CS1 pins of microcomputer, respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures 4.18 to 4.20 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer
for the case of a connection example in Figure 4.17.
In microprocessor mode, or in memory expansion mode where the PM13 bit in the PM1 register is “0”,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to “1”(offset) allows the
accessed address to be offset by 4000016, so that even the data overlapping a bank boundary can be
accessed in succession.
In memory expansion mode where the PM13 bit is “1”, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them over with the OFS bit.
____
_______
Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 =“L”, CS0
_______
____
and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins to accept
____
_______
_______
“H” active and “L” active chip select signals(S1, S2), CS0 and CS2 should be decoded external to the
chip.
M306V8
A17
A19
DQ0 to DQ7
17
AD0 to AD16
AD17
AD18
CS1
AD19
CS2
AD20
CS3
AD21
OE
RD
CS0
CS
WR
DQ0 to DQ7
AD0 to AD16
OE
S2
S1
W
(Note)
4M bytes ROM
A0 to A16
8
128K bytes SRAM
D0 to D7
Note: If only one chip select pin (S1 or S2) is present,
decoding by use of an external circuit is required.
Figure 4.17. External Memory Connect Example in 4M Byte Mode
Rev.1.31 Apr 18, 2005
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Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 47 of 363
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFS
Access
area
0
FFFF16
000016
3CFFFF16
3FFFFF16
3C000016
3C000016
3BFFFF16
39000016
3BFFFF16
37FFFF16
35000016
31000016
33FFFF16
2D000016
29000016
2FFFFF16
2BFFFF16
25000016
27FFFF16
21000016
1D000016
23FFFF16
1FFFFF16
19000016
1BFFFF16
15000016
11000016
17FFFF16
13FFFF16
0D000016
0FFFFF16
09000016
05000016
0BFFFF16
07FFFF16
01000016
Address input for 4Mbyte ROM
Internal ROM access
Internal ROM access
A19
A18 N.C. A17
A16 A15–A0
Address input for 4-Mbyte ROM
0
0
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
A15–A0
D000016
A20
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
DFFFF16
A21
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
Internal ROM access
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
A17
Address output
A18
Internal ROM access
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
A19
D000016
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
CS1
DFFFF16
C000016
CFFFF16
1
1
BFFFF16
1
1
1
1
1
1
8000016
1
1
1
1
1
1
0
1
5000016
7FFFF16
5000016
BFFFF16
1
1
5000016
BFFFF16
1
1
5000016
BFFFF16
0
0
1
1
0
5000016
BFFFF16
1
5000016
0
0
0
1
1
0
1
BFFFF16
1
1
1
1
5000016
1
1
BFFFF16
1
5000016
BFFFF16
0
0
5000016
BFFFF16
0
0
BFFFF16
0
0
5000016
BFFFF16
5000016
1
0
BFFFF16
0
1
0
0
0
0
0
0
0
0
0
CS2
0
0
0
0
CS3
Output from the microcomputer pins
CS output
0
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
N.C.: No connected
7
6
5
4
3
2
1
0
Bank
number
Memory expansion mode where PM13 =0
Program or data
Program or data
Data
3FFFFF16
3C000016
39000016
34000016
30000016
2C000016
28000016
24000016
20000016
1C000016
18000016
14000016
10000016
0C000016
08000016
04000016
00000016
ROM address
bank 7
bank 6
bank 5
bank 4
bank 3
bank 2
bank 1
bank 0
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
bank 6
5000016
BFFFF16
bank 5
5000016
BFFFF16
bank 4
5000016
BFFFF16
bank 3
5000016
BFFFF16
bank 2
5000016
BFFFF16
bank 1
5000016
BFFFF16
bank 0
5000016
OFS bit of the DBR register=1
Microcomputer address
OFS bit of the DBR register=0
M306V8FJFP
Figure 4.18. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (1)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
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1
7
Access
area
0
1
1
1
1
5000016
7FFFF16
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
A17
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
000016
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
A15–A0
3BFFFF16
39000016
37FFFF16
33FFFF16
35000016
31000016
2FFFFF16
2D000016
29000016
2BFFFF16
27FFFF16
25000016
23FFFF16
21000016
1D000016
1FFFFF16
1BFFFF16
19000016
17FFFF16
15000016
11000016
13FFFF16
0FFFFF16
0D000016
0BFFFF16
09000016
05000016
07FFFF16
03FFFF16
01000016
1
1
FFFF16
3D000016
3FFFFF16
A21
A20
A18
N.C.
A17
A16
Address input for 4-Mbyte ROM
A19
A15–A0
Address input for 4Mbyte ROM
Internal ROM access
0
Internal ROM access
1
8000016
1
FFFFF16
1
1
1
1
Internal ROM access
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A18
FFFFF16
5000016
7FFFF16
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A19
Internal ROM access
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
CS1
Address output
8000016
1
1
1
1
1
1
1
1
0
5000016
7FFFF16
7FFFF16
5000016
1
7FFFF16
0
0
1
1
0
0
0
0
1
1
1
5000016
5000016
7FFFF16
7FFFF16
5000016
1
1
7FFFF16
0
1
0
5000016
1
1
7FFFF16
1
1
1
1
1
0
0
5000016
0
0
5000016
7FFFF16
0
0
7FFFF16
0
0
0
0
7FFFF16
5000016
5000016
7FFFF16
5000016
0
7FFFF16
0
0
0
7FFFF16
5000016
0
0
CS2
0
0
0
0
CS3
CS output
0
0
5000016
7FFFF16
5000016
N.C.: No connected
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFS
7
6
5
4
3
2
1
0
Bank
number
Output from the microcomputer pins
Memory expansion mode where PM13 =1
Data
Program or data
Data
3FFFFF16
3C000016
39000016
34000016
30000016
2C000016
28000016
24000016
20000016
1C000016
18000016
14000016
10000016
0C000016
08000016
04000016
00000016
ROM address
bank 7
bank 6
bank 5
bank 4
bank 3
bank 2
bank 1
bank 0
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
7FFFF16
5000016
5000016
bank 7
7FFFF16
5000016
bank 6
7FFFF16
5000016
bank 5
7FFFF16
5000016
bank 4
7FFFF16
5000016
bank 3
7FFFF16
5000016
bank 2
7FFFF16
5000016
bank 1
7FFFF16
5000016
bank 0
7FFFF16
OFS bit of the DBR register=1
Microcomputer address
OFS bit of the DBR register=0
M306V8FJFP
Figure 4.19. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (2)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 49 of 363
1
1
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
1
0
1
0
1
0
1
0
1
0
0
1
1
1
5000016
BFFFF16
0
1
0
0
0
5000016
BFFFF16
0
0
0
0
0
1
1
1
1
1
5000016
BFFFF16
1
A20
A21
C000016
FFFFF16
1
1
1
1
1
8000016
BFFFF16
1
1
1
5000016
7FFFF16
1
1
1
1
1
1
1
1
1
0
1
5000016
BFFFF16
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
5000016
BFFFF16
0
5000016
BFFFF16
0
0
0
0
0
0
0
CS2
0
CS3
A18
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
A19
N.C.
1
1
0
0
1
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
A18
A17
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
1
0
A17
A16
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A16
Address input for 4-Mbyte ROM
A19
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
0
0
CS1
Address output
Output from the microcomputer pins
CS output
5000016
BFFFF16
5000016
BFFFF16
Access
area
1
0
OFS
N.C.: No connected
7
6
5
4
3
2
1
0
Bank
number
Microprocessor mode
A15–A0
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
FFFF16
000016
000016
FFFF16
FFFF16
000016
A15–A0
Address input for 4Mbyte ROM
3FFFFF16
3FFFFF16
3C000016
3C000016
3BFFFF16
39000016
3BFFFF16
37FFFF16
35000016
31000016
33FFFF16
2D000016
29000016
2FFFFF16
2BFFFF16
25000016
27FFFF16
21000016
1D000016
23FFFF16
1FFFFF16
19000016
1BFFFF16
15000016
11000016
17FFFF16
13FFFF16
0D000016
0FFFFF16
09000016
05000016
0BFFFF16
07FFFF16
01000016
Program or data
Program or data
Data
3FFFFF16
3C000016
39000016
34000016
30000016
2C000016
28000016
24000016
20000016
1C000016
18000016
14000016
10000016
0C000016
08000016
04000016
00000016
ROM address
bank 7
bank 6
bank 5
bank 4
bank 3
bank 2
bank 1
bank 0
FFFFF16
7FFFF16
C000016
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
5000016
BFFFF16
bank 6
5000016
BFFFF16
bank 5
5000016
BFFFF16
bank 4
5000016
BFFFF16
bank 3
5000016
BFFFF16
bank 2
5000016
BFFFF16
bank 1
5000016
BFFFF16
bank 0
5000016
OFS bit of the DBR register=1
Microcomputer address
OFS bit of the DBR register=0
M306V8FJFP
Figure 4.20. Relationship Between Addresses on 4-M Byte ROM and Those on Microcomputer (3)
M306V8FJFP
Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
Table 5.1 lists the clock generation circuit specifications. Figure 5.1 shows the clock generation circuit.
Figures 5.2 to 5.6 show the clock-related registers.
Table 5.1. Clock Generation Circuit Specifications
Main clock
oscillation circuit
Use of clock
Sub clock
oscillation circuit
• CPU clock source •CPU clock source
• Peripheral function • Timer A, B's clock
clock source
source
Clock frequency
16 MHz
32.768 kHz
Usable oscillator
• Ceramic oscillator
• Crystal oscillator
• Crystal oscillator
Pins to connect
oscillator
XIN, XOUT
XCIN, XCOUT
Oscillation stop,
restart function
Presence
Presence
Oscillator status
after reset
Oscillating
Stopped
Other
Externally derived clock can be input
Item
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 50 of 363
M306V8FJFP
XCIN
CM01–CM00=002
Sub-clock
generating circuit
I/O ports
PM01–PM00=002, CM01–CM00=012
CLKOUT
PM01–PM00=002,
CM01–CM00=112
PM01–PM00=002, CM01–CM00=102
XCOUT
fC32
1/32
CM04
f1
PCLK0=1
Sub-clock
f2
PCLK0=0
fC
f8
f32
fAD
f1SIO
PCLK1=1
f2SIO
PCLK1=0
f8SIO
CM10=1(stop mode)
S Q
XIN
XOUT
f32SIO
e b c
R
a
Main
clock
CM05
Main clock
generating circuit
CM07=0
d
Divider
CPU clock
fC
BCLK
CM07=1
CM02
S
WAIT instruction
Q
R
e
a
RESET
c
b
1/2
1/2
1/2
1/2
1/2
1/32
1/2
1/4
1/8
Software reset
1/16
CM06=0
CM17–CM16=112
CM06=1
CM06=0
CM17–CM16=102
Interrupt request level judgment output
CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
CM06=0
CM17–CM16=012
CM06=0
CM17–CM16=002
Figure 5.1. Clock Generation Circuit
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 51 of 363
d
Details of divider
M306V8FJFP
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Address
000616
Bit symbol
After reset
010010002
Bit name
Function
RW
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
CM02
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8) RW
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
RW
Port XC select bit
(Note 2)
Main clock stop bit
(Notes 3, 11, 12)
0 : I/O port P86, P87
1 : XCIN-XCOUT generation function(Note 9)
RW
0 : On
1 : Off (Note 4, Note5)
RW
CM06
Main clock division select
bit 0 (Notes 7, 11)
0 : CM16 and CM17 valid
1 : Division by 8 mode
RW
CM07
System clock select bit
(Notes 6, 10)
0 : Main clock
1 : Sub-clock
RW
CM00
CM01
CM04
CM05
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: The CM03 bit is set to “1” (high) when the CM04 bit is set to “0” (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode is selected.
This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the following setting
is required:
(1) Set the CM07 bit to “1” (Sub-clock select) with the sub-clock stably oscillating.
(2) Set the CM05 bit to “1” (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the sub clock is not
chosen as a CPU clock.
Note 5: When CM05 bit is set to “1, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to “1” (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to “1”. Also make sure ports P86 and P87 are directed for input, with no pull-ups.
Note 10: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to “0” (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM07 bit to “0”.
Note 11: When the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to “1”
(divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High). Please do not change bits CM06, CM17 to CM16 in
low power consumption mode.
Figure 5.2. CM0 Register
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System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0 0
0
0
b0
Symbol
CM1
Address
000716
Bit symbol
After reset
001000002
Bit
Function
RW
name
All clock stop
control bit
(Notes 4, 5)
0 : Clock on
1 : All clocks off (stop mode)
RW
(b4-b1)
Reserved bit
Must set to “0”
RW
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
RW
CM10
b7 b6
CM16
Main clock division
select bit 1 (Note 3)
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state.
Note 5: Effective when CM07 bit is “0” .
Figure 5.3. CM1 Register
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System clock control register 2 (Note 1)
b7
0
b6
b5
b4
0 0
b3
b2
b1
b0
0
0
0
Symbol
CM2
Bit symbol
(b2-b0)
CM23
Address
000C16
Bit name
Reserved bit
XIN moniter flag
Reserved bit
After reset
0X0000002
Function
Must set to “1”
RW
R
W
RW
0: Main clock on
1: Main clock turned off
RO
Must set to “1”
RW
(b5-b4)
(b6)
(b7)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
Reserved bit
Must set to “1”
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Figure 5.4. CM2 Register
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RW
M306V8FJFP
Peripheral clock select register (Note 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
PCLKR
b0
0 0 0 0 0 0
Address
025E16
When reset
000000112
Bit symbol
Bit name
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A, B, and the dead
timer)
0 : f2
1 : f1
RW
SI/O clock select bit
(Clock source for UART0
to UART2)
0 : f2SIO
1 : f1SIO
RW
Reserved bit
Must set to “0”
PCLK1
(b7-b2)
Function
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Reserved register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0
Symbol
RSVREG001E
Bit symbol
(b4-b3)
(b7-b5)
Address
001E16
Bit name
Reserved bit
When reset
XXX000002
Function
Must set to “0”
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Figure 5.5. PCLKR Register and PM2 Register
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RW
RW
M306V8FJFP
Reserved register
b7
b6
b5
b4
b3
0 0 0 1
b2
b1
b0
0 1 0
Symbol
RSVREG001C
Bit
symbol
After reset
0001X0102
Bit name
Function
RW
(b0)
Reserved bit
Must set to “0”
RW
(b1)
Reserved bit
Must set to “1”
RW
(b2)
Reserved bit
Must set to “0”
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is indeterminate.
(b4)
Reserved bit
Must set to “1”
RW
(b7-b5)
Reserved bits
Must set to “0”
RW
Figure 5.6. PLC0 Register
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Address
001C16
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M306V8FJFP
The following describes the clocks generated by the clock generation circuit.
(1) Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as
the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured
by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a
feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the
amount of power consumed in the chip. The main clock oscillator circuit may also be configured by
feeding an externally generated clock to the XIN pin. Figure 5.7 shows the examples of main clock connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main
clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock. In this
case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains on, XIN is pulled “H” to
XOUT via the feedback resistor. Note that if an externally generated clock is fed into the XIN pin, the main
clock cannot be turned off by setting the CM05 bit to “1”, unless the sub clock is chosen as a CPU clock.
If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
VCC
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 5.7. Examples of Main Clock Connection Circuit
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(2) Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 5.8 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub
clock becomes oscillating stably.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
VCC
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 5.8. Examples of Sub Clock Connection Circuit
OSD Oscillation Circuit
The OSD clock oscillation circuit can be chosen to be an external oscillator circuit comprised of an LC
oscillator or a ceramic resonator (or a quartz-crystal oscillator) connected between the OSC1 and OSC2
pins, or an internal oscillator circuit with a filter connected to the OSC1 pin. Which of LC oscillator or a
ceramic resonator (or a quartz-crystal oscillator) is selected by setting bits 0, 1 and 2 of the clock control
register (address 020516) and bit 1 of the extended register 1C (address 02DC16).
Microcomputer
Microcomputer
OSC1
OSC2
OSC1
L
C1
OPEN
1KΩ
C2
0.015µF
OSC2
2pF
Note: When mounting a resistor and capacitors,
use the shortest possible wiring to prevent leakage.
Connecting an external oscillator circuit
Figure 5.9. OSD clock connection example
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Connecting an internal oscillator circuit
M306V8FJFP
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
(1) CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock or sub clock.
If the main clock is selected as the clock source for the CPU clock, the selected clock source can be
divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the
CM17 to CM16 bits in CM1 register to select the divide-by-n value.
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to “0” (output enabled).
Note that when entering stop mode from high or middle speed mode, or when the CM05 bit of CM0
register is set to “1” (main clock turned off) in low-speed mode, the CM06 bit of CM0 register is set to “1”
(divide-by-8 mode).
(2) Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock. The clock fi is used for timers A and
B, and fiSIO is used for serial I/O. The f8 and f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, and is used for the A/D converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to
CM00 bits of CM0 register to select.
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Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes
are referred to as normal operation mode here.
(1) Normal Operation Mode
Normal operation mode is further classified into four modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait
time in a program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used
as the count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock.
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
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Table 5.2. Setting Clock Related Bit and Modes
Modes
High-speed mode
Mediumdivided by 2
speed
divided by 4
mode
divided by 8
divided by 16
Low-speed mode
Low power dissipation mode
CM1 register
CM17, CM16
002
012
102
112
CM07
0
0
0
0
0
1
1
CM0 register
CM06
CM05
CM04
0
0
0
0
0
0
1
0
0
0
0
1
1(Note 1) 1(Note 1)
1
Note 1: When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes
to low power dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
(2) Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. Because the main clock and sub clock, all are on, the peripheral functions using these
clocks keep operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,
f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced
that much. However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode
Table 5.3 lists pin status during wait mode
• Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt.
If the microcomputer is to be moved out of exit wait mode by a hardware reset, set the peripheral
function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing the WAIT
instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait
mode. If CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked
by external signals can be used to exit wait mode.
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Table 5.3. Pin Status During Wait Mode
Pin
Memory expansion mode
Microprocessor mode
_______
Single-chip mode
_______
A0 to A19, D0 to D15, CS0 to CS3,
Retains status before wait mode
________
BHE
_____
______
________ _________
RD, WR, WRL, WRH
“H”
__________
HLDA,BCLK
ALE
I/O ports
CLKOUT
“H”
“L”
Retains status before wait mode
When fC selected
When f8, f32 selected
Retains status before wait mode
Does not stop
Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is maintained.
Table 5.4. Interrupts to Exit Wait Mode
Interrupt
Serial I/O interrupt
CM02=0
Can be used when operating
with internal or external clock
CM02=1
Can be used when operating
with external clock
key input interrupt
A/D conversion
interrupt
Can be used
Can be used in one-shot mode
or single sweep mode
Can be used
(Do not use)
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Can be used
Table 5.4 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the periph
eral function interrupt to be used to exit wait mode.
Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0
bits to “0002” (interrupt disable).
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit wait mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU
clock that was on when the WAIT instruction was executed.
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(3) Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
• Key interrupt
______
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit of CM1 register is set to “1” (main clock oscillator circuit drive capability high).
• Pin Status in Stop Mode
Table 5.5 lists pin status during stop mode
• Exiting Stop Mode
The microcomputer is moved out of stop mode by a hardware reset, or peripheral function interrupt.
If the microcomputer is to be moved out of stop mode by a hardware reset or, set the peripheral
function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the CM10 bit
to “1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the
following before setting the CM10 bit to “1”.
1. In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0
bits to “0002”.
2. Set the I flag to “1”.
3. Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an
interrupt service routine is executed.
Which CPU clock will be used after exiting stop mode by a peripheral function is determined by the
CPU clock that was on when the microcomputer was placed into stop mode as follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
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Table 5.5. Pin Status in Stop Mode
Pin
Memory expansion mode
Microprocessor mode
_______
Single-chip mode
_______
A0 to A19, D0 to D15, CS0 to CS3,
Retains status before stop mode
________
BHE
_____
______
________ _________
RD, WR, WRL, WRH
“H”
__________
HLDA, BCLK
ALE
I/O ports
CLKOUT
When fc selected
When f8, f32 selected
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“H”
undefined
Retains status before stop mode Retains status before stop mode
“H”
Retains status before stop mode
M306V8FJFP
Figure 5.10 shows the state transition from normal operation mode to stop mode and wait mode. Figure
5.11 shows the state transition in normal operation mode.
Reset
All oscillators stopped
WAIT
instruction
CM10=1
Medium-speed mode
(divided-by-8 mode)
Stop mode
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM10=1
(Note 1)
Wait mode
Interrupt
WAIT
instruction
High-speed, mediumspeed mode
Stop mode
CM10=1
When
low power When
dissipation lowmode
speed
mode
CM10=1
Stop mode
Interrupt
Low-speed, low power
dissipation mode
Normal mode
Note 1: Please write to CM0 and CM1 register simultaneously by word access.
Figure 5.10. State Transition to Stop Mode and Wait Mode
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Wait mode
Interrupt
WAIT
instruction
Interrupt
Wait mode
M306V8FJFP
Main clock oscillation
High-speed mode
CPU clock: f(XIN)
Middle-speed mode
(divide by 2)
CPU clock: f(XIN)/2
Middle-speed mode
(divide by 4)
CPU clock: f(XIN)/4
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/8
CPU clock: f(XIN)
CM07=0
CM06=0
CM17=1
CM06=1
CM04=1
High-speed mode
CPU clock: f(XIN)/16
CM07=0
CM16=1
CM04=0
Middle-speed mode
(divide by 2)
CPU clock: f(XIN)/2
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/4
CPU clock: f(XIN)/8
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
CM07=1
(Note 2)
CPU clock: f(XIN)/16
CM07=0
CM06=1
CM07=0
CM06=0
CM17=1
CM16=1
CM07=0
(Note 1, Note 3)
Low-speed mode
CPU clock: f(XCIN)
CM07=0
CM05=1
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Wait for td(M-L) or the main clock oscillation stabilization time whichever is longer before switching over.
2: Switch clock after oscillation of sub-clock is sufficiently stable.
3: Change CM17 and CM16 before changing CM06.
4: Transit in accordance with arrow.
Figure 5.11. State Transition in Normal Mode
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M306V8FJFP
Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 6.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1, CM2 and PCLKR registers, reserved register address
001C16.
• Registers protected by PRC1 bit: PM0 and PM1 registers, reserved registers address 001E16, 039E16,
034816, and 034916
• Registers protected by PRC2 bit: PD9 register, reserved registers address 036216 and 036616
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automatically cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A16
Bit symbol
Bit name
0 0 0
PRC0
Protect bit 0
After reset
XX0000002
Function
Enable write to CM0, CM1, CM2,
PCLKR and register 001C16
0 : Write protected
1 : Write enabled
PRC1
Protect bit 1
RW
Enable write to PM0, PM1
registers 001E16, 039E16,
034816 and 034916
RW
RW
0 : Write protected
1 : Write enabled
PRC2
Protect bit 2
Enable write to PD9, registers
036216 and 036616
0 : Write protected
1 : Write enabled (Note)
(b5-b3)
(b7-b6)
Reserved bits
Must set to “0”
RW
RW
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.
Figure 6.1. PRCR Register
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M306V8FJFP
Interrupts
Type of Interrupts
Figure 7.1 shows types of interrupts.












Hardware
Special
(Non-maskable interrupt)
















Interrupt
Software
(Non-maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
________
DBC (Note 2)
Watchdog timer
Single step (Note 2)
Address match
Peripheral function (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 7.1. Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be
executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP then selected is used.
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Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
(1) Special Interrupts
Special interrupts are non-maskable interrupts.
________
• DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
• Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
• Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or
AIER1 bit or the AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details about the address match interrupt, refer to the section "address match interrupt".
(2) Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in “Table 7.2. Relocatable
Vector Tables”. For details about the peripheral functions, refer to the description of each peripheral
function in this manual.
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Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 7.2 shows the interrupt vector.
MSB
Vector address (L)
LSB
Low address
Mid address
Vector address (H)
0000
High address
0000
0000
Figure 7.2. Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 7.1 lists the
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite
disabling function".
Table 7.1. Fixed Vector Tables
Interrupt source
Vector table addresses
Remarks
Reference
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16
Interrupt on UND instruction
M16C/60, M16C/20
Overflow
FFFE016 to FFFE316
Interrupt on INTO instruction
serise software
If
the
contents
of
address
BRK instruction
FFFE416 to FFFE716
maual
FFFE716 is FF16, program execution starts from the address
shown by the vector in the
relocatable vector table.
Address match
FFFE816 to FFFEB16
Address match interrupt
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
Watchdog timer
________
DBC (Note)
FFFF416 to FFFF716
Reset
FFFFC16 to FFFFF16
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools.
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• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector
table area. Table 7.2 lists the relocatable vector tables. Setting an even address in the INTB register
results in the interrupt sequence being executed faster than in the case of odd addresses.
Table 7.2. Relocatable Vector Tables
Interrupt source
BRK instruction (Note 3)
Vector address (Note 1)
Address (L) to address (H)
Software interrupt
number
Reference
+0 to +3 (000016 to 000316)
0
M16C/60, M16C/20
series software
manual
1 to 3
(Reserved)
INT3
+16 to +19 (001016 to 001316)
4
Timer B5/OSD1
+20 to +23 (001416 to 001716)
5
Timer
+24 to +27 (001816 to 001B16)
6
+28 to +31 (001C16 to 001F16)
7
Timer
Serial I/O
Data slicer 1
+32 to +35 (002016 to 002316)
8
Data slicer 2
+36 to +39 (002416 to 002716)
9
UART 2 bus collision detection/I2C-bus0
+40 to +43 (002816 to 002B16)
10
DMA0
+44 to +47 (002C16 to 002F16)
11
DMA1
+48 to +51 (003016 to 003316)
12
Key input interrupt/VSYNC
+52 to +55 (003416 to 003716)
13
Key input interrupt, OSD
A/D/I 2C-bus1NACK
+56 to +59 (003816 to 003B16)
14
A/D convertor/I2C-bus
UART2 transmit
+60 to +63 (003C16 to 003F16)
15
UART2 receive
+64 to +67 (004016 to 004316)
16
UART0 transmit
+68 to +71 (004416 to 004716)
17
UART0 receive
+72 to +75 (004816 to 004B16)
18
UART1 transmit
+76 to +79 (004C16 to 004F16)
19
UART1 receive
+80 to +83 (005016 to 005316)
20
Timer A0/I2C-bus0
+84 to +87 (005416 to 005716)
21
Timer A1/I2C-bus1
+88 to +91 (005816 to 005B16)
22
Timer A2/OSD2
+92 to +95 (005C16 to 005F16)
23
Timer A3/VSYNC
(Note 2)
Timer B4, UART1 bus collision detect
(Note 2)
Timer B3, UART0 bus collision detect
Data slicer
+96 to +99 (006016 to 006316)
24
A4/I2C-bus0NACK
+100 to +103 (006416 to 006716)
25
Timer B0/I2C-bus1NACK
+104 to +107 (006816 to 006B16)
26
Timer B1/I2C-bus2NACK
+108 to +111 (006C16 to 006F16)
27
Timer B2/I2C-bus2
+112 to +115 (007016 to 007316)
28
INT0
+116 to +119 (007416 to 007716)
29
INT1
+120 to +123 (007816 to 007B16)
30
+124 to +127 (007C16 to 007F16)
31
+128 to +131 (008016 to 008316)
32
to
63
Timer
INT2/OSD2
Software interrupt (Note 3)
to
+252 to +255 (00FC16 to 00FF16)
Notes 1: Address relative to address in INTB
.
2: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select
.
3: These interrupts cannot be disabled using the I flag
.
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Serial I/O/I2C-bus
DMAC
Serial I/O
Timer/I2C-bus
INT interrupt, OSD
M16C/60, M16C/20
series software
manual
M306V8FJFP
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable
the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 7.3 shows the interrupt control registers.
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Interrupt control register (Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB5IC
TB4IC
TB3IC
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Bit symbol
ILVL0
Address
004516
004616
004716
004A16
004B16, 004C16
004D16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
Bit
name level
Interrupt priority
select bit
ILVL1
ILVL2
I
R
(b7-b4)
Interrupt request bit
After reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Functio
n
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
RW
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Note 1: IR bit write “0” only (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “Notes of interruption” of the Usage Notes Reference Book.
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
INT0IC to INT2IC
Bit
symbol
ILVL0
Address
005D16 to 005F16
Bit
name level
Interrupt priority
select bit
ILVL1
ILVL2
IR
POL
(b5)
(b7-b6)
After reset
XX00X0002
Functio
n
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
RW
RW
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
Polarity select bit
0 : Selects falling edge (Notes 3, 5)
1 : Selects rising edge
RW
Must always be set to “0”
RW
Reserved bit
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the “Notes of interruption” of the Usage Notes Reference Book.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 2) is “1” (both edges), set the INTiIC register’s POL bit to “0” (falling edge).
Figure 7.3. Interrupt Control Registers
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Interrupt control register
b7
b6
b5
b4
b3
b2
b1
Symbol
INT3IC
DSC1IC
DSC2IC
b0
0 0
Bit
symbol
ILVL0
Address
004416
004816
004916
Bit
name level
Interrupt priority
select bit
ILVL1
ILVL2
IR
(b7-b6)
After reset
XX00X0002
XX00X0002
XX00X0002
Functio
n
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
RW
RW
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
RW
(Note 1)
Reserved bit
Must always be set to “0”
RW
Reserved bit
Must always be set to “0”
RW
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
Note 1: This bit can only be reset by writing “0” (Do not write “1”).
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the “precautions for interrupts” of the Usage Notes Reference Book.
Figure 7.4. Interrupt Control Registers
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I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 7.3 shows the settings of interrupt priority levels and Table 7.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = “1”
· IR bit = “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 7.4. Interrupt Priority Levels
Enabled by IPL
Table 7.3. Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
Interrupt priority
level
0002
Level 0 (interrupt disabled)
0012
Level 1
0102
Priority
order
IPL
Enabled interrupt priority levels
0002
Interrupt levels 1 and above are enabled
0012
Interrupt levels 2 and above are enabled
Level 2
0102
Interrupt levels 3 and above are enabled
0112
Level 3
0112
Interrupt levels 4 and above are enabled
1002
Level 4
1002
Interrupt levels 5 and above are enabled
1012
Level 5
1012
Interrupt levels 6 and above are enabled
1102
Level 6
1102
Interrupt levels 7 and above are enabled
1112
Level 7
1112
All maskable interrupts are disabled
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Low
High
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Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
The CPU behavior during the interrupt sequence is described below. Figure 7.5 shows time required for
executing the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal
temporary register(Note 1).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start
address of the interrupt routine.
Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address bus
Data bus
RD
Address
000016
Interrupt
information
Indeterminate (Note 1)
Indeterminate (Note 1)
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec
contents
vec+2
PC
vec+2
contents
Indeterminate (Note 1)
WR
(Note 2)
Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 7.5. Time Required for Executing Interrupt Sequence
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Interrupt Response Time
Figure 7.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 7.6) and a time during which the interrupt
sequence is executed ((b) in Figure 7.6).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value 16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Figure 7.6. Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 7.5 is set in the IPL. Shown in Table 7.5 are the IPL values of software and special interrupts
when they are accepted.
Table 7.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Watchdog timer
Level that is set to IPL
7
_________
Software, address match, DBC, single-step
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Not changed
M306V8FJFP
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
7.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Address
MSB
Stack
m–4
m–4
PCL
m–3
m–3
PCM
m–2
m–2
FLGL
Address
MSB
LSB
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
SP value before
interrupt request is
accepted.
LSB
FLGH
[SP]
New SP value
PCH
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 7.7. Stack Status Before and After Acceptance of Interrupt Request
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The operation of saving registers carried out in the interrupt sequence is dependent on whether the
SP(Note), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is
even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits
at a time. Figure 7.8 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Sequence in which order
registers are saved
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
PCL
[SP] – 3(Odd)
PCM
[SP] – 2 (Even)
FLGL
FLGH
[SP] – 1(Odd)
[SP]
(2) Saved simultaneously,
all 16 bits
PCH
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
PCL
(3)
[SP] – 3 (Even)
PCM
(4)
[SP] – 2(Odd)
FLGL
(1)
Saved, 8 bits at a time
[SP] – 1 (Even)
[SP]
FLGH
PCH
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 7.8. Operation of Saving Register
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Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to
ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority
is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 7.9 shows
the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
High
DBC
Watchdog timer
Peripheral function
Single step
Address match
Low
Figure 7.9. Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 7.10 shows the circuit that judges the interrupt priority level.
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Priority level of each interrupt
Level 0 (initial value)
INT1
Highest
Timer B2/I2C-bus2
Timer B0/I2C-bus1NACK
Timer A3/VSYNC
Timer A1/I2C-bus1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1/I2C-bus2NACK
Timer A4/I2C-bus0NACK
Timer A2/OSD2
Timer B3, UART0 bus collision
Timer B5/OSD1
UART1 reception, ACK1
UART0 reception, ACK0
Priority of peripheral function interrupts
(if priority levels are same)
UART2 reception, ACK2
A/D conversion/I 2C-bus1NACK
DMA1
UART 2 bus collision/I2C-bus0
Data slicer 1
Timer A0/I2C-bus0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
Key input interrupt/VSYNC
DMA0
Lowest
Data slicer 2
Interrupt request level resolution output to clock
generating circuit (Fig.7.1. Interrupts)
IPL
I flag
Address match
DBC
Figure 7.10. Interrupts Priority Select Circuit
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Interrupt
request
accepted
M306V8FJFP
______
INT Interrupt
_______
INTi interrupt (i=0 to 3) is triggered by the edges of external inputs. The edge polarity is selected using the
IFSR register's IFSRi bit.
Figure 7.11 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7
b6
b5
0
0
0 0
b4
b3
b2
b1
b0
Symbol
IFSR
Address
035F16
Bit name
Bit symbol
IFSR0
IFSR1
IFSR2
IFSR3
After reset
0016
Function
RW
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
Reserved bit
Must always be set to “0”
RW
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT2IC register’s POL bit
is set to “0” (= falling edge).
Interrupt request cause select register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR2A
Bit symbol
(b5-b0)
IFSR26
IFSR27
Address
035E16
Bit name
After reset
00XXXXXX2
Function
RW
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Interrupt request cause
select bit
(Note 1)
0 : Timer B3
1 : UART0 bus collision
detection
RW
Interrupt request cause
select bit
(Note 2)
0 : Timer B4
1 : UART1 bus collision
detection
RW
Note 1: Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using the
timer B3 interrupt, clear the IFSR26 bit to “0” (timer B3). When using UART0 bus collision detection, set the
IFSR26 bit to “1”.
Note 2: Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using the
timer B4 interrupt, clear the IFSR27 bit to “0” (timer B4). When using UART1 bus collision detection, set the
IFSR27 bit to “1”.
Figure 7.11. IFSR Register and IFSR2A Register
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M306V8FJFP
Key Input Interrupt
Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has
had the PD10 register’s PD10_4 to PD10_7 bits set to “0” (= input) goes low. Key input interrupts can be
used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.
However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure
7.12 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which
has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port
are not detected as interrupts.
PUR2 register's PU25 bit
Pull-up
transistor
KUPIC register
PD10 register's
PD10_7 bit
PD10 register's PD10_7 bit
KI3
Pull-up
transistor
PD10 register's
PD10_6 bit
Interrupt control circuit
KI2
Pull-up
transistor
PD10 register's
PD10_5 bit
KI1
Pull-up
transistor
PD10 register's
PD10_4 bit
KI0
Figure 7.12. Key Input Interrupt
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Key input interrupt
request
M306V8FJFP
Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one
of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 7.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for external
areas.
Figure 7.13 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 7.6. Value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Value of the PC that is
saved to the stack area
Instruction at the address indicated by the RMADi register
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ.B:S
#IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Table 7.7. Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources
Address match interrupt 0
Address match interrupt 1
Address match interrupt 2
Address match interrupt 3
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Address match interrupt enable bit
AIER0
AIER1
AIER20
AIER21
page 85 of 363
Address match interrupt register
RMAD0
RMAD1
RMAD2
RMAD3
M306V8FJFP
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
After reset
XXXXXX002
Bit symbol
Function
RW
AIER0
Address match interrupt 0
enable bit
Bit name
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
(b7-b2)
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt enable register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER2
Address
01BB16
After reset
XXXXXX002
Bit symbol
Bit name
Function
RW
AIER20
Address match interrupt 2
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER21
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
(b7-b2)
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
001216 to 001016
001616 to 001416
01BA16 to 01B816
01BE16 to 01BC16
Function
Address setting register for address match interrupt
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 7.13. AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
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After reset
X0000016
X0000016
X0000016
X0000016
M306V8FJFP
Notes of interruption
(1) Address 0000016 read-out
● Please do not read address 0000016 by the program. When the interruption demand of maskable
interruption is received, CPU interrupts in an interruption sequence and reads information (it interrupts
with an interruption number and is a demand level) from address 0000016.IR bit of received interruption is
set to "0" at this time.If address 0000016 is read by the program, IR bit of high interruption of a priority will
be most set to "0" among interruption permitted.Therefore, interruption may be canceled or unexpected
interruption may occur.
(2) Setting of SP
● Please assign a value to SP before receiving interruption.After reset, SP is "000016." Therefore, if
interruption is received before assigning a value to SP, it will become the factor of a reckless run.
______
(3) INT interrupt
● Regardless of CPU clock, "L" width or "H" width for 250ns or more is required for the signal inputted into
_______
_______
pins INT0 to INT3.
_______
● IR bit may be set to "1" (those with an interruption demand) when changing the polarity of pins INT0 to
_______
INT3. Please set IR bit to "0" (with no interruption demand) after changing. The example of a change
______
procedure of an INT interruption generating factor is shown in Fig. 7.14.
I flag is set to “0” (Disable interruption).
Bits ILVL2 to ILVL0 are set to “0002” (level 0)
(Disable INT interruption).
POL bit is set up.
IR bit is set to “0” (with no interruption demand).
Bits ILVL2 to ILVL0 are made into “0012” (level 1)
to “1112” (level 7)
(INT interruption demand receptionist is possible).
I flag is set to “1”
(interruption permission).
Note 1. Please perform the above-mentioned setup separately. Please do not perform
two or more setup simultaneously (by one command).
Figure 7.14. The example of change procedure of INT interruption generating factor
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M306V8FJFP
(4) Watchdog timer interruption
After watchdog timer interruption generating should initialize watchdog timer.
(5) Change of an interrupt control register
● Please make a change of an interrupt control register in the part which the interruption demand
corresponding to the register does not generate. When an interruption demand may occur, please
change after forbidding interruption. The example of a reference program is shown below.
<The example of program which rewrites an interruption control register>
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00H, 0055H
NOP
NOP
FSET
I
; Disable interrupts.
; TA0IC register is set to "0016."
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00H, 0055H
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; TA0IC register is set to "0016."
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts.
AND.B #00H, 0055H ; TA0IC register is set to "0016."
POPC FLG
; Enable interrupts.
The reason which has a dummy lead in Example 1 before two pieces (they are four pieces at the time of
HOLD functional use) and an FSET I command in Example 2 of an NOP command before an FSET I
command.
Under the influence of a command cue buffer, before writing to an interruption control register, it prevents
setting I flag to "1."
When you forbid interruption, you interrupt and you change a control register, be careful of the command to
be used.
Change of bits other than IR bit
During execution of a command, when the interruption demand corresponding to the register occurs, IR bit
is not set to "1" (those with an interruption demand), but interruption may be disregarded.
The target command : AND, OR, BCLR, BSET
Change of IR bit
When setting IR bit to "0" (with no interruption demand), IR bit may not be set to "0" depending on the
command to be used. Please set IR bit to "0" using MOV command.
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M306V8FJFP
Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot be
set to “0” (watchdog timer interrupt) in a program. Refer to “Watchdog Timer Reset” for the details of
watchdog timer reset.
When the main clock source is selected for CPU clock, the divide-by-N value for the prescaler can be
chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the divide-by-N value for the prescaler is
always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given
below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock source chosen for CPU clock
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
With sub-clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released.
Figure 8.1 shows the block diagram of the watchdog timer. Figure 8.2 shows the watchdog timer-related
registers.
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M306V8FJFP
Prescaler
CM07 = 0
WDC7 = 0
1/16
PM12 = 0
CPU
clock
CM07 = 0
WDC7 = 1
1/128
Watchdog timer
interrupt request
PM22 = 0 (Fix)
HOLD
Watchdog timer
CM07 = 1
1/2
PM12 = 1
Watchdog timer
Reset
Set to
“7FFF16”
Write to WDTS register
RESET
Figure 8.1. Watchdog Timer Block Diagram
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Address
000F16
After reset
00XXXXXX2
Bit name
Bit symbol
Function
RW
(b4-b0)
High-order bit of watchdog timer
RO
(b5, b6)
Reserved bit
Must set to “0”
RW
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Watchdog timer start register (Note)
b7
b0
Symbol
WDTS
Address
000E16
After reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction to
WO
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 8.2. WDC Register and WDTS Register
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M306V8FJFP
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of
a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time
after a DMA request is generated. Figure 9.1 shows the block diagram of the DMAC. Table 9.1 shows the
DMAC specifications. Figures 9.2 to 9.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003616 to 003416)
(addresses 003916, 003816)
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
DMA latch high-order bits
DMA latch low-order bits
Note: Pointer is incremented by a DMA request.
Figure 9.1. DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0–1)’s DSR bit, as well as by an interrupt
request which is generated by any function specified by the DMiSL register’s DMS and DSEL3–DSEL0 bits.
However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the
interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be
accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts,
the interrupt control register’s IR bit does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit =
“1” (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to “DMA Requests”.
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M306V8FJFP
Table 9.1. DMAC Specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
DMA request factors
(Note 1, Note 2)
Channel priority
Transfer unit
Transfer address direction
Transfer mode •Single transfer
•Repeat transfer
DMA interrupt request generation timing
DMA startup
DMA shutdown •Single transfer
•Repeat transfer
Reload timing for forward address pointer and transfer
counter
________
Falling edge of
INT0 or
INT1
________
________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
A/D conversion interrupt requests
Software triggers
OSD1, OSD2 interrupt
VSYNC interrupt
Multi-master I2C-bus interface 0, 1, 2 interrupt
I2C-bus 0, 1, 2 NACK interrupt
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter (i = 0–1)
underflows after reaching the terminal count.
When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
• When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1” (en
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016–003F16) are accessed by the DMAC.
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M306V8FJFP
DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0SL
Address
03B816
Bit symbol
DSEL0
DSEL1
After reset
0016
Function
Bit name
DMA request cause
select bit
Refer to note
RW
RW
RW
DSEL2
RW
DSEL3
RW
(b5-b4)
DMS
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0(basic cause of request)
Falling edge of INT0 pin
Software trigger
Timer A0/I2C-bus0
Timer A1/I2C-bus1
Timer A2/OSD2
Timer A3/VSYNC
Timer A4/I2C-bus0NACK
Timer B0/I2C-bus1NACK
Timer B1/I2C-bus2NACK
Timer B2/I2C-bus2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A/D conversion
UART1 transmit
Figure 9.2. DM0SL Register
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DMS=1(extended cause of request)
–
–
–
–
–
–
Two edges of INT0 pin
Timer B3
Timer B4
Timer B5/OSD1
–
–
–
–
–
–
M306V8FJFP
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
Symbol
DM1SL
b0
Address
03BA16
DSEL1
DSEL2
Function
Bit name
Bit symbol
DSEL0
After reset
0016
DMA request cause
select bit
RW
RW
DSEL3
(b5-b4)
DMS
RW
RW
Refer to note
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0 (basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0/I2C-bus0
Timer A1/I2C-bus1
Timer A2/OSD2
Timer A3/VSYNC
Timer A4/I2C-bus0NACK
Timer B0/I2C-bus1NACK
Timer B1/I2C-bus2NACK
Timer B2 /I2C-bus2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 receive/ACK1
DMS=1 (extended cause of request)
–
–
–
–
–
–
–
Two edges of INT1 pin
–
–
–
–
–
–
–
–
DMAi control register(i=0,1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
Bit symbol
After reset
00000X002
00000X002
Bit name
F unction
RW
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
RW
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
DMAS
DMA request bit
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
RW
DSD
Source address direction
select bit (Note 2)
0 : Fixed
1 : Forward
RW
DAD
Destination address
0 : Fixed
direction select bit (Note 2) 1 : Forward
RW
(b7-b6)
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
RW
(Note 1)
Notes 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
2: At least one of the DAD and DSD bits must be “0” (address direction fixed)
Figure 9.3. DM1SL Register, DM0CON Register, and DM1CON Registers
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M306V8FJFP
DMAi source pointer (i = 0, 1) (Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
Function
Set the source address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
Function
Set the destination address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
Figure 9.4. SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
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After reset
Indeterminate
Indeterminate
Setting range
RW
000016 to FFFF16
RW
M306V8FJFP
1. Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory extension and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
_______
(d) Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area
________
________
are affected by the RDY signal. Refer to “RDY signal”.
Figure 9.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units using an 8-bit bus ((2) in Figure 9.5), two source read bus cycles and two destination write bus
cycles are required.
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M306V8FJFP
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
RD signal
WR signal
Data
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1
Source
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
Destination
Source
CPU use
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 9.5. Transfer Cycles for Source Read
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M306V8FJFP
2. DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 9.2 shows the
number of DMA transfer cycles. Table 9.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 9.2. DMA Transfer Cycles
Single-chip mode
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Memory expansion mode
Bus width
Access address
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
Even
1
1
1
1
(BYTE= “L”)
Odd
1
1
1
1
8-bit
Even
—
—
1
1
(BYTE = “H”)
Odd
—
—
1
1
16-bit
Even
1
1
1
1
(BYTE = “L”)
Odd
2
2
2
2
8-bit
Even
—
—
2
2
(BYTE = “H”)
Odd
—
—
2
2
Table 9.3. Coefficient j, k
Internal area
External area
Internal ROM, RAM
SFR
Separate bus
2-wait2
Multiplex bus
No wait
With wait
1-wait2
With wait1
1 wait
2 waits
3 waits
1wait
2 waits
3 waits
j
1
2
2
3
1
2
3
4
3
3
4
k
1
2
2
3
2
2
3
4
3
3
4
No wait
Notes:
1. Depends on the set value of CSE register.
2. Depends on the set value of PM20 bit in PM2 register.
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With wait1
M306V8FJFP
3. DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register
is “1” (forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
4. DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the
DMS and DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 9.4 shows the timing
at which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is
set to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in
a program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 9.4. Timing at Which the DMAS Bit Changes State
DMAS bit of the DMiCON register
DMA factor
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
Software trigger
When the DSR bit of DMiCON
register is set to “1”
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiCON register
has its IR bit set to “1”
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• Immediately before a data transfer starts
• When set by writing “0” in a program
M306V8FJFP
5. Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 9.6 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 9.6, occurs more than one time, the DMAS bit is set to “0” as soon as
getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
__________
Refer to “(7) HOLD Signal in Bus Control” for details about bus arbitration between the CPU and DMA.
An example where DMA requests for external causes are detected active at the same
BCLK
DMA0
DMA1
CPU
INT0
Bus
arbitration
DMAS bit of
DMA0
INT1
DMAS bit of
DMA1
Figure 9.6. DMA Transfer by External Factors
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M306V8FJFP
Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function
as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such
timer operations as counting, reloading, etc. Figures 10.1 and 10.2 show block diagrams of timer A and
timer B configuration, respectively.
1/2
• Main clock
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f1 or f2 f8 f32 fC32
1/32
XCIN
PCLK0 bit = 1
f32
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
fC32
Reset
• Timer mode
• One-shot timer mode
• Pulse Width Measuring (PWM) mode
Timer A0 interrupt
Noise
filter
TA0IN
Timer A0
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Noise
filter
TA1IN
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2 interrupt
Noise
filter
TA2IN
Timer A2
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3 interrupt
Noise
filter
TA3IN
Timer A3
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4 interrupt
Timer A4
• Event counter mode
Timer B2 overflow or underflow
Note: Be aware that TA0IN shares the pin with RxD2 and TB5IN.
Figure 10.1. Timer A Configuration
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M306V8FJFP
1/2
• Main clock
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f32
fC32
1/32
XCIN
PCLK0 bit = 1
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
Reset
f1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB0IN
Timer B0 interrupt
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB1IN
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B2 interrupt
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B3 interrupt
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Timer B4 interrupt
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note: Be aware that TB5IN shares the pin with RxD2 and TA0IN.
Figure 10.2. Timer B Configuration
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Timer B5 interrupt
M306V8FJFP
Timer A
Figure 10.3 shows a block diagram of the timer A. Figures 10.4 to 10.6 show registers related to the timer
A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of
other timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count
“000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1 or f2
f8
f32
fC32
Low-order
8 bits
• Timer
(gate function)
High-order
8 bits
Reload register
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 3)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
(Note)
TB2 overflow
To external
trigger circuit
(Note)
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
(Note)
Down count
Addresses
038716 - 038616
038916 - 038816
038B16 - 038A16
038D16 - 038C16
038F16 - 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 3)
Toggle flip-flop
Note: Overflow or underflow
Figure 10.3. Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
Address
039616 to 039A16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
After reset
0016
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Figure 10.4. TA0MR to TA4MR Registers
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RW
RW
Count source selection bit
(Function varies with each operation mode)
RW
MR3
TCK1
RW
Function varies with each
operation mode
MR2
TCK0
RW
b1 b0
RW
RW
RW
RW
M306V8FJFP
Timer Ai register (i= 0 to 4) (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer
mode
Event
counter
mode
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
RW
Divide the count source by FFFF16 – n + 1
where n = set value when counting up or
by n + 1 when counting down (Note 5)
000016 to FFFF16
One-shot
timer mode
Divide the count source by n where n = set
value and cause the timer to stop
000016 to FFFF16
(Notes 2, 4)
Function
Mode
Pulse width Modify the pulse width as follows:
modulation PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
mode
(16-bit PWM) where n = set value, fj = count source
frequency
Pulse width Modify the pulse width as follows:
modulation PWM period: (28 – 1) x (m + 1)/ fj
mode
High level PWM pulse width: (m + 1)n / fj
(8-bit PWM) where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
RW
WO
000016 to FFFE16
(Note 3, 4)
WO
0016 to FE16
(High-order address)
0016 to FF16
(Low-order address) WO
(Note 3, 4)
Note 1: The register must be accessed in 16-bit units.
Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘0016’
while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
After reset
0016
Bit name
Function
RW
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
Up/down flag (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Bit symbol
Address
038416
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
After reset
0016
Function
0 : Down count
1 : Up count
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
RW
RW
RW
RW
RW
RW
Timer A2 two-phase pulse 0 : two-phase pulse signal
WO
processing disabled
signal processing select bit
1 : two-phase pulse signal
processing enabled
Timer A3 two-phase pulse
WO
(Notes 2, 3)
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
WO
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA3IN and TA2OUT to TA3OUT pins are set to
“0” (input mode).
Note 3: When not using the two-phase pulse signal processing function, set corresponding bits to “0”.
Figure 10.5. TA0 to TA4 Registers, TABSR Register, and UDF Register
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M306V8FJFP
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
ONSF
b0
Address
038216
After reset
0016
Bit symbol
Bit name
Function
RW
TA0OS
Timer A0 one-shot start flag
RW
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits of TAiMR register (i =
0 to 4) = ‘102’ (= one-shot timer
mode) and the MR2 bit of TAiMR
register = “0” (=TAiOS bit enabled).
When read, its content is “0”.
TA4OS
Z-phase input enable bit
TA0TGL
Timer A0 event/trigger
select bit
TA0TGH
0 : Z-phase input disabled
1 : Z-phase input enabled
RW
RW
RW
RW
RW
b7 b6
RW
0 0 : Input on TA0IN is selected (Note 1)
0 1 : TB2 overflow is selected (Note 2)
1 0 : TA4 overflow is selected (Note 2) RW
1 1 : TA1 overflow is selected (Note 2)
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
Trigger select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Bit symbol
TA1TGL
Address
038316
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Timer A3 event/trigger
select bit
TA3TGH
TA4TGL
Timer A4 event/trigger
select bit
TA4TGH
After reset
0016
Function
RW
b1 b0
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA0 is selected
1 1 : TA2 is selected
b3 b2
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA1 is selected
1 1 : TA3 is selected
RW
RW
RW
RW
b5 b4
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
b7 b6
0 0 : Must not to be set
0 1 : TB2 is selected
1 0 : TA3 is selected
1 1 : TA0 is selected
RW
RW
RW
RW
Note : Make sure the port direction bits for the TA1IN to TA3IN pins are set to “0” (= input mode).
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Address
038116
After reset
0XXXXXXX2
(b6-b0)
Bit name
Function
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
CPSR
Clock prescaler reset flag
RW
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
Figure 10.6. ONSF Register, TRGSR Register, and CPSRF Register
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RW
M306V8FJFP
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 10.1). Figure 10.7 shows
TAiMR register in timer mode.
Table 10.1. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and continues counting
1/(n+1) n: set value of TAiMR register (i= 0 to 4)
000016 to FFFF16
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
At underflow
I/O port or gate input
I/O port or pulse output
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
While the TAiS bit is set to “0”, the pin outputs an “L” level signal during the count stop.
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Timer Ai mode register (i=0 to 4)
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
TMOD1
Address
039616 to 039A16
After reset
0016
Bit name
Operation mode
select bit
Function
b1 b0
0 0 : Timer mode
Pulse output function
MR0
(Note 3) select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
Gate function select bit
MR1
(Note 3)
b4 b3
MR2
(Note 3)
0 0 : Gate function not available
} (TAiIN pin functions as I/O port)
01:
1 0 : Counts while input on the TAiIN pin
is low (Note 2)
1 1 : Counts while input on the TAiIN pin
is high (Note 2)
MR3
Must be set to “0” in timer mode
TCK0
Count source select bit
TCK1
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RW
RW
RW
RW
RW
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Note 3: Bits MR0, MR1 and MR2 of TA4MR are set to “0”.
Figure 10.7. TAiMR Register in Timer Mode
RW
RW
RW
RW
M306V8FJFP
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 10.2 lists specifications
in event counter mode (when not processing two-phase pulse signal). Figure 10.8 shows TAiMR register
in event counter mode (when not processing two-phase pulse signal).
Table 10.2. Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TAiIN pin (i=0 to 3) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
Count operation
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
I/O port or count source input
TAiOUT pin function
I/O port, pulse output, or up/down-count select input
Read from timer
Count value can be read by reading TAi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
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M306V8FJFP
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
0 1
Bit symbol
TMOD0
Address
039616 to 039A16
After reset
0016
Bit name
Operation mode select bit
Function
b1 b0
0 1 : Event counter mode (Note 1)
TMOD1
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 2)
RW
R
W
RW
RW
MR0
(Note 5)
Pulse output function
select bit
MR1
(Note 5)
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge RW
1 : Counts external signal's rising edge
MR2
(Note 5)
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (Note 4)
RW
(TAiOUT pin functions as pulse output pin)
RW
MR3
Must be set to “0” in event counter mode
RW
TCK0
Count operation type
select bit
RW
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
0 : Reload type
1 : Free-run type
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
Note 2: TA0OUT pin is N-channel open drain output.
Note 3: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Note 5: Bits MR0, MR1 and MR2 of TA4MR are set to “0”.
Figure 10.8. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
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M306V8FJFP
Table 10.3 lists specifications in event counter mode (when processing two-phase pulse signal with the
timers A2, A3 and A4).
Figure 10.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-phase pulse
signal with the timers A2, A3 and A4).
Table 10.3. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Specification
Count source
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 3)
Count operation
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
Two-phase pulse input
TAiOUT pin function
Two-phase pulse input
Read from timer
Count value can be read by reading timer A2, A3 or A4 register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
Select function (Note)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Upcount
Upcount
Upcount
Downcount
Downcount
Downcount
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3) pin goes “H” when the input
signal on TAkOUT pin is “H”, the timer counts up rising and falling edges on
TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin
goes “L” when the input signal on TAkOUT pin is “H”, the timer counts down
rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count up all edges
Count down all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to 0 by Z-phase input.
Note: Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed
to multiply-by-4 processing operation.
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M306V8FJFP
Timer Ai mode register (i=2 to 3)
(When using two-phase pulse signal processing)
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
TA2MR to TA3MR
Address
039816 to 039916
Function
RW
0 1 : Event counter mode
RW
RW
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
After reset
0016
b1 b0
To use two-phase pulse signal processing, set this bit to “0”.
RW
To use two-phase pulse signal processing, set this bit to “0”.
RW
MR2
To use two-phase pulse signal processing, set this bit to “1”.
RW
MR3
To use two-phase pulse signal processing, set this bit to “0”.
RW
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
RW
TCK1
Two-phase pulse signal
processing operation
select bit (Notes 1 and 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
MR1
Note 1: Timer A3 can be chosew. Timer A2 is usually fixation irrespective of this bit at processing operation.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register’s TAiP bit to “1” (two-phase pulse signal processing function enabled).
• Set the TRGSR register’s TAiGH and TAiGL bits to ‘002’ (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to “0” (input mode).
Figure 10.9. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2 or A3)
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M306V8FJFP
• Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during twophase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal process________
ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting
the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the rising or falling edge by using the POL bit of INT2IC register. The Z-phase pulse width
_______
applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 10.10 shows
the relationship between the two-phase pulse (A phase and B phase) and the Z phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
INT2 (Note)
(Z phase)
Input equal to or greater than one clock cycle
of count source
Timer A3
m
m+1
1
2
3
4
5
Note: This timing diagram is for the case where the POL bit of INT2IC register = “1” (= rising edge).
Figure 10.10. Two-phase Pulse (A phase and B phase) and the Z Phase
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M306V8FJFP
3. One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 10.4.) When the
trigger occurs, the timer starts up and continues operating for a given period. Figure 10.11 shows the
TAiMR register in one-shot timer mode.
Table 10.4. Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
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f1, f2, f8, f32, fC32
• Down-count
• When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : set value of TAi register 000016 to FFFF16
However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
When the counter reaches “000016”
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
The timer outputs a low when not counting and a high when counting.
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M306V8FJFP
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
b2
0
b1
b0
1 0
Symbol
TA0MR to TA4MR
After reset
0016
Bit name
Bit symbol
TMOD0
Address
039616 to 039A16
Operation mode select bit
TMOD1
Function
b1 b0
1 0 : One-shot timer mode
RW
RW
RW
MR0
Pulse output function
(Note 4) select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
RW
1 : Pulse is output (Note 1)
(TAiOUT pin functions as a pulse output pin)
MR1
External trigger select
(Note 4) bit (Note 2)
0 : Falling edge of input signal to TAiIN pin (Note 3)
1 : Rising edge of input signal to TAiIN pin (Note 3) RW
MR2
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
Trigger select bit
MR3
Must be set to “0” in one-shot timer mode
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Note 4: Bits MR0 and MR1 of TA4MR are set to “0”.
Figure 10.11. TAiMR Register in One-shot Timer Mode
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M306V8FJFP
4. Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 10.5). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 10.12 shows
TAiMR register in pulse width modulation mode. Figures 10.13 and 10.14 show examples of how a 16-bit
pulse width modulator operates and how an 8-bit pulse width modulator operates.
Table 10.5. Specifications in PWM Mode
Item
Specification
Count source
Count operation
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
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f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting
• High level width
n / fj
n : set value of TAi register (i=0 to 3)
• Cycle time (216-1) / fj fixed
fj: count source frequency (f1, f2, f8, f32, fC32)
• High level width n x (m+1) / fj n : set value of TAiMR register high-order address
• Cycle time (28-1) x (m+1) / fj m : set value of TAiMR register low-order address
• TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1) overflow or underflow
TAiS bit is set to “0” (= stop counting)
PWM pulse goes “L”
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
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M306V8FJFP
Timer Ai mode register (i= 0 to 3)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
1
Symbol
TA0MR to TA3MR
Bit symbol
TMOD0
TMOD1
Address
039616 to 039916
After reset
0016
Bit name
Operation mode
select bit
RW
Function
RW
b1 b0
1 1 : PWM mode
(Note 1) RW
RW
MR0
Must be set to “1” in PWM mode
MR1
External trigger select
bit (Note 2)
0: Falling edge of input signal to TAiIN pin(Note 3)
RW
1: Rising edge of input signal to TAiIN pin(Note 3)
MR2
Trigger select bit
0 : Write “1” to TAiS bit in the TASF register RW
1 : Selected by TAiTGH to TAiTGL bits
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
b7 b6
TCK1
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 10.12. TAiMR Register in PWM Mode
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M306V8FJFP
1 / fi X (2
16
– 1)
Count source
Input signal to
TAiIN pin
“H”
“L”
Trigger is not generated by this signal
1 / fj X n
PWM pulse output
from TAiOUT pin
“H”
IR bit of TAiIC
register
“1”
“L”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 3
Note 1: n = 000016 to FFFE16.
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiGH and TAiGL bits of ONSF
or TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2
bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 10.13. Example of 16-bit Pulse Width Modulator Operation
1 / fj X (m + 1) X (2 8 – 1)
Count source (Note1)
Input signal to
TAiIN pin
“H”
“L”
1 / fj X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fj X (m + 1) X n
PWM pulse output
from TAiOUT pin
IR bit of TAiIC
register
“H”
“L”
“1”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 3
Set to “0” upon accepting an interrupt request or by writing in program
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiGH and TAiGL bits of ONSF or
TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 10.14. Example of 8-bit Pulse Width Modulator Operation
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M306V8FJFP
Timer B
Figure 10.15 shows a block diagram of the timer B. Figures 10.16 and 10.17 show registers related to the
timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5)
to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
Low-order 8 bits
• Timer
• Pulse period measuremnet,
pulse width measurement
f1 or f2
f8
f32
fC32
High-order 8 bits
Reload register
Clock selection
Counter
• Event counter
TABSR register
TBSR register
Polarity switching,
edge pulse
TBiIN
(i = 0, 1, 5)
Counter reset circuit
Can be selected in only
event counter mode
TBj overflow (Note)
(j = i – 1, except j = 2 if i = 0, j = 5 if i = 3)
Note: Overflow or underflow.
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Address
039116 - 039016
039316 - 039216
039516 - 039416
035116 - 035016
035316 - 035216
035516 - 035416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 10.15. Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
After reset
00XX00002
00XX00002
Function
Bit name
Operation mode select bit
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
Function varies with each operation mode
MR1
MR2
RW
RW
RW
RW
RW
RW
(Note 1)
(Note 2)
RO
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 10.16. TB0MR to TB5MR Registers
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RW
RW
M306V8FJFP
Timer Bi register (i=0 to 5)(Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
039116, 039016
039316, 039216
039516, 039416
035116, 035016
035316, 035216
035516, 035416
Function
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
RW
Event counter
mode
Divide the count source by n + 1
where n = set value (Note 2)
000016 to FFFF16
RW
Mode
Pulse period
Measures a pulse period or width
modulation mode,
Pulse width
modulation mode
RO
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
After reset
0016
Bit name
Bit symbol
Function
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
RW
Timer B3, B4, B5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
034016
After reset
000XXXXX2
Bit symbol
(b4-b0)
Bit name
Function
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
After reset
0XXXXXXX2
Function
RW
(b6-b0)
CPSR
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
Clock prescaler reset flag Setting this bit to “1” initializes the
RW
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
Figure 10.17. TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register
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M306V8FJFP
1. Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 10.6). Figure 10.18 shows
TBiMR register in timer mode.
Table 10.6. Specifications in Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1) n: set value of TB register (i= 0 to 5)
000016 to FFFF16
(Note)
Count start condition
Set TBiS bit
to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
I/O port
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i= 0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Operation mode select bit
TMOD1
MR0
MR1
MR2
After reset
00XX00002
00XX00002
Bit name
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Function
b1 b0
0 0 : Timer mode
RW
RW
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
RW
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
TCK0
Count source select bit
TCK1
Figure 10.18. TBiMR Register in Timer Mode
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RO
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
M306V8FJFP
2. Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 10.7) . Figure 10.19 shows TBiMR register in event counter mode.
Table 10.7. Specifications in Event Counter Mode
Item
Specification
Count source
• External signals input to TBiIN pin (i=0, 1, 5) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
1
Count start condition
Set TBiS bit to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note: The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode select bit
TMOD1
MR0
Count polarity select
bit (Note 1)
MR1
MR2
After reset
00XX00002
00XX00002
Function
b1 b0
0 1 : Event counter mode
RW
RW
RW
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
RW
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
MR3
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to “0” or “1”.
RW
Event clock select
TCK1
(Note 3)
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1.”
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Note 3: Bit TCK1 of TB2MR, TB3MR and TB4MR set to “1.”
Figure 10.19. TBiMR Register in Event Counter Mode
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M306V8FJFP
3. Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 10.8). Figure 10.20 shows TBiMR register in pulse period and pulse width
measurement mode. Figure 10.21 shows the operation timing when measuring a pulse period. Figure
10.22 shows the operation timing when measuring a pulse width.
Table 10.8. Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to “000016” to continue counting.
Count start condition
Set TBiS (i=0, 1, 5) bit (Note 3) to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input (Note 1)
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function
Measurement pulse input
Read from timer
Contents of the reload register (measurement result) can be read by reading
TBi register (Note 2)
Write to timer
Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB1S bits are assigned to the TABSR register bit 5 to bit 6, and the TB5S bit is assigned to the TBSR
register bit 7.
Timer Bi mode register (i=0, 1, 5)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TB0MR to TB1MR
TB5MR
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039C16
035D16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
MR3
TCK0
After reset
00XX00002
00XX00002
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
TCK1
RW
RW
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
TB0MR register
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
0 : Timer did not overflow
flag ( Note)
1 : Timer has overflowed
Count source
select bit
RW
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RO
RW
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB1S bits are assigned to the TABSR register's bit 5 to bit 6, and the TB5S bit is assigned to the
TBSR register's bit 7.
Figure 10.20. TBiMR Register in Pulse Period and Pulse Width Measurement Mode
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M306V8FJFP
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
TBiS bit
“0”
TBiIC register's
IR bit
“1”
TBiMR register's
MR3 bit
“1”
“0”
Set to “0” upon accepting an interrupt request or by writing in
program
“0”
The TB0S and TB1S bits are assigned to the TABSR register's bit 5 and bit 6, and the TB5S bit is
assigned to the TBSR register's bit 7.
i = 0, 1, 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “002” (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 10.21. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
TBiS bit
“0”
“1”
TBiIC register's
IR bit
“0”
“1”
TBiMR register's
MR3 bit
i = 0, 1, 5
Set to “0” upon accepting an interrupt request or by
writing in program
“0”
The TB0S and TB1S bits are assigned to the TABSR register's bit 5 and bit 6, and the TB5S bit is
assigned to the TBSR register's bit 7.
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 10.22. Operation timing when measuring a pulse width
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M306V8FJFP
Serial I/O
Serial I/O is configured with 3 channels: UART0 to UART2.
Each is explained below.
UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each
other.
Figure 11.1 shows the block diagram of UARTi. Figures 11.2 shows the block diagram of the UARTi
transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 2
• Special mode 1 (Bus collision detection function, IE mode) : UART0, UART1
Figures 11.3 to 11.8 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
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M306V8FJFP
1/2 f2SIO
PCLK1=0
f1SIO or f2SIO
f1SIO
Main clock
PCLK1=1
1/8
f8SIO
1/4
(UART0)
f32SIO
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD0
Clock source selection
UART reception
1/16
CLK1 to CLK0
002
f1SIO or f2SIO
Internal CKDIR=0
012
f8SIO
102
f32SIO
Reception
control circuit
Clock synchronous
type
U0BRG
register
1 / (n0+1)
1/16
UART transmission
Transmission control
Clock synchronous
circuit
type
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
External
TxD0
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK0
CTS/RTS selected
CRS=1
CTS0 / RTS0
CTS/RTS disabled
RTS0
“H”
CRS=0
CTS/RTS disabled
CRD=1
RCSP=0
CTS0
CRD=0
CTS0 from UART1
RCSP=1
(UART1)
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
Internal CKDIR=0
012
f8SIO
102
f32SIO
External
UART reception
1/16
1 / (n1+1)
CTS1 / RTS1/
CTS0/ CLKS1
1/16
UART transmission
CLKMD0=0
Clock output
pin select
CLKMD1=1
Transmission
control circuit
Clock synchronous
type
CKDIR=1
CLK
polarity
reversing
circuit
Reception
control circuit
Clock synchronous
type
U1BRG
register
CKPOL
CLK1
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD1
TxD1
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLKMD0=1
CTS/RTS selected
CRS=1
CLKMD1=0
CRS=0
CTS/RTS disabled
RTS1
“H”
CTS/RTS disabled
RCSP=0
CRD=1
CTS1
CRD=0
CTS0 from UART0
RCSP=1
(UART2)
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
012
Internal CKDIR=0
f8SIO
102
f32SIO
External
CKPOL
CLK2
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
CLK
polarity
reversing
circuit
CTS/RTS
selected
CRS=1
CTS2 / RTS2
CRS=0
1/16
Clock synchronous
type
U2BRG
register
1 / (n2+1)
UART reception
1/16
UART transmission
Clock synchronous
type
CKDIR=1
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CTS/RTS disabled
RTS2
“Vcc”
CTS/RTS disabled
CRD=1
CTS2
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 11.1. UARTi Block Diagram
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Reception
control circuit
Transmission
control circuit
Receive
clock
Transmit
clock
(Note)
Transmit/
receive
unit
TxD2
M306V8FJFP
No reverse
IOPOL=0
RxD data
reverse circuit
RxDi
Reverse IOPOL=1
Clock
synchronous type
1SP
PAR
disabled
STPS= 0
PRYE=0
SP
2SP
SP
UARTi receive register
UART(7 bits)
PAR
PRYE=1
PAR
enabled
STPS= 1
0
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
UART
(9 bits)
D6
D5
D4
D3
D2
D1
D0
UiTB register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
PAR
2SP STPS= 1 enabled PRYE=1 UART
SP
SP
PAR
STPS
=0
1SP
PRYE=0
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
UiERE: UiC0 register's bit
Figure 11.2. UARTi Transmit/Receive Unit
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UARTi transmit register
UART(7 bits)
Error signal output
disable
UiERE=1
No reverse
IOPOL=0
UiERE=0
Error signal
output circuit
Error signal output
enable
IOPOL=1
TxD data
reverse circuit
Reverse
TxDi
M306V8FJFP
UARTi transmit buffer register (i=0 to 2)(Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
03A316-03A216
03AB16-03AA16
037B16-037A16
After reset
Indeterminate
Indeterminate
Indeterminate
Function
RW
WO
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b15)
b7
(b8)
b0 b7
b0
Bit
symbol
Symbol
U0RB
U1RB
U2RB
Address
03A716-03A616
03AF16-03AE16
037F16-037E16
Function
Bit name
(b7-b0)
(b8)
(b10-b9)
After reset
Indeterminate
Indeterminate
Indeterminate
RW
Receive data (D7 to D0)
RO
Receive data (D8)
RO
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
0 : Not detected
1 : Detected
ABT
Arbitration lost detecting
flag (Note 2)
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
RO
FER
Framing error flag (Note 1)
0 : No framing error
1 : Framing error found
RO
PER
Parity error flag (Note 1)
0 : No parity error
1 : Parity error found
RO
SUM
Error sum flag (Note 1)
0 : No error
1 : Error found
RO
RW
Note 1: When the UiMR register’s SMD2 to SMD0 bits = “000 2” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)
UARTi baud rate generation register (i=0 to 2)(Notes 1, 2)
b7
Symbol
U0BRG
U1BRG
U2BRG
b0
Address
03A116
03A916
037916
After reset
Indeterminate
Indeterminate
Indeterminate
Function
Setting range
RW
Assuming that set value = n, UiBRG divides the count source
by n + 1
0016 to FF16
WO
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 11.3. U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register
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M306V8FJFP
UARTi transmit/receive mode register (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0MR to U2MR
Bit
symbol
SMD0
Address
03A016, 03A816, 037816
After reset
0016
Function
Bit name
Serial I/O mode select bit
(Note 2)
RW
b2 b1 b0
RW
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : Must not be set
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
RW
STPS
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
RW
PRY
Odd/even parity select bit Effective when PRYE = 1
SMD1
SMD2
RW
0 : Odd parity
1 : Even parity
RW
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
RW
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0 to U2C0
Bit
symbol
CLK0
Address
After reset
03A416, 03AC16, 037C16 000010002
Bit name
BRG count source
select bit
CLK1
CRS
TXEPT
CRD
CTS/RTS function
select bit
(Note 4)
Function
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Transmit register empty 0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
flag
(transmission completed)
CTS/RTS disable bit
RW
RW
RW
RW
RO
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
RW
NCH
Data output select bit
(Note 2)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
RW
CKPOL
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
RW
UFORM Transfer format select bit 0 : LSB first
(Note 3)
1 : MSB first
RW
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2 is N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).
Figure 11.4. U0MR to U2MR Register and U0C0 to U2C0 Register
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M306V8FJFP
UARTi transmit/receive control register 1 (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
U0C1, U1C1
b0
Bit
symbol
Address
03A516,03AD16
After reset
00XX00102
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
RO
(b5-b4)
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
UiLCH
Data logic select bit
0 : No reverse
1 : Reverse
RW
UiERE
Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
U2C1
b0
Bit
symbol
Address
037D16
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RO
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
RW
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
U2IRS UART2 transmit interrupt
cause select bit
Figure 11.5. U0C1 to U2C1 Registers
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After reset
000000102
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M306V8FJFP
UART transmit/receive control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
After reset
X00000002
Function
RW
Bit
name
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
RW
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
CLKMD0 UART1 CLK/CLKS
select bit 0
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
RW
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
RW
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
U0IRS
U1IRS
Separate UART0
CTS/RTS bit
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UARTi special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
Address
U0SMR to U2SMR 036F16, 037316, 037716
0
Bit
symbol
After reset
X00000002
Function
Bit
name
Reserved bits
Set to “0”
RW
ABSCS
Bus collision detect
sampling clock select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 1)
RW
ACSE
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
RW
SSS
Transmit start condition
select bit
0 : Not synchronized to RXDi
1 : Synchronized to RXDi (Note 2)
RW
(b7)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
Note 1: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 2: SSS bit will be set to “0” (unrelated to RXDi) if transmission starts.
Figure 11.6. UCON Register and U0SMR to U2SMR Registers
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RW
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M306V8FJFP
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
0 0
Symbol
Address
U0SMR2 to U2SMR2 036E16, 037216, 037616
0 0
Bit
symbol
Bit name
After reset
X00000002
Function
Reserved bits
Set to “0”
RW
RW
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
(b7)
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
U0SMR3 to U2SMR3
0
Bit
symbol
(b0)
CKPH
(b2)
NODC
(b4)
Address
036D16, 037116, 037516
Bit name
After reset
000X0X0X2
Function
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Reserved bits
Set to “0”
Figure 11.7. U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
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RW
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RW
M306V8FJFP
UARTi special mode register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
0
0 0
Symbol
Address
U0SMR4 to U2SMR4 036C16, 037016, 037416
Bit
symbol
Bit name
Reserved bits
Figure 11.8. U0SMR4 to U2SMR4 Registers
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After reset
0016
Function
Set to “0”
RW
RW
M306V8FJFP
Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 11.1
lists the specifications of the clock synchronous serial I/O mode. Table 11.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 11.1. Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer clock
Transfer data length: 8 bits
● UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
● CKDIR bit = “1” (external clock
) : Input from CLKi pin
_______
_______
_______ _______
● Selectable from CTS function, RTS function or CTS/RTS function disable
● Before transmission can start, the following requirements must be met (Note 1)
• The TE bit of UiC1 register= 1 (transmission enabled)
• The TI bit of UiC1 register = 0 (data present in UiTB register)
●
Transmission, reception control
Transmission start condition
_______
_______
• If CTS function is selected, input on the CTSi pin = “L”
Reception start condition
Interrupt request
generation timing
Before reception can start, the following requirements must be met (Note 1)
• The RE bit of UiC1 register= 1 (reception enabled)
• The TE bit of UiC1 register= 1 (transmission enabled)
• The TI bit of UiC1 register= 0 (data present in the UiTB register)
● For transmission, one of the following conditions can be selected
• The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
●
For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
● Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
● CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
● LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
● Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
● Switching serial data logic
This function reverses the logic value of the transmit/receive data
● Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
● Separate CTS/RTS pins (UART0)
●
Error detection
Select function
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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M306V8FJFP
Table 11. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB(Note3)
Bit
Function
0 to 7
Set transmission data
UiRB(Note3) 0 to 7
UiBRG
Reception data can be read
OER
Overrun error flag
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
UiC0
Set to “0012”
CKDIR
Select the internal clock or external clock
IOPOL
Set to “0”
CLK1 to CLK0
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
_______
_______
_______
UiC1
_______
NCH
Select TxDi pin output mode (Note 2)
CKPOL
Select the transfer clock polarity
UFORM
Select the LSB first or MSB first
TE
Set this bit to “1” to enable transmission/reception
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 1)
Select the source of UART2 transmit interrupt
U2RRM (Note 1)
Set this bit to “1” to use continuous receive mode
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set this bit to “1” to use continuous receive mode
CLKMD0
Select the transfer clock output pin when CLKMD1 = 1
CLKMD1
Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
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Table 11.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
11.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 11.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a
period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an
“H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)
Table 11.3. Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
I/O port
UiC0 register’s CRD bit=1
Table 11.4. P64 Pin Functions
Pin function
P64
CTS1
RTS1
CTS0(Note1)
CLKS1
Bit set value
U1C0 register
CRS
CRD
1
0
0
1
0
0
0
RCSP
0
0
0
1
UCON register
CLKMD1 CLKMD0
0
0
0
0
1(Note 2)
PD6 register
PD6_4
Input: 0, Output: 1
0
0
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CKPOL bit = 0
• Low if the U1C0 register’s CKPOL bit = 1
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(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
“0”
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
TCLK
“L”
Stopped pulsing because CTSi = “H”
Stopped pulsing because the TE bit = “0”
CLKi
TxDi
D0 D 1 D2 D3 D4 D5 D6 D7
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
D0 D 1 D2 D3 D4 D5 D 6 D7
D 0 D1 D2 D 3 D 4 D 5 D6 D7
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
“1”
UiC1 register
RE bit
“0”
UiC1 register
TE bit
“0”
UiC1 register
TI bit
“1”
Write dummy data to UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
RTSi
“L”
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
1 / fEXT
CLKi
Receive data is taken in
D 0 D1 D 2 D3 D 4 D5 D6 D 7
RxDi
UiC1 register
RI bit
“1”
SiTIC register
IR bit
“1”
Transferred from UARTi receive register
to UiRB register
D0 D 1 D 2
D3 D4 D5
Read out from UiRB register
“0”
“0”
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input
as follows:
to the CLKi pin before receiving data is high:
• UiMR register CKDIR bit = 1 (external clock)
• UiC0 register TE bit = 1 (transmit enabled)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC0 register RE bit = 1 (Receive enabled)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive • Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 11.9. Transmit and Receive Operation
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Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "000b" (Serial I/O disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to "001b" (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to "1" (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register "000b" (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register "001b" (Clock synchronous serial I/O mode)
(3) "1" is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi
register
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M306V8FJFP
(a) CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 11.10 shows
the polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
(Note 2)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(Note 3)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 11.10. Transfer Clock Polarity
(b) LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 11.11 shows the
transfer format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
R XD i
D0
D1
D2
D3
D4
D5
D6
D7
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 11.11. Transfer Format
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M306V8FJFP
(c) Continuous Receive Mode
In continuous receive mode, receive operation becomes enable when the receive buffer register is
read. It is not necessary to write dummy data into the transmit buffer register to enable receive operation in this mode. However, a dummy read of the receive buffer register is required when starting the
operation mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not
write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 4.
(d) Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when
read from the UiRB register. Figure 11.12 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the UFORM bit = 0
(LSB first).
i = 0 to 2
Figure 11.12. Serial Data Logic Switching
(e) Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins. (See
Figure 11.13.) This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Note: This applies to the case where the U1MR register's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1
(transfer clock output from multiple pins).
Figure 11.13. Transfer Clock Output From Multiple Pins
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_______ _______
(f) CTS/RTS Function
_______
________
When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/
________
________ ________
RTSi (i=0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the
“L” signal is switched to “H” during a transmit or receive operation, the operation stops before the next
data.
_______
________ ________
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is
ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.
_______ _______
• CRD bit in UiC0 register = 1 ( CTS/RTS function disabled)
________ ________
CTSi/RTSi pin is programmable I/O function
_______
________ ________
_______
• CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function
_______
________ ________
_______
• CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
_______ _______
(g) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
RXD0 (P62)
IN
OUT
CLK0 (P61)
CLK
RTS0 (P60)
CTS
CTS0 (P64)
RTS
_______ _______
Figure 11.14. CTS/RTS Separate Function
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Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 11.5 lists the specifications of the UART mode.
Table 11.5. UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
Specification
Character bit (transfer data): Selectable from 7, 8 or 9 bits
● Start bit: 1 bit
● Parity bit: Selectable from odd, even, or none
● Stop bit: Selectable from 1 or 2 bits
● UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
● CKDIR bit = “1” (external clock
) : fEXT/16(n+1)
fEXT: Input from CLKi
pin. n :Setting
value of UiBRG
register
0016 to FF16
_______
_______
_______ _______
● Selectable from CTS function, RTS function or CTS/RTS function disable
● Before transmission can start, the following requirements must be met
• The TE bit of UiC1 register= 1 (transmission enabled)
• The
TI bit of UiC1 register = 0 (data present
in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = “L”
● Before reception can start, the following requirements must be met
• The RE bit of UiC1 register= 1 (reception enabled)
• Start bit detection
● For transmission, one of the following conditions can be selected
• The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
● For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
● Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
● Framing error (Note 3)
This error occurs when the number of stop bits set is not detected
● Parity error (Note 3)
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
● Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
●
LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
● Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
● TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels_______
of all_______
I/O data is reversed.
● Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
●
Notes 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
3: The timing when the framing error flag or parity flag are generated is detected when the data is transferred
from the UARTi receive register to the UiRB register.
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Table 11. 6. Registers to Be Used and Settings in UART Mode
Register
UiTB
UiRB
Bit
Function
0 to 8
Set transmission data (Note 1)
0 to 8
Reception data can be read (Note 1)
OER,FER,PER,SUM Error flag
UiBRG
–
Set a transfer rate
UiMR
SMD2 to SMD0
Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
UiC0
CKDIR
Select the internal clock or external clock
STPS
Select the stop bit
PRY, PRYE
Select whether parity is included and whether odd or even
IOPOL
Select the TxD/RxD I/O polarity
CLK0, CLK1
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
_______
_______
_______
_______
NCH
Select TxDi pin output mode (Note 3)
CKPOL
Set to “0”
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
bit to “0” when transfer data is 7 or 9 bits long.
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 2)
Select the source of UART2 transmit interrupt
U2RRM (Note 2)
Set to “0”
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set to “0”
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1
Set to “0”
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2
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Table 11.7 lists the functions of the input/output pins during UART mode. Table 11.8 lists the P64 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin
is in a high-impedance state.)
Table 11.7. I/O Pin Functions
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Input/output port
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
Input/output port
UiC0 register’s CRD bit=1
Table 11.8. P64 Pin Functions
Pin function
Bit set value
U1C0 register
CRS
CRD
P64
CTS1
RTS1
CTS0 (Note)
1
0
0
0
UCON register
RCSP CLKMD1
0
1
0
0
0
0
1
0
0
0
0
PD6 register
PD6_4
Input: 0, Output: 1
0
0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).
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(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
TE bit
“1”
“0”
UiC1 register
TI bit
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
UiC0 register
TXEPT bit
Stopped pulsing
because the TE bit
= “0”
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
“1”
“0”
SiTIC register
IR bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiIRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
Write data to the UiTB register
“0”
“1”
“0”
Start
bit
TxDi
Stop Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
Transferred from UiTB register to UARTi
transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 0 (parity disabled)
fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 1 (2 stop bits)
n : value set to UiBRG
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
i: 0 to 2
• UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 11.15. Transmit Operation
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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
UiC1 register
RE bit
“1”
“0”
Stop bit
Start bit
RxDi
D7
D1
D0
Sampled “L”
Receive data taken in
Transfer clock
UiC1 register
RI bit
RTSi
SiRIC register
IR bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
“0”
“H”
“L”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 11.16. Receive Operation
(a) Bit Rates
In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.
Table 11.9 lists example of bit rates and settings.
Table 11.9 Example of Bit Rates and Settings
Bit Rate
(bps)
Count Source
of BRG
Peripheral Function Clock : 16MHz
Set Value of BRG : n
Actual Time (bps)
Peripheral Function Clock : 24MHz
Set value of BRG : n
Actual Time (bps)
1200
f8
103 (67h)
1202
155 (96h)
1202
2400
f8
51 (33h)
2404
77 (46h)
2404
4800
f8
25 (19h)
4808
38 (26h)
4808
9600
f1
103 (67h)
9615
155 (96h)
9615
14400
f1
68 (44h)
14493
103 (67h)
14423
19200
f1
51 (33h)
19231
77 (46h)
19231
28800
f1
34 (22h)
28571
51 (33h)
28846
31250
f1
31 (1Fh)
31250
47 (2Fh)
31250
38400
f1
25 (19h)
38462
38 (26h)
38462
51200
f1
19 (13h)
50000
28 (1Ch)
51724
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M306V8FJFP
(b) Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b”, “101b”, “110b”.
(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiCi
register
(c) LSB First/MSB First Select Function
As shown in Figure 11.17, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 11.17. Transfer Format
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M306V8FJFP
(d) Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 11.18 shows serial data
logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D5
D6
D7
P
SP
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge of the transfer clock), the
UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's
STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity
enabled).
Figure 11.18. Serial Data Logic Switching
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ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
M306V8FJFP
(e) TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input/output data (including the start, stop and parity bits) are inversed. Figure 11.19 shows the TXD
pin output and RXD pin input polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
RxDi
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse) “L”
(2) When the UiMR register's IOPOL bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
RxDi
(reverse)
Note: This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the
UiMR register's PRYE bit = 1 (parity enabled).
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Figure 11.19. TXD and RXD I/O Polarity Inverse
_______ _______
(f) CTS/RTS Function
_______
________ ________
When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i=0 to 2)
________ ________
pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H”
during a transmit operation, the operation stops before the next data.
_______
________ ________
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is
ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.
_______ _______
• CRD bit in UiC0 register = 1 (disable CTS/RTS function of UART0)
________ ________
CTSi/RTSi pin is programmable I/O function
_______
________ ________
_______
• CRD bit = 0, CRS bit = 0 (CTS function is selected) CTSi/RTSi pin is CTS function
_______
________ ________
_______
• CRD bit = 0, CRS bit = 1 (RTS function is selected) CTSi/RTSi pin is RTS function
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M306V8FJFP
_______ _______
(g) CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0
from the P64 pin. To use this function, set the register bits as shown below.
_______ _______
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
_______
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
_______ _______
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
_______
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
_______
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
IC
Microcomputer
TXD0 (P63)
RXD0 (P62)
IN
OUT
RTS0 (P60)
CTS
CTS0 (P64)
RTS
_______ _______
Figure 11.20. CTS/RTS Separate Function
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M306V8FJFP
Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 11.10 lists the specifications of Special Mode 2. Table 11.11 lists the registers used in
Special Mode 2 and the register values set. Figure 11.21 shows communication control example for
Special Mode 2.
Table 11.10. Special Mode 2 Specifications
Item
Transfer data format
Transfer clock
Specification
Transfer data length: 8 bits
● Master mode
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
● Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Transmit/receive control
Controlled by input/output ports
Transmission start condition ● Before transmission can start, the following requirements must be met (Note 1)
• The TE bit of UiC1 register= 1 (transmission enabled)
• The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition
● Before reception can start, the following requirements must be met (Note 1)
• The RE bit of UiC1 register= 1 (reception enabled)
• The TE bit of UiC1 register= 1 (transmission enabled)
• The TI bit of UiC1 register= 0 (data present in the UiTB register)
Interrupt request
● For transmission, one of the following conditions can be selected
generation timing
• The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
● Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function
● Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.
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●
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M306V8FJFP
P13
P12
P93
P72(CLK2)
P72(CLK2)
P71(RxD2)
P71(RxD2)
P70(TxD2)
P70(TxD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK2)
P71(RxD2)
P70(TxD2)
Microcomputer
(Slave)
Figure 11.21. Serial Bus Communication Control Example (UART2)
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Table 11. 11. Registers to Be Used and Settings in Special Mode 2
Register
Bit
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
UiBRG
0 to 7
UiMR(Note3) SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
U2RRM(Note 1),
U2LCH, UiERE
UiSMR
0 to 7
UiSMR2
0 to 7
UiSMR3
CKPH
NODC
0, 2, 4 to 7
UiSMR4
0 to 7
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to ‘0012’
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TxDi pin output format(Note 2)
Clock phases can be set in combination with the UiSMR3 register's CKPH bit
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to “0”
Set to “0”
Set to “0”
Clock phases can be set in combination with the UiC0 register's CKPOL bit
Set to “0”
Set to “0”
Set to “0”
Select UART0 and UART1 transmit interrupt cause
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Notes 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
2: TxD2 pin is N channel open-drain output. Nothing is assigned. When writing, set the NCH bit in the
U2C0 register to “0”.
3: Not all register bits are described above. Set those bits to “0” when writing to the registers in
Special Mode 2.
i = 0 to 2
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M306V8FJFP
• Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3
register’s CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
(a) Master (Internal Clock)
Figure 11.22 shows the transmission and reception timing in master (internal clock).
(b) Slave (External Clock)
Figure 11.23 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 11.24 shows the transmission and reception timing (CKPH=1) in slave (external clock).
"H"
Clock output
(CKPOL=0, CKPH=0) "L"
"H"
Clock output
(CKPOL=1, CKPH=0) "L"
Clock output
"H"
(CKPOL=0, CKPH=1) "L"
"H"
Clock output
(CKPOL=1, CKPH=1) "L"
Data output timing
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Figure 11.22. Transmission and Reception Timing in Master Mode (Internal Clock)
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M306V8FJFP
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=0) "L"
"H"
Clock input
(CKPOL=1, CKPH=0) "L"
Data output timing
"H"
(Note)
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 11.23. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=1) "L"
"H"
Clock input
(CKPOL=1, CKPH=1) "L"
Data output timing
(Note)
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 11.24. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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M306V8FJFP
Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 11.12 lists the registers used in IE mode and the register values set. Figure 11.25 shows the
functions of bus collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect
function.
Table 11. 12. Registers to Be Used and Settings in IE Mode
Register
Bit
UiTB
0 to 8
UiRB(Note3) 0 to 8
OER,FER,PER,SUM
UiBRG
0 to 7
UiMR
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
UiRRM (Note 1),
UiLCH, UiERE
UiSMR
0 to 3, 7
ABSCS
ACSE
SSS
UiSMR2
0 to 7
UiSMR3
0 to 7
UiSMR4
0 to 7
IFSR2A
IFSR26, IFSR27
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1,RCSP,7
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TxD/RxD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TxDi pin output mode (Note 2)
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Notes 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
2: TxD2 pin is N channel open-drain output. Nothing is assigned. When writing, set the NCH bit in the
U2C0 register to “0”.
3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IE
mode.
i= 0 to 2
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M306V8FJFP
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
UiBCNIC register
IR bit (Note)
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
UiC1 register
TE bit
Note: BCNIC register when UART2.
(3) UiSMR register SSS bit (Transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D6
D7
D8
SP
TxDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
CLKi
ST
TxDi
D0
D1
D2
D3
D4
D5
(Note 2)
RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 11.25. Bus Collision Detect Function-Related Bits
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M306V8FJFP
A/D Converter
The microcomputer contains one A/D converter circuit based on 8-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P103 to P107, P04 to
P07, and P24 to P27.
When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for ANi, AN0i, and AN2i pins (i = 0 to 7).
Table 12.1 shows the performance of the A/D converter. Figure 12.1 shows the block diagram of the A/D
converter, and Figures 12.2 and 12.3 show the A/D converter-related registers.
Table 12.1. Performance of A/D Converter
Item
Performance
Method of A/D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to VCC1
Operating clock φAD (Note 2) fAD/divide-by-2 of fAD/divide-by-3 of fAD/divide-by-4 of fAD/divide-by-6 of
fAD/divide-by-12 of fAD
Resolution
8-bit
Integral nonlinearity error ±5LSB
Operating modes
One-shot mode, repeat mode, single sweep mode and repeat sweep mode 0
Analog input pins
5 pins (AN3 to AN7) + 4 pins (AN04 to AN07) + 4 pins (AN24 to AN27)
A/D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
Conversion speed per pin • Without sample and hold function
49 φAD cycles
• With sample and hold function
28 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Operation clock frequency (φAD frequency) must be 10 MHz or less.
A case without sample and hold function turn (φAD frequency) into 250kHz or more .
A case with the sample and hold function turn (φAD frequency) into 1MHz or more.
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M306V8FJFP
A/D conversion rate
selection
CKS1=1
CKS2=0
1/2
1/2
fAD
1/3
CKS0=1
øAD
CKS1=0
CKS0=0
CKS2=1
VREF
VCUT=0
AVSS
Resistor ladder
VCUT=1
Successive conversion register
ADCON1 register
ADCON0 register
Decoder
for A/D register
AD3 register (8)
AD4 register (8)
AD5 register (8)
AD6 register (8)
AD7 register (8)
Data bus high-order
Data bus low-order
ADCON2 register
PM00
PM01
(Note)
Vref
Decoder
for channel
selection
VIN
Port P10 group
CH2 to CH0
ADGSEL1 to ADGSEL0=002
OPA1 to OPA0=002
Port P0 group
CH2 to CH0
AN04
AN05
AN06
AN07
=1002
=1012
=1102
=1112
Port P2 group
CH2 to CH0
AN24
AN25
AN26
AN27
AN3
AN4
AN5
AN6
AN7
=0112
=1002
=1012
=1102
=1112
PM01 to PM00=002 (Note)
ADGSEL1 to ADGSEL0=102
OPA1 to OPA0=002
PM01 to PM00=002
ADGSEL1 to ADGSEL0=112
OPA1 to OPA0=002
=1002
=1012
=1102
=1112
Note: Port P0 group (AN04 to AN07) can be used as analog input pins even when PM01
to PM00 bits are set to “012” (memory expansion mode) and PM05 to PM04 bits are
set to “112” (multiplex bus allocated to the entire CS space).
Figure 12.1. A/D Converter Block Diagram
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Comparator
M306V8FJFP
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
ADCON0
Address
03D616
After reset
00000XXX2
Bit symbol
Bit name
Function
RW
CH0
Analog input pin select bit
Function varies with each operation mode
RW
CH1
RW
RW
CH2
MD0
A/D operation mode
select bit 0
MD1
Reserved bit
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
RW
Must always be set to “0”
RW
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
See Note 2 for the ADCON2 register
RW
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
0 0
b5
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
Bit name
A/D sweep pin select bit
After reset
0016
Function
RW
Function varies with each operation mode
SCAN0
RW
SCAN1
RW
Reserved bit
Must always be set to “0”
RW
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
0 : Vref not connected
1 : Vref connected
RW
Reserved bit
Must always be set to “0”
RW
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.2. ADCON0 to ADCON1 Registers
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M306V8FJFP
A/D control register 2 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
Address
After reset
ADCON2
03D416
0016
Bit symbol
Bit name
A/D conversion method
select bit
SMP
ADGSEL0
A/D input group select bit
Function
RW
0 : Without sample and hold
1 : With sample and hold
RW
b2 b1
0 0 : Port P10 group is selected
0 1 : Must not be set
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
RW
Reserved bit
Must always be set to “0”
RW
CKS2
Frequency select bit 2
(Note 2)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
(b7-b5)
Nothing is assigned. In an attempt to write to these bits, write “0”.
The value, if read, turns out to be “0”.
ADGSEL1
(b3)
RW
RW
Notes 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate
.
2:The ØAD frequency must be 10 MHz or less. The selected ØAD frequency is determined by a combination of
the ADCON0 register's CKS0 bit, ADCON1 register's CKS1 bit, and ADCON2 register's CKS2 bit.
CKS2
CKS1
CKS0
ØAD
0
0
0
Divide-by-4 of fAD
0
0
1
Divide-by-2 of fAD
0
1
0
fAD
0
1
1
1
0
0
Divide-by-12 of fAD
1
0
1
Divide-by-6 of fAD
1
1
0
Divide-by-3 of fAD
1
1
1
A/D register i (i=3 to 7)
b7
Symbol
AD3
AD4
AD5
AD6
AD7
Address
03C616
03C816
03CA16
03CC16
03CE16
b0
Function
A/D conversion result
Figure 12.3. ADCON2 Register, and AD3 to AD7 Registers
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After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
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RW
RO
M306V8FJFP
(1) One-shot Mode
In this mode, the input voltage on one selected pin is A/D converted once. Table 12.2 shows the specifications of one-shot mode. Figure 12.4 shows the ADCON0 to ADCON1 registers in one-shot mode.
Table 12.2. One-shot Mode Specifications
Item
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A/D converter
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Specification
Bits CH2 to CH0 of ADCON0 register and bits ADGSEL1 to ADGSEL0 bit of
ADCON2 register
Writing “1” to ADST bit of ADCON0 register
• End of A/D conversion
• Writing “0” to ADST bit
End of A/D conversion
One of AN3 to AN7, AN04 to AN07, AN24 to AN27, as selected
Read AD3 to AD7 registers corresponding to selected pin
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M306V8FJFP
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
ADCON0
b0
0 0 0
Address
03D616
Bit symbol
CH0
Bit name
Analog input pin select
bit
CH1
CH2
MD0
MD1
When reset
00000XXX2
A/D operation mode
select bit 0
Reserved bit
Function
RW
b2 b1 b0
0 0 0 : Do not set
0 0 1 : Do not set
0 1 0 : Do not set
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
(Note 2)
(Note 3)
b4 b3
0 0 : One-shot mode
(Note 3)
Must always be set to “0”
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
CKS0
Frequency select bit 0
1 : Refer to note 3 of ADCON2 register
Notes 1: If the A/D control register is rewritten during A/D conversion, the conversion
result is indeterminate.
2: AN04 to AN07 and AN24 to AN27 can be used like AN4 to AN7.
Please choose by bits ADGSEL1 to ADGSEL0 of ADCON2 register.
3: Please re-set up bits CH2 to CH0 by another command after rewriting bits MD1
to MD0.
A/D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A/D sweep pin
select bit
Invalid in one-shot mode
A/D operation mode
select bit 1
Set to “0” in one-shot mode
RW
SCAN1
MD2
Reserved bit
Must always be set to “0”
CKS1
Frequency select bit1
1 : Refer to note 3 of ADCON2 register
VCUT
Vref connect bit (Note 2) 1 : Vref connected
Reserved bits
Must always be set to “0”
Notes 1: If the A/D control register is rewritten during A/D conversion, the conversion result
is indeterminate.
2: When VCUT bit is set to “1” (connection) from “0” (un-connecting), after 1 microsecond
or more passes, please start A/D conversion.
Figure 12.4 ADCON0 Register and ADCON1 Register (One-shot Mode)
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M306V8FJFP
(2) Repeat mode
In this mode, the input voltage on one selected pin is A/D converted repeatedly. Table 12.3 shows the
specifications of repeat mode. Figure 12.5 shows the ADCON0 to ADCON1 registers in repeat mode.
Table 12.3. Repeat Mode Specifications
Item
Function
A/D conversion start conditions
A/D conversion stop conditions
Interruption demand generating timing
Analog input pin
Read-out of A/D conversion value
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Specification
Bits CH2 to CH0 of ADCON0 register and bits ADGSEL1 to ADGSEL0 of
ADCON2 register.
ADST bit of ADCON0 register is set to “1” (A/D conversion start).
ADST bit is set to “0” (A/D conversion stop).
At the time of a A/D conversion end
One pin is chosen from AN3 to AN7 and AN04 to AN07 and AN24 to AN27.
Read out of registers AD3 to AD7 corresponding to the selected pin.
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M306V8FJFP
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 1
Symbol
ADCON0
Address
03D6 16
Bit symbol
CH0
Bit name
Analog input pin
select bit
CH1
CH2
MD0
MD1
When reset
00000XXX 2
A/D operation mode
select bit 0
Function
RW
b2 b1 b0
0 0 0 : Do not set
0 0 1 : Do not set
0 1 0 : Do not set
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
(Note 2)
(Note 3)
b4 b3
0 1 : Repeat mode
(Note 3)
Must always be set to “0”
Reserved bit
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
CKS0
Frequency select bit 0
1 : Refer to note 3 of ADCON2 register
Notes 1: If the A/D control register is rewritten during A/D conversion, the conversion result is
indeterminate.
2: AN04 to AN07, and AN24 to AN27 can be used like AN4 to AN7.
Please choose by bits ADGSEL1 and ADGSEL2 of ADCON2 register.
3: Please re-set up CH2 to CH0 bits by another command after rewriting MD1 to MD0 bits.
A/D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D7 16
When reset
00 16
Bit name
Function
A/D sweep pin
select bit
Invalid in repeat mode
A/D operation mode
select bit 1
Set to “0” in one-shot mode
RW
SCAN1
MD2
Reserved bit
Must always be set to “0”
CKS1
Frequency select bit 1
1 : Refer to note 3 of ADCON2 register
VCUT
Vref connect bit (Note 2)
1 : Vref connected
Reserved bits
Must always be set to “0”
Notes 1: If the A/D control register is rewritten during A/D conversion, the conversion result is
indeterminate.
2: When VCUT bit is set to “1” (connection) from “0” (un-connecting), after 1 microsecond
or more passes, please start A/D conversion.
Figure 12.5. ADCON0 Register and ADCON1 Register (Repeat Mode)
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M306V8FJFP
(3) Single Sweep Mode
In this mode, the input voltages on selected pins are A/D converted, one pin at a time. Table 12.4 shows
the specifications of single sweep mode. Figure 12.6 shows the ADCON0 to ADCON1 registers in single
sweep mode.
Table 12.4. Single Sweep Mode Specifications
Item
Specification
Function
A/D conversion of the input voltage of pin chosen by bits SCAN1 to SCAN0
of ADCON1register and bits ADGSEL1 to ADGSEL0 of ADCON2 register
is carried out by a unit of 1 time.
A/D conversion start conditions
ADST bit of ADCON0 register is set to “1” (A/D conversion start).
A/D conversion stop conditions
● A/D conversion end
● ADST bit is set to “0”
Interruption demand generating timing At the time of a A/D conversion end
Analog input pin
From ANi4 to ANi5 (two pins), and ANi4 to ANi7 (four pins) to selection (i=0, 2) (Note 1)
Read-out of A/D conversion value
Read out of registers AD4 to AD7 corresponding to the selected pin.
Note: AN4 to AN7 can be used like AN04 to AN07, and AN24 to AN27. In this case, it becomes selection from
AN4 to AN5 (two pins), and AN4 to AN7 (four pins).
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M306V8FJFP
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
unction
RW
Invalid in single sweep mode
F
RW
CH1
RW
CH2
RW
MD0
A/D operation mode
select bit 0
b4 b3
RW
1 0 : Single sweep mode
MD1
RW
Reserved bit
Must always be set to “0”
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
See Note 3 for the ADCON2 register
RW
Note: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A/D sweep pin select bit
After reset
0016
RW
Function
When single sweep mode is selected
RW
b1 b0
0 0 : Must not be set
0 1 : Must not be set
1 0 : ANi4 to ANi5 (2 pins)
1 1 : ANi4 to ANi7 (4 pins)
SCAN1
(i=0, 2)
(Note 2)
RW
Reserved bit
Must always be set to “0”
RW
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 3 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 3)
1 : Vref connected
RW
Reserved bits
Must always be set to “0”
RW
Notes 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2: AN4 to AN7 can be used like AN04 to AN07, and AN24 to AN27. In this case, it becomes selection from AN4 to AN5
(two pins), and AN4 to AN7 (four pins).
0 0 : Must not be set
0 1 : Must not be set
1 0 : AN4 to AN5 (2 pins)
1 1 : AN4 to AN7 (4 pins)
3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1µs or more before starting
A/D conversion.
Figure 12.6. ADCON0 Register and ADCON1 Register (Single Sweep Mode)
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M306V8FJFP
(4) Repeat Sweep Mode 0
In this mode, the input voltages on selected pins are A/D converted repeatedly. Table 12.5 shows the
specifications of repeat sweep mode 0. Figure 12.7 shows the ADCON0 to ADCON1 registers in repeat
sweep mode 0.
Table 12.5. Repeat Sweep Mode 0 Specifications
Item
Specification
A/D conversion of the input voltage of pin chosen by bits SCAN1 to SCAN0 of ADCON1
register and bits ADGSEL1 to ADGSEL0 of ADCON2 register is carried out by a unit of
1 time.
A/D conversion start conditions ADST bit of ADCON0 register is set to “1” (A/D conversion start).
A/D conversion stop conditions ADST bit is set to “0” (A/D conversion stop).
Interruption demand generating timing An interruption demand is not generated.
Analog input pin
From ANi4 to ANi5 (two pins), and ANi4 to ANi7 (four pins) to selection (i=0, 2) (Note 1)
Read-out of A/D conversion value
Read out of registers AD3 to AD7 corresponding to the selected pin.
Function
Note: AN4 to AN7 can be used like AN04 to AN07, and AN24 to AN27. In this case, it becomes selection from AN4
to AN5 (two pins), and AN4 to AN7 (four pins).
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M306V8FJFP
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
After reset
00000XXX2
Bit name
Analog input pin
select bit
F
unction
RW
Invalid in repeat sweep mode 0
RW
RW
CH1
RW
CH2
MD0
A/D operation mode
select bit 0
MD1
CKS0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
RW
Must always be set to “0”
RW
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
Frequency select bit 0
See Note 3 for the ADCON2 register
RW
Reserved bit
ADST
b4 b3
Note : If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
SCAN0
After reset
0016
Bit name
A/D sweep pin select bit
RW
Function
When repeat sweep mode 0 is selected
RW
b1 b0
0 0 : Must not be set
0 1 : Must not be set
1 0 : ANi4 to ANi5 (2 pins)
1 1 : ANi4 to ANi7 (4 pins)
SCAN1
(i=0, 2)
(Note 2)
RW
Reserved bit
Must always be set to “0”
RW
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 3 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 3)
1 : Vref connected
RW
Must always be set to “0”
RW
Reserved bits
Notes 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2: AN4 to AN7 can be used like AN04 to AN07, and AN24 to AN27. In this case, it becomes selection from AN4 to AN5
(two pins), and AN4 to AN7 (four pins).
0 0 : Must not be set
0 1 : Must not be set
1 0 : AN4 to AN5 (2 pins)
1 1 : AN4 to AN7 (4 pins)
3: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1µs or more before starting
A/D conversion.
Figure 12.7. ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)
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M306V8FJFP
Sample and Hold
If the SMP bit of ADCON2 register is set to “1” (those with a sample & hold), the conversion speed per one
pin will improve and it will become a 28 φAD cycle. However, in all modes, be sure to specify before
starting A/D conversion whether sample and hold is to be used.
Current Consumption Reducing Function
When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be
separated using the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin
into the resistor ladder, helping to reduce the power consumption of the chip.
To use the A/D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s
ADST bit to “1” (A/D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A/D conversion.
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M306V8FJFP
Notes at the time of using A/D converter
(1) Please set to "0" (input mode) the direction bit of a port corresponding to the pin used as an analog
input pin.
(2) When you use key input interruption, please do not use all of pins AN4 to AN7 as an analog input pin
(if A/D input voltage is set to "L", a key input interruption demand will occur).
(3) In order to reduce prevention of incorrect operation and the latch rise by the noise, and a conversion
error, please insert a capacitor, respectively between VCC1 pin, VCC2 pin, an analog input pin (ANi
(i=3 to 7), AN0i, AN2i), and a VSS pin. The example of processing of each pin is shown in Fig.12.8.
(4) A/D conversion is completed, and the mistaken value is stored in an ADi register when CPU reads an
ADi register to the timing which stores the result in an ADi register (i=0 to 7). This phenomenon is
generated when the clock which divided the main clock, or a sub clock is chosen as a CPU clock.
● When using it in one-shot mode or single sweep mode
Please read the target ADi register after checking that A/D conversion has been completed (completion of A/D conversion can be judged in IR bit of ADIC register).
● When using it in repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Please use a CPU clock, without divide a main clock.
(5) When the ADST bit of ADCON0 register is set to "0" (A/D conversion stop) and it forces by the
program during A/D conversion operation to terminate, the conversion result of a A/D conversion
machine becomes unfixed. Moreover, the ADi register which omits A/D conversion may also become
unfixed. During A/D conversion operation, when an ADST bit is set to "0" by the program, please use
no value of ADi registers.
Microcomputer
VCC1
C1
VSS
VSS
VCC2
C2
C3
ANi
VSS
ANi: ANi (i=3 to 7), AN0i , AN2i
Note 1: C1≥0.1µF, C2≥0.1µF, C3≥100pF (reference value).
Note 2: Please connect a capacitor in the shortest distance using thick wiring.
Figure 12.8. Example of noise measure processing of each pin
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M306V8FJFP
Multi-master I2C-BUS Interface 0 to 2
The multi-master I2C-BUS interface i (i=0 to 2) have each dedicated circuit and operate independently.
The multi-master I2C-BUS interface i is a serial communications circuit, conforming to the Philips I2CBUS data transfer format. This interface i, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figures 13.1 and 13.2 show a block diagram of the multi-master I2C-BUS interface i and Table 13.1
shows multi-master I2C-BUS interface i functions.
This multi-master I2C-BUS interface i consists of the I2Ci address register, the I2Ci data shift register, the
I2Ci clock control register, the I2Ci control register, the I2Ci status register, the I2Ci port selection register
and other control circuits.
Table 13.1 Multi-master I2C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
Power supply voltage on bus line
Function
In conformity with Philips I2C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at BCLK = 16 MHz)
(SCL1/SDA1), (SCL3/SDA3), (SCL5/SDA5), (SCL6/SDA6) : 3.3V
(SCL2/SDA2), (SCL4/SDA4) : 3.3V or 5V
Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable
to the use of the control function (bits 1 and 0 of the I2C control register at address 02D916) for
connections between the I2C-BUS interface 0, 1 and ports (SCL1, SCL3, SCL5, SCL6, SDA1,
SDA3, SDA5, SDA6).
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M306V8FJFP
Multi-master I2C-BUS Interface Ports
Communication control is more possible for I2C-BUS0 to I2C-BUS2 than the following pin. Please choose
the pin used by register set up.
SCLSDA1EN
I
O
P66/RXD1/SCL1
SCLSDA1EN
I
I2C-BUS0
FIIC0ON
P67/TXD1/SDA1
O
SCL
“0” “1”
SDA
“0” “1”
BUSON1(✽2)
When choosing SCL2 and SDA2: SCL0INSEL=SDA0INSEL=0.
When choosing SCL5 and SDA5: SCL0INSEL=SDA0INSEL=1.
SCLSDA2EN
I
O
P71/RXD1/SCL2/TA0IN/
TB5IN
(✽1)
SCLSDA2EN
I
FIIC1ON
I2C-BUS1
SDA
SCLSDA3EN
When choosing SCL3 and SDA3: SCL1INSEL0=SDA1INSEL0=0.
When choosing SCL6 and SDA6: SCL1INSEL0=SDA1INSEL0=1.
When choosing SCL1 and SDA1: SCL1INSEL1=SDA1INSEL1=1.
I
I
I
SCL
I2C-BUS2
O
P60/CTS0/RTS0/SCL3
SCLSDA3EN
SCLSDA4EN
FIIC2ON
P70/TXD1/SDA2/TA0OUT
(✽1)
O
SCL
P61/CLK0/SDA3
O
SCL4(✽1)
O
SCLSDA4EN
SDA
I
SDA4(✽1)
O
SCLSDA5EN
I
O
SCL5(✽1)
SCLSDA5EN
I
SDA5(✽1)
O
“0” “1”
“0” “1”
BUSON2(✽2)
SCLSDA6EN
I
O
SCL6(✽1)
SCLSDA6EN
✽1: N channel open-drain pin
✽2: When using the bus switch, apply to DRVUP signal = “L”
from ENABLE signal of the unused pin = “L”.
I
O
SDA6(✽1)
Note: When using the bus switch between SCL5 to SCL6 and SDA5 to SDA6, there are following 2 ways.
(1) When operating I2C0, apply “L” to the buffer ENABLE signal (SCLSDA6EN) of the SCL6 and SDA6 since the buffer is used.
Also, apply to SCL6DRVUP, SDA6DRVUP = “L”.
(2) When operating I2C1, apply “L” to the buffer ENABLE signal (SCLSDA5EN) of the SCL5 and SDA5 since the buffer is used. Also,
apply to SCL5DRVUP, SDA5DRVUP = “L”.
Figure 13.1 Block diagram of multi-master I2C-BUS interface i (i=0 to 2)
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(SCL)
Serial
clock
(SDA)
Serial
data
Noise
elimination
circuit
Noise
elimination
circuit
Clock
control
circuit
BB
circuit
AL
circuit
Data
control
circuit
I2Ci address register (IICiS0D)
b0
b0
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0
MODE
BIT
I2Ci data shift register (IICiS0)
I2Ci clock control register
(IICiS2)
Clock division
ACK
b7
b7
Address comparator
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
b7
BCLK
10BIT
SAD
ALS
b0
ESO BC2 BC1 BC0
b0
I2Ci status
register (IICiS1)
AL AAS AD0 LRB
Interrupt
request signal
(IICiRQ)
Fig. 13.2 Block Diagram of Multi-master I2C-BUS Interface i (i = 0 to 2)
Bit counter
I2Ci control register (IIC1SiD)
b7
Internal data bus
MST TRX BB PIN
b7
Interrupt
generating
circuit
M306V8FJFP
M306V8FJFP
(1) Reserved register
Reserved register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
0 0
Symbol
RSVREG02E5
RSVREG02ED
RSVREG02F5
Bit Symbol
Bit name
When reset
00?000002
Function
RW
Reserved bits
Must always be set to “0”
WO
Multi-master I2C-BUS i (i=0 to 2)
RSVREG02E52 interface enable bit
02E516 = i = 0
RSVREG02ED2
02ED16 = i = 1
RSVREG02F52
02F516 = i =2
0 = Non active
1 = Active
RW
Reserved bits
Must always be set to “0”
WO
Fig. 13.3 Reserved register
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Address
02E516, 02ED16, 02F516
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M306V8FJFP
(2) I2Ci data shift register, I2Ci transmit buffer register (i = 0 to 2)
The I2Ci data shift register is an 8-bit shift register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL
clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.
The I2Ci data shift register is in a write enable status only when the ESO bit of the I2Ci control register
is “1.” The bit counter is reset by a write instruction to the I2Ci data shift register. When both the ESO
bit and the MST bit of the I2Ci status register are “1,” the SCL is output by a write instruction to the I2Ci
data shift register. Reading data from the I2Ci data shift register is always enabled regardless of the
ESO bit value.
The I2Ci transmit buffer register is a register to store transmit data (slave address) to the I2Ci data shift
register before RESTART condition generation. That is, in master, transmit data written to the I2Ci
transmit buffer register is written to the I2Ci data shift register simultaneously. However, the SCL is not
output. The I2Ci transmit buffer register can be written only when the ESO bit is “1,” reading data from
the I2Ci transmit buffer register is disabled regardless of the ESO bit value.
Notes 1: To write data into the I2Ci data shift register or the I2Ci transmit buffer register after the MST
bit value changes from “1” to “0” (slave mode), keep an interval of 20 BCLK or more.
2: To generate START/RESTART condition after the I2Ci data shift register or the I2Ci transmit
buffer register is written, keep an interval of 4 BCLK or more.
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M306V8FJFP
I2Ci data shift register (i = 0 to 2)
Symbol
IIC0S0
IIC1S0
IIC2S0
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
D0
Address
02E016
02E816
02F016
Bit name
When reset
Indeterminate
Indeterminate
Indeterminate
Function
Data shift register
D1
This is an 8-bit shift register to store
receive data and write transmit data.
RW
RW
D2
D3
D4
D5
D6
D7
Note: To write data into the I2Ci data shift register after setting the MST bit to “0” (slave
mode), keep an interval of 8 machine cycles or more.
Fig. 13.4 I2Ci data shift register (i = 0 to 2)
I2Ci transmit buffer register (i = 0 to 2)
Symbol
IIC0S0S
IIC1S0S
IIC2S0S
b7 b6 b5 b4 b3 b2 b1 b0
Address
02E616
02EE16
02F616
Bit Symbol
Bit name
S0S0
Transmit buffer register
S0S1
S0S2
S0S3
S0S4
S0S5
S0S6
S0S7
Fig. 13.5 I2Ci transmit buffer register (i = 0 to 2)
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When reset
Indeterminate
Indeterminate
Indeterminate
Function
This is an 8-bit register to write transmit
data to I2Ci data shift register.
RW
WO
M306V8FJFP
(3) I2Ci address register (i = 0 to 2)
_______
The I2Ci address register consists of a 7-bit slave address and a read/write bit. In the addressing
mode, the slave address written in this register is compared with the address data to be received
immediately after the START condition are detected.
_______
■ Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2Ci
address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
■ Bits 1 to 7: slave address (SAD0 to SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
I2Ci address register (i = 0 to 2)
Symbol
IIC0S0D
IIC1S0D
IIC2S0D
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
Bit name
When reset
0016
0016
Indeterminate
Function
RBW
Read/write bit
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0 : Wait the first byte of slave address
after START condition
(read state)
1 : Wait the first byte of slave address
after RESTART condition
(write state)
SAD0
Slave address
<In both modes>
The address data is compared.
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
Fig. 13.6 I2Ci address register (i = 0 to 2)
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Address
02E116
02E916
02F116
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RW
RW
RW
M306V8FJFP
(4) I2Ci clock control register (i = 0 to 2)
The I2Ci clock control register is used to set ACK control, SCL mode and SCL frequency.
■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
■ Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the
bit is set to “1,” the high-speed clock mode is set.
■ Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK
return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK
clock.
However, when the slave address matches the address data in the reception of address data at ACK
BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
■ Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after
data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an
ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data
and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives
the ACK bit generated by the data receiving device.
Note: Do not write data into the I2Ci clock control register during transmission. If data is written during
transmission, the I2Ci clock generator is reset, so that data cannot be transmitted normally.
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M306V8FJFP
I2Ci clock control register (i = 0 to 2)
Symbol
IIC0S2
IIC1S2
IIC2S2
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
CCR0
Address
02E416
02EC16
02F416
When reset
0016
0016
0016
Bit name
SCL frequency control
bits
Function
Setup value of
CCR4–CCR0
00 to 02
CCR1
CCR2
RW
Setup disabled Setup disabled
Setup disabled
04
Setup disabled
250
05
100
400 (See note)
83.3
166
:
CCR4
RW
High speed
clock mode
03
06
CCR3
Standard
clock mode
333
500/CCR value 1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at BCLK = 10 MHz, unit : kHz)
FAST MODE
ACK BIT
ACK
SCL mode specification 0 : Standard clock mode
bit
1 : High-speed clock mode
RW
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
RW
ACK clock bit
0 : No ACK clock
1 : ACK clock
RW
Note: At 400 kHz in the high-speed clock mode, the duty is as below.
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Fig. 13.7 I2Ci clock control register (i = 0 to 2)
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M306V8FJFP
(5) I2Ci control register (i = 0 to 2)
The I2Ci control register controls the data communication format.
■ Bits 0 to 2: bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request
signal occurs immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits.
Note: When the bit counter value = “1112,” a STOP condition and START condition cannot be waited.
■ Bit 3: I2C-BUS interface i use enable bit (ESO)
This bit enables usage of the multimaster I2C-BUS interface i. When this bit is set to “0,” the use
disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2Ci status register).
• Writing data to the I2Ci data shift register and the I2Ci transmit buffer register is disabled.
■ Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a general call (refer to “(6) I2Ci status
register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recognized.
■ Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing
format is selected. In this case, only the high-order 7 bits (slave address) of the I2Ci address register
are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all
the bits of the I2Ci address register are compared with address data.
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M306V8FJFP
I2Ci control register (i = 0 to 2)
Symbol
IIC0S1D
IIC1S1D
IIC2S1D
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
BC0
Address
02E316
02EB16
02F316
When reset
0016
0016
0016
Bit name
Function
b2 b1 b0
ESO
I2C-BUS interface i use
enable bit
0 : Disabled
1 : Enabled
RW
ALS
Data format selection
bit
0 : Addressing format
1 : Free data format
RW
BC1
BC2
10BIT SAD
0
0
0
0
1
1
1
1
Fig. 13.8 I2Ci control register (i = 0 to 2)
page 180 of 363
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:8
:7
:6
:5
:4
:3
:2
:1
Address format selection 0 : 7-bit addressing format
bit
1 : 10-bit addressing format
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
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RW
Bit counter
(Number of
transmit/receive bits)
RW
RW
M306V8FJFP
(6) I2Ci status register (i = 0 to 2)
The I2Ci status register controls the I2C-BUS interface i status. Bits 0 to 3, 5 are read-only bits and bits
4, 6, 7 can be read out and written to.
■ Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If
ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is
changed from “1” to “0” by executing a write instruction to the I2Ci data shift register or the I2Ci transmit
buffer register.
■ Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode.
By a general call of the master device, every slave device receives control data after the general call.
The AD0 bit is set to “0” by detecting the STOP condition or START condition.
✽General call: The master transmits the general call address “0016” to all slaves.
■ Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
<<In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one
of the following conditions.>>
• The address data immediately after occurrence of a START condition matches the slave address
stored in the high-order 7 bits of the I2Ci address register.
• A general call is received.
<<In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with
the following condition.>>
• When the address data is compared with the I2Ci address register (8 bits consists of slave address
and RBW), the first bytes match.
<<The state of this bit is changed from “1” to “0” by executing a write instruction to the I2Ci data shift
register or the I2Ci transmit buffer register.>>
■ Bit 3: arbitration lost✽ detecting flag (AL)
n the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”,
arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set
to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the
MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0”
and the reception mode is set. Consequently, it becomes possible to receive and recognize its own
slave address transmitted by another master device.
<<This bit changes “1” to “0” by writing instruction to I2Ci data shift register or I2Ci transmit buffer
register.>>
✽Arbitration lost: The status in which communication as a master is disabled.
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M306V8FJFP
■ Bit 4: I2C-BUS interface i interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the
PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The
PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of
an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the
PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt
request bit (IR) is set to “1” (interrupt requested) regardless of falling of PIN bit. When the PIN bit is “0,”
the SCL is kept in the “0” state and clock generation is disabled. Figure 13.10 shows an interrupt
request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Writing “1” to the PIN bit
• Executing a write instruction to the I2Ci data shift register or the I2Ci transmit buffer register (See note).
• When the ESO bit is “0”
• At reset
Note: It takes 12 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed
to these registers.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or
general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
■ Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not
busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and
the occurrence of a START condition is disabled by the START condition duplication prevention function (See note).
This flag can be written by software only in the master transmission mode. In the other modes, this bit is
set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit
of the I2Ci control register is “0” and at reset, the BB flag is kept in the “0” state.
■ Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception
mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission
mode is selected and address data and control data are output into the SDA in synchronization with
the clock generated on the SCL.
When the ALS bit of the I2Ci control register is “0” in the slave reception mode is selected, the TRX bit
___
is set to “1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master
___
is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention
function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
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M306V8FJFP
■ Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is
specified, so that a START condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the clock generated by the master.
When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing
function (See note).
• At reset
Note: The START condition duplication prevention function disables the following: the START condition generation; bit counter reset, and SCL output with the generation. This bit is valid from
setting of BB flag to the completion of 1-byte transmittion/reception (occurrence of transmission/
reception interrupt request) <IICIRQ>.
I2Ci status register (i = 0 to 2)
Symbol
IIC0S1
IIC1S1
IIC2S1
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
LRB
Address
02E216
02EA16
02F216
When reset
0001000?2
0001000?2
0001000?2
Bit name
Last receive bit
Function
0 : Last bit = “0”
1 : Last bit = “1”
RO
(See note 1)
AD0
General call detecting
flag
AAS
Slave address comparison 0 : Address mismatch
flag
1 : Address match
(See note 1)
Arbitration lost detecting 0 : Not detected
flag
1 : Detected
(See note 1)
AL
0 : No general call detected
1 : General call detected (See note 1)
RO
RO
RO
PIN
I2C-BUS interface i
interrupt request bit
0 : Interrupt request issued
RO
1 : No interrupt request issued (See note 2)
BB
Bus busy flag
0 : Bus free
1 : Bus busy
TRX
Communication mode
specification bits
MST
b7b6
0
0
1
1
0 : Slave receive mode
1 : Slave transmit mode
0 : Master receive mode
1 : Master transmit mode
Notes 1: These bits and flags can be read out, but cannot be written.
2: This bit can be written only “1.”
Fig. 13.9 I2Ci status register (i = 0 to 2)
SCL
PIN
IICIRQ
Fig. 13.10 Interrupt request signal generation timing
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RW
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(See note 1)
RO
RW
M306V8FJFP
(7) START condition generation method
When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register
to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit
counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and
BB bit set timing are different in the standard clock mode and the high-speed clock mode. Refer to
Figure 13.11 for the START condition generation timing diagram, and Table 13.2 for the START
condition/STOP condition generation timing table.
I2Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Set time
for BB flag
Fig. 13.11 START condition generation timing diagram
(8) STOP condition generation method
When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be
generated. The STOP condition generation timing and the BB flag reset timing are different in the
standard clock mode and the high-speed clock mode. Refer to Figure 13.12 for the STOP condition
generation timing diagram, and Table 13.2 for the START condition/STOP condition generation timing
table.
I2Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time
for
BB flag
Fig. 13.12 STOP condition generation timing diagram
Table 13.2 START condition/STOP condition generation timing table
Item
Setup time (Min.)
Hold time (Min.)
Set/reset time for BB flag
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Standard Clock Mode
5.6 µs
4.8 µs
3.5 µs
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High-speed Clock Mode
2.1 µs
2.3 µs
0.75 µs
M306V8FJFP
(9) START/STOP condition detect conditions
The START/STOP condition detect conditions are shown in Figure 13.13 and Table 13.3. Only when
the 3 conditions of Table 13.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal
<IICIRQ> is generated to the CPU.
SCL release time
SCL
SDA
Setup
time
(START condition)
SDA
(STOP condition)
Setup
time
Hold
time
Hold
time
Fig. 13.13 START condition/STOP condition detect timing diagram
Table 13.3 START condition/STOP condition detect conditions
Standard Clock Mode
High-speed Clock Mode
6.5 µs < SCL release time
1.0 µs < SCL release time
3.25 µs < Setup time
0.5 µs < Setup time
3.25 µs < Hold time
0.5 µs < Hold time
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M306V8FJFP
(10) Address data communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below.
■ 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “0.” The first
7-bit address data transmitted from the master is compared with the high-order 7-bit slave address
stored in the I2Ci address register. At the time of this comparison, address comparison of the RBW bit
of the I2Ci address register is not made. For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 13.14, (1) and (2).
■ 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “1.” An
address comparison is made between the first-byte address data transmitted from the master and the
7-bit slave address stored in the I2Ci address register. At the time of this comparison, an address
___
comparison between the RBW bit of the I2Ci address register and the R/W bit which is the last bit of
___
the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit
which is the last bit of the address data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I2Ci status register is
set to “1.” After the second-byte address data is stored into the I2Ci data shift register, make an
address comparison between the second-byte data and the slave address by software. When the
address data of the 2nd bytes matches the slave address, set the RBW bit of the I2Ci address register
___
to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2Ci address register. For the data
transmission format when the 10-bit addressing format is selected, refer to Figure 13.14, (3) and (4).
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M306V8FJFP
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and
in the ACK return mode is shown below.
➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2Ci clock control register.
➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH.
➃ Set a communication enable status by setting “0816” in the I2Ci control register.
➄ Set the address data of the destination of transmission in the high-order 7 bits of the I2Ci data shift
register and set “0” in the least significant bit.
➅ Set “F016” in the I2Ci status register to generate a START condition. At this time, an SCL for 1 byte
and an ACK clock automatically occurs.
➆ Set transmit data in the I2Ci data shift register. At this time, an SCL and an ACK clock automatically
occurs.
➇ When transmitting control data of more than 1 byte, repeat step ➆.
➈ Set “D016” in the I2Ci status register. After this, if ACK is not returned or transmission ends, a STOP
condition will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the
ACK non-return mode, using the addressing format, is shown below.
➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2Ci clock control register.
➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH.
➃ Set a communication enable status by setting “0816” in the I2Ci control register.
➄ When a START condition is received, an address comparison is made.
➅
•When all transmitted address are“0” (general call):
AD0 of the I2Ci status register is set to “1”and an interrupt request signal occurs.
•When the transmitted addresses match the address set in ➀:
ASS of the I2Ci status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I2Ci status register are set to “0” and no interrupt request signal occurs.
➆ Set dummy data in the I2Ci data shift register.
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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M306V8FJFP
S
Slave address
7 bits
R/W
A
Data
A
1 to 8 bits
"0"
Data
A/A
P
A
P
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
R/W
7 bits
"1"
A
Data
A
1 to 8 bits
Data
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
7 bits
R/W
A
Slave address
2nd byte
"0"
A
A
Data
1 to 8 bits
8 bits
A/A
Data
P
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
7 bits
R/W
A
Slave address
2nd byte
"0"
A
8 bits
Sr
Slave address
1st 7 bits
7 bits
R/W
A
"1"
Data
1 to 8 bits
A
Data
A
P
1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W :Read/Write bit
From master to slave
From slave to master
Fig. 13.14 Address data communication format
(13) Precautions when using multi-master I2C-BUS interface i
■ BCLK operation mode
Select the no-division mode.
■ Used instructions
Specify byte (.B) as data size to access multi-master I2C-BUS interface i-related registers.
■ Read-modify-write instruction
The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for
each register of the multi-master I2C-BUS interface i are described below.
•I2Ci data shift register (IICiS0)
When executing the read-modify-write instruction for this register during transfer, data may
become a value not intended.
•I2Ci address register (IICiS0D)
When the read-modify-write instruction is executed for this register at detecting the STOP
con______
dition, data may become a value not intended. It is because hardware changes the read/write
bit (RBW) at the above timing.
2
•I Ci status register (IICiS1)
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
•I2Ci control register (IICiS1D)
When the read-modify-write instruction is executed for this register at detecting the START
condition or at completing the byte transfer, data may become a value not intended. Because
hardware changes the bit counter (BC0–BC2) at the above timing.
•I2Ci clock control register (IICiS2)
The read-modify-write instruction can be executed for this register.
•I2Ci port selection register (IICiS2D)
Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction
cannot be used.
•I2Ci transmit buffer register (IICiS0S)
Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.
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M306V8FJFP
■ START condition generating procedure using multi-master
:
FCLR
I
(Interrupt disabled)
BTST
5, IICiS1
(BB flag confirming and branch process)
JC
BUSBUSY
BUSFREE:
MOV.B
SA, IICiS0
(Writing of slave address value <SA>)
NOP
➀
➁
NOP
NOP
NOP
MOV.B
#F0H, IICiS1
(Trigger of START condition generating)
FSET
I
(Interrupt enabled)
:
BUSBUSY:
FSET
I
(Interrupt enabled)
:
➀ Be sure to add NOP instruction ✕ 4 between writing the slave address value and setting trigger of
START condition generating shown the above procedure example.
➁ When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
■ RESTART condition generating procedure
:
➀
MOV.B
SA, IICiS0S
(Writing of slave address value <SA>)
NOP
NOP
MOV.B
#F0H, IICiS1
(Trigger of RESTART condition generating)
:
➀ Use the I2Ci transmit buffer register to write the slave address value to the I2Ci data shift register.
And also, be sure to add NOP instruction ✕ 4.
■ Writing to I2Ci status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become
the same as above.
■ Process of after STOP condition generating
Do not write data in the I2Ci data shift register (IICiS0) and the I2Ci status register (IICiS1) until the bus
busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not have
the problem.
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M306V8FJFP
Data Slicer
This microcomputer includes the data slicer function for the closed caption decoder (referred to as the
CCD) and video ID (referred to as the ID1). This function takes out CC and ID1 (note 1) superimposed in
the vertical blanking interval of a composite video signal. A composite video signal which makes the sync.
tip’s polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit
can be cut off by setting bit 0 of the data slicer control register 1 (address 026016/030016) to “0.” These
settings can realize the low-power dissipation.
Notes 1. 525i (480i)/525p (480p):ID1 data slice can be performed. No CC data slice at 525p (480p).
2. When there is no specification, it becomes the publication about 525i (480i) below.
Composite video
signal
Input amplitude = 1.75 Vpp
0.1 µF
470 Ω
Note 2 (P190)
680 pF
1 MΩ
1 kΩ
2.2 µF
200 pF
Note 1 (P190)
CVIN
HSYNC
HLF
Synchronizing
signal counter
ID1 reserved register 0
ID1 reserved register 1
(address 031C16/031D16)
Clamping
circuit
1 1
Low-pass
filter
Synchronizing
separation
circuit
Sync slice
circuit
Timing signal
generating
circuit
VHOLD
Reference
voltage
generating
1000 pF circuit
+
Comparator 1
Data slicer control register 1
(address 026016/030016)
–
Note : Make the length of wiring which is
connected to VHOLD, HLF, and CVIN pin
as short as possible so that a leakage
current may not be generated when
mounting a resistor or
a capacitor on each pin.
Internal absolute
standard voltage
generating
circuit
Clock run-in
determination
circuit
+
–
Start bit detecting
circuit
ID1 reference
detection circuit
Data clock
generating circuit
Data clock position register
(address 026A16/030A16)
Data register
control circuit
ID1 data clock
generating circuit
CRCC data register
(addresses 026D16 and 030D16)
Caption position register
(address 026616/030616)
Clock run-in detect
register
(address 026916/030916)
Comparator 2
ID1 reference
judgment circuit
Standard clock detection register
(addresses 026C16 and 030C16)
Data slice line
specification
circuit
Address 026716
b1, b0
control circuit
External circuit
1 0 0
ID1 control register
(addresses 026B16 and 030B16)
Data slicer control register 2
(address 026116/030116)
Interrupt request
generating circuit
Caption register 2
(addresses 026516 and 026416/
030516 and 030416)
Data slicer
interrupt
request
Caption register 1
(addresses 026316 and 026216/
030316 and 030216)
Data bus
0 0 0 0 0 0 0 0
Data slicer 0 reserved register 1
Data slicer 1 reserved register 1
(addresses 026816 and 030816)
0
Reserved register
(addresses 026F16 and 030F16)
Figure 14.1 Data slicer block diagram
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1 0 1 0 0 0 0 0
Test reserved register 0
(addresses 026E16)
0 0 0 0 0 0 0 0
Test reserved register 1
(addresses 030E16)
M306V8FJFP
Note 1 : Set up the amplitude inputted from CVIN pin to satisfy the following conditions.
(1) Set up as below :
input amplitude + synchronized chip clamp potential < VCCi + 0.3 V.
Vcci shows Vcci power supply pin voltage.
Sink tip clamp pin serves as (43/120) x VCCi .
Example) In the case of VCCi = 3.3V input amplitude = 2.0V
2.0V + 1.18 V = 3.18 V < 3.6 V = 3.3 V + 0.3 V
(2) Each signal level to input amplitude of CVIN pin is shown in Figure 14.2.
White level
ID1 data
max
A : 140 IRE = CVIN input amplitude
D : 70IRE
CC data
max
B : 50IRE
Pedestal
C : 40IRE
synchronized
chip
Example) When it inputs by 1.75Vpp(s) from CVIN pin, each level becomes the following.
A = 140 IRE = 1.75 V
B = 50 IRE = 1.75 x (50/140) = 0.625 V
C = 40 IRE = 1.75 x (40/140) = 0.5 V
D = 70 IRE = 1.75 x (70/140) = 0.875 V
Figure 14.2 Each signal level to input amplitude of CVIN pin
Note 2 : External each constant shown in Figure 14.1 is an example, and is greatly influenced by video
signal output impedance, substrate capacity, etc. on a system. Evaluate input amplitude and
external each constant perfectly, and determine it.
Notes when not Using Data Slicer
When bit 0 of data slicer control register 1 (address 026016/030016) is “0,” terminate the pins as shown in
Figure 14.3
<When data slicer circuit and timing signal generating circuit is in OFF state>
HLF1/HLF2
Pull-down HLF pin and VHOLD pin to
Vss through a resistor of 5 kΩ or more.
VHOLD1/VHOLD2
VCC1
5 kΩ or more
Pull-up CVIN pin to Vcc through
a resistor of 5 kΩ or more.
CVIN1/CVIN2
Figure 14.3 Termination of data slicer input/output pins when data slicer circuit and timing
generating circuit is in OFF state
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M306V8FJFP
Figures 14.4 and 14.5 the data slicer control registers.
Data slicer control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
Address
When reset
DSC01
DSC11
026016
030016
0016
00 16
Bit symbol
Bit name
Function
0: Stopped (Set at slicer unused)
1: Operating (Set at slicer used)
Selection bit of data slice reference 0: F2
1: F1
voltage generating field
At two lines: CC21, and CCX or ID1 are sliced
(notes 1 and 2)
1: Select F1, normally
At only ID1 is sliced
0/1: Select either (note 3)
525p (480p):When ID1 data slice
X:This bit setting is invalid.
Data slicer and timing signal
generating circuit control bit
DSC010/
DSC110
DSC011/
DSC111
Reference clock source
selection bit
DSC012/
DSC112
Reserved bits
RW
RW
RW
0: Video signal (Set “0”, normally)
1: HSYNC signal
RW
Must always be set to “0”
RW
Notes 1. Selected by addresses 026616, 026B16, 030616 and 030B16 register setting.
2. When ID1 slice is set, addresses 026B16 and 030B16 are need to be set.
3. It is required to superimpose F1 and F2 on the same data.
4. CC21: line 21data of CC format.
CCX: the line data which can be selected by addresses 026616 and 030616 of CC format.
ID1: ID1 format data.
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Figure 14.4 Data slicer control register 1
Data slicer control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
DSC02
DSC12
Address
026116
030116
Function
Bit name
Bit symbol
DSC020/
DSC120
When reset
?0?0??0?2
?0?0??0?2
Caption data latch
completion flag 1
When two lines of CC21 and CCX are sliced,
0: Incompletion of CC21 caption data latch, or no clock run-in.
1: Completion of CC21 caption data latch, and clock run-in.
When only CCX is sliced,
0: Incompletion of CCX caption data latch, or no clock run-in.
1: Completion of CCX caption data latch, and clock run-in.
When only ID1 is sliced,
0: Incompletion of ID1 caption data latch.
1: Completion of ID1 caption data latch.
RW
RO
note: A flag is reset by 0 in falling of vertical synchronized signal.
Reserved bit
Must always be set to “0”
RW
Test bit
Read-only
RO
0: F2
1: F1
RO
DSC023/
DSC123
Field determination flag
(*)This flag is invalid at 026B16 and 030B16 at the time of 525p(480p)
selection.
DSC024/
DSC124
Vertical synchronous signal
(Vsep) generating method
selection bit
0: Method (1)
1: Method (2)
RW
DSC025/
DSC125
V-pulse shape
determination flag
0: Match
1: Mismatch
RO
Reserved bit
Must always be set to “0”
RW
Test bit
Read-only
RO
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Figure 14.5 Data slicer control register 2
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M306V8FJFP
Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync. tip part of the composite video signal input from the CVIN pin. The lowpass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video
signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CVIN pin with a resistor of
hundreds of kiloohms to 1 MΩ. In addition, we recommend to install externally a simple low-pass filter
using a resistor and a capacitor at the CVIN pin (refer to Figure 14.1 and notes).
Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
Set bit 6 and 7 to 11b of ID1 reserved register 0 and 1 (addresses 031C16 and 031D16) show in Fig 14.21.
Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit.
(1) Horizontal synchronous signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync
signal.
(2) Vertical synchronous signal (Vsep)
As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit
4 of the data slicer control register 2 (address 026116/030116).
•Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, a Vsep signal is generated in synchronization with the rising of the timing
signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, it is detected whether a falling of the composite sync signal exits or not in the
“L” level period of the timing signal immediately after this “L” level. If a falling exists, a Vsep
signal is generated in synchronization with the rising of the timing signal (refer to Figure
14.6).
Figure 14.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the
reference clock which the timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the
composite sync signal. As shown in Figure 14.7, when the A level matches the B level, this bit is “0.” In the
case of a mismatch, the bit is “1.”
Composite sync
Bit 5 of
DSC02/DSC12
“L” level width is measured
Timing
signal
0
“L” level period of a timing signal
Composite
sync signal
1
Vsep signal
1
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Figure 14.6 Vsep generating timing (method 2)
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A
B
Figure 14.7 Determination of v-pulse waveform
M306V8FJFP
Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal
frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer
control register 1 (address 026016/030016) to “1.”
The reference clock is the HSYNC signal can be used as a count source instead of the composite sync
signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the
reference clock can be selected by bit 2 of data slicer control register 1 (address 026016/030016).
For the pins HLF, connect a resistor and a capacitor as shown in Figure 14.1 Make the length of wiring
which is connected to these pins as short as possible so that a leakage current may not be generated.
Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and
the timing signal generating circuit are started. In this period, various timing signals, Hsep signals
and Vsep signals become unstable. For this reason, take stabilization time into consideration
when programming.
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M306V8FJFP
Data Slice Line Specification Circuit
(1) Specification of data slice line
This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate
line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their
data. The caption position register (address 026616/030616) is used for each setting (refer to Table
14.1).
The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the
counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate
line, refer to Table 14.1). Figure 14.8 shows the signals in the vertical blanking interval. Figure 14.9
shows the caption position register.
When slice ID1, set bits 0 to 4 of addresses 026616 and 030616 = 10000b.
525p (480p):When ID1 data slice, set up addresses 026616/030616 bit 4-0 = 00001b and the data
clock position register (addresses 026A16 and 030A16) bit 6, and 5 = 01b.
(2) Specification of line to set slice voltage
When slice CC21 and CCX, the reference voltage for slicing (slice voltage) is generated for the clock
run-in pulse in the particular line (refer to Table 14.1). The field to generate slice voltage is specified
by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6,
7 of the caption position register (refer to Table 14.1).
When slice ID1, set bit 6 and 7 of addresses 026616 and 030616 = 00b or 01b.
525p (480p):When ID1 data slice, set up the addresses 026616 and 030616 bit 7 and 6 = 01b.
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer control register 2. This flag change
at the falling edge of Vsep.
525p (480p):When ID1 data slice, this bit setting is invalid.
Vertical blanking interval
Video signal
Composite video
signal
1 appropriate line is set by
the caption position register
Line 21 (fixed)
(when setting line 19)
Vsep
Hsep
Count value to be set in the caption position register (“0F16” in this case)
Hsep
Clock run-in
S
T
B
Composite video
signal
Window for
deteminating
clock-run-in
Figure 14.8 Signals in vertical blanking interval
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C
C
1
C
C
2
..........
C C
C C
15 16
*STB shows start bit.
CC1 to 16 show CC data.
Magnified drawing
M306V8FJFP
Caption position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPS0
CPS1
Address
026616
030616
Bit symbol
When reset
00?000002
00?00000 2
Bit name
CPS00/CPS10 Caption position bits
CPS01/CPS11
CPS02/CPS12
CPS03/CPS13
CPS04/CPS14
CPS05/CPS15 Caption data latch
completion flag 2
Function
RW
Set caption position (CCX or ID1).
For CCX, refer to Table 15.1.
For ID1 slice, set bits 4 to 0 = 10000b (line 20 selection)
When 525p (480p) ID1 data slice,
set up bit 4-0 = 00001b (line 41 selection).
(*) addresses 026A16 and 030A16
bit 6 and 5 = 01b need to be set up.
When two lines of CC21 and CCX are sliced,
0: Incompletion of CCX caption data latch, or no clock run-in.
1: Completion of CCX caption data latch, and clock run-in.
When two lines of CC21 and ID1 are sliced,
0: Incompletion of ID1 caption data latch.
1: Completion of ID1 caption data latch.
This bit is invalid when slice only any one line of CC21,
CCX and ID1.
RW
RW
RW
RW
RW
RO
note: A flag is reset by 0 in rising of vertical synchronized signal.
CPS06/CPS16 Slice line mode
specification bits
CPS07/CPS17
Refer to Table 15.1 at slice CC21 or CCX.
Set bits 6 and 7 = 00b or 01b when ID1 slice.
When 525p (480p) ID1 data slice, set bit 7 and 6 = 01b.
RW
RW
Figure 14.9 Caption position register
Table 14.1 Specification of data slice line
CPS0/CPS1
Field and Line to Generate Slice Voltage
Field and Line to Be Sliced Data
b7
b6
0
0
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 (total 1 line)
0
1
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS0/CPS1
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC01/DSC11
• A line specified by bits 4 to 0 of CPS0/CPS1
(total 1 line) (See note 3)
1
0
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 (total 1 line)
1
1
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
Notes 1: DSC01/DSC11 is data slicer control register 1.
CPS0/CPS1 is caption position register.
2: Set the value of “0016” – “1016” to bits 4 to 0 of CPS0/CPS1.
3: Set the value of “0016” – “1F16” to bits 4 to 0 of CPS0/CPS1.
Slice standard voltage selection register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
Symbol
SBV0
SBV1
Address
26716
30716
Bit symbol
SVB00/SVB10
SVB01/SVB11
When reset
0016
0016
Bit name
Slice standard voltage
selection bit
Reseved bits
Function
b1, b0
0
0
0
1
1
0
1
1
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RW
Standard voltage selection by standard voltage
generating circuit.
Internal absolute standard voltage selection.
CC21 is the voltage by the standard voltage generating
circuit. CCX or ID1 is internal absolute standard voltage
selection.
Do not set
Must be set to “0.”
Figure 14.10 Slice standard voltage selection register
RW
RW
M306V8FJFP
Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating
circuit and the comparator 1 and 2.
(1) Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in
pulse in line specified by the data slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage
current may not be generated.
Note: It takes a few tens of lines to generate slice voltage until the slice voltage becomes stable after
the data slicer is started. In this period, the slice data becomes unstable. For this reason, take
stabilization time into consideration when programming.
(2) Comparator 1
The comparator 1 compares the voltage of the composite video signal with the voltage (reference
voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
(3) Comparator 2
The comparator 2 compares the absolute standard voltage generated inside from the voltage and
power supply voltage of a composite video signal, and converts the composite video signal into a
digital value.
CC Start Bit • ID1 Reference Bit Detection Circuit
This circuit detects a CC start bit • ID1 reference bit at line decided in the data slice line specification
circuit.
In the case of CC start bit
1) Detect a clock run impulse at counting the input pulse of a data slice line.
2) When a clock run impulse is detected, the sampling clock outputted from a timing generating circuit
detects a start bit pattern, and judge CC start bit.
In the case of ID1 reference bit
1) Detect ID1 reference bit all over the window generated after fixed time from Hsep in a timing signal
generating circuit.
Clock Run-in Determination Circuit • ID1 Reference Bit Detection Circuit
Clock run in judging
By counting the number of pulses all over the specific window of a data slice line, it judges that it is clock
run in. When it judges with having no clock run in, the completion flag of a caption data latch is not set to
1. Moreover, the number of standard clocks counted in clock run impulse 1 cycle is stored in the bits 7-3
of a clock run in detection register (addresses 026916/030916).
ID1 reference bit judging
The number of standard clocks counted during fixed of ID1 reference bit is stored in the bits 5-0 of a
standard clock detection register (addresses 026916/the 030C16). Read these bits after generating of
data slicer interruption ("Interrupt Request Generating Circuit").
Clock run-in detection register is shown in Fig. 14.11, standard clock detection register is shown in Fig.
14.12.
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M306V8FJFP
Clock run-in detection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CRD0
CRD1
Bit symbol
Address
026916
030916
Bit name
Test bits
CRD03/CRD13 Clock run-in detection bits
CRD04/CRD14
When reset
00000???2
00000???2
Function
RW
Read-only
RO
Number of reference clocks to
be counted in one clock run-in
pulse period.
RO
RO
CRD05/CRD15
RO
CRD06/CRD16
RO
CRD07/CRD17
RO
Figure 14.11 Clock run-in detection register
Standard clock detection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BCD0
BCD1
Bit symbol
Address
026C16
030C16
When reset
??16
??16
Bit name
BCD00/BCD10 ID1 REF width detection bit
BCD01/BCD11
BCD02/BCD12
BCD03/BCD13
BCD04/BCD14
BCD05/BCD15
Function
The number of standard clocks counted in a fixed
period of ID1 REF.
It is effective, only when "1" is set as the 026C16 and
030C16th bits 0 and ID1 slice function is operating.
Nothing is assigned.
If an attempt to write to these bits, write “0.” The read turns out to be “0.”
RW
RO
–
Figure 14.12 Standard clock detection register
Data Clock Generating Circuit
At the time of CC data slice
It synchronizes with CC start bit detected in CC start bit detection circuit, and a data clock is generated
after the fixed offset set up by the data clock position register (addresses 026A16/030A16). A data clock is
a clock for storing caption data in a caption register. When 16-bit data is stored in a caption register and
judged in a clock run in judging circuit that has clock run in, the completion flag of a caption data latch is
set.
A data clock position register is shown in Fig. 14.13.
At the time of ID1 data slice
The data clock which synchronized with ID1 reference bit is generated. With this data clock, the 6 bit data
of the remaining CRCC is stored in a caption register for 14-bit data among 20-bit data at a CRCC data
register (addresses 026D16/030D16). If 20-bit data is stored in each register, the completion flag of a
caption data latch will be set.
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M306V8FJFP
Data clock position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DPS0
DPS1
Address
026A16
030A16
Bit name
Bit symbol
DPS00/DPS10
DPS01/DPS11
DPS02/DPS12
DPS03/DPS13
When reset
X0000000 2
X0000000 2
Function
RW
Only when CC21 or CCX slice is effective.
Data clock position
set bits
RW
DPS04/DPS14
DPS05/DPS15
Reserved bit
Caption position bit 2
It is effective only at the time of 525p (480p) ID1
slice.
b6 b5
0 1
DPS06/DPS16
RW
Nothing is assigned.
If an attempt to write to this bit, write “0.” The read turns out to be “0.”
Figure 14.13 Data clock position register
Caption Register and CRCC Data Register
The caption data converted into a digital value by the comparator is stored into the caption register and
CRCC data register in synchronization with the data clock. The contents of the stored caption data can be
obtained by reading out the stored caption register and CRCC data register. These registers are reset to
“0” at a falling edge of Vsep. Read out these registers after the occurrence of a data slicer interrupt.
Caption register 1L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C1L0
C1L1
Address
0262 16
0302 16
Bit symbol
C1L00/C1L10
Bit name
Caption data 1L
C1L01/C1L11
C1L02/C1L12
C1L03/C1L13
C1L04/C1L14
C1L05/C1L15
C1L06/C1L16
C1L07/C1L17
Figure 14.14 Caption register 1L
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When reset
?? 16
?? 16
Function
RW
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 16-9 of CC21 is stored in bit 7-0.
0
1
Data 16-9 of CCX is stored in bit 7-0.
1
0
Data 16-9 of CC21 is stored in bit 7-0.
1
1
Data 16-9 of CC21 is stored in bit 7-0.
In the case of ID1 caption
b7, b6
0
0
Data 16-9 of CC21 is stored in bit 7-0.
0
1
Data 14-7 of ID1 is stored in bit 7-0(*).
1
0
Data 16-9 of CC21 is stored in bit 7-0.
1
1
Do not set.
(*)When 525p (480p) ID1 data slice, set it as b7 and b6 = 01b.
The caption data stored also becomes the same.
RO
M306V8FJFP
Caption register 1H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C1H0
C1H1
Address
0263 16
0303 16
Bit symbol
C1H00/C1H10
When reset
?? 16
?? 16
Bit name
Caption data 1H
Function
RW
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 8-1 of CC21 is stored in bit 7-0.
0
1
Data 8-1 of CCX is stored in bit 7-0.
1
0
Data 8-1 of CC21 is stored in bit 7-0.
1
1
Data 8-1 of CC21 is stored in bit 7-0.
C1H01/C1H11
C1H02/C1H12
C1H03/C1H13
RO
In the case of ID1 caption
b7, b6
0
0
Data 8-1 of CC21 is stored in bit 7-0.
0
1
Data 6-1 of ID1 is stored in bit 7-2 (note).
1
0
Data 8-1 of CC21 is stored in bit 7-0.
1
1
Do not set.
Note: The reading value of bits 1 and 0 is unfixed.
525p (480p):When ID1 data slice, set it as b7 and b6 = 01b.
The caption data stored also becomes the same.
C1H04/C1H14
C1H05/C1H15
C1H06/C1H16
C1H07/C1H17
Figure 14.15 Caption register 1H
Caption register 2L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C2L0
C2L1
Address
0264 16
0304 16
Bit symbol
C2L00/C2L10
When reset
?? 16
?? 16
Bit name
Caption data 2L
Function
In the case of CC caption
b7, b6
0
0
Data 16-9 of CCX is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Data 16-9 of CCX is stored in bit 7-0.
C2L01/C2L11
C2L02/C2L12
C2L03/C2L13
C2L04/C2L14
RW
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
RO
In the case of ID1 caption
b7, b6
0
0
Data 14-7 of ID1 is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Do not set.
C2L05/C2L15
C2L06/C2L16
C2L07/C2L17
Figure 14.16 Caption register 2L
Caption register 2H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C2H0
C2H1
Address
0265 16
0305 16
Bit symbol
C2H00/C2H10
Bit name
Caption data 2H
C2H01/C2H11
C2H02/C2H12
C2H03/C2H13
C2H04/C2H14
C2H05/C2H15
C2H06/C2H16
C2H07/C2H17
Figure 14.17 Caption register 2H
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When reset
?? 16
?? 16
Function
RW
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 8-1 of CCX is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Data 8-1 of CCX is stored in bit 7-0.
In the case of ID1 caption
b7, b6
0
0
Data 6-1 of ID1 is stored in bit 7-2 (note).
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Do not set.
Note : The reading value of bits 1 and 0 is unfixed.
RO
M306V8FJFP
CRCC data register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CRC0
CRC1
Bit symbol
Address
026D16
030D16
When reset
00?????? 2
00?????? 2
Bit name
CRC00/CRC10 CRCC data register
CRC01/CRC11
CRC02/CRC12
CRC03/CRC13
CRC04/CRC14
CRC05/CRC15
Function
RW
Data 20-15 of ID1 is stored in bit 5-0.
It is effective, only when "1" is set as the bit 0 of addresses
026B16 and 030B16, and ID1 slice function is operating.
RO
Nothing is assigned.
If an attempt to write to these bits, write “0.” The read turns out to be “0.”
Figure 14.18 CRCC data register
Interrupt Request Generating Circuit
The interrupt requests as shown in Table 14.2 are generated by combination of the following bits; bits 6
and 7 of the caption position register (addresses 026616/030616). Read out the contents of caption data
registers 1 and 2, CRCC data register, clock run-in detection register and standard clock detect register
after the occurrence of a data slicer interrupt request.
Table 14.2 Occurrence sources of Interrupt request
CPS
b7
Occurrence Sources of Interrupt Request at End of Data Slice Line
b6
0
1
0
After slicing line 21
1
After a line specified by bits 4 to 0 of CPS (Note)
0
After slicing line 21
1
After slicing line 21
CPS: Caption position register
Note: When 525p (480p), it becomes the one-line back specified caption position register bits 4 to 0 and
the data clock position register bits 6 and 5.
Data slicer 0 reserved register 1
Data slicer 1 reserved register 1
b7
0
b6
b5
0 0
b4
b3
0 0
b2
b1
0 0
b0
0
Symbol
DR01
DR11
Bit symbol
Address
When reset
026816
030816
0016
0016
Bit name
Reserved bits
Figure 14.19 Data slicer i reserved register 1 (i = 1, 2)
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Description
Must always be set to “0”
RW
RW
M306V8FJFP
ID1 data slice
When data slice ID1, ID1 control register of Fig 14.20 needs to be set.
ID1 control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
IDC0
IDC1
0 1 0 0
Bit symbol
When reset
0016
0016
Address
026B16
030B16
Bit name
Function
IDC00/IDC10
ID1 selection bit
IDC01/IDC11
ID1 limitation slice select bit 0: Set this bit when slice simultaneously with CC21.
1: Set this bit when slice only ID1.
IDC02/IDC12
IDC03/IDC13
IDC04/IDC14
Internal absolute standard
voltage setting bit
RW
0: ID1 slice unused
1: ID1 slice operate
* Must always be set to "0" at ID1 slice unused.
When set to "1", be sure to set bits 4 to 0 = 10000b of
addresses 026616/030616.
525p (480p):When ID1 data slice,
Set up bit 4-0 = 00001b at addresses 026616/030616.
Set bit 6 and 5 = 01b of addresses 026A16/030A16.
RW
b4 b3 b2
1 0 0
Reserved bit
Must always be set to "0."
IDC0b/IDC1b
525i (480i)/525p (480p) Selection bit
0:525i (480i) set up at CC21, CCX, and ID1 slice
0:525p (480p) set up at ID1 slice
Reserved bit
Must always be set to "0."
Figure 14.20 ID1 control register
ID1 reserved register 0 and 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IRSV0
IRSV1
1 1
Bit symbol
Address
031C16
031D16
When reset
0016
0016
Bit name
Function
The register only for read-out
RW
The contents are unfixed when it reads.
RW
IRSV06/IRSV16 Sync slice setting bit
Must always be set to "1."
IRSV07/IRSV17
Figure 14.21 ID1 reserved register
Line 41 at 525p (480p)
Line 20 at 525i (480i)
Hsep
ID1 reference bit
Composite
video signal
I
D
1
I
D
2
I
D
3
• • • • • • •
* ID1 to ID20 shows ID1 data
ID1 reference
detection timing signal
Figure 14.22 ID1 signal in vertial blanking interval
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I
D
19
I
D
20
M306V8FJFP
HSYNC Counter
The synchronous signal counter counts HSYNC from HSYNC count input pins (HC0 and HC1) as a count
source.
The count value in a certain time (T time; 1024 µs, 2048 µs, 4096 µs and 8192 µs) divided system clock
is stored into the 8-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count
value exceeds “FF16,” “FF16” is stored into the latch.
The latch value can be obtained by reading out the HSYNC counter latch (address 027F16). A count
source and count update cycle (T time) are selected by bits 0, 3 and 4 of the HSYNC counter register.
Figure 15.1 shows the HSYNC counter and Figure 15.2 shows the synchronous signal counter block
diagram.
Note: HSYNC counter latch is a register only for read-out.
HSYNC counter register
b7
Symbol
HC
Address
027E16
When reset
XXX00X0016
RW
Bit symbol
Bit name
HCC0
Count source switch bit
0 : HC0 pin input
1 : HC1 pin input
RW
HCC1
Input polarity
switch bit
0:
RW
Function
1:
(Falling edge count)
(Rising edge count)
Nothing is assigned. In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
HCC3
Count freguency
selection bits
b4 b3 <Count freguency>
0 0 : 1024 µs
0 1 : 2048 µs
1 0 : 4096 µs
1 1 : 8192 µs
RW
Nothing is assigned. In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
WO
HCC4
RW
Note: When HC0 and HC1 input are positive polarity (negetive polarity),
HIGH width (LOW width) needs 3 main clock cycles or more of system clock.
Figure 15.1 HSYNC counter register
1024 ∝s
System clock f32
2048 ∝s
Freguency divider
4096 ∝s
HCC3, HCC4
8192 ∝s
HC0
HCC1
HC1
Polarity switch
Reset
8-bit counter
Counter
Latch (8 bits)
HSYNC
counter latch
HCC0
Selection gate : connected to black
side when reset.
Figure 15.2 HSYNC counter block diagram
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Data bus
M306V8FJFP
OSD Functions
Table 16.1 outlines the OSD functions of this microcomputer. This OSD function can display the following:
the block display (32 characters ✕ 16 lines or 42 characters ✕ 16 lines) and the SPRITE display, and can
display the both display at the same time. There are 3 display modes and they are selected by a block unit.
The display modes are selected by block control register i (i = 1 to 16). The features of each display are
described below.
Note: When using OSD function, select “No-division mode” as BCLK operating mode and set the main
clock frequency to f(XIN) = 16 MHz.
Table 16.1 Features of each display style
Display style
Parameter
Block display
CC mode
(Closed caption mode)
OSD mode
(On-screen display mode)
OSDS mode
Number of display characters
16 ✕ 20 dots
12 ✕ 20 dots
8 ✕ 20 dots
4 ✕ 20 dots
16 ✕ 20 dots
(Character display area:
16 ✕ 26 dots)
OSDL
enable mode
OSDL
disable mode
Kinds of character sizes
(See note 1) Pre-divide
ratio (Note)
Dot size
OSDL mode
32 characters ✕ 16 lines/42 characters ✕ 16 lines
Dot structure
Kinds of
character
ROM
OSDP mode
254 kinds
SPRITE display
1 character ✕ 2 lines
24 ✕ 32 dots
16 ✕ 26 dots
32 ✕ 20 dots
254 kinds
126 kinds
2 kinds of RAM font
508 kinds
254 kinds
14 kinds
4 kinds
12 kinds
1TC ✕ 1/2H,
1TC ✕ 1H,
1.5TC ✕ 1/2H,
1.5TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
Attribute
Smooth italic,
under line,
flash
Border
Character font
coloring
1 screen: 8 kinds
(a character unit)
1 screen: 16 kinds
(a character unit)
Character
background
coloring
Max. 512 kinds
Possible
(a character unit, 1 screen: 4
kinds, Max. 512 kinds)
Max. 512 kinds
Possible
(a character unit,1 screen: 16 kinds,
Max. 512 kinds)
Display layer
Layer 1
OSD output (See note 2)
14 kinds
✕ 1, ✕ 2, ✕ 3
✕ 1, ✕ 2
1TC ✕ 1/2H,
1TC ✕ 1H
1TC ✕ 1/2H,
1TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
1TC ✕ 1/2H,
1TC ✕ 1H,
1.5TC ✕ 1/2H,
1.5TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
Possible (a screen unit, max 512 kinds)
Auto solid space function
Triple layer OSD function, Window function, Blank function
Display expansion
(multiline display)
Possible
Notes 1: The character size is specified with dot size and pre-divide ratio (refer to “Dot Size”).
2: As for SPRITE display, OUT2 is not output.
3: As for SPRITE display, the window function does not operate.
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8 kinds
✕ 1, ✕ 2
1TC ✕ 1/2H,
1TC ✕ 1H,
2TC ✕ 1H,
2TC ✕ 2H
1 screen: 16 kinds (a dot unit)
1 screen: 16 kinds
(only specified dots are colored (a dot unit)
by a character unit)
Max. 512 kinds
Max. 512 kinds
Layers 1, 2
Layer 1
Layers 1, 2
Analog R, G, B output (each 8 adjustment levels: 512 colors), Digital OUT1, OUT2 output
Raster coloring
Other function
(See note 3)
CDOSD mode
(Color dot on-screen
display mode)
Layer 3 (with highest priority)
M306V8FJFP
The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be
displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the
block for which display is terminated by software.
Figure 16.1 shows the display-enable fonts for each display style. Figure 16.2 shows the block diagram of
the OSD circuit. Figure 16.3 shows the OSD control register 1. Figure 16.4 shows the block control register i.
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M306V8FJFP
Display Styles
Display-enable Fonts
16 dots
← Blank area
26 dots
CC Mode
← Underline area
← Blank area
16 dots
20 dots
OSDS Mode
20 dots
20 dots
8 dots
*
**
4 dots
**
20 dots
12 dots
20 dots
16 dots
OSDP Mode
* : Character code
fixation
**: Blank font
24 dots
32 dots
OSDL Mode
26 dots
CDOSD Mode
32 dots
20 dots
SPRITE
Figure 16.1 Display-enable fonts for each display style
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M306V8FJFP
Clock for OSD
OSC1 OSC2
HSYNC VSYNC1/2
Control register for OSD
Display
oscillation
circuit
Internally generated clock
OSD control circuit
OSD RAM (SPRITE)
32 dots ✕ 20 dots ✕ 4 planes ✕ 2 lines
SPRITE OSD control register
OSD control register 1
OSD control register 2
Horizontal position register
Clock control register i
I/O polarity control register
OSD control register 3
Raster color register
Top border control register
Bottom border control register
Block control register i
Vertical position register i
Color palette register i
OSD reserved register i
(address 020116)
(address 020216)
(address 020316)
(address 020416)
(addresses 020516, 020B16)
(address 020616)
(address 020716)
(addresses 020916, 020816)
(addresses 020D16, 020C16)
(addresses 020F16, 020E16)
(addresses 021016 to 021F16)
(addresses 022016 to 023F16)
(addresses 024016 to 025B16)
(addresses 020A16, 025D16,
027A16, 027B16, 027C16)
(address 025F16)
(addresses 027116, 027016)
(addresses 027316, 027216)
(addresses 027416 to 027716)
(addresses 027916, 027816)
(address 028016)
(address 028116)
(address 028216)
OSD control register 4
Left border control register
Right border control register
SPRITE vertical position register
SPRITE horizontal position register
Internal oscillation control register 1
Internal oscillation control register 2
Internal oscillation control register 3
Shift register
OSD RAM (See note 1)
19 bits ✕ 32 characters ✕ 16 lines
OSD ROM (character font) (See note 2)
16 dots ✕ 20 dots ✕ 254 characters
24 dots ✕ 32 dots ✕ 254 characters
Shift register
Output circuit
Shift register
R
G
B
OUT1
OUT2
OSD ROM (color dot font)
16 dots ✕ 26 dots ✕ 4 planes ✕
94 characters
Shift register
Data bus
Figure 16.2 Block diagram of OSD circuit
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Notes 1: In 42 character-mode, 19 bits ✕ 42 characters ✕ 16 lines
2: In OSDL disable mode, 16 dots ✕ 20 dots ✕ 762 characters.
M306V8FJFP
OSD control register 1
b7
Symbol
OC1
OC16 .
OC10
OC11
OC12
Address
020216
Bit name
OSD control bit
(See note 1)
Scan mode
selection bit
Border type
selection bit
When reset
0016
Function
RW
0 : All bordered
1 : Shadow bordered (See note 2)
RW
RW
OC13
Flash mode
selection bit
0 : Color signal of character background
part does not flash
1 : Color signal of character background
part flashes
RW
OC14
Automatic solid
space control bit
0 : OFF
1 : ON
RW
OC15
Vertical window/blank
control bit
0 : OFF
1 : ON
RW
OC16
Layer mixing
control bits
(See note 3)
OC17
b7 b6
0 0: Logic sum (OR) of layer 1’s
color and layer 2’s color
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
Notes 1 : When this bit is switched "1" from "0", the display screen remains
unchanged until a rising (falling) of the next VSYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : OUT2 is always ORed, regardless of values of these bits.
Figure 16.3 OSD control register 1
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RW
0 : All-blocks and SPRITE display OFF
1 : All-blocks and SPRITE display ON
0 : Normal scan mode
1 : Bi-scan mode
page 208 of 363
RW
RW
M306V8FJFP
Block control register i
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BCi (i = 1 to 16)
Bit symbol
BCi_0
Address
021016 to 021F16
Bit name
Display mode
selection bits
BCi_1
BCi_2
BCi_3
Dot size
selection bits
Function
b2 b1
0
0
0
0
1
1
1
1
b6
0
0
1
1
0
0
1
1
BCi_6
0
1
0
1
0
1
0
1
Functions
Display OFF
OSDS mode (No bordered)
CC mode
CDOSD mode
OSDP mode (No bordered)
OSDS mode (Bordered)
OSDP mode (Bordered)
OSDL mode
b3 Pre-divide
Dot size
ratio
0
Pre-divide ratio
selection bits
b0
b5 b4
0
BCi_4
BCi_5
When reset
Indeterminate
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
✕ 1
✕ 2
✕3
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1.5Tc ✕ 1/2H (See notes 3, 4)
1.5Tc ✕ 1H (See notes 3, 4)
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
Nothing is assigned. In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit
2: H is HSYNC
3: This character size is available only in Layer 2. At this time, set layer 1’s
pre-divide ratio = ✕ 2, layer 1’s horizontal dot size = 1Tc.
4: In OSDL and OSDP modes, 1.5Tc size cannot be used.
Figure 16.4 Block control register i (i = 1 to 16)
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RW
RW
RW
RW
RW
RW
RW
RW
M306V8FJFP
Triple Layer OSD
Three built-in layers of display screens accommodate triple display of channels, volume, etc., closed
caption, and sprite displays within layers 1 to 3.
The layer to be displayed in each block is selected by bit 0 or 1 of the OSD control register 2 for each
display mode (refer to Figure 16.7). Layer 3 always displays the sprite display.
When the layer 1 block and the layer 2 block overlay, the screen is composed with layer mixing by bit
6 or 7 of the OSD control register 1, as shown in Figure 16.5. Layer 3 always takes display priority of
layers 1 and 2.
Notes 1: When mixing layer 1 and layer 2, note Table 16.2.
2: OSDP mode is always displayed on layer 1. And also, it cannot be overlapped with layer 2’s block.
3: OUT2 is always ORed, regardless of values of bits 6, 7 of the OSD control register 1. And
besides, even when OUT2 (layer 1 and layer 2) overlaps with SPRITE display (layer 3),
OUT2 is output without masking.
Table 16.2 Mixing layer 1 and layer 2
Block
Block in Layer 1
Parameter
Display mode
Block in Layer 2
CC, OSDS/L, CDOSD mode
OSDS/L, CDOSD mode
✕ 1, ✕ 2 (CC mode)
Same as layer 1 (See note)
Pre-divide ratio
✕ 1 to ✕ 3 (OSD, CDOSD mode)
Dot size
1TC ✕ 1/2H, 1TC ✕ 1H
Pre-divide ratio = ✕ 1
Pre-divide ratio = ✕ 2
(CC mode)
1TC ✕ 1/2H
1TC ✕ 1/2H, 1.5TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H, 1.5TC ✕ 1H (See note)
1TC ✕ 1H, 1TC ✕ 1/2H, 2TC ✕ 2H, • Same size as layer 1
3TC ✕ 3H
(OSDS/L, CDOSD mode)
•1.5TC can be selected only when: layer 1’s pre-divide ratio =
✕ 2 AND layer 1’s horizontal dot size = 1TC.
As this time, vertical dot size is the same as layer 1.
Arbitrary
Horizontal display start position
Same position as layer 1
Arbitrary
Vertical display start position
However, when dot size is 2Tc ✕ 2H or 3Tc ✕ 3H, set difference between vertical display position
of layer 1 and that of layer 2 as follows.
•2Tc ✕ 2H: 2H units
•3Tc ✕ 3H: 3H units
Note: In the OSDL mode, 1.5TC size cannot be used.
Note : When layer 1/layer 2 and SPRITE display
overlay each other, only OUT2 in layer 1/layer 2
is output.
SPRITE
Layer 1/layer 2
(except transparent)
Block 9
Block 10
...
Sprite
A
Layer 3
Block 15
Block 16
Block 1
Block 2
...
Layer 2
Block 7
Block 8
SPRITE
R, G, B of layer 1/layer 2
OUT2 of layer 1/layer 2
Layer 1
Figure 16.5 Triple layer OSD
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A'
M306V8FJFP
Display example of layer 1 = “HELLO,” layer 2 = “CH5”
CH5
HELLO
CH5
HELLO
Layer 1’s color has priority
OC17 = “0”, OC16 = “1”
Logical sum (OR) of
layer 1’s color and
layer 2’s color (See note)
OC17 = “0,” OC16 = “0”
CH5
HELLO
Layer 2’s color has priority
OC17 = “1,” OC16 = “0”
Note: The logical sum (OR) of layer mixing is not OR of the color palette registers’ contents
(color), but that of color pallet registers’ numbers (i).
Example) When the logical sum (OR) is performed on the color palettes 1 and 4;
the number 1 (00012) and number 4 (01002) are ORed and it results in the number 5
(01012). That is, the contents (color) of color palette register 5 is output. The color of
color palette register 5 is output in the ORed part, regardless of colors of color palettes
registers 1 and 4.
Figure 16.6 Display example of layer mixing OSD
OSD control register 2
b7 b6
Symbol
OC2
Bit symbol
OC20
Address
020316
When reset
0016
Function
Bit name
Display layer
selection bits
OC21
b1
0
0
1
1
b0
0
1
0
1
Layer 1
Layer 2
CC, OSDS/L/P, CDOSD
CC, OSDS/L/P
CDOSD
CC, OSDP, CDOSD
OSDS/L
CC, OSDP
CDOSD
OSDS/L
RW
RW
OC22
R, G, B signal output 0: Digital output
selection bit
1: Analog output (8 gradations)
RW
OC23
Solid space output bit
RW
1: OUT2 output
OC24
OC25
Horizontal
window/blank control
bit
Window/blank
selection bit 1
(horizontal)
0: OFF
1: ON
RW
0: Horizontal blank function
1: Horizontal window function
RW
OC26
Window/blank
selection bit 2
(vertical)
0: Vertical blank function
1: Vertical window function
RW
OC27
OSD interrupt
request selection bit
0: At completion of layer 1 block display
1: At completion of layer 2 block display
RW
Figure 16.7 OSD control register 2
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RW
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M306V8FJFP
Display Position
The display positions of characters are specified by a block. There are 16 blocks, blocks 1 to 16. Up to 32
characters (32-character mode)/42 characters (42-character mode)/ can be displayed in each block (refer to Memory for OSD).
The display position of each block can be set in both horizontal and vertical directions by software.
The display position in the horizontal direction can be selected for all blocks in common from 256-step
display positions in units of 4 TOSC (TOSC = OSD oscillation cycle).
The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle).
Blocks are displayed in conformance with the following rules:
• When the display position is overlapped with another block in the same layer (Figure 16.8 (b)), a low
block number (1 to 16) is displayed on the front.
• When another block display position appears while one block is displayed in the same layer (Figure 16.8
(c)), the block with a larger set value as the vertical display start position is displayed. However, do not
display block with the dot size of 2TC ✕ 2H or 3TC ✕ 3H during display period (✽) of another block.
✽ In the case of OSDS/P mode block: 20 dots in vertical from the vertical display start position.
✽ In the case of OSDL mode block: 32 dots in vertical from the vertical display start position.
✽ In the case of CC or CDOSD mode block: 26 dots in vertical from the vertical display start position.
HP
VP1
Block 1
VP2
Block 2
VP3
Block 3
(a) Example when each block is separated
HP
VP1 = VP2
Block 1
(Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
HP
VP1
VP2
Block 1
Block 2
(c) Example when block 2 overlaps in process of block 1
Note: VPi (i = 1 to 16) indicates the vertical display start position of display block i.
Figure 16.8 Display position
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M306V8FJFP
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC).
At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising
edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So
interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs
enough time (2 ✕ BCLK cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can
select with the I/O polarity control register (address 020616).
8 ✕ BCLK cycles or more
VSYNC signal input
100 to 200 [ns]
(BCLK = 10 MHz)
62.5 to 125 [ns]
(BCLK = 16 MHz)
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
(Note 2)
HSYNC
signal input
26 ✕ BCLK cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 020616) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of V SYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of HSYNC needs 26 ✕ BCLK cycles or more.
Figure 16.9 Supplement explanation for display position
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M306V8FJFP
The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle))
as values “00216” to “3FF16” in vertical position register i (i = 1 to 16) (addresses 022016 to 023F16). The
vertical position register i is shown in Figure 16.10.
Vertical position register i
(b8)
(b15)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VPi (i = 1 to 16)
Bit symbol
Address
When reset
Even addresses within addresses 022016 to 023F16, Indeterminate
Odd addresses within addresses 022016 to 023F16
Bit name
VPi_9 to VPi_0 Vertical display start
position control bits of
SPRITE font
Function
RW
Vertical display start position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set VPi ≤ “00116,” VPi ≥ “40016.”
Figure 16.10 Vertical position register i (i = 1 to 16)
The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TOSC, TOSC
being OSD oscillation cycle) as values “0016” to “FF16” in bits 0 to 7 of the horizontal position register
(address 020416). The horizontal position register is shown in Figure 16.11.
Horizontal position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HP
Bit symbol
Address
020416
Bit name
HP_7 to HP_0 Horizontal display start
position control bits
Function
Horizontal display start position = 4TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
Note : The setting value synchronizes with the VSYNC.
Figure 16.11 Horizontal position register
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When reset
0016
RW
RW
M306V8FJFP
Note : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs between the horizontal display
start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not
match.
Ordinary, this gap is 1TC regardless of character sizes, however, the gap is 1.5TC only when the
character size is 1.5TC.
HSYNC
1TC
Note 1
Tdef
4TOSC ✕ N
Block 1 (Pre-divide ratio = 1)
1TC
Block 2 (Pre-divide ratio = 2)
1TC
Block 3 (Pre-divide ratio = 3)
1.5TC
Block 4 (Pre-divide ratio = 2, character size = 1.5Tc)
N = Value of horizontal position register (decimal notation)
Tc = OSD clock cycle divided in pre-divide circuit
Tosc = OSD oscillation cycle
Tdef = 50Tosc (When analog RGB output selected: 51Tosc)
Figure 16.12 Notes on horizontal display start position
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M306V8FJFP
Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing
HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source
(internally generated clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the predivide circuit is defined as 1TC.
The dot size is specified by bits 3 to 6 of the block control register.
Refer to Figure 16.4 (the block control register i), refer to Figure 16.15 (the clock control register).
The block diagram of dot size control circuit is shown in Figure 16.13.
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control
register i.
3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal
mode. Refer to “Scan Mode” about the scan mode.
Clock cycle
= 1TC
OSC1
Synchronous
circuit
Internally generated
clock
Cycle✕2
Horizontal dot size
control circuit
Cycle✕3
Pre-divide circuit
Vertical dot size
control circuit
HSYNC
OSD control circuit
Figure 16.13 Block diagram of dot size control circuit
1 dot
1TC
1/2H
1TC
2TC
3TC
Scanning line of F1 (F2)
Scanning line of F2 (F1)
1H
2H
3H
In normal scan mode
Figure 16.14 Definition of dot sizes
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M306V8FJFP
Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 3 types.
• Internally generated clock output by the internal oscillator
• Clock from the LC oscillator supplied from the pin OSC1
• Clock from the ceramic resonator (or the quartz-crystal oscillator) from the pin OSC1
When the clock control register i (i=1-2) is set to choose an internally generated clock for the OSD clock,
use the internal oscillation control register i (i=1-3) to select the oscillation frequency.
Clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0
Symbol
CS1
Bit symbol
Address
020516
When reset
0016
Function
Bit name
RW
CS10
Clock selection bit
0: Internally generated clock
1: OSC1 clock
RW
CS11
OSC1 oscillating mode
selection bits
b2 b1
RW
CS12
Reserved bit
CS14
R, G, B output pin
control bit
0
0
1
1
0: Stopped
1: Do not set.
0: LC oscillating mode
1: Ceramic • quartz-crystal
oscillating mode
RW
Must always be set to “0”
RW
0: Outputs 8 or 2 gray levels from the R, G
and B pins.
1: Converts the 8 gray levels output for
R, G and B each into 3-bit digital quantities
which are output from the respective ports.
RW
Reserved bit
Must always be set to “1”
RW
Reserved bits
Must always be set to “0”
RW
Figure 16.15 Clock control register 1
Clock control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
0
Symbol
CG
Bit symbol
Address
020B16
Bit name
Reserved bit
CS21
Clock adjustment bit
Reserved bits
CS27
Clock devided bit
(Note)
When reset
0016
Function
RW
Must always be set to “0”.
RW
Set the value which is same as CS27.
RW
Must always be set to “0”.
RW
0: Devided in 2
1: No-division
RW
Note: At the time of internal oscillation use for clock display,
set this bit to “0” and set this bit the “1” at the time of ceramic resonator use.
This bit does not function at the time of LC oscillator use.
Figure 16.16 Clock control register 2
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M306V8FJFP
Internally generated clock
Internal oscillator
“0”
OSD control circuit
“10”
LC
Ceramic •
quartz-crystal
OSC1 clock
CS2, CS1
CS0
“1”
“11”
Oscillating mode for OSD
Figure 16.17 Block Diagram of OSD selection circuit
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M306V8FJFP
Internal oscillation control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
DIV0
Address
0280
BIt name
BIt symbol
DIV00
When reset
0016
Reference clock divide bit
Function
RW
Set "001112" or "001102"
DIV01
DIV02
RW
DIV03
DIV04
DIV05
Set "1" at the time of internal oscillation circuit
use, and set "0" at non-uisng.
Reserved bits
Must always be set to "0"
Internal oscillation control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
DIV1
Address
0281
BIt name
BIt symbol
DIV10
DIV11
When reset
0016
Internal oscillation frequency
select bit
Function
RW
Internal oscillation frequency
=n • 4(N+1)/(m+1)(MHz)
N : Values that can be set by DIV16 to DIV10
DIV12
m : Values that can be set by DIV04 to DIV00
DIV13
RW
n : Values set by VCO05/04
DIV14
Set N, m, and n as shown below:
DIV15
N="3B16"–"7F16", m=0616 , n=2 when VCO01="0"
DIV16
N="2716"–"3B16", m=0716 , n=1 when VCO01="1"
Reserved bit
Must always be set to "0"
Internal oscillation control register 3 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol
VCO
Address
0282
When reset
0016
BIt name
BIt symbol
VCO00
Internal oscillator operating bit
VCO01
Internal oscillator operating bit
Function
RW
0 : OFF
1 : ON
0 : Selects oscillator for 30 to 65 MHz
1 : Selects oscillator for 20 to 30 MHz
VCO02
VCO03
Oscillation characteristic switch
bits
VCO05/04
Reserved bits
Must be fixed to (b3, b2)=(0, 0)
Must be fixed to (b5, b4)=(1, 0), When VCO01 is set to "0"
Must be fixed to (b5, b4)=(0, 0), When VCO01 is set to "1"
Must always be set to "0"
Note: Since there is a possibility that jitter may occer, do not access these registers during display.
Figure 16.18 Internal oscillation control register i (i=1 to 3)
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RW
M306V8FJFP
2.16.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined
through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to
Figure 16.20) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where both the horizontal sync signal and
the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined
by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC
control signal (refer to Figure 16.9) in the microcomputer and then comparing this time with the time of the
previous field. When the time is longer than the comparing time, it is regarded as even field. When the
time is shorter, it is regarded as odd field.
The field determination flag changes at a rising edge of VSYNC control signal in the microcomputer .
The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control
register at address 020616). A dot line is specified by bit 6 of the I/O polarity control register (refer to
Figure 16.19).
However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field,
regardless of bit 6.
I/O polarity control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Address
020616
Symbol
POLC
Bit symbol
When reset
8016
Bit name
Function
HSYNC input
polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
RW
POLC1
VSYNC input
polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
RW
POLC2
R, G, B output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
RW
Reserved bit
Must always be set to “0.”
RW
POLC4
OUT1 output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
RW
POLC5
OUT2 output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
RW
POLC6
Display dot line
selection bit
0 :“
“
1 :“
“
POLC7
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” at even field
” at odd field
” at even field
RW
” at odd field
Field determination 0 : Even field
flag
1 : Odd field
Figure 16.19 I/O polarity control register
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RW
POLC0
RO
M306V8FJFP
Both HSYNC signal and VSYNC signal are negative-polarity input
HSYNC
Field
VSYNC and
VSYNC
control
signal
in microcomputer
Upper :
VSYNC signal
(n - 1) field
(Odd-numbered)
Field
Display dot line
determination
selection bit
flag(Note)
Odd
T1
0.5 to 0.1 [µs] at
f(BCLK) = 10 MHz
(n) field
(Even-numbered)
Even
(n + 1) field
(Odd-numbered)
Odd
2 3 4 5
6 7 8 9 10 11 12 13 14 15 16
1 2
Dot line 1
1
Dot line 0
0
Dot line 0
1
Dot line 1
1 (T3 < T2)
T3
1
0
0 (T2 > T1)
T2
Lower :
VSYNC control
signal in
microcomputer
Display dot line
3 4 5
6 7 8 9 10 11 12 13 14 15 16
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSDS mode
24
25
26
CC mode · CDOSD mode
When the display dot line selection bit is “0,”
the “
” font is displayed at even field, the
“
” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in
the microcomputer.
Figure 16.20 Relation between field determination flag and display font
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M306V8FJFP
Memory for OSD
There are 2 types of memory for OSD : OSD ROM (addresses 3000016 to 4FFFF16) used to store character dot data and OSD RAM (addresses 800016 to 8FFF16) used to specify the kinds of display characters, display colors, and SPRITE display. The following describes each type of memory.
(1) ROM for OSD (addresses 3000016 to 4FFFF16)
The dot pattern data for OSD characters is stored in the character font area in the OSD ROM and the
CD font data for OSD characters is stored in the color dot font area in the OSD ROM. To specify the
kinds of the character font and the CD font, it is necessary to write the character code into the OSD
RAM.
For character font, there are the following 2 mode.
• OSDL enable mode
16 ✕ 20-dot font and 24 ✕ 32-dot font
• OSDL disable mode
16 ✕ 20-dot font
The modes are selected by bit 0 of the OSD control register 4 for each screen.
The conditions for each OSDL enable/disable mode are shown in Figure 16.22.
During OSDL enable mode, character codes 00016 through 1FF16 can be used. In this case, the
character codes 00016 through 0FF16 are turned to 16 ✕ 20-dot fonts, whereas the character codes
10016 through 1FF16 are turned to 24 ✕ 32- dot fonts. Of these, however, character codes 0FE16,
0FF16, 10016, and 18016 cannot be used.
During OSDL disable mode, character codes 00016 through 2FF16 can be used. In this case, all
characters are turned to 16 ✕ 20-dots. Of these, however, character codes 0FE16, 0FF16, 10016,
18016, 20016, and 28016 cannot be used.
CD codes 0016 through 7F16 can be used. In this case, all characters are turned to 16 ✕ 26-dot fonts.
Of these, however, CD codes 3F16 and 4016 cannot be used.
OSD control register 4
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
OC4
Bit symbol
OC40
OC41
Address
025F16
Bit name
When reset
XXXXX002
Function
OSDL mode
selection bit
0 : OSDL enable mode
1 : OSDL disable mode
Number of horizontal
display characters
selection bit
0 : 32 characters for each block
(32-character mode)
1 : 42 characters for each block
(42-character mode)
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be “0.”
Figure 16.21 OSD control register 4
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RW
M306V8FJFP
Depending on the relationship of OSDL enable/disable mode, display mode and character code, note the conditions below.
OSDL enable/
disable mode
Display mode
CC
OSDS/P
OSDL
OSDL disable mode
Character size
Character size
Display mode
& character code
Specified
character
code
OSDL enable mode
(Bit 0 of OSD control register 4 = “0”)
(Bit 0 of OSD control register 4 = “1”)
CC
OSDS/P
OSDL
00016
to
0FF16
S
Used
Used
Not used
(See note 3)
Used
Used
Display OFF
10016
to
1FF16
L
Used
(See note 1)
Used
(See note 1)
Used
Used
Used
Display OFF
Used
Display OFF
S
20016
to
27F16
28016
to
2FF16
Not used
(See note 3)
Not used
(See note 3)
30016
to
3FF16
Display OFF
Not used
(See note 3)
16
24
20
Notes 1: Part of 24 ✕ 32 font is displayed.
2: In OSDL disable mode, character
codes “28016” to “2FF16” are used
in OSDS/P mode (no border).
3: As setting this make output of
font data indeterminate, do not use.
However, “3FE16” and “3FF16” can
be used as character codes of
blank font output in OSDP mode.
32
Figure 16.22 Conditions for each OSDL enable/disable mode
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Used
(No border ) Display OFF
(See note 2)
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M306V8FJFP
(2) OSD RAM (OSD RAM for character, addresses 840016 to 8EFF16)
The OSD RAM for character is allocated at addresses 840016 to 8EFF16, and is divided into a display
character code specification part, color code 1 specification part, and color code 2 specification part
for each block. The number of characters for 1 block (32- or 42-character mode) is selected by bit 1 of
the OSD control register 4. Tables 16.3 to 16.7 show the address map.
For example, to display 1 character position (the left edge) in block 1, write the character code in
address 840016, write color code 1 at 840116, and write color code 2 at 848016. The structure of the
OSD RAM is shown in Figure 16.23.
Note : For blocks of the following dot sizes, the 3nth (n = 1 to 14) character is skipped as compared
with ordinary block.
■In OSDL mode: all dot size.
■In OSDS and CDOSD modes of layer 2: 1.5Tc ✕ 1/2H or 1.5Tc ✕ 1H
Accordingly, maximum 22 characters (32-character mode)/28 characters (42-character mode)
are only displayed in 1 block (refer to Fig 16.22). The RAM data for the 3nth character does not
effect the display. Any character data can be stored here. And also, note the following only in
32-character mode. As the character is displayed in the 28th’s character area in 42-character
mode, set ordinarily.
• In OSDS mode
The character is not displayed, and only the left 1/3 part of the 22nd character back
ground is displayed in the 22nd’s character area. When not displaying this background, set transparent for character background color.
• In OSDL mode
Set a blank character or a character of transparent color to the 22nd character.
• In CDOSD mode
The character is not displayed, and color palette color specified by bits 3 to 6 of color
code 1 can be output in the 22nd’s character area (left 1/3 part).
Display
sequence
RAM
address
order
1
2
3
4
5
6
1
2
4
5
7
8
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32
• 1.5Tc size block
• OSDL block
Display
sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RAM
address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
order
Figure 16.23 RAM data for 3rd character (in 32-character mode)
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• 1Tc size block
M306V8FJFP
Table 16.3 Contents of OSD RAM (1st to 32nd character)
Block
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 8
Block 9
Block 10
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
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Character Code Specification
840016
840216
:
843C16
843E16
844016
844216
:
847C16
847E16
850016
850216
:
853C16
853E16
854016
854216
:
857C16
857E16
860016
860216
:
863C16
863E16
864016
864216
:
867C16
867E16
870016
870216
:
873C16
873E16
874016
874216
:
877C16
877E16
880016
880216
:
883C16
883E16
884016
884216
:
887C16
887E16
Color Code 1 Specification
840116
840316
:
843D16
843F16
844116
844316
:
847D16
847F16
850116
850316
:
853D16
853F16
854116
854316
:
857D16
857F16
860116
860316
:
863D16
863F16
864116
864316
:
867D16
867F16
870116
870316
:
873D16
873F16
874116
874316
:
877D16
877F16
880116
880316
:
883D16
883F16
884116
884316
:
887D16
887F16
Color Code 2 Specification
848016
848216
:
84BC16
84BE16
84C016
84C216
:
84FC16
84FE16
858016
858216
:
85BC16
85BE16
85C016
85C216
:
85FC16
85FE16
868016
868216
:
86BC16
86BE16
86C016
86C216
:
86FC16
86FE16
878016
878216
:
87BC16
87BE16
87C016
87C216
:
87FC16
87FE16
888016
888216
:
88BC16
88BE16
88C016
88C216
:
88FC16
88FE16
M306V8FJFP
Table 16.4 Contents of OSD RAM (1st to 32nd character) (continued)
Block
Block 11
Block 12
Block 13
Block 14
Block 15
Block 16
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
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Character Code Specification
890016
890216
:
893C16
893E16
894016
894216
:
897C16
897E16
8A0016
8A0216
:
8A3C16
8A3E16
8A4016
8A4216
:
8A7C16
8A7E16
8B0016
8B0216
:
8B3C16
8B3E16
8B4016
8B4216
:
8B7C16
8B7E16
Color Code 1 Specification
890116
890316
:
893D16
893F16
894116
894316
:
897D16
897F16
8A0116
8A0316
:
8A3D16
8A3F16
8A4116
8A4316
:
8A7D16
8A7F16
8B0116
8B0316
:
8B3D16
8B3F16
8B4116
8B4316
:
8B7D16
8B7F16
Color Code 2 Specification
898016
898216
:
89BC16
89BE16
89C016
89C216
:
89FC16
89FE16
8A8016
8A8216
:
8ABC16
8ABE16
8AC016
8AC216
:
8AFC16
8AFE16
8B8016
8B8216
:
8BBC16
8BBE16
8BC016
8BC216
:
8BF016
8BFE16
M306V8FJFP
Table 16.5 Contents of OSD RAM (33rd to 42nd character)
Block
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
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Character Code Specification
8C0016
8C0216
:
8C0C16
8C0E16
8E0016
8E0216
8C1016
8C1216
:
8C1C16
Color Code 1 Specification
8C0116
8C0316
:
8C0D16
8C0F16
8E0116
8E0316
8C1116
8C1316
:
8C1D16
Color Code 2 Specification
8C8016
8C8216
:
8C8C16
8C8E16
8E8016
8E8216
8C9016
8C9216
:
8C9C16
8C1E16
8E0816
8E0A16
8C2016
8C2216
:
8C1F16
8E0916
8E0B16
8C2116
8C2316
:
8C9E16
8E8816
8E8A16
8CA016
8CA216
:
8C2C16
8C2E16
8E1016
8E1216
8C3016
8C3216
:
8C3C16
8C3E16
8E1816
8E1A16
8C4016
8C4216
:
8C4C16
8C4E16
8E2016
8E2216
8C2D16
8CAC16
8C2F16
8E1116
8E1316
8C3116
8C3316
:
8C3D16
8C3F16
8E1916
8E1B16
8C4116
8C4316
:
8C4D16
8C4F16
8E2116
8E2316
8CAE16
8E9016
8E9216
8CB016
8CB216
:
8CBC16
8CBE16
8E9816
8E9A16
8CC016
8CC216
:
8CCC16
8CCE16
8EA016
8EA216
8C5016
8C5216
:
8C5C16
8C5E16
8E2816
8E2A16
8C6016
8C6216
:
8C6C16
8C5116
8C5316
:
8C5D16
8C5F16
8E2916
8E2B16
8C6116
8C6316
:
8C6D16
8CD016
8CD216
:
8CDC16
8CDE16
8EA816
8EAA16
8CE016
8CE216
:
8CEC16
8C6E16
8E3016
8E3216
8C6F16
8E3116
8E3316
8CEE16
8EB016
8EB216
M306V8FJFP
Table 16.6 Contents of OSD RAM (33rd to 42nd character) (continued)
Block
Block 8
Block 9
Block 10
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
Block 11
Block 12
Block 13
Block 14
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
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Character Code Specification
8C7016
8C7216
:
8C7C16
8C7E16
8E3816
8E3A16
8D0016
8D0216
:
8D0C16
8D0E16
8E4016
8E4216
8D1016
8D1216
:
8D1C16
8D1E16
8E4816
8E4A16
8D2016
8D2216
:
8D2C16
8D2E16
8E5016
8E5216
8D3016
8D3216
:
8D3C16
8D3E16
8E5816
8E5A16
8D4016
8D4216
:
8D4C16
8D4E16
8E6016
8E6216
8D5016
8D5216
:
8D5C16
8D5E16
8E6816
8E6A16
Color Code 1 Specification
8C7116
8C7316
:
8C7D16
8C7F16
8E3916
8E3B16
8D0116
8D0316
:
8D0D16
8D0F16
8E4116
8E4316
8D1116
8D1316
:
8D1D16
8D1F16
8E4916
8E4B16
8D2116
8D2316
:
8D2D16
8D2F16
8E5116
8E5316
8D3116
8D3316
:
8D3D16
8D3F16
8E5916
8E5B16
8D4116
8D4316
:
8D4D16
8D4F16
8E6116
8E6316
8D5116
8D5316
:
8D5D16
8D5F16
8E6916
8E6B16
Color Code 2 Specification
8CF016
8CF216
:
8CFC16
8CFE16
8EB816
8EBA16
8D8016
8D8216
:
8D8C16
8D8E16
8EC016
8EC216
8D9016
8D9216
:
8D9C16
8D9E16
8EC816
8ECA16
8DA016
8DA216
:
8DAC16
8DAE16
8ED016
8ED216
8DB016
8DB216
:
8DBC16
8DBE16
8ED816
8EDA16
8DC016
8DC216
:
8DCC16
8DCE16
8EE016
8EE216
8DD016
8DD216
:
8DDC16
8DDE16
8EE816
8EEA16
M306V8FJFP
Table 16.7 Contents of OSD RAM (33rd to 42nd character) (continued)
Block
Block 15
Block 16
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
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Character Code Specification
8D6016
8D6216
:
8D6C16
8D6E16
8E7016
8E7216
8D7016
8D7216
:
8D7C16
8D7E16
8E7816
8E7A16
Color Code 1 Specification
8D6116
8D6316
:
8D6D16
8D6F16
8E7116
8E7316
8D7116
8D7316
:
8D7D16
8D7F16
8E7916
8E7B16
Color Code 2 Specification
8DE016
8DE216
:
8DEC16
8DEE16
8EF016
8EF216
8DF016
8DF216
:
8DFC16
8DFE16
8EF816
8EFA16
M306V8FJFP
Blocks 1 to 16
b0
b7
C9 RC21 RC20 RC17 RC16 RC15 RC14 RC13 RC12 RC11 C8
C7
b2
b1
b0
b7
Color code 2
C6
C5
Color code 1
C4
C3
C2
C1
C0
Character code
OSDS/L/P mode
CC mode
Bit name
Function
Bit
b0
Bit name
CDOSD mode
Bit name
Function
Function
C0
C1
C2
Character
C3
code
C4
(Low-order 9 bits)
Character
Specify
character code in
code
(Low-order 9 bits)
OSD ROM
C5
CD code
Specify
(7 bits)
character code in
Specify
character code
in
OSD ROM
(color dot)
OSD ROM
C6
C7
C8
Not used
RC11
(See note 3)
Color palette
selection bit 1
Color palette
selection bit 2
RC13
RC16 Underline control 0: Underline OFF
1: Underline ON
RC17
C9
OUT2 output
control
1: OUT2 output ON
Color palette Specify color palette
for background
selection bit 0
(See note 3)
Color palette
selection bit 1
Character background
RC21
Character background
RC20
0: OUT2 output OFF
OUT2 output
control
Color palette Specify color palette
selection bit 0
for character
Color palette
selection bit 1
0: Color palette set 0
1: Color palette set 1
Color palette
selection bit 0
Dot color
1: Flash ON
Character background
0: Flash OFF
Flash control
Color palette
selection bit 4
(See note 3)
Color palette
selection bit 1
Color palette
selection bit 3
1: Italic ON
RC15
Color palette Specify color palette
selection bit 0
for character
Color palette
selection bit 2
0: Italic OFF
Italic control
RC14
Character
Character
RC12
Color palette Specify color palette
selection bit 0
for character
Color palette
selection bit 1
Color palette
selection bit 2
Specify a dot
which selects
color palette 0
by OSD ROM
(See note 4)
(See note 3)
Color palette
selection bit 3
0: OUT2 output OFF
1: OUT2 output ON
OUT2 output
control
0: OUT2 output OFF
1: OUT2 output ON
Color palette Specify color palette
for background
selection bit 2
(See note 3)
Not used
Specify character
code in OSD ROM
Not used
Color palette
selection bit 3
Character code
Specify character Character code
(High-order 1 bit) code in OSD ROM (High-order 1 bit)
Notes 1: Read value of bits 3 to 7 of the color code 2 is undefined.
2: For “not used” bits, the write value is read.
3: Refer to Figure 16.25.
4: Only in CDOSD mode, a dot which selects color palette 0 is colored to the color palette set and color palette by RC13
to RC16 of OSD RAM in character units. When the character size is 1.5TC ✕ 1H or 1.5TC ✕ 1/2H, however, set RCI3
to RC16 and RC17 of all characters (including the 3nth character) within the same block to the same value.
Figure 16.24 Structure of OSD RAM
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M306V8FJFP
(3) OSD RAM (OSD RAM for SPRITE, addresses 800016 to 83E716)
The OSD RAM for SPRITE fonts 1 and 2, consisting of 4 planes for each font, is assigned to addresses 800016 to 83E716. Each plane corresponds to each color palette selection bit and the color
palette of each dot is determined from among 16 kinds.
Table 16.8 OSD RAM address (SPRITE font 1)
Planes
Plane 3
Plane 2
(Color paleltte selection bit 3)
9 to 16
Plane 1
(Color paleltte selection bit 2)
9 to 16
Plane 0
(Color paleltte selection bit 1)
9 to 16
(Color paleltte selection bit 0)
Dots
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24 25 to 32
1 to 8
Bits
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
9 to 16
b7 to b0
17 to 24
25 to 32
Line 1
80C016
80C116
81C016
81C116
808016
808116
818016
818116
804016
804116
814016
814116
800016
800116
810016
810116
Line 2
•
•
•
Line 19
80C216
•
•
•
80E416
80C316
•
•
•
80E516
81C216
•
•
•
81E416
81C316
•
•
•
81E516
808216
•
•
•
80A416
808316
•
•
•
80A516
818216
•
•
•
81A416
818316
•
•
•
81A516
804216
•
•
•
806416
804316
•
•
•
806516
814216
•
•
•
816416
814316
•
•
•
816516
800216
•
•
•
802416
800316
•
•
•
802516
810216
•
•
•
812416
810316
•
•
•
812516
Line 20
80E616
80E716
81E616
81E716
80A616
80A716
81A616
81A716
806616
806716
816616
816716
802616
802716
812616
812716
b7 to b0
Table 16.9 OSD RAM address (SPRITE font 2)
Planes
Plane 3
Plane 2
(Color paleltte selection bit 3)
9 to 16
Plane 1
(Color paleltte selection bit 2)
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24 25 to 32
1 to 8
Bits
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0
Line 1
82C016
82C116
83C016
83C116
828016
828116
838016
838116
824016
824116
834016
834116
820016
820116
830016
830116
Line 2
•
•
•
Line 19
82C216
•
•
•
82E416
82C316
•
•
•
82E516
83C216
•
•
•
83E416
83C316
•
•
•
83E516
828216
•
•
•
82A416
828316
•
•
•
82A516
838216
•
•
•
83A416
838316
•
•
•
83A516
824216
•
•
•
826416
824316
•
•
•
826516
834216
•
•
•
836416
834316
•
•
•
836516
820216
•
•
•
822416
820316
•
•
•
822516
830216
•
•
•
832416
830316
•
•
•
832516
Line 20
82E616
82E716
83E616
83E716
82A616
82A716
83A616
883A716
826616
826716
836616
836716
822616
822716
832616
832716
page 231 of 363
9 to 16
(Color paleltte selection bit 0)
Dots
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9 to 16
Plane 0
(Color paleltte selection bit 1)
9 to 16
17 to 24
25 to 32
b7 to b0
M306V8FJFP
Character Color
As shown in Figure 16.25, there are 16 built-in color codes. Color palette 0 is fixed at transparent, and
color palette 8 is fixed at black. The remaining 14 colors can be set to any of the 512 colors available. The
setting procedure for character colors is as follows:
• CC mode ........................................ 8 kinds
Color palette selection range (color palettes 0 to 7 or 8 to 15) can be selected by bit 0 of the OSD control
register 3 (address 020716). Color palettes are set by bits RC11 to RC13 of the OSD RAM from among
the selection range.
• OSDS/L/P mode ........................... 16 kinds
Color palettes are set by bits RC11 to RC14 of the OSD RAM.
• CDOSD mode ............................... 16 kinds
Color palettes are set in dot units according to CD font data.
Only in CDOSD mode, a dot which selects color palette 0 or 8 is colored to the color palette set by RC13
to RC16 of OSD RAM in character units (refer to Figure 16.25). And, selection of color palette set is
possible by RC12 of OSDRAM.
• SPRITE display ............................ 16 kinds
Color palettes are set in dot units according to the CD font data.
Notes 1: Color palette 8 is always selected for bordering and solid space output (OUT 1 output) regardless
of the set value in the register.
2: Color palette 0 (transparent) and the transparent setting of other color palettes will differ. When
there are multiple layers overlapping (on top of each other, piled up), and the priority layer is color
palette 0 (transparent), the bottom layer is displayed, but if the priority layer is the transparent
setting of any other color palette, the background is displayed without displaying the bottom layer
(refer to Figure 16.27).
Character Background Color
The display area around the characters can be colored in with a character background color. Character
background colors are set in character units.
• CC mode ........................................ 4 kinds
Color palette selection range (color codes 0 to 3, 4 to 7, 8 to 11, or 12 to 15) can be selected by bits 1 and
2 of the OSD control register 3 (address 020716). Color palettes are set by bits RC20 and RC21 of the
OSD RAM from among the selection range.
• OSDS/L/P mode ........................... 16 kinds
Color palettes are set by bits RC15, RC16, RC20, and RC21 of the OSD RAM.
Note: The character background is displayed in the following part:
(character display area) – (character font) – (border).
Accordingly, the character background color and the color signal for these two sections cannot be
mixed.
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M306V8FJFP
CC mode
(background)
CC mode
(character)
Palette set 0
OSDS/L/P mode (character, background)
CDOSD mode (character) (See notes 2 and 3)
SPRITE display
Palette set 1 (possible only CDOSD mode)
Color palette 0 (Transparent)
Color palette 0´(Transparent)
Color palette 1
Color palette 1´
Color palette 2
Color palette 2´
Color palette 3
Color palette 3´
Color palette 4
Color palette 4´
Color palette 5
Color palette 5´
Color palette 6
Color palette 6´
Color palette 7
Color palette 8 (Black)
Color palette 9
Select one
palette in
screen units.
(See note 1)
Select either
palette in
screen units.
(See note 1)
Any palette
can be
selected.
Color palette 7´
Color palette 8´ (Black)
Color palette 9´
Color palette 10
Color palette 10´
Color palette 11
Color palette 11´
Color palette 12
Color palette 12´
Color palette 13
Color palette 13´
Color palette 14
Color palette 14´
Color palette 15
Color palette 15´
Notes 1: Color palettes are selected by OSD control register 3 (address 020716).
2: Only in CDOSD mode, a dot which selects color palette 0 is colored to RC13 to RC16
of OSD RAM in character units.
3: Selection of color palette set is possible only CDOSD mode.
Figure 16.25 Color palette selection
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M306V8FJFP
Dot area specified to color palette 1
Set values of OSD RAM (RC16 to RC13)
0000
0001
0010
Transparent
Black
Blue
Dot area specified to color palette 0
When setting black and blue to color palettes 1 and 2, respectively
(only in CDOSD mode).
Figure 16.26 Set of color palette 0 or 8 in CDOSD mode
Color palette 1 (Transparent)
Layer 1
(CC mode)
26 dots
Color palette 0 (Transparent)
Black
Layer 2
(OSDS/L mode)
20 dots
Color palette 2 (Blue)
26 dots
20 dots
Blue
Transparent
(video signal)
When layer 1 has priority.
Color palette 8 (Black)
Figure 16.27 Difference between color palette 0 (transparent) and transparent setting of other
color palettes
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M306V8FJFP
OSD control register 3
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
OC3
Address
020716
When reset
0016
RW
Bit symbol
OC30
CC mode character
color selection bit
0: Color palettes 0 to 7
1: Color palettes 8 to 15
OC31
CC mode character
background color
selection bits
(See note)
b2
OC32
Reserved bit
0
0
1
1
0: Color palettes 0 to 3
1: Color palettes 4 to 7
0: Color palettes 8 to 11
1: Color palettes 12 to 15
RW
RW
RW
Must always be set to “0”
RW
OC34
Flash cycle
selection bit
0: 1 cycle = VSYNC cycle ✕ 32
1: 1 cycle = VSYNC cycle ✕ 64
RW
OC35
OSD mode
window control bit
0: Window OFF
1: Window ON
RW
OC36
CC mode window
control bit
0: Window OFF
1: Window ON
RW
OC37
CDOSD mode
window control bit
0: Window OFF
1: Window ON
RW
Note: Color palette 8 is always selected for solid space (when OUT1 output is
selected), regardless of value of this register.
Figure 16.28 OSD control register 3
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M306V8FJFP
Color palette register i
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CRi (i = 1 to 7)
CRi (i = 9 to 15)
Bit symbol
Addresses
Even addresses within addresses 024016 to 024D16,
Odd addresses within addresses 024016 to 024D16
Even addresses within addresses 024E16 to 025B16,
Odd addresses within addresses 024E16 to 025B16
Bit name
CRi_2 to CRi_0 R signal output
control bits
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
VSS
1/7V
2/7V
3/7V
4/7V
5/7V
6/7V
7/7V
:
:
:
:
:
:
:
:
VSS
1/7V
2/7V
3/7V
4/7V
5/7V
6/7V
7/7V
:
:
:
:
:
:
:
:
VSS
1/7V
2/7V
3/7V
4/7V
5/7V
6/7V
7/7V
When reset
Indeterminate
Indeterminate
RW
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_6 to CRi_4 G signal output
control bits
b6 b5 b4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_10 to CRi_8 B signal output
control bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_12
OUT1 signal output
control bit
0: No output
1: Output
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note 1: When set up color palette of the palette set 1, set up the color palette register i after setting the bit 6 of an extended register
(address 02D516) as 1.
The color palette register of the palette set 1 cannot be read out.
Figure 16.29 Color palette register i (i = 1 to 7, 9 to 15)
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RW
M306V8FJFP
OUT1, OUT2 Signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of
the OUT1, OUT2 signals is controlled by bit 6 of the color palette register i (refer to Figure 16.29), bits 0
to 2 of the block control register i (refer to Figure 16.4) and RC17 of OSD RAM. The setting values for
controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 16.30.
Conditions
OUT2 output
control
(RC 17 of
OSD RAM)
Border output
(See note 1)
OUT1 signal output control bit
(See note 2)
bit12(CRi12) of color pallet
Output
register i
Background
Character
waveform
0
H
L
1
H
L
0
H
L
1
H
L
0
H
L
1
H
L
0
H
L
1
H
L
H
L
0
No output
1
OUT1
signal
✕
0
Output
(See note 1)
1
0
✕
✕
✕
1
✕
✕
✕
OUT2
signal
H
L
Notes 1: This control is only valid in the OSDS/P mode. It is invalid in CC/CDOSD/OSDL mode .
2: In the CDOSD mode, coloring is performed for each dot. Accordingly, OUT1 outputs to dots
which bit 12 (CRi12) of the color pallet register i is set to “0.”
3: OUT2 cannot be output in sprite OSD.
4: ✕ is an arbitrary value.
Figure 16.30 Setting value for controlling OUT1, OUT2 and corresponding output waveform
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M306V8FJFP
Attribute
The attributes (flash, underline, italic fonts) are controlled to the character font. The attributes to be controlled are different depending on each mode.
CC mode ................... Flash, underline, italic for each character
OSDS/P mode .......... Border (all bordered, shadow bordered can be selected) for each block
(1) Underline
The underline is output at the 23rd and 24th lines in vertical direction only in the CC mode. The
underline is controlled by RC16 of OSD RAM. The color of underline is the same color as that of the
character font.
(2) Flash
The parts of the character font, the underline, and the character background are flashed only in the CC
mode. The flash for each character is controlled by RC15 of OSD RAM. The ON/OFF for flash is
controlled by bit 3 of the OSD control register 1 (refer to Figure 16.3). When this bit is “0,” only
character font and underline flash. When “1,” for a character without solid space output, R, G, B and
OUT1 (all display area) flash, for a character with solid space output, only R, G, and B (all display
area) flash. The flash cycle bases on the VSYNC count and is selected by bit 4 of OSD control register
3.
<NTSC method>
■ When bit 4 = “0”
■ When bit 4 = “1”
· VSYNC cycle ✕ 24 ≈ 400 ms (at flash ON)
· VSYNC cycle ✕ 8 ≈ 133 ms (at flash OFF)
· VSYNC cycle ✕ 48 ≈ 800 ms (at flash ON)
· VSYNC cycle ✕ 8 ≈ 267 ms (at flash OFF)
(3) Italic
The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic
is controlled by RC14 of OSD RAM.
The display example attribute is shown in Figure 16.31. In this case, “R” is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: When a flash character (with flash character background) adjoin on the right side of a non-flash italic
character, parts out of the non-flash italic character is also flashed.
3: OUT2 is not flashed.
4: When the pre-divide ratio = 1, the italic character with slant of 1 dot ✕ 5 steps is displayed ; when the
pre-divide ratio = 2, the italic character with slant of 1/2 dot ✕ 10 steps is displayed (refer to Figure
16.32 (c), (d)).
5: The boundary of character color is displayed in italic. However, the boundary of character background
color is not affected by the italic (refer to Figure 16.32).
6: The adjacent character (one side or both side) to an italic character is displayed in italic even when the
character is not specified to display in italic (refer to Figure 16.32).
7: When displaying the 32nd character (in 32-character mode)/42nd character (in 42-character mode) in
the italic and when solid space is off (OC14 = “0”), parts out of character area is not displayed (refer to
Figure 16.32).
8: When use the italic character which the pre-divide ratio = 1, do not use the character in which dot data
exists for the right end of a font.
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M306V8FJFP
Color code
Color code
Bit 4
Bit 6
(RC 16) (RC 14)
Bit 4
Bit 6
(RC 16) (RC 14)
0
0
1
(a) Ordinary
0
(b) Underline
Color code
Color code
Bit 6
Bit 4
(RC 16) (RC 14)
0
Bit 6
Bit 4
(RC 16) (RC 14)
1
(c) Italic (pre-divide ratio = 1)
0
1
(d) Underline and Italic (pre-divide ratio = 2)
Color code
Bit 4
Bit 5
Bit 6
(RC 16) (RC 15) (RC 14)
flash
flash
flash
ON
OFF
ON
OFF
(e) Underline and Italic and flash
Figure 16.31 Example of attribute display (in CC mode)
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1
1
1
M306V8FJFP
32nd chracter (Note 2)
(Refer to “Attribute Notes 6, 7”)
26th chracter
(Refer to “Attribute Notes 5, 6”)
Bit 4 of color
code 1
1
0
0
Notes 1 : The dotted line is the boundary of character color.
2 : When bit 4 of OSD control register 1 is “0.”
Figure 16.32 Example of italic display
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1
1
0
1
M306V8FJFP
(4) Border
The border is output in the OSDS/P mode. The all bordered (bordering around of character font) and
the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure
16.33) by bit 2 of the OSD control register 1 (refer to Figure 16.3). The ON/OFF switch for borders can
be controlled in block units by bits 0 to 2 of the block control register i (refer to Figure 16.4).
The OUT1 signal is used for border output. The border color is fixed at color palette 8 (block). The
border color for each screen is specified by the border color register i.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of
the character font dot size. However, only when the pre-divide ratio = 2 and character size = 1.5TC, the
horizontal size is 1.5TC. The vertical size (y) different depending on the screen scan mode and the
vertical dot size of character font.
Notes 1 : The border dot area is the shaded area as shown in Figure 16.33.
2 : When the border dot overlaps on the next character font, the character font has priority
(refer to Figure 16.36 A). When the border dot overlaps on the next character back
ground, the border has priority (refer to Figure 16.36 B).
3 : The border in vertical out of character area is not displayed (refer to Figure 16.36).
All bordered
Shadow bordered
Figure 16.33 Example of border display
y
x
Scan mode
Border
dot size
Vertical dot size of
character font
Normal scan mode
1/2H
1/2H
Figure 16.34 Horizontal and vertical size of border
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1/2H, 1H, 2H, 3H
1TC (OSD clock cycle divided in pre-divide circuit)
1.5TC when selecting 1.5TC for character size.
Horizontal size (x)
Vertical size (y)
1H, 2H, 3H
Bi-scan mode
1H
1H
M306V8FJFP
OSDS/P mode
16 dots
12 dots
Character
font area
20 dots
20 dots
Character
font area
1 dot width of border
1 dot width of border
1 dot width of border
Figure 16.35 Border area
Character boundary
B
Figure 16.36 Border priority
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Character boundary
A
Character boundary
B
1 dot width of border
M306V8FJFP
Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area
in the CC mode.
The solid space is output in the following area :
• the character area except character code “00916 ”
•the character area on the left and right sides
This function is turned on and off by bit 4 of the OSD control register 1 (refer to Figure 16.3).
OUT1 or OUT2 output is selected by bit 3 of the OSD control register 2.
Notes 1: When selecting OUT1 as solid space output, character background color with solid space
output is fixed to color palette 8 (black) regardless of setting.
2: When selecting any font except blank font as the character code “00916,” the set font is output.
Table 16.10 Setting for automatic solid space
0
Bit 4 of OSD control register 1
1
0
Bit 3 of OSD control register 2
0
RC17 of OSD RAM
OUT1 output signal
1
1
0
0
•Character font area
•Character background
area
1
0
1
1
•Character font area
•Solid space area
•Character background
area
0
1
•Character font area
•Character background
area
OUT2 output signal
OFF
•Character
display area
OFF
•Character
display area
OFF
•Solid space
•Character
•Solid space •Character
display area
display area
When setting the character code “00516” as the character A, “00616” as the character B.
(OSD RAM)
005 009 009 009 006 006 •
16
16
16
16
16
• •
16
006
16
(Display screen)
• • •
1st
2nd
character character
No solid space
output
Figure 16.37 Display screen example of automatic solid space
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32nd character (in 32-character mode)
42nd character (in 42-character mode)
M306V8FJFP
Particular OSD Mode Block
This function can display with mixing the fonts below within the OSDP mode block.
<horizontal dot structure with vertical dot structure of 20 dots>
• 16 dots
• 12 dots
• 8 dots
• 4 dots
Each font is selected by a character code. Figure 16.38 shows the display example of particular OSD
mode block and Table 16.11 shows the corresponding between character codes and display fonts.
Note: As for 8 ✕ 20-dot and 4 ✕ 20-dot fonts, only these character background color can be displayed.
And also, any character is not displayed on the right side area nor any following areas of these
fonts.
12 dots
16 dots
16 dots
12 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
OSDP mode
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
8 dots
OSDP mode
Any character is not displayed on the right side area nor any following areas of this font.
Figure 16.38 Display example of OSD mode block
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M306V8FJFP
Table 16.11 Corresponding between character codes and display fonts
Character code
Display fonts
Notes
16 dots
(except 10016, 18016,
20016, 28016)
20 dots
00016 to 0EF16,
10016 to 2FF16
12 dots
0F016 to 0FD16
Not displayed
• The left 12-dot part (16 ✕ 12 dots) of set
font is displayed.
20 dots
• In CC and OSDS modes, entire part
(16 ✕ 20 dots) of set font is displayed.
8 dots
• The blank font (only character background)
is displayed.
• Any character is not displayed on the right
side area nor any following areas of this
font.
20 dots
3FE16
• Do not set this font for the 1st character
(left edge) of a block.
4 dots
• The blank font (only character background)
is displayed.
20 dots
3FF16
• Any character is not displayed on the right
side area nor any following areas of this
font.
• Do not set this font for the 1st character
(left edge) of a block.
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M306V8FJFP
Multiline Display
This microcomputer can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different
vertical positions. In addition, it can display up to 16 lines by using OSD1 interrupts.
An OSD1 interrupt request occurs at the point at which display of each block has been completed. In
other words, when a scanning line reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that block starts, and an interrupt occurs at
the point at which the scanning line exceeds the block. The mode in which an OSD1 interrupt occurs is
different depending on the setting of the OSD control register 2 (refer to Figure 16.7).
• When bit 7 of the OSD control register 2 is “0”
An OSD1 interrupt request occurs at the completion of layer 1 block display.
• When bit 7 of the OSD control register 2 is “1”
An OSD1 interrupt request occurs at the completion of layer 2 block display.
Notes 1: An OSD1 interrupt does not occur at the end of display when the block is not displayed. In other
words, if a block is set to off display by the display control bit of the block control register i
(addresses 021016 to 021F16), an OSD1 interrupt request does not occur (refer to Figure 16.39
(A)).
2: When another block display appears while one block is displayed, an OSD1 interrupt request
occurs only once at the end of the another block display (refer to Figure 16.39 (B)).
3: On the screen setting window, an OSD1 interrupt occurs even at the end of the CC mode block
(off display) out of window (refer to Figure 16.39 (C)).
Block 1 (on display)
Block 2 (on display)
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 3 (on display)
Block 1 (on display)
“OSD1 interrupt request”
Block 2 (on display)
“OSD1 interrupt request”
Block 3 (off display)
No
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 4 (on display)
Block 4 (off display)
No
“OSD1 interrupt request”
“OSD1 interrupt request”
On display (OSD1 interrupt request occurs
at the end of block display)
Off display (OSD1 interrupt request does
not occur at the end of block display)
(A)
Block 1
“OSD1 interrupt request”
Block 1
Block 2
No
“OSD1 interrupt request”
Block 2
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 3
“OSD1 interrupt request”
Window
(B)
(C)
Figure 16.39 Note on occurrence of OSD1 interrupt
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M306V8FJFP
SPRITE OSD Function
This is especially suitable for cursor and other displays as its function allows for display in any position,
regardless of the validity of block OSD displays or display positions. SPRITE font consists of 2 characters: SPRITE fonts 1 and 2. Each SPRITE font is a RAM font consisting of 32 horizontal dots ✕ 20 vertical
dots, 4 planes, and 4 bits of data per dot. Each plane has corresponding color palette selection bit, and
16 kinds of color palettes can be selected by the plane bit combination (three bits) for each dot. The color
palette is set in dot units according to the OSD RAM (SPRITE) contents from among the selection range.
It is possible to add arbitrary font data by software as the SPRITE fonts consist of RAM font.
The SPRITE OSD control register can control SPRITE display and dot size. The display position can
also be set independently of the block display by the SPRITE horizontal position registers and the sprite
horizontal vertical position registers. The vertical fonts 1 and 2 can be set independently. OSD2 interrupt
request occurs at each completion of font display. The horizontal position is set in 2048 steps in 2TOSC
units, and the vertical position is set in 1024 steps in 1TH units.
When SPRITE display overlaps with other OSD displays, SPRITE display is always given priority. However, the SPRITE display overlaps with the display which includes OUT2 output, OUT2 in the OSD is
output without masking.
Notes 1: The SPRITE OSD function cannot output OUT2.
2: When using SPRITE OSD, do not set HS ≤ “00316”, HS ≥ “80016.”
3: When using SPRITE OSD, do not set VSi = “00016,” VSi ≥ “40016.”
4: When displaying with SPRITE fonts 1 and 2 overlapped, the SPRITE font with a larger set value
as the vertical display start position is displayed. When the set values of the vertical display
start position are the same, the SPRITE font 1 is displayed.
dot
1
......
dot dot
16 17
......
dot
32
Line 1
......
SPRITE font 1
Video adjustment
Tint
Contrast
Color tone
Picture
Brightness
Line 20
Line 1
–••|••+
–••|••+
–••|••+
–••|••+
–••|••+
......
SPRITE font 2
Example of SPRITE display
Line 20
Example of SPRITE font
Figure 16.40 SPRITE OSD display example
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M306V8FJFP
SPRITE OSD control register
Symbol
SC
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Address
020116
When reset
XXX000002
Bit name
Function
SC0
SPRITE font 1
control bit
0: Do not display
1: Display
SC1
Pre-divide ratio
selection bit
0: Pre-divide ratio 1
1: Pre-divide ratio 2
SC2
Dot size selection
bits
b3
SC3
SC4
SPRITE font 2
control bit
0
0
1
1
b2
0: 1Tc
1: 1Tc
0: 2Tc
1: 2Tc
✕ 1/2H
✕ 1H
✕ 1H
✕ 2H
0: Do not display
1: Display
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit.
2: H is HSYNC
Figure 16.41 SPRITE OSD control register
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RW
RW
M306V8FJFP
SPRITE horizontal position register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HS
Address
027916, 027816
Bit symbol
Bit name
HS10 to HS0
Horizontal display start
position control bits of
SPRITE font
When reset
Indeterminate
Function
RW
Horizontal display start position = 2TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set HS ≤ “00316,” HS ≥ “80016.”
Figure 16.42 SPRITE horizontal position register
SPRITE vertical position register i
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VS1
VS2
Bit symbol
VSi9 to VSi0
Address
027516, 027416
027716, 027616
Bit name
Vertical display start
position control bits of
SPRITE font i (i = 1, 2)
Function
Vertical display start position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set VSi = “00016,” VSi ≥ “40016” (i = 1, 2).
Figure 16.43 SPRITE vertical position register i (i = 1, 2)
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When reset
Indeterminate
Indeterminate
RW
RW
M306V8FJFP
Window Function
The window function can be set windows on-screen and output OSD within only the area where the
window is set.
The ON/OFF for vertical window function is performed by bit 5 of the OSD control register 1 and is used
to select vertical window function or vertical blank function by bit 6 of the OSD control register 2. Accordingly, the vertical window function cannot be used simultaneously with the vertical blank function. The
display mode to validate the window function is selected by bits 5 to 7 of the OSD control register 3. The
top border is set by the top border control register (TBR) and the bottom border is set by the bottom
border control register (BBR).
The ON/OFF for horizontal window function is performed by bit 4 of the OSD control register 2 and is
used interchangeably for the horizontal blank function with bit 5 of the OSD control register 2. Accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function.
The display mode to validate the window function is selected by bits 5 to 7 of the OSD control register 3.
The left border is set by the left border control register (LBR), and the right border is set by the right
border control register (RBR).
Notes 1: Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be
used simultaneously.
2: When the window function is ON by OSD control registers 1 and 2, the window function of
OUT2 is valid in all display mode regardless of setting value of the OSD control register 3 (bits
5 to 7). For example, even when make the window function valid in only CC mode, the function
of OUT2 is valid in OSDS/L/P and CDOSD modes.
3: As for SPRITE display, the window function does not operate.
Left border
of window
Right border
of window
Window
Top border
of window
A B C D E
F
G H
K L
I
CDOSD mode
J
M N O
CC mode
Window
P Q R S T
U V W X Y
OSDS/L/P mode
Screen
Figure 16.44 Example of window function (When CC mode is valid)
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Bottom border
of window
M306V8FJFP
Blank Function
The blank function can output blank (OUT1) area on all sides (vertical and horizontal) of the screen. This
provides the blank signal, wipe function, etc., when outputting a 3 : 4 image on a wide screen.
The ON/OFF for vertical blank function is performed by bit 5 of the OSD control register 1 and is used to
select vertical window function or vertical blank function by bit 6 of the OSD control register 2. Accordingly, the vertical blank function cannot be used simultaneously with the vertical window function. The top
border is set by the top border control register (TBR), and the bottom border is set by the bottom border
control register (BBR), in 1H units.
The ON/OFF for horizontal blank function is performed by bit 4 of the OSD control register 2 and is used
interchangeably for the horizontal window function with bit 5 of the OSD control register 2 . Accordingly,
the horizontal blank function cannot be used simultaneously with the horizontal window function. The left
border is set by the left border control register (LBR) and the right border is set by the right border control
register (RBR), in 4TOSC units.
The OSD output (except raster) in area with blank output is not deleted.
These blank signals are not output in the horizontal/vertical blanking interval.
Notes 1. Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be
used simultaneously.
2. When using the window function, be sure to set “1” to bit 0 of OSD control register 1.
A
OUT1 B
4
A
Blank output
signal in
microcomputer
4
A'
H
OUT1
L
H
B
L
Blank output
signal in
microcomputer
H
A'
L
Output example of horizontal blank
Output example of top and vertical blank
Figure 16.45 Blank output example (when OSD output is B + OUT1)
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L H L H
L H
M306V8FJFP
Top border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBR
Bit symbol
Address
020D16, 020C16
Bit name
When reset
Indeterminate
Function
TBR_9 to TBR_0 Top border control bits
RW
Top border position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set TBR ≤ “00116,” TBR ≥ “40016.”
2 : Set as TBR < BBR.
Figure 16.46 Top border control register
Bottom border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BBR
Bit symbol
Address
020F16, 020E16
Bit name
When reset
Indeterminate
Function
BBR_9 to BBR_0 Bottom border control bits Bottom border position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set BBR ≥ “40016.”
2 : Set as TBR < BBR.
Figure 16.47 Bottom border control register
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RW
RW
M306V8FJFP
Left border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LBR
Bit symbol
Address
027116, 027016
Bit name
When reset
XXXXX000000000012
Function
LBR_10 to LBR_0 Left border control bits
RW
Left border position = 4TOSC ✕ n
RW
(n: setting value, TOSC: OSD oscillation cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set LBR ≤ “00316,” LBR ≥ “80016.”
2 : Set as LBR < RBR.
Figure 16.48 Left border control register
Right border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RBR
Bit symbol
Address
027316, 027216
Bit name
RBR_10 to RBR_0 Right border control bits
Function
Figure 16.49 Right border control register
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RW
Left border position = 4TOSC ✕ n
RW
(n: setting value, TOSC: OSD oscillation cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set RBR ≥ “80016.”
2 : Set as LBR < RBR.
When reset
XXXXX000000000002
M306V8FJFP
Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of
the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 512 raster colors can be
obtained.
When the character color/the character background color overlaps with the raster color, the color (R, G,
B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the
raster color. This ensures that the character color/the character background color is not mixed with the
raster color.
The raster color register is shown in Figure 16.50, the example of raster coloring is shown in Figure 16.51.
Note: Raster is not output to the area which includes blank area.
Raster color register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RC
Bit symbol
RC2 to RC0
Address
020916, 020816
Bit name
R singnal output
control bits
When reset
000016
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
RW
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
RC6 to RC4
G singnal output
control bits
b6 b5 b4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
RC10 to RC8
B singnal output
control bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
RC12
OUT1 singnal output
control bit
0: No output
1: Output
RW
RC13
OUT2 singnal output
control bit
0: No output
1: Output
RW
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Figure 16.50 Raster color register
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M306V8FJFP
: Character color “RED” (R and OUT1)
: Border color “BLACK” (OUT1)
: Background color “MAGENTA” (R, B and OUT1)
: Raster color “BLUE” (B and OUT1)
A'
A
HSYNC
OUT1
Signals
across
A-A'
R
G
B
<At horizontal blank output>
: Character color “RED” (R and OUT1)
: Border color “BLACK” (OUT1)
: Background color “MAGENTA” (R, B and OUT1)
: Raster color “BLUE” (B and OUT1)
: Horizontal blank (OUT1)
A'
A
HSYNC
OUT1
Signals
across
A-A'
R
G
B
Blank control
signal in
microcomputer
Figure 16.51 Example of raster coloring
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M306V8FJFP
Scan Mode
This microcomputer has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the
bi-scan mode, the vertical start display position and the vertical size is two times as compared with the
normal scan mode. The scan mode is selected by bit 1 of the OSD control register 1 (refer to Figure 16.3).
Table 16.12 Setting for scan mode
Scan Mode
Parameter
Bit 1 of OSD control register 1
Vertical display start position
Normal Scan
Bi-Scan
0
1
Value of vertical position register ✕ 1H
Value of vertical position register ✕ 2H
1TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H
1TC ✕ 2H
2TC ✕ 2H
2TC ✕ 4H
3TC ✕ 3H
3TC ✕ 6H
Vertical dot size
R, G, B Signal Output Control
The form of R, G, B signal output is controlled by bit 4 of the clock register and bit 2 of the OSD control
register 2 as the table below.
Table 16.13 R, G, B signal output control
Bit 4 of clock
Bit 2 of OSD
Bit 0 of extended
control register 1
control register 2
register
(address 020516) (address 020316)
0
Form of R, G, B signal output
(address 02D516)
0
1
1
0
0
0
1
Each R, G, B pin outputs 2 values (digital output).
Each R, G, B pin outputs 8 values (analog output). (Note 1)
DIGR0, DIGR1, DIGR2
DIGG0, DIGG1, DIGG2
DIGB0, DIGB1, DIGB2
Each of these pins output two-level values.
(Corresponding to each signal output control bit in color palette
register i)
DIGR0~2 correspond to CRi0~2, respectively.
DIGG0~2 correspond to CRi4~6, respectively.
DIGB0~2 correspond to CRi8~10, respectively.
Note 1: In addition to this, set the ANARGBCLKEN bit (address 02DE16, bit 4) and the RGBRON bit
(address 025D16, bit 6) to “1.”Also, set the ANARGBCAPON bit (address 2DE, bit3) and attach the
capacitor for analog RGB internal operation stability ( 0.47 µF (reference value)) to the CAP pin.
2: To use the OUT1 and OUT2 pin, set the OUT1EN bit (address 02DB16, bit 4) and the OUT2EN bit
(address 02DB16, bit 5) to “1.”
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M306V8FJFP
OSD Reserved Register
OSD reserved register 1
b7
b6
0
b5
b4
b3
0 0 0
b2
b1
0 0
b0
Symbol
Address
When reset
0
OR1
025D16
0016
Bit symbol
Bit name
Description
Reserved bits
Must always be set to “0”
Reserved bit
Must always be set to “0”
RGBRON
Analog RGB output control bit
Reserved bit
RW
RW
0: OFF
1: ON
Must always be set to “0”
Figure 16.52 OSD reserved register 1
OSD reserved register i (i=2, 3, 5)
b7
b6
0
0 0 0 0
b5
b4
b3
b2
b1
0 0
b0
0
Symbol
Address
OR2
OR3
OR5
027C16
027B16
020A 16
Bit symbol
When reset
0016
0016
0016
Bit name
Reserved bits
Description
Must always be set to 0
RW
RW
Figure 16.53 OSD reserved register i (i=2, 3, 5)
OSD reserved register 4
b7
b6
0 0
b5
b4
b3
0 0 0
b2
b1
0 0
b0
0
Symbol
Address
When reset
OR4
027A16
X0000000 2
Bit symbol
Bit name
Reserved bits
Figure 16.54 OSD reserved register 4
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Description
Must always be set to “0”
RW
RW
M306V8FJFP
TEST reserved register 0
b7
b6
0
1 0
b5
b4
b3
b2
b1
0 0
0
0 0
Symbol
IDT0
b0
Bit symbol
Address
026E16
When reset
0016
Bit name
Function
RW
Reserved bits
Must always be set to “0”
RW
Reserved bit
Must always be set to “1”
RW
Reserved bit
Must always be set to “0”
RW
Figure 16.55 TEST reserved register 0
TEST reserved register 1
b7
b6
0 0
b5
b4
b3
0 0 0
b2
b1
0 0
b0
0
Symbol
Address
When reset
IDT1
030E16
0016
Bit symbol
Reserved bits
Figure 16.56 TEST reserved register 1
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Bit name
Description
Must always be set to “0”
RW
RW
M306V8FJFP
TB0IN noise filter
The noise filter is built in the input of a TB0IN pin. ON/OFF of a noise filter and selection of a filter clock are
performed in the bit 2 to bit 4 of extended register 1D.
Peripheral mode register
b7
b6
b5
b4
b3
b2
1 0 0
b1
b0
Symbpl
PM
Bit symbol
Address
027D16
After reset
000XXXXX2
Bit name
Function
RW
W
Reserved bit
Must be set to "0".
RW
Reserved bit
Must be set to "0".
RW
Reserved bit
Must be set to "1".
RW
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be Indeterminate.
Figure 16.57 Peripheral mode register
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M306V8FJFP
Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 75 lines P0 to
P10. Each port can be set for input or output every line by using a direction register, and can also be chosen
to be or not be pulled high every 4 lines.
Figures 17.1 to 17.5 show the I/O ports. Figure 17.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output, or a bus control pin.
(1) Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 17.7 shows the PDi registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
No direction register bit for P85 is available.
(2) Port Pi Register (Pi Register, i = 0 to 10)
Figure 17.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register,
and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. The bits in the Pi register correspond one for one to each port.
During memory extension and microprocessor modes, the PDi registers for the pins functioning as bus
_______
_______ _______ _________ ______ __________________
_________ _________ _________
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
(3) Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)
Figure 17.10 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high
in 4 bit units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
However, the pull-up control register has no effect on P0 to P3, P40 to P43, and P5 during memory
extension and microprocessor modes. Although the register contents can be modified, no pull-up resistors are connected.
(4) Port Control Register (PCR Register)
Figure 17.11 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch
can be read no matter how the PD1 register is set.
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M306V8FJFP
Pull-up selection
Direction register
P04 to P07, P24 to P27
P00 to P03, P20 to P23,
P30 to P37, P40 to P47,
P50 to P54, P56,
(inside dotted-line
included)
Data bus
Port latch
(inside dotted-line
not included)
(Note)
Analog input
Pull-up selection
Direction register
P10 to P14, P16, P17,
Port P1 control register
Data bus
Port latch
(Note)
Pull-up selection
Direction register
P15
Port P1 control register
Data bus
Port latch
(Note)
Input to respective peripheral functions
Pull-up selection
Direction
register
P57, P60, P64, P73 to P76, P90
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.1. I/O Ports (1)
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M306V8FJFP
Pull-up selection
Direction
register
P61, P65, P72
"1"
Output
Data bus
Port latch
Switching
between
CMOS and
Nch
(Note)
Input to respective peripheral functions
Pull-up selection
P82 to P83
Direction register
Port latch
Data bus
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P77, P91
Data bus
Port latch
(Note)
Input to respective peripheral functions
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.2. I/O Ports (2)
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M306V8FJFP
Pull-up selection
Direction register
P62, P66
Port latch
Data bus
(Note 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
“1”
Data bus
Port latch
Output
(Note 1)
Switching between CMOS and Nch
Direction register
P70, P71
“1”
Output
Data bus
Port latch
(Note 2)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2:
symbolizes a parasitic diode.
Figure 17.3. I/O Ports (3)
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M306V8FJFP
Pull-up selection
P103
(inside dotted-line
not included)
P104 to P107
(inside dotted-line
included)
Direction register
Data bus
Port latch
(Note)
Analog input
Input to respective peripheral functions
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Figure 17.4. I/O Ports (4)
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M306V8FJFP
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Rd
Direction register
P86
"1"
Data bus
Port latch
Output
(Note)
R/DIGR0, G/DIGG0, B/DIGB0
DIGR1, DIGG1, DIGB1
DIGR2,DIGG2,DIGB2
OUT1,OUT2,OSCOUT
Internal circuit
VCCI
Analog RGB controller
Internal circuit
(Note)
(Note)
SCL4,SDA4,SCL5,SDA5,SCL6,SDA6
Output
Input
HSYNC
(Note)
Input
CVIN1,VHOLD1,HLF1
CVIN2,VHOLD2,HLF2
Analog I/O
(Note)
Note:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Figure 17.5. I/O Ports (5)
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(Note)
M306V8FJFP
(Note 2)
BYTE
BYTE signal input
(Note 1)
(Note 2)
CNVSS1, CNVSS2
signal input
(Note 1)
RESET
RESET signal input
(Note 1)
HSYNC
VSYNC
signal input
(Note 1)
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Note 2: A parasitic diode on the VCC side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed VCC.
Figure 17.6. I/O Pins
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M306V8FJFP
Port Pi direction register (i=0 to 7) (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PD0 to PD3
PD4 to PD7
Bit symbol
Address
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03EE16, 03EF16
Bit name
PDi_0
PDi_1
Port Pi0 direction bit
Port Pi1 direction bit
PDi_2
Port Pi2 direction bit
PDi_3
Port Pi3 direction bit
PDi_4
Port Pi4 direction bit
PDi_5
Port Pi5 direction bit
PDi_6
PDi_7
Port Pi6 direction bit
Port Pi7 direction bit
After reset
0016
0016
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: During memory extension and microprocessor modes, the PD register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Port P8 direction register
b7
b6
b5
b4
b3
b2
0
b1
b0
Address
03F216
Symbol
0 0
PD8
Bit symbol
Bit name
(b1,b0)
Reserved bit
PD8_2
Port P82 direction bit
PD8_3
Port P83 direction bit
After reset
00X000002
Function
Must be set to “0”.
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(b5)
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
Port P86 direction bit
PD8_7
Port P87 direction bit
RW
RW
RW
(b4)
Reserved bit
PD8_6
RW
RW
Must be set to “0”.
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
Port P9 direction register
b7
b6
b5
b4
b3
b2
b1
b0
Address
03F316
Symbol
0 0 0 0 0 0
PD9
Bit symbol
PD9_0
Bit name
Port P90 direction bit
PD9_1
Port P91 direction bit
(b7-b2)
Reserved bit
After reset
0016
RW
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Must be set to “0”.
RW
RW
RW
Note: PD9 register should write PRC2 bit of PRCR register by the next command set to “1” (write-in permitted.)
Port P10 direction register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
Address
03F616
PD10
Bit symbol
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1 1 1 1 1 1
Function
(b2-b0)
PD10_3
Reserved bit
Must be set to “0”.
Port P103 direction bit
PD10_4
Port P104 direction bit
PD10_5
Port P105 direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
PD10_6
Port P106 direction bit
PD10_7
Port P107 direction bit
Symbol
RSVREG03F7
RSVREG03FA
RSVREG03FB
Bit symbol
(b7-b0)
Figure 17.7. PD0 to PD10 Registers
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REJ03B0082-0131
Bit name
After reset
0016
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Address
03F716, 03FA16, 03FB16
Bit name
Reserved bit
Function
Must be set to “1”.
RW
RW
RW
RW
RW
RW
RW
After reset
0016
RW
RW
M306V8FJFP
Port Pi register (i=0 to 7) (Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P0 to P3
P4 to P7
Address
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03EC16, 03ED16
Bit symbol
Bit name
Pi_0
Port Pi0 bit
Pi_1
Pi_2
Port Pi1 bit
Port Pi2 bit
Pi_3
Port Pi3 bit
Pi_4
Port Pi4 bit
Pi_5
Port Pi5 bit
Pi_6
Port Pi6 bit
Pi_7
Port Pi7 bit
After reset
Indeterminate
Indeterminate
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Note 2: During memory extension and microprocessor modes, the Pi register for the pins
functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE,
ALE, RDY, HOLD, HLDA and BCLK) cannot be modified.
Port P8 register
b7
b6
b5
b4
b3
b2
0 0
b1
b0
0 0
Symbol
P8
Address
03F016
Bit symbol
After reset
Indeterminate
Bit name
(b5-b4, b1-b0)
Reserved bit
P8_2
Port P82 bit
P8_3
Port P83 bit
P8_6
Port P86 bit
P8_7
Port P87 bit
Function
Must be set to "0".
The pin level on any I/O port which is set for input mode can
be read by reading the corresponding bit in this register.
The pin level on any I/O port which is set for output mode
can be controlled by writing to the corresponding bit in this
register
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
RW
Port P9 register
b7
b6
0 0
b5
b4
0 0
b3
b2
b1
b0
0 0
Symbol
P9
Address
03F116
Bit symbol
After reset
Indeterminate
Bit name
P9_0
Port P90 bit
P9_1
Port P91 bit
(b7-b2)
Reserved bit
Function
The pin level on any I/O port which is set for input mode can
be read by reading the corresponding bit in this register.
The pin level on any I/O port which is set for output mode
can be controlled by writing to the corresponding bit in this
register
0 : “L” level
1 : “H” level
Must be set to "0".
RW
RW
RW
RW
Port P10 register
b7
b6
b5
b4
b3
b2
b1
0
0 0
b0
Symbol
P10
Address
03F416
Bit symbol
(b7-b2)
Reserved register
b7
b6
b5
0 0 0
b4
b3
b2
0 0 0
b1
b0
0 0
Bit name
Must be set to "0".
The pin level on any I/O port which is set for
input mode can be read by reading the
corresponding bit in this register.
The pin level on any I/O port which is set for
output mode can be controlled by writing to the
corresponding bit in this register
0 : “L” level
1 : “H” level
P10_3
Port Pi1 bit
Port Pi2 bit
P10_5
Port Pi3 bit
P10_6
P10_7
Port Pi4 bit
Port Pi5 bit
Symbol
RSVREG03F5
RSVREG03F8
RSVREG03F9
Bit symbol
Address
03F516, 03F816, 03F916
Bit name
Reserved bit
Figure 17.8. P0 to P10 Registers
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REJ03B0082-0131
Function
Reserved bit
P10_4
(b7-b2)
After reset
Indeterminate
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RW
RW
RW
RW
RW
RW
RW
After reset
Indeterminate
Function
Must be set to "0".
RW
RW
M306V8FJFP
Pull-up control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FC16
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
After reset
0016
Function
0 : Not pulled high
1 : Pulled high (Note 2)
PU07
P34 to P37 pull-up
Note 1: During memory extension and microprocessor modes, the pins are not pulled high although their
corresponding register contents can be modified.
Note 2: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
RW
RW
RW
RW
RW
RW
RW
RW
RW
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
PU10
Address
03FD16
Bit name
P40 to P43 pull-up (Note 2)
PU11
P44 to P47 pull-up (Note 4)
PU12
P50 to P53 pull-up (Note 2)
PU13
P54 to P57 pull-up (Note 2)
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
PU16
P72 to P73 pull-up (Note 1)
After reset(Note 5)
000000002
000000102
Function
0 : Not pulled high
1 : Pulled high (Note 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
PU17
P74 to P77 pull-up
Note 1: The P70 and P71 pins do not have pull-ups.
Note 2: During memory extension and microprocessor modes, the pins are not pulled high although the contents
of this bit can be modified.
Note 3: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Note 4: If the PM01 to PM00 bits are set to “012” (memory expansion mode) or “112” (microprocessor mode) in a
program during single-chip mode, the PU11 bit becomes “1”.
Note 5: The values after hardware reset 1 and 2 are as follows:
• 000000002 when input on CNVss1 pin is “L“
• 000000102 when input on CNVss1 pin is “H“
The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows:
• 000000002 when PM 01 to PM00 bits of PM0 register are “002“ (single-chip mode)
• 000000102 when PM 01 to PM00 bits of PM0 register are “012“ (memory expansion mode) or
“112“ (microprocessor mode)
Pull-up control register 2
b7
b6
b5
b4
b3
b2
0 0
b1
b0
Symbol
PUR2
Bit symbol
PU20
Address
03FE16
Bit name
P80 to P83 pull-up
After reset
0016
Function
PU21
P84 to P87 pull-up (Note 2)
0 : Not pulled high
1 : Pulled high (Note 1)
(b3-b2)
PU24
Reserved bit
Must be set to "0".
P103 pull-up
PU25
P104 to P107 pull-up
0 : Not pulled high
1 : Pulled high (Note 1)
(b7-b6)
Nothing is assigned. In an attempt to write to these bits, write
“0”. The value, if read, turns out to be “0”.
Note 1: The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.
Figure 17.9. PUR0 to PUR2 Registers
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RW
RW
RW
RW
RW
RW
M306V8FJFP
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Bit symbol
PCR0
Address
03FF16
Bit name
Port P1 control bit
After reset
0016
Function
Nothing is assigned. In an attempt to write to these bits,
(b7-b1)
Figure 17.10. PCR Register
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RW
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17
RW
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
write “0”. The value, if read, turns out to be “0”.
M306V8FJFP
Table 17.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
Ports P0 to P10
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1)
XOUT (Note 2)
Open
BYTE
Connect to VSS
Note 1: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 2: With external clock input to XIN pin.
Table 17.2. Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin name
Connection
Ports P6 to P10
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2)
P45 / CS1 to P47 / CS3
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
corresponding direction bit for CSi (i=1 to 3) to “0” (input mode) and the CSR
register’s CSi bit to “0” (chip select disabled).
BHE, ALE, HLDA, XOUT(Note 3),
BCLK (Note 4)
Open
HOLD, RDY
Connect via resistor to VCC2 (pull-up)
Note 1: If the CNVSS1 pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become
indeterminate, causing the power supply current to increase while they remain set for input ports.
Note 2: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 3: With external clock input to XIN pin.
Note 4: If the PM07 bit in the PM0 register is set to “1” (BCLK output is not carried out), connect this pin to VCC via a
resistor (pulled high).
Microcomputer
Microcomputer
Port P6 to P10
Port P0 to P10
(Input mode)
·
·
·
(Input mode)
(Input mode)
·
·
·
(Input mode)
··
·
(Output mode)
Open
XOUT
Open
(Output mode)
Port P45 / CS1
to P47 / CS3
BHE
HLDA
ALE
XOUT
BCLK (Note)
··
·
Open
Open
VCC
HOLD
BYTE
RDY
VSS
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Note: When PM07 bit of PM0 register is set to “1” (BCLK output is not carried out) please connect with VCC
through register (pull-up).
Figure 17.11. Unassigned Pins Handling
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M306V8FJFP
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbpl
RSVREG026F
Bit symbol
(b0)
(b7-b1)
Address
026F16
After reset
XXXXXXX02
Bit name
Reserved bit
Function
Must be set to “0”.
RW
RW
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbpl
RSVREG030F
Bit symbol
(b0)
(b7-b1)
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Address
030F16
Bit name
Reserved bit
After reset
XXXXXXX02
Function
Must be set to “0”.
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
RW
RW
M306V8FJFP
Reserved register
b7
b0
Symbpl
RSVREG0342
Bit symbol
(b7-b0)
Address
034216
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG0343
Bit symbol
(b7-b0)
Address
034316
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG0344
Bit symbol
(b7-b0)
Address
034416
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG0345
Bit symbol
(b7-b0)
Address
034516
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG0346
Bit symbol
(b7-b0)
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Address
034616
Bit name
Reserved bit
After reset
Indeterminate
Function
Setup is arbitrary.
RW
WO
M306V8FJFP
Reserved register
b7
b0
Symbpl
RSVREG0347
Bit symbol
(b7-b0)
Address
034716
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
RSVREG0348
After reset
0016
Bit name
Bit symbol
(b7-b0)
Address
034816
Reserved bit
Function
Must be set to "0".
RW
RW
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
RSVREG0349
Bit symbol
(b7-b0)
Address
034916
After reset
0016
Bit name
Reserved bit
Function
Must be set to "0".
RW
RW
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbpl
RSVREG034A
RSVREG034B
Bit symbol
Address
034A16
034B16
Bit name
After reset
0016
0016
Function
(b5-b0)
Reserved bit
(b7-b6)
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
Must be set to “0”.
RW
RW
Reserved register
b7
b0
Symbpl
RSVREG034C
Bit symbol
(b7-b0)
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Address
034C16
Bit name
Reserved bit
After reset
Indeterminate
Function
Setup is arbitrary.
RW
WO
M306V8FJFP
Reserved register
b7
b0
Symbpl
RSVREG03BC
Bit symbol
(b7-b0)
Address
03BC16
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG03BD
Bit symbol
(b7-b0)
Address
03BD16
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG03BE
Bit symbol
(b7-b0)
Address
03BE16
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG03C0
Bit symbol
(b7-b0)
Address
03C016
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
RO
Reserved register
b7
b0
Symbpl
RSVREG03C1
Bit symbol
(b7-b0)
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Address
03C116
Bit name
Reserved bit
After reset
Indeterminate
Function
Setup is arbitrary.
RW
RO
M306V8FJFP
Reserved register
b7
b0
Symbpl
RSVREG03C2
Bit symbol
(b7-b0)
Address
03C216
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
RO
Reserved register
b7
b0
Symbpl
RSVREG03C3
Bit symbol
(b7-b0)
Address
03C316
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
RO
Reserved register
b7
b0
Symbpl
RSVREG03C4
Bit symbol
(b7-b0)
Address
03C416
After reset
Indeterminate
Bit name
Reserved bit
Function
Setup is arbitrary.
RW
RO
Reserved register
b7
b0
Symbpl
RSVREG03C5
Bit symbol
(b7-b0)
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Address
03C516
Bit name
Reserved bit
After reset
Indeterminate
Function
Setup is arbitrary.
RW
RO
M306V8FJFP
Reserved register
b7
b6
b5
b4
b3
b2
1 1
b1
b0
0 0
Symbpl
RSVREG03DE
Bit symbol
(b1-b0)
(b3-b2)
Address
03DE16
After reset
XX00XXXX2
Bit name
Reserved bits
Function
Must be set to "0".
RW
RW
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be indeterminate.
(b5-b4)
Reserved bits
Must be set to "1".
(b7-b6)
Nothing is assigned. In an attempt to write to these bits,
RW
write “0”. The value, if read, turns out to be indeterminate.
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
1 0 0 0 0 0 0 0
Symbpl
RSVREG03DF
Bit symbol
(b6-b0)
(b7)
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Address
03DF16
Bit name
After reset
0016
Function
RW
Reserved bits
Must be set to "0".
RW
Reserved bit
Must be set to "1".
RW
M306V8FJFP
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
RSVREG034D
Bit symbol
Address
034D16
After reset
Indeterminate
Bit name
Function
Setup is arbitrary.
(b3-b0)
Reserved bit
(b7-b4)
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be .Indeterminate
RW
WO
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
RSVREG039E
Bit symbol
Address
039E16
After reset
XXXXXX002
Bit name
Function
Must be set to “0”.
(b1-b0)
Reserved bit
(b7-b2)
Nothing is assigned. In an attempt to write to these bits,
write “0”. The value, if read, turns out to be “0”.
RW
RW
Reserved register
b7
b6
0 1
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbpl
RSVREG0362
RSVREG0366
Bit symbol
Address
036216
036616
Bit name
After reset
010000002
010000002
Function
RW
(b5-b0)
Reserved bit
Must be set to “0”.
RW
(b6)
Reserved bit
Must be set to “1”.
RW
(b7)
Reserved bit
Must be set to “0”.
RW
Reserved register
b7
b0
Symbpl
RSVREG0363
RSVREG0367
Bit symbol
(b0)
Address
036316
036716
Bit name
Reserved bit
After reset
Indeterminate
Indeterminate
Function
Setup is arbitrary.
RW
WO
Reserved register
b7
b0
Symbpl
RSVREG0360
RSVREG0364
Bit symbol
(b0)
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Address
036016
036416
Bit name
Reserved bit
After reset
Indeterminate
Indeterminate
Function
Setup is arbitrary.
RW
RW
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
( EXTREG02C0 )
Bit symbol
Address
( 02C016 )
After reset
( 0016 )
Bit
name
Function
IREQSELSIG0 Interrupt DMA factor selection
IREQSELSIG1 Interrupt DMA factor selection
IREQSELSIG2 Interrupt DMA factor selection
0 : TIMERA0
1 : I2C-bus0
0 : TIMERA1
1 : I2C-bus1
0 : TIMERA2
1 : OSD2
IREQSELSIG3 Interrupt DMA factor selection
0 : TIMERA3
1 : VSYNC
IREQSELSIG4 Interrupt DMA factor selection
0 : TIMERA4
1 : I2C-bus0NACK
IREQSELSIG5 Interrupt DMA factor selection
0 : TIMERB0
1 : I2C-bus1NACK
IREQSELSIG6 Interrupt DMA factor selection
IREQSELSIG7 Interrupt DMA factor selection
R
W
0 : TIMERB1
1 : I2C-bus2NACK
0 : TIMERB2
1 : I2C-bus2
Extended register
b7
b6
b5
b4
b3
b2
1 1
b1
b0
Symbpl
( EXTREG02C1 )
Bit symbol
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
Address
( 02C116 )
After reset
( 0016 )
Bit
name
Function
IREQSELSIG8
Interrupt DMA factor selection
0 : TIMERB3
1 : Do not set
IREQSELSIG9
Interrupt DMA factor selection
0 : TIMERB4
1 : Do not set
IREQSELSIG10 Interrupt DMA factor selection
0 : TIMERB5
1 : OSD1
IREQSELSIGA1 Interrupt factor selection
0 : UART2 bus shock detection
1 : I2C-bus0
Reserved bit
Must be set to "1".
Reserved bit
Must be set to "1".
IREQSELSIGA4 Interrupt DMA factor selection
0 : Key input
1 : VSYNC
IREQSELSIGA5 Interrupt DMA factor selection
0 : AD
1 : I2C-bus1NACK
page 279 of 363
R
W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0
Symbpl
( EXTREG02C2 )
Bit symbol
Address
( 02C216 )
After reset
( 0016 )
Bit name
Function
IREQSELSIGA6 Interrupt DMA factor selection
Reserved bit
R W
0 : INT2
1 : OSD2
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C3 )
Bit symbol
Reserved bit
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REJ03B0082-0131
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Address
( 02C316 )
Bit name
Must be set to "0".
After reset
( 0016 )
Function
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C4 )
Bit symbol
Reserved bit
Address
( 02C416 )
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C5 )
Bit symbol
Reserved bit
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REJ03B0082-0131
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Address
( 02C516 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C6 )
Bit symbol
Reserved bit
Address
( 02C616 )
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C7 )
Bit symbol
Reserved bit
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REJ03B0082-0131
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Address
( 02C716 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C8 )
Bit symbol
Reserved bit
Address
( 02C816 )
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02C9 )
Bit symbol
Reserved bit
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REJ03B0082-0131
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Address
( 02C916 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02CA ) ( 02CA16 )
Bit symbol
Reserved bit
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02CB ) ( 02CB16 )
Bit symbol
Reserved bit
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REJ03B0082-0131
page 284 of 363
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02CC ) ( 02CC16 )
Bit symbol
Reserved bit
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02CD ) ( 02CD16 )
Bit symbol
Reserved bit
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REJ03B0082-0131
page 285 of 363
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02CE ) ( 02CE16 )
Bit symbol
Reserved bit
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02CF )
Bit symbol
Reserved bit
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REJ03B0082-0131
page 286 of 363
Address
( 02CF16 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02D0 )
Bit symbol
Reserved bit
Address
( 02D016 )
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02D1 )
Bit symbol
Reserved bit
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REJ03B0082-0131
page 287 of 363
Address
( 02D116 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02D2 )
Bit symbol
Reserved bit
Address
( 02D216 )
After reset
( 0016 )
Bit name
Function
R W
Function
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02D3 )
Bit symbol
Reserved bit
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REJ03B0082-0131
page 288 of 363
Address
( 02D316 )
Bit name
Must be set to "0".
After reset
( 0016 )
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02D4 )
Bit symbol
(b7-b0)
Address
( 02D416 )
After reset
( 0016 )
Bit name
Function
Must
Reserved
be setbits
to "0".
R W
Must be set to "0".
Extended register
b7
1
b6
b5
b4
b3
b2
b1
0 0 0 0 0
b0
Symbpl
( EXTREG02D5 )
Bit symbol
After reset
( 0016 )
Bit name
RGBSEL
RGB signal output selection bit
Reserved
(b5-b1) bit
Must
Reserved
be set
bits
to "0".
CREGCPUSEL
Palette register selection
(b7)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
Address
( 02D516 )
page 289 of 363
Reserved bit
Function
0: RGB 3-bit or analog output
1: RGB 2 values output
Must be set to "0".
0: Palette register setting of palette set 0
1: Palette register setting of palette set 1
Must be set to "1".
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbpl
( EXTREG02D6 )
Bit symbol
Address
( 02D616 )
After reset
( 0016 )
Bit name
Function
SCL3DRVUP
SCL3 output buffer size adjustment
SDA3DRVUP
SDA3 output buffer size adjustment
SCL5DRVUP
SCL5 output buffer size adjustment
SDA5DRVUP
SDA5 output buffer size adjustment
SCL6DRVUP
SCL6 output buffer size adjustment
SDA6DRVUP
SDA6 output buffer size adjustment
Reserved bit
Must be set to "0".
Reserved bit
Must be set to "0".
R W
0 : weak
1 : strong
0 : weak
1 : strong
0 : weak
1 : strong
0 : weak
1 : strong
0 : weak
1 : strong
0 : weak
1 : strong
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 1 1 0 1 0 1 0
Symbpl
( EXTREG02D7 )
Bit symbol
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
Address
( 02D716 )
Bit name
Reserved bit
Must be set to "0".
Reserved bit
Must be set to "1".
page 290 of 363
After reset
( 0016 )
Function
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbpl
( EXTREG02D8 )
Bit symbol
Address
( 02D816 )
After reset
( 0016 )
Bit name
Function
SCL0INSEL
I2C-bus0 SCL input pin selection
0 : Pin "SCL2"
1 : Pin "SCL5"
SDA0INSEL
I2C-bus0 SDA input pin selection
0 : Pin "SDA2"
1 : Pin "SDA5"
SCL1INSEL0
I2C-bus1 SCL input pin selection
0 : Pin "SCL3"
1 : Pin "SCL6"
SDA1INSEL0
I2C-bus1 SDA input pin selection
0 : Pin "SDA3"
1 : Pin "SDA6"
SCL1INSEL1
I2C-bus1 SCL input pin selection
SDA1INSEL1
I2C-bus1 SDA input pin selection
(b7-b6)
Reserved bits
R W
0 : SCL3 or SCL6
(SCL1INSEL0 available)
1 : Pin "SCL1"
0 : SDA3 or SDA6
(SDA1INSEL0 available)
1 : Pin "SDA1"
Must be set to "1".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
( EXTREG02D9 )
Bit symbol
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
Address
( 02D916 )
After reset
( 0016 )
Bit name
Function
BUSON1
SCL1-SCL3, SDA1-SDA3 bus switch
0 : OFF
1 : ON
BUSON2
SCL5-SCL6, SDA5-SDA6 bus switch
0 : OFF
1 : ON
SCLSDA1EN
SCL1, SDA1 pin control
0 : SCL1 and SDA1 are not used
.
1 : SCL1 and SDA1 are used.
SCLSDA2EN
SCL2, SDA2 pin control
0 : SCL2 and SDA2 are not used
.
1 : SCL2 and SDA2 are used.
SCLSDA3EN
SCL3, SDA3 pin control
0 : SCL3 and SDA3 are not used
.
1 : SCL3 and SDA3 are used.
SCLSDA4EN
SCL4, SDA4 pin control
0 : SCL4 and SDA4 are not used
.
1 : SCL4 and SDA4 are used.
SCLSDA5EN
SCL5, SDA5 pin control
0 : SCL5 and SDA5 are not used
.
1 : SCL5 and SDA5 are used.
SCLSDA6EN
SCL6, SDA6 pin control
0 : SCL6 and SDA6 are not used
.
1 : SCL6 and SDA6 are used.
page 291 of 363
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
Address
( EXTREG02DA ) ( 02DA16 )
Bit symbol
Reserved bit
(b7-b0)
After reset
( 0016 )
Bit name
Function
Must
Reserved
be setbitto "0".
R W
Must be set to "0".
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
Address
( EXTREG02DB ) ( 02DB16 )
Bit symbol
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
After reset
( 0016 )
Bit name
Function
0 : VSYNC1
1 : VSYNC2
SELVIN
VSYNC input selection
DIGREN
R digital 3BIT output control
DIGGEN
Q digital 3BIT output control
0 : DISABLE
1 : ENABLE
0 : DISABLE
1 : ENABLE
DIGBEN
B digital 3BIT output control
0 : DISABLE
1 : ENABLE
OUT1EN
OUT1 output control
0 : DISABLE
1 : ENABLE
OUT2EN
OUT2 output control
0 : DISABLE
1 : ENABLE
OSCOUTEN
OSCOUT output control
0 : DISABLE
1 : ENABLE
OSCEN
Selection of OSD2/VSYNC1/INT2
function
0 : VSYNC1/INT2 input
1 : OSC2 output
page 292 of 363
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
b2
b1
0 0 0 0 0 0
b0
0
Symbpl
Address
( EXTREG02DC ) ( 02DC16 )
Bit symbol
(b0)
TST11
Reserved bit
(b7-b2)
After reset
( 0016 )
Bit name
Function
Reserved bit
Must be set to "0".
OSD oscillation circuit
0: Used (LC or ceramic)
1: Not used
Must
Reserved
be setbits
to "0".
Must be set to "0".
R W
Extended register
b7
b6
b5
b4
b3
b2
0 0 0
b1
b0
0 0
Symbpl
Address
( EXTREG02DD ) ( 02DD16 )
Bit symbol
(b1-b0)
WSWL0
After reset
( 0016 )
Bit name
Reserved bits
(b7-b5)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 293 of 363
Must be set to "0".
TB0IN pin noise filter clock
selection bit
b3 b2
TB0IN pin noise filter ON/OFF
selection
0 : Noise filter OFF
1 : Noise filter ON
Reserved bits
Must be set to "0".
WSWL1
NFON
Function
0 0 : 0.25∝s
(The removable maximum
bus width=1∝s)
0 1 : 8∝s
(The removable maximum
bus width=32∝s)
1 0 : 16∝s
(The removable maximum
bus width=64∝s)
1 1 : 32∝s
(The removable maximum
bus width=128∝s)
R W
M306V8FJFP
Extended register
b7
b6
b5
b4
b3
0 0 0
b2
b1
b0
0 0 0
Symbpl
Address
( EXTREG02DE ) ( 02DE16 )
Bit symbol
After reset
( 0016 )
Bit name
Function
Reserved bit
Must be set to "0".
ANARGBCAPON
The CAP pin for inside operation
of analog RGB stable
0 : CAP pin is not used
1 : CAP pin is used
ANARGBCLKEN
Analog RGB internal clock input
control
0 : OFF
1 : ON
(b6-b5)
Reserved bits
Must be set to "0".
(b7)
Reserved bit
Must be set to "0".
(b2-b0)
R W
Extended register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbpl
( EXTREG02DF )
Bit symbol
Reserved bit
(b7-b0)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 294 of 363
Address
( 02DF16 )
Bit name
Must
Reserved
be setbitto "0".
After reset
( 0016 )
Function
Must be set to "0".
R W
M306V8FJFP
Electrical Characteristics
Table 18.1. Absolute Maximum Ratings
Symbol
Parameter
VCC1,VCC2, Supply voltage
VCC3
VI
Input
voltage
Condition
Rated value
Unit
VCC1=VCC2=
VCC3
-0.3 to 6.5
V
-0.3 to V CC1+0.3
V
-0.3 to 6.5
V
-0.3 to V CC1+0.3
V
RESET, CNVSS1, BYTE, CNVSS2,
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P4 0 to P47, P50 to P57,
P60 to P67, P72 to P77, P82, P8, P87
P90 to P91, P103 to P107, VSYNC1, OSC1,
HLF2, VHOLD2, CVIN2, HLF1,VHOLD1,
CVIN1, HSYNC, XIN, SCL5, SDA5,SCL6, SDA6
P70, P71, SCL4, SDA4
VO
Output
voltage
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P82, P83, P86, P87
P90 to P91, P103 to P107, OUT1, OUT2,
OSC2, OSCHLF, HLF2, VHOLD2, CVIN2,
HLF1, VHOLD1, CVIN1, XOUT,
DIGR1, DIGR2, DIGG1, DIGG2, DIGB1,
DIGB2, OSCOUT, R, G, B, SCL5, SDA5,
SCL6,SDA6
P70, P71, SCL4, SDA4
Pd
Power dissipation
Topr
Operating ambient
temperature
Tstg
Topr=25°C
At microcomputer operate
At flash memory erase
Storage temperature
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 295 of 363
-0.3 to 6.5
V
500
mW
-20 to 70
°C
0 to 60
°C
-40 to 125
°C
M306V8FJFP
Table 18.2. Recommended Operating Conditions (Note 1)
Parameter
Symbol
VCC1, VCC2, VCC3
Vss
Supply voltage(VCC1=VCC2=VCC3)
3.15
Supply voltage
HIGH input
voltage
VIH
I OH (peak)
I OH (avg)
I OL (peak)
I OL (avg)
3.45
V
V
VCC1
V
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
0.8VCC1
VCC1
V
P00 to P07, P10 to P17, P20 to P27, P30
(data input during memory expansion and microprocessor modes)
0.5VCC1
VCC1
V
0.8VCC1
VCC1
V
6.5
V
V
P31 to P37, P40 to P47, P50 to P57
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
P00 to P07, P10 to P17, P20 to P27, P30
(data input during memory expansion and microprocessor modes)
P60 to P67, P70 to P77, P82, P83, P86, P87, P90 to P91,
P103 to P107,
XIN, RESET, CNVSS1, BYTE, VSYNC1,OSC1,HSYNC,
SCL4,SDA4,SCL5,SDA5,SCL6,SDA6
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
HIGH peak output
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
current
P82 to P83,P86,P87,P90,P91,P103 to P107,
R,G,B,OUT1,OUT2,OSCOUT,DIGR1,DIGR2,
DIGG1,DIGG2,DIGB1,DIGB2
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
HIGH average
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
output current
P82,P83,P86,P87,P90,P91,P103 to P107,
R,G,B,OUT1,OUT2,OSCOUT,DIGR1,DIGR2,
DIGG1,DIGG2,DIGB1,DIGB2
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW peak output
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
current
P82,P83,P86,P87,P90,P91,P103 to P107,
R,G,B,OUT1,OUT2,OSCOUT,DIGR1,DIGR2,DIGG1,DIGG2,
DIGB1,DIGB2, SCL4, SDA4, SCL5, SDA5, SCL6,SDA6
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW average
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
output current
P82,P83,P86,P87,P90,P91,P103 to P107,
R,G,B,OUT1,OUT2,OSCOUT,DIGR1,DIGR2,DIGG1,DIGG2,
DIGB1,DIGB2, SCL4, SDA4, SCL5, SDA5, SCL6,SDA6
Main clock input oscillation frequency
f (XCIN)
Sub-clock oscillation frequency
f OSC
Oscillation frequency (for OSD)
VI
Unit
0.8VCC1
f (XIN)
f CVIN
3.3
Max.
P31 to P37, P40 to P47, P50 to P57
P70 , P71, SCL4,SDA4
LOW input
voltage
Standard
Typ.
0
P60 to P67, P72 to P77, P82, P83, P86, 87, P90 to P91, P103 to P107,
XIN, RESET, CNVSS1, BYTE, VSYNC1,OSC1,HSYNC
SCL5,SDA5,SCL6,SDA6
VIL
Min.
Input frequency
0.8VCC1
0
0
0.2VCC1
0.2VCC1
0
0.16VCC1
V
0
0.2VCC1
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
16
MHz
32.768
OSC1
LC oscillation mode
Ceramic oscillation mode
Internal oscillation mode (XIN=16MHz)
The level synchronized signal of 525i (480i) video signal
The level synchronized signal of 525p (480p) video signal
Video signal CVIN1, CVIN2
Input amplitude
V
kHz
8.0
20.0
30
30
20.0
15.262
–
65
1.5
15.734
31.47
1.75
MHz
16.206
–
kHz
2.00
V
Note 1: Referenced to VCC = VCC1 = VCC2 = VCC3 = 3.3V ± 0.15V at Topr = -20 to 70 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P86, P87 and P9 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6,
P7 and P80 to P84 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be -40mA max. The total IOH
(peak) for ports P3, P4 and P5 must be -40mA max. The total IOH (peak) for ports P6, P7, and P80 to P84 must be -40mA
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 296 of 363
M306V8FJFP
Table 18.3. A/D Conversion Characteristics (Note 1)
Symbol
Parameter
VREF =VCC1
VREF=VCC1=3.3V
Resolution
INL
Absolute accura cy
tCONV
Conversion time, Sample & hold
function available
tSAMP
Sampling time
VREF
VIA
Reference voltage
Analog input voltage
Standard
Unit
Min. Typ. Max.
Measuring condition
8
+5
ØAD=10 MHz
Bits
LSB
2.8
µs
0.3
µs
V
VCC1
0
VCC1
V
Note 1: Referenced to VCC1= 3.3V, VSS=0V at Topr = -20 to 70°C unless otherwise specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD and make ØAD frequency
equal to or lower than fAD/2.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 2.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 2.
Table 18.4. Analog R,G,B output specifications (VCC1=3.3V, VSS=0V, Ta=25°C, Load capacity
RI=nothing, Load capacity CI=nothing, unless otherwise specified)
Symbol
Vppm
Voe
IO
RO
Tst
Parameter
Measuring condition
Maximum output amplitude RGB each output control bit=111b setup
Output deviation
RGB each output control bit=111b setup
Maximum output current
Output register
Set ring time
30 to 70% or 70 to 30%
V 0E
Min.
α ✕ 0.8
2.2
190
Standard
Unit
Typ.
Max.
α =100 0.71 α ✕ 1.2
V
140
±20
%
4.0
5.8
mA
ΩA
400
nS
33
2/7(V )
70%V P-P
V P-P
30%V P-P
1/7(V)
V 0E
T ST
V SS
* This figure is the publication about 0/7=Vss, 1/7, and 2/7 in maximum output amplitude Vppm=7/7(V).
Figure 18.1. Analog RGB output characteristic
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 297 of 363
M306V8FJFP
Table 18.5. Flash Memory Version Electrical Characteristics (Note 1)
Parameter
Min.
Word program time
Block erase time
Erase all unlocked blocks time
Stantard
Typ.
Max.
200
30
Unit
µs
1
4
s
1Xn
4Xn
30
200
s
µs
Lock bit program time
Note 1: Referenced to VCC1=3.3V at Topr=0 to 60°C unless otherwise specified.
Note 2: n denotes the number of block erases.
Table 18.6. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60oC)
Flash program, erase voltage
Flash read operation voltage
VCC1 = 3.3 V ± 0.15V
VCC1=3.3 to 0.15 V
Table 18.7. Power Supply Circuit Timing Characteristics
Symbol
Measuring Condition
Parameter
td(P-R)
Time for Internal Power Supply Stabilization During Powering-On
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode Wait Mode Release Time
VCC1=2.7 to 3.45V
Note: When VCC1 = 5V.
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC
td(P-R)
CPU clock
td(R-S)
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
td(R-S)
(b)
td(W-S)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 298 of 363
Min.
Standard
Typ.
Max.
Unit
2
ms
150
µs
150
µs
M306V8FJFP
Table 18.8. Electrical Characteristics (Note 1)
Symbol
VOH
VOH
HIGH output P00 to P07,P10 to P17,P20 to P27,P30 to P37,P40 to P47,
voltage
P50 to P57,P60 to P67,P72 to P77,P82,P83,P86,P87,
IOH=-1mA
P90,P91,P103 to P107,R,G,B,OUT1,OUT2,
OSCOUT,DIGR1,DIGR2,DIGG1,DIGG2,DIGB1,DIGB2
HIGHPOWER
IOH=-0.1mA
HIGH output voltage
XOUT
IOH=-50µA
LOWPOWER
HIGH output voltage
XCOUT
HIGHPOWER
LOWPOWER
VOL
Min.
LOW output voltage
Hysteresis
VT+-VT-
XOUT
XCOUT
VCC -0.5
VCC
VCC -0.5
VC C
2 .5
1 .6
With no load applied
With no load applied
HIGHPOWER
IOL = 0.1 mA
LOWPOWER
IOL = 50 µA
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
HOLD,RDY,TA0IN to TA3IN,TB0IN,TB1IN,INT0 to INT3,
CTS0 to CTS2,SCL0 to SCL6,SDA0 to SDA6,
CLK0 to CLK2,TA0OUT to TA3OUT,KI1 to KI3,RXD0 to RXD2
VSYNC1,VSYNC2,HC0,HC1,HSYNC2
0.2
Hysteresis
RESET
0.2
VT+-VT-
Hysteresis
XIN
0.2
IIH
HIGH input P00 to P07,P10 to P17,P20 to P27,P30 to P37,P40 to P47,
P50 to P57,P60 to P67,P72 to P77,P82,P83,P86,P87,
current
VI = 3V
P90,P91,P103 to P107,XIN,RESET,CNVSS1,BYTE,
VSYNC1,OSC1,HSYNC,SCL4,SDA4,SCL5,SDA5,
SCL6,SDA6
RPULLUP
LOW input
current
P00 to P07,P10 to P17,P20 to P27,P30 to P37,P40 to P47,
P50 to P57,P60 to P67,P72 to P77,P82,P83,P86,P87,
VI = 0V
P90,P91,P103 to P107,XIN,RESET,CNVSS1,BYTE,
VSYNC1,OSC1,HSYNC,SCL4,SDA4,SCL5,SDA5,
SCL6,SDA6
Pull-up
resistance
P00 to P07,P10 to P17,P20 to P27,P30 to P37,P40 to P47,
P50 to P57,P60 to P67,P72 to P77,P82,P83,P86,P87,
VI = 0V
P90,P91,P103 to P107
66
(0.7)
160
RfXIN
Feedback resistance
XIN
3.0
RfXCIN
Feedback resistance
XCIN
25
RBS
I2C-bus, Bus switch
page 299 of 363
Unit
V
V
V
0.5
V
0.5
0.5
V
V
0.8
V
1.8
V
0.8
V
40
µA
-4.0
µA
500
kΩ
MΩ
MΩ
130
Note 1: Referenced to VCC = VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, Topr = -20 to 70 °C unless otherwise specified.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
Max.
VCC
VCC -0.5
VT+-VT-
IIL
Standard
Typ.
LOW output P00 to P07,P10 to P17,P20 to P27,P30 to P37,P40 to P47,
voltage
P50 to P57,P60 to P67,P72 to P77,P82,P83,P86,P87,
IOL = 1mA
P90,P91,P103 to P107,R,G,B,OUT1,OUT2,
OSCOUT,DIGR1,DIGR2,DIGG1,DIGG2,DIGB1,DIGB2
SCL4,SDA4,SCL5,SDA5,SCL6,SDA6
LOW output voltage
VOL
Measuring condition
Parameter
Ω
M306V8FJFP
Table 18.9. Electrical Characteristics (2) (Note 1)
Symbol
Measuring condition
Parameter
In single-chip mode, the output
pins are open and other pins are
VSS
Mask ROM
Flash memory
Mask ROM
ICC
Flash memory
Power supply current
Mask ROM
Flash memory
OSD ON
Data slicer ON
OSD OFF
f(BCLK)=16MHz, Data slicer OFF
No division
OSD ON
Data slicer ON
OSD OFF
Data slicer OFF
f(XCIN)=32kHz,
Low power dissipation mode,
ROM(Note 3)
Min.
Standard
Typ.
Max.
100
140
mA
mA
15
120
Unit
170
mA
mA
15
25
µA
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
25
µA
f(BCLK)=32kHz
Low power dissipation mode,
Flash memory(Note 3)
420
µA
6.0
µA
1.8
µA
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscillation capacity Low
Stop mode,
Topr=25°C
Note 1: Referenced to VCC = VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, Topr = -20 to 70 °C unless otherwise specified.
Note 2: With one timer operated using fC32.
Note 3: This indicates the memory in which the program to be executed exists.
Rev.1.31 Apr 18, 2005
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page 300 of 363
0.7
3.0
µA
M306V8FJFP
Timing Requirements
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 18.10. External Clock Input
Symbol
Parameter
tc
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
Unit
ns
62
25
25
15
15
ns
ns
ns
ns
Table 18.11. Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
tac1(RD-DB)
Data input access time (for setting with no wait)
tac2(RD-DB)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
Standard
Min.
Max.
(Note 1)
(Note 2)
(Note 3)
50
Unit
ns
ns
ns
50
ns
ns
ns
0
ns
0
ns
0
ns
40
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 60
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 60
f(BCLK)
[ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
setting.
Note 3: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 60
f(BCLK)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
page 301 of 363
M306V8FJFP
Timing Requirements
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 18.12. Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
Parameter
TAi IN input cycle time
Standard
Min.
Max.
300
Unit
ns
tw(TAH)
TAi IN input HIGH pulse width
60
ns
tw(TAL)
TAi IN input LOW pulse width
60
ns
Table 18.13. Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
tc(TA)
TAi IN input cycle time
tw(TAH)
tw(TAL)
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
600
Unit
ns
ns
300
300
ns
Table 18.14. Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAi IN input cycle time
300
ns
tw(TAH)
tw(TAL)
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
150
150
ns
ns
Table 18.15. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
150
150
Unit
ns
ns
Table 18.16. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
tc(UP)
TAi OUT input cycle time
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAi OUT input HIGH pulse width
Standard
Min.
Max.
3000
1500
TAi OUT input LOW pulse width
TAi OUT input setup time
TAi OUT input hold time
1500
600
600
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
Table 18.17. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Parameter
tc(TA)
TAi IN input cycle time
tsu(TA IN-TA OUT)
tsu(TA OUT-TA IN)
TAi OUT input setup time
TAi IN input setup time
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REJ03B0082-0131
page 302 of 363
Standard
Min.
Max.
2
500
500
Unit
µs
ns
ns
M306V8FJFP
Timing Requirements
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 18.18. Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
60
300
ns
tc(TB)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
160
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
160
ns
ns
Table 18.19. Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
300
300
ns
ns
Table 18.20. Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input HIGH pulse width
300
ns
tw(TBL)
TBiIN input LOW pulse width
300
ns
Table 18.21. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input HIGH pulse width
150
ns
tw(CKL)
CLKi input LOW pulse width
150
ns
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
160
ns
0
100
ns
90
ns
ns
_______
Table 18.22. External Interrupt INTi Input
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
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REJ03B0082-0131
page 303 of 363
Standard
Min.
380
380
Max.
Unit
ns
ns
M306V8FJFP
Switching Characteristics
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C, CM15 = “1” unless otherwise specified)
Table 18.23. Memory Expansion and Microprocessor Modes (for setting with no wait)
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Measuring condition
Parameter
Symbol
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
Standard
Min.
Max.
30
4
0
(Note 2)
30
4
30
–4
30
Fig.19.11
0
30
0
40
4
(Note 1)
(Note 2)
40
td(BCLK-HLDA) HLDA output delay time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
– 40
[ns]
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 10
f(BCLK)
[ns]
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 18.2. Ports P0 to P10 Measurement Circuit
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30pF
R
DBi
C
M306V8FJFP
Switching Characteristics
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C, CM15 = “1” unless otherwise specified)
Table 18.24. Memory Expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Parameter
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
Data output hold time (refers to WR)(Note 3)
Measuring condition
Standard
Min.
Max.
30
4
0
(Note 2)
30
4
30
–4
30
Fig.19.11
0
30
0
40
4
(Note 1)
(Note 2)
td(BCLK-HLDA) HLDA output delay time
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
– 40
f(BCLK)
[ns]
n is “1” for 1-wait setting, “2” for 2-wait
setting and “3” for 3-wait setting.
Note 2: Calculated according to the BCLK frequency as follows:
0.5 X 109
– 10
f(BCLK)
[ns]
Note 3: This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2)
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REJ03B0082-0131
page 305 of 363
R
DBi
C
M306V8FJFP
Switching Characteristics
(VCC1 = VCC2 = VCC3 = 3.3V, VSS = 0V, at Topr = – 20 to 70°C, CM15 = “1” unless otherwise specified)
Table 18.25. Memory Expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
Symbol
Parameter
Measuring condition
Standard
Min.
Max.
50
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
(Note 1)
ns
ns
th(WR-AD)
Address output hold time (refers to WR)
(Note 1)
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
Chip select output delay time
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
Chip select output hold time (refers to WR)
RD signal output delay time
RD signal output hold time
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
th(BCLK-DB)
td(DB-WR)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
Data output hold time (refers to WR)
HLDA output delay time
ALE signal output delay time (refers to BCLK)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (refers to Adderss)
RD signal output delay from the end of Adress
td(AD-WR)
WR signal output delay from the end of Adress
tdZ(RD-AD)
Address output floating start time
4
50
4
(Note 1)
(Note 1)
40
0
40
Fig.19.11
0
50
4
–10
(Note 1)
40
–50
(Note 4)
0.5 X 109
f(BCLK)
–40
[ns]
Note 4: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
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REJ03B0082-0131
–15
[ns]
page 306 of 363
ns
ns
ns
ns
0
0
n is “2” for 2-wait setting, “3” for 3-wait setting.
Note 3: Calculated according to the BCLK frequency as follows:
ns
ns
ns
ns
ns
(Note 3)
[ns]
[ns]
ns
ns
ns
40
–4
Note 2: Calculated according to the BCLK frequency as follows:
(n–0.5) X 109
f(BCLK)
ns
ns
ns
ns
ns
(Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
0.5 X 109
f(BCLK)
ns
ns
8
ns
M306V8FJFP
XIN input
tf
tw(H)
tr
tw(L)
tc
tc(TA)
tw(TAH)
TAi IN input
tw(TAL)
tc(UP)
tw(UPH)
TAi OUT input
tw(UPL)
TAi OUT input
(Up/down input)
During event counter mode
TAi IN input
th(TIN–UP)
(When count on falling
edge is selected)
tsu(UP–TIN)
TAi IN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAi IN input
tsu(TA IN-TA OUT)
tsu(TA IN-TA OUT)
tsu(TA OUT-TA IN)
TAi OUT input
tsu(TA OUT-TA IN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
Figure 18.3. Timing Diagram (1)
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REJ03B0082-0131
page 307 of 363
M306V8FJFP
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 18.4. Timing Diagram (2)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 308 of 363
th(C–D)
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait )
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Common to setting with wait and setting without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register.
Measuring conditions :
• V CC1=VCC2=VCC3 =3.3V
• Input timing voltage : Determined with V IL=0.6V, V IH=2.4V
• Output timing voltage : Determined with V OL=1.5V, V OH=1.5V
Figure 18.5. Timing Diagram (3)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 309 of 363
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
30ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 X tcyc-60)ns.max
Hi-Z
DBi
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
30s.max
th(WR-AD)
-4ns.min
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
1
tcyc=
f(BCLK)
Measuring conditions
• VCC1=VCC2=VCC3=3.3V
• Input timing voltage : VIL=0.6V, V IH=2.4V
• Output timing voltage : VOL=1.5V, VOH =1.5V
Figure 18.6. Timing Diagram (4)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 310 of 363
th(WR-DB)
(0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
0ns.min
-4ns.min
30ns.max
ALE
td(BCLK-RD)
th(BCLK-RD)
30ns.max
0ns.min
RD
tac2(RD-DB)
(1.5 X tcyc-60)ns.max
Hi-Z
DBi
th(RD-DB)
tSU(DB-RD)
0ns.min
50ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
-4ns.min
30ns.max
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
tcyc=
(0.5 X tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
• VCC1=VCC2=VCC3=3V
• Input timing voltage : VIL=0.6V, V IH=2.4V
• Output timing voltage : VOL=1.5V, V OH=1.5V
Figure 18.7. Timing Diagram (5)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 311 of 363
th(WR-DB)
(0.5 X tcyc-10)ns.min
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access )
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
30ns.max
4ns.min
CSi
th(BCLK-AD)
td(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
30ns.max
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(2.5 X tcyc-60)ns.max
DBi
Hi-Z
tSU(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
(0.5 X tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
DB
Hi-Z
td(DB-WR)
(1.5 X tcyc-40)ns.min
tcyc=
th(BCLK-DB)
4ns.min
1
f(BCLK)
Measuring conditions
• V CC1=VCC2=VCC3=3.3V
• Input timing voltage
: V IL=0.6V, V IH=2.4V
• Output timing voltage : V OL=1.5V, V OH=1.5V
Figure 18.8. Timing Diagram (6)
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REJ03B0082-0131
page 312 of 363
th(WR-DB)
(0.5 X tcyc-10)ns.min
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access )
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
30ns.max
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
30ns.max
0ns.min
RD
tac2(RD-DB)
(3.5 X tcyc-60)ns.max
DBi
Hi-Z
tSU(DB-RD)
th(RD-DB)
50ns.min
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
CSi
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
(0.5 X tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DB
td(DB-WR)
(2.5 X tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
• V CC1=VCC2=VCC3=3.3V
• Input timing voltage
: V IL=0.6V, V IH=2.4V
• Output timing voltage : V OL=1.5V, V OH=1.5V
Figure 18.9. Timing Diagram (7)
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th(WR-DB)
(0.5 X tcyc-10)ns.min
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(RD-CS)
(0.5 X tcyc) ns mi.n
tcyc
40ns.max
th(BCLK-CS)
4ns.min
CSi
td(AD-ALE)
(0.5 X tcyc-40)ns.min
th(ALE-AD)
30ns.min
ADi
/DBi
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5 X tcyc-60)ns.max
tSU(DB-RD)
th(RD-DB)
0ns.min
50ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5 X tcyc)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
tcyc
40ns.max
4ns.min
(0.5 X tcyc-10)ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Data output
td(DB-WR)
td(AD-ALE)
(1.5 X tcyc-50)ns.min
(0.5 X tcyc-40)ns.min
Address
th(WR-DB)
(0.5 X tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
td(AD-WR)
-4ns.min
0ns.min
th(WR-AD)
(0.5 X tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
W RH
tcyc=
1
f(BCLK)
Measuring conditions
• VCC1=VCC2=VCC3=3.3V
• Input timing voltage : VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 18.10. Timing Diagram (8)
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th(BCLK-WR)
0ns.min
M306V8FJFP
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5 X tcyc)ns.min
td(BCLK-CS)
th(BCLK-CS)
6ns.min
40ns.max
CSi
td(AD-ALE)
(0.5 X tcyc-40)ns.min
th(ALE-AD)
30ns.min
ADi
/DBi
Address
td(BCLK-AD)
td(AD-RD)
40ns.max
ADi
BHE
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
tac3(RD-DB)
(2.5 X tcyc-60)ns.max
0ns.min
tSU(DB-RD)
0ns.min
th(BCLK-AD)
50ns.min
4ns.min
(no multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5 X tcyc)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
40ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5 X tcyc-10)ns.min
td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
50ns.max
ADi
/DBi
Address
4ns.min
Data output
td(AD-ALE)
td(DB-WR)
(0.5 X tcyc-40)ns.min
(2.5 X tcyc-50)ns.min
th(WR-DB)
(0.5 X tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
td(AD-WR)
td(BCLK-WR)
40ns.max
WR, WRL
WRH
tcyc=
(0.5 X tcyc-10)ns.min
0ns.min
ALE
1
f(BCLK)
Measuring conditions
• VCC1=VCC2=3.3V
• Input timing voltage
: VIL=0.6V, VIH=2.4V
• Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 18.11. Timing Diagram (9)
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th(BCLK-WR)
0ns.min
M306V8FJFP
Flash Memory Version
Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally contains flash memory.
The flash memory version has three modes—CPU rewrite, standard serial input/output, and parallel input/
output modes—in which its internal flash memory can be operated on.
Table 19.1 shows the outline performance of flash memory version (refer to “Table 1.1. Performance outline of M306V8FJFP” for the items not listed in Table 19.1.).
Table 19.1. Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
User ROM area
Refer to “Figure 19.1. Flash Memory Block Diagram”
Boot ROM area
1 block (4 Kbytes) (Note 1)
Erase block
Method for program
In units of word, in units of byte (Note 2)
Method for erasure
Collective erase, block erase
Program, erase control method
Program and erase controlled by software command
Protect method
Protected for each block by lock bit
Number of commands
8 commands
Number of program and erasure
100 times
ROM code protection
Parallel I/O and standard serial I/O modes are supported.
Notes 1: The boot ROM area contains a standard serial I/O mode rewrite control program which is stored in it when
shipped from the factory. This area can only be rewritten in parallel input/output mode
.
2: Can be programmed in byte units in only parallel input/output mode.
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Table 19.2. Flash Memory Rewrite Modes Overview
Flash memory CPU rewrite mode (Note 1)
rewrite mode
The user ROM area is rewritFunction
ten by executing software
commands from the CPU.
EW0 mode:
Can be rewritten in any
area other than the flash
memory (Note 2)
EW1 mode:
Can be rewritten in the
flash memory
Areas which User ROM area
can be rewritten
Operation
Single chip mode
mode
Memory expansion mode
(EW0 mode)
Boot mode (EW0 mode)
ROM
None
programmer
Standard serial I/O mode
Parallel I/O mode
The user ROM area is rewritten by using a dedicated serial programmer.
Standard serial I/O mode 1:
Clock sync serial I/O
Standard serial I/O mode 2:
UART
The boot ROM and user
ROM areas are rewritten by
using a dedicated parallel
programmer.
User ROM area
Boot mode
User ROM area
Boot ROM area
Parallel I/O mode
Serial programmer
Parallel programmer
Note 1: The PM13 bit remains set to “1” while the FMR0 register FMR01 bit = 1 (CPU rewrite mode enabled).
The PM13 bit is reverted to its original value by clearing the FMR01 bit to “0” (CPU rewrite mode
disabled). However, if the PM13 bit is changed during CPU rewrite mode, its changed value is not
reflected until after the FMR01 bit is cleared to “0”.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM or in an external area that is enabled for
use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode,
the extended accessible area (5000016 to BFFFF16) cannot be used.
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M306V8FJFP
Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area, OSD
ROM area. Figure 19.1 shows the block diagram of flash momoery. The user ROM area has a 4K-byte
block A, in addition to the area that stores a program for microcomputer operation during singe-chip or
memory expansion mode.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial
input/output, and parallel input/output modes. Block A is enabled for use by setting the PM1 register’s
PM10 bit to “1” (block A enabled, CS2 area at addresses 1000016 to 26FFF16).
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in
parallel input/output mode. After a hardware reset that is performed by applying a high-level signal to the
CNVSS1 and P50 pins and a low-level signal to the P55 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS1 pin, the program in
the user ROM area is executed (but the boot ROM area cannot be read). OSD ROM area that stores
character font data. It is rewritten in CPU rewriting mode, standard serial I/O mode, or parallel I/O mode.
00F00016
00FFFF16
30000 16
4FFFF16
08000016
Block A :4K bytes (Note 4)
3000016
Block 20 : 32K bytes
Block 12 : 64K bytes
3800016
08FFFF16
Block 19 : 16K bytes
09000016
3C00016
Block 18 : 8K bytes
Block 11 : 64K bytes
3FFFF16
Block 17 : 8K bytes
4000016
09FFFF16
0A000016
Block 16 : 32K bytes
Block 10 : 64K bytes
4800016
0AFFFF16
Block 15 : 16K bytes
0B000016
4C00016
Block 14 : 8K bytes
Block 9 : 64K bytes
4FFFF16
Block 13 : 8K bytes
5000016
0BFFFF16
OSD ROM area
0F000016
0C000016
Block 8 : 64K bytes
0CFFFF16
Block 5 : 32K bytes
0D000016
Block 7 : 64K bytes
0DFFFF16
0F7FFF16
0F800016
0E000016
Block 4 : 8K bytes
Block 6 : 64K bytes
0F9FFF16
0FA00016
Block 3 : 8K bytes
0EFFFF16
0FBFFF16
0FC00016
0F000016
Block 2 : 8K bytes
Block 0 to Block 5 (32+8+8+8
+4+4)K bytes
0FDFFF16
0FE00016
0FEFFF16
0FF00016
0FFFFF16
0FFFFF16
User ROM area
Block 1 : 4K bytes
Block 0 : 4K bytes
0FF00016
0FFFFF16
4K bytes
Boot ROM area (Note 1)
Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Note 4: Block A can be made usable by setting the PM1 register’s PM10 bit to “1” (block A enabled, CS2 area allocated at addresses 1000016 to 26FFF16).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it.
Figure 19.1. Flash Memory Block Diagram
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M306V8FJFP
Boot Mode
After a hardware reset which is performed by applying a low-level signal to the P55 pin and a high-level
signal to the CNVSS1 and P50 pins, the microcomputer is placed in boot mode, thereby executing the
program in the boot ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0
register.
The boot ROM area contains a standard serial input/output mode based rewrite control program which was
stored in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite
control program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the
system.
Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM
code protect and standard serial input/output mode has an ID code check function.
• ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
input/output mode. Figure 19.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area. The ROM code protect function is enabled when
the ROMCR bits are set to other than "11b". In this case, set the bit 5 to bit 0 to "111111b".
When exiting ROM code protect, erase the block including the ROMCP1 register by the CPU rewrite
mode or the standard serial I/O mode.
• ID Code Check Function
Use the ID code check function in standard serial I/O mode. The ID code sent from the serial programmer
is compared with the ID code written in the flash memory for a match. If the ID codes do not match,
commands sent from the serial programmer are not accepted. However, if the four bytes of the reset
vector are "FFFFFFFFh", ID codes are not compared, allowing all commands to be accepted.
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh,
0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a
program with the ID codes set in these addresses.
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M306V8FJFP
ROM code protect control address
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
Symbol
ROMCP
Address
0FFFFF16
Bit name
Bit symbol
ROMCP1
Value when shipped
FF16 (Note 4)
Function
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
Reserved bit
Set this bit to “1”
RW
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
b7 b6
00:
Protect enabled
01:
10:
11: Protect disabled
}
RW
RW
Notes 1: If the ROMCP1 bits are set to other than "11b" (ROM code protect enabled), the flash memory
is disabled against reading and rewriting in parallel I/Ot mode.
2: When the ROMCP1 bits are set to other than "11b," set the bit 5 to bit 0 to "111111b".
3: When exiting ROM code protect, erase the block including the ROMCP1 register by CPU rewrite
mode or standard serial I/O mode.
4: If a memory block that including ROMCP1 register is erased, the ROMCP register is set to "FFh".
Figure 19.2. ROMCP Register
Address
0FFFDF16 to 0FFFDC16 ID1
0FFFE316 to 0FFFE016
ID2
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
Undefined instruction vector
Overflow vector
BRK instruction vector
ID3
0FFFEF16 to 0FFFEC16 ID4
Address match vector
Single step vector
0FFFF316 to 0FFFF016
ID5
Watchdog timer vector
0FFFF716 to 0FFFF416
ID6
DBC vector
0FFFFB16 to 0FFFF816
ID7
0FFFFF16 to 0FFFFC16
ROMCP Reset vector
4 bytes
Figure 19.3. Address for ID Code Stored
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M306V8FJFP
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area or OSD ROM area can be rewritten by executing software
commands from the CPU. Therefore, the user ROM area or OSD ROM area can be rewritten directly while
the microcomputer is mounted on-board without having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 19.1 can be rewritten and the boot ROM
area cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on
each block in the user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase
Write 1 (EW1) mode. Table 19.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1
(EW1) modes.
Table 19.3. EW0 Mode and EW1 Mode
Item
Operation mode
Areas in which a
rewrite control
program can be located
Areas in which a
rewrite control
program can be executed
Areas which can be
rewritten
EW0 mode
• Single chip mode
• Memory expansion mode
• Boot mode
• User ROM area
• Boot ROM area
EW1 mode
Single chip mode
Must be transferred to any area other
than the flash memory (e.g., RAM)
before being executed (Note 2)
User ROM area
OSD ROM area
Can be executed directly in the user
ROM area
Software command
limitations (Note 3)
None
Modes after Program or
Erase
CPU status during Auto
Write and Auto Erase
Read Status Register mode
Operating
Flash memory status
detection (Note 3)
User ROM area
User ROM area
OSD ROM area
However, this does not include the area
in which a rewrite control program
exists
• Program, Block Erase command
Cannot be executed on any block in
which a rewrite control program exists
• Erase All Unlocked Block command
Cannot be executed when the lock bit
for any block in which a rewrite control
program exists is set to “1” (unlocked)
or the FMR0 register’s FMR02 bit is set
to “1” (lock bit disabled)
• Read Status Register command
Cannot be executed
Read Array mode
Hold state (I/O ports retain the state in
which they were before the command
was executed) (Note 1)
Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a program
• Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
Note 1: Make sure no interrupts (except watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the PM13
bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended accessible area
(5000016 to BFFFF16) cannot be used.
Note 3: The register name in explanatory note and a bit name are the cases of rewriting of user ROM area.
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M306V8FJFP
• EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit
= 0, EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status
register to check the status of program or erase operation at completion.
• EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status
register cannot be read during EW1 mode.
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M306V8FJFP
Flash memory Control Register (FIDR, FMR0 and FMR1 registers)
Figure 19.4 shows the FIDR, FMR0 and FMR1 registers.
FMR00 Bit
This bit indicates the flash memory operating state. It is set to "0" while the program, block erase, erase all
unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to "1".
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode). During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit is disabled by setting the FMR02 bit to "1" (lock bit disabled). (Refer to 22.3.6 Data Protect
Function.) The lock bit is enabled by setting the FMR02 bit to "0" (lock bit enabled).
The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or
erase all unlocked block command is executed when the FMR02 bit is set to "1", the lock bit status
changes "0" (locked) to "1" (unlocked) after command execution is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. Setting the FMSTP bit to “1” makes the internal flash memory
inaccessible. Set the FMSTP bit by program in a space other than the flash memory.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00
bit not reset to “1” (ready))
• When entering low power mode or ring low power mode
Figure 19.8 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power
for the internal flash memory is automatically turned off and is turned back on again after returning from
stop or wait mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area
(for read, write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase
error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
Figure 19.6 show the setting and resetting of EWO mode and 19.7 show the setting and resetting of EW1
mode, respectively.
FMR11 Bit
When the FMR11 bit is set to “0” (EW0 mode), the MCU (microcomputer) enters EW0 mode.
When the FMR11 bit is set to “1” (EW1 mode), the MCU (microcomputer) enters EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.
While the block is locked, the FMR16 bit is set to “0”. While the block is not locked, this bit is set to “1”.
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M306V8FJFP
Flash memory (USER) identification register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
FIDR
01B416
XXXXXX002
Bit name
Bit symbol
Flash module type
identification value
FIDR0
FIDR1
Function
b1 b0
0 0: M16C/62N, M3062GF8N type flash module
1 0: M16C/62P type flash module
1 1: M16C/62M, M16C/62A type flash module
RW
RO
RO
Nothing is assigned.
When write, set to “0”. When read, their contents are indeterminate.
(b7-b2)
Note: This register identifies on-chip flash module type of M16C/62 group. Note, however, no chip version is known
by this register. Follow the procedure described below for the identification.
(1) Write FF16 to FIDR register
(2) Read FIDR register
(3) Check two low-order bits of read value
Make sure no access to external memories or other SFRs or no interrupts or DMA transfers will occur between
the above two instructions no. 1 and no. 2. FIDR register does not discriminate the type of built-in flash
module, and does not show a chip version.
Flash memory (USER) ontrol register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After reset
FMR0
01B716
XX0000012
Bit name
Bit symbol
Function
RW
FMR00
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMR01
CPU rewrite mode select bit
(Note 1)
0: Disables CPU rewrite mode
1: Enables CPU rewrite mode
RW
Lock bit disable select bit
(Note 2)
0: Enables lock bit
1: Disables lock bit
RW
Flash memory stop bit
(Note 3, Note 5)
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
flash memory initialized)
FMR02
FMSTP
Reserved bit
RO
RW
Must always be set to “0”
RW
User ROM area select bit
(Note 3)
(Effective in only boot mode)
0: Boot ROM area is accessed
1: User ROM area is accessed
RW
FMR06
Program status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
FMR07
Erase status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
(b4)
FMR05
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Also, while in EW0 mode, write to this bit from a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMR03 bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Note 6: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.
Flash memory (USER) control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol
Address
After reset
FMR1
01B516
0X00XX0X2
Bit name
Bit symbol
(b0)
FMR11
Reserved bit
EW1 mode select bit (
Note)
Function
The value in this bit when read is
indeterminate.
0: EW0 mode
1: EW1 mode
RW
RO
RW
(b3-b2)
Reserved bit
The value in this bit when read is
indeterminate.
(b5-b4)
Reserved bit
Must always be set to “0”
RW
FMR06
Lock bit status flag
0: Lock
1: Unlock
RO
Reserved bit
Must always be set to “0”
RW
(b7)
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 19.4. FIDR Register and FMR0 and FMR1 Registers
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Figure 19.5 shows the register FMOSi0, figure 19.5-2 shows registers FMOSi1 and FMOSi4 (i=A, B).
FMOSi00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or erase
suspend mode is running; otherwise, the bit is “1”.
FMOSi01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite
mode).
FMOSi02 Bit
When FMR02 bit is "0" (rewriting is forbidden,) block 0 and block 1 do not receive the command of a
program and block erase.
FMOSiSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. Setting the FMSTP bit to “1” makes the internal flash memory
inaccessible. Therefore, FMSTP bit should program of domains other than a flash memory.
In the following cases, set the FMSTP bit to “1”:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to “1” (ready))
• When entering low power mode
Figure 19.8 shows a flow chart to be followed before and after entering low power mode.
When CPU rewriting mode shifts at stop mode or wait mode at the time of invalid, the FMR0 register does
not need to be set because the power for the internal flash memory is automatically turned off and is turned
back on again after returning from stop or wait mode.
FMOSi06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program
error occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
FMOSi07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase error
occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
FMOSi11 Bit
Setting this bit to “1” places the microcomputer in EW1 mode.
FMOSi40 Bit
When FMR40 bit is set to “1” (permission), an erase suspension function will be permitted.
FMOSi41 Bit
In the EW0 mode, when FMR41 bit is set to “1” by the program, it will shift to erase suspension mode. In the
EW1 mode, if the interruption demand of permitted interruption occurs, FMR41 bit will be automatically set
to “1” (suspension request), and they will shift to erase suspension mode.
When resome automatic elimination operation, set FMR41 bit to “0” (erase restart.)
FMOSi46 Bit
FMR46 is set to “0” during automatic elimination execution. It is set to “1” by the inside of erase suspension
mode. Between “0”, access to a flash memory is prohibition.
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Flash memory (USER/OSD) switching register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
After reset
FMSEL
02A016
00000000 2
Bit symbol
Bit name
OSELBIT1 USER/OSD1/OSD2
switching bit
OSELBIT2
Function
W
RRW
00 USER
01: OSD1
10: OSD2
11: Nothing is assigned.
RW
RW
Must always be set to “0”
RW
(b6-b2)
Reserved bit
(b7)
Nothing is assigned.
When write, set to “0”. When read, their contents are “0”.
RW
Flash memory (OSD1/OSD2) control register 0
b7
b6
b5
b4
b3
b2
0
b1
b0
Symbol
FMOSi0
Bit symbol
Address
After reset
02A716/02B716
XX0000012
Bit name
Function
W
RRW
FMOSi00
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
RO
FMOSi01
CPU rewrite mode select
bit (Note 1)
0 : Disables CPU rewrite mode
1 : Enables CPU rewrite mode
RW
FMOSi02
Blocks 0 and 1 rewrite
enable bit (Note 2)
0 : Enables blocks 0 and 1 rewrite
1 : Disables blocks 0 and 1 rewrite
RW
FMOSiSTP
Flash memory stop bit
(Note 3, Note 5)
0 : Enables flash memory operation
1 : Stops flash memory operation
(placed in low power mode, flash
memory initialized)
Reserved bit
Must always be set to “0”
RW
FMOSi06
Program status flag
(Note 4)
0 : Terminated normally
1 : Terminated in error
RO
FMOSi07
Erase status flag (Note 4)
0 : Terminated normally
1 : Terminated in error
RO
(b4-b5)
RW
(i = A, B)
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers will occur before
writing “1” after writing “0”. While in EW0 mode, write to this bit from a program in other than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no interrupts or no
DMA transfers will occur before writing “1” after writing “0”.
Note 3: Write to this bit from a program in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMOSi01 bit = 1 (CPU rewrite mode). If the FMOSi01 bit = 0, although the FMOSiSTP bit can be
set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode nor initialized.
Figure 19.5-1. Register FMOSA0/FMOSB0/FMSEL
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Flash memory (OSD1/OSD2) control register 1
b7
b6
0
b5
b4
0
0
b3
b2
b1
b0
Symbol
0
FMOSi1
Bit symbol
Address
After reset
02A516/02B516
0X00XX0X 2
Bit name
Function
W
RRW
Reserved bit
Undeterminate when it reads
RO
EW1 mode select bit
(Note 1)
0: EW0 mode
1: EW1 mode
RW
(b3-b2)
Reserved bit
Undeterminate when it reads
RW
(b5-b4)
Reserved bit
Must always be set to “0”
RW
(b0)
FMOSi11
(b6)
Nothing is assigned.
When write, set to “0”. When read, their contents are “0”.
(b7)
Reserved bit
Must always be set to “0”
RW
Note 1: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no interrupts or no
DMA transfers will occur before writing “1” after writing “0.”
Both of bits FMR01 and FMR11 will be set to "0" if bit FMOSi01 is set to "0."
Flash memory (OSD1/OSD2) control register 4
b7
0
b6
b5
b4
0
0 0 0
b3
b2
b1
b0
Symbol
Address
FMOSi4
02A316/02B316
After reset
0100000012
Bit symbol
Bit name
FMOSi40
Erase suspend functional
permission bit (Note 1)
FMOSi41
Erase suspend request bit 0 : Erase restart
1 : Suspend request
(Note 2)
RW
Reserved bit
RW
(b5-b2)
FMOSi46
(b7)
Erase status
Reserved bit
Function
0 : Enable
1 : Disable
Must always be set to “0”
W
RRW
RO
0 : Under automatic elimination operation
RW
1 : Automatic elimination stop
(Erase suspension mode)
Must always be set to “0”
RW
(i = A, B)
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers will occur before
writing “1” after writing “0”.
Note 2: This bit becomes effective only when erase suspend permission bit (FMOSi40) is “1”, and it is that only the period
from erase command issue to an erase end can be written in. (It is set to “1” except the above-mentioned period.)
In the EW0 mode, “0” and “1” writing of this bit are attained by the program.
In the EW1 mode, if maskable interruption occurs during elimination when bit of FMOSi40 are “1”, it will be
automatically set to “1.” “1” cannot be written in by the program (“0” writing is possible.)
Figure 19.5-2. Registers FMOSA1, FMOSB1, FMOSA4 and FMOSB4
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EW0 mode operation procedure
Rewrite control program
Single-chip mode, memory expansion
mode, or boot mode
For only boot mode
set the FMR05 bit to “1” (user ROM area access)
Transfer a CPU rewrite mode based rewrite control
program to any area other than the flash memory
(Note 5)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)
Execute software commands
Set CM0, CM1, and PM1 registers (Note 1)
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory)
Execute the Read Array command
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write “0” to the FMR05 bit (Boot ROM area
accessed) (Note 4)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6 bits.
Also, set the PM1 register’s PM17 bit to “1” (with wait state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA
transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory.
Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to “1”.
Note 5: When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the
PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4M-byte mode, the extended
accessible area (5000016 to BFFFF16) cannot be used.
Figure 19.6. Setting and Resetting of EW0 Mode
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EW1 mode operation procedure
Program in ROM
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit by writing “0” and then “1” (CPU
rewrite mode enabled)
Set the FMR11 bit by writing “0” and then “1” (EW1
mode) (Note 3)
Execute software commands
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Notes 1: In EW1 mode, do not set the microcomputer in memory expansion or boot mode
.
2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to CM16 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait
state).
3: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
When setting the FMR11 bit to “1”, write “1” to this bit immediately after writing “0”
while the FMR01 bit is set to “1”. Do not generate an interrupt or a DMA transfer until
“1” is written after writing “0”.
Figure 19.7. Setting and Resetting of EW1 Mode
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Low power dissipation
mode program
Transfer a low power dissipation mode program
to any area other the flash memory
Jump to the low power dissipation mode program
which has been transferred to any area other the
flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled)
Set FMSTP bit to “1”
(flash memory stopped. Low power state)(Note 1)
Switch the clock source for CPU clock.
Turn main clock off. (Note 2)
Process of low power dissipation mode
Turn main clock on wait until oscillation stabilizes
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to “0” (flash memory operation)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (tPS)
(Note 3)
Jump to a specified address in the flash memory
Notes 1: Set the FMSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).
2: Before the clock source for CPU clock can be changed to
main clock or sub clock, the clock to which to be changed
must be stable.
3: Insert a tPS wait time in a program. The flash memory
cannot be accessed during this wait time
.
4: Before entering wait mode or stop mode, be sure to set the FMR01 bit to "0".
Figure 19.8. Processing Before and After Low Power Dissipation Mode
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Precautions on CPU Rewrite Mode
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using
the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17
bit in the PM1 register to “1” (with wait state).
(2) Instructions to Prevent from Using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
(3) Interrupt (EW0 Mode)
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
• The watchdog timer interrupts can be used because the FMR0 register and FMR1 register are
initialized when one of those interrupts occurs. The jump addresses for those interrupt service
routines should be set in the fixed vector table.
When a monitor timer interrupt is generated, the rewriting operation ends. Execute the rewriting
program again after an interrupt routine ends.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
(4) Interrupt (EW1 Mode)
• Make sure that any interrupt which has a vector in the variable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
(5) How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary
to ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”.
(6) Rewrite user ROM area (EW0 Mode)
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
(7) Rewrite user ROM area (EW1 Mode)
• Avoid rewriting any block in which the rewrite control program is stored.
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(8) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
(9) Writing Command and Data
Write the command code and data at even addresses.
(10) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing
the WAIT instruction.
(11) Stop Mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
0, CM1
; Stop mode
JMP.B
L1
L1:
Program after returning from stop mode
(12) Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program software command
• Read lock bit status
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Software Commands
Software commands are described below. The command code and data must be read and written in 16bit units, to and from even addresses in the user ROM area. When writing command code, the 8 highorder bits (D15–D8) are ignored.
Table 19.4. Software Commands
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D15 to D0)
Mode
Address
Data
(D15 to D0)
Read array
Write
X
xxFF16
Read status register
Write
X
xx7016
Read
X
SRD
Clear status register
Write
X
xx5016
Program
Write
WA
xx4016
Write
WA
WD
Write
X
xx2016
Write
BA
xxD016
Erase all unlocked block
Write
X
xxA716
Write
X
xxD016
Lock bit program (Note 2)
Write
BA
xx7716
Write
BA
xxD016
Read lock bit status (Note 2)
Write
X
xx7116
Write
BA
xxD016
Block erase
(Note 1, 2)
Note 1: It is only blocks 0 to 12 that can be erased by the Erase All Unlocked Block command.
Block A cannot be erased. Use the Block Erase command to erase block A.
Note 2: It can perform only to USER area. The execution to OSD area serves as error.
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address
as the write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
xx: High-order 8 bits of command code (ignored)
Read Array Command (FF16)
This command reads the flash memory.
Writing ‘xxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read
address in the next or subsequent bus cycles, and the content of the specified address can be read in
16-bit units.
Because the microcomputer remains in read array mode until another command is written, the contents of multiple addresses can be read in succession.
Read Status Register Command (7016)
This command reads the status register.
Write ‘xx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
to “Status Register.”) When reading the status register too, specify an even address in the user ROM
area.
Do not execute this command in EW1 mode.
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Clear Status Register Command (5016)
The clear status register command clears the status register. By writing "xx50h" in the first bus cycle,
the FMR07 to FMR06 bits in the FMR0 register are set to "00b" and the SR5 to SR4 bits in the status
register are set to "00b".
Program Command (4016)
This command writes data to the flash memory in 1 word (2 byte) units.
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is
“0” during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check.”)
Additional writing to the programmed address cannot be performed. Figure 19.9 shows the program
flow chart. Also, each block can disable a program by the lock bit.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to
“0” at the same time auto programming starts, and set back to “1” when auto programming finishes. In
this case, the microcomputer remains in read status register mode until a read command is written
next. The result of auto programming can be known by reading the status register after auto programming has finished.
Start
Write the command code ‘xx4016’
to the write address
Write data to the write address
FMR00=1?
NO
YES
Full status check
Program
completed
Note: Write the command code and data at even number.
Figure 19.9. Program Command
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Block Erase
Write ‘xx2016’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” (busy) during auto erasing and set to “1" (ready) when auto erasing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing
can be known. (Refer to “Full Status Check.”)
Figure 19.10 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
Writing over already programmed addresses is inhibited.
In EW1 mode, do not execute this command on any address at which the rewrite control program is
located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at
the same time auto erasing starts, and set back to “1” when auto erasing finishes. In this case, the
microcomputer remains in read status register mode until the Read Array or Read Lock Bit Status
command is written next.
Start
Write the command code ‘xx2016’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Block erase completed
Note: Write the command code and data at even number.
Figure 19.10. Block Erase Command
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Erase All Unlocked Block (User area only)
Write ‘xxA716’ in the first bus cycle and write ‘xxD016’ in the second bus cycle, and all blocks except
block A will be erased successively, one block at a time.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished. The result of the auto erase
operation can be known by inspecting the FMR0 register’s FMR07 bit.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”)
In EW1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the
rewrite control program is stored, or when the FMR0 register’s FMR02 bit = 1 (lock bit disabled).
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing
starts, making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0”
(busy) at the same time auto erasing starts, and set back to “1” (ready) when auto erasing finishes. In
this case, the microcomputer remains in read status register mode until the Read Array or Read Lock
Bit Status command is written next.
Note that only blocks 0 to 12 can be erased by the Erase All Unlocked Block command. Block A
cannot be erased. Use the Block Erase command to erase block A.
Lock Bit Program Command (User area only)
This command sets the lock bit for a specified block to “0” (locked).
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that
is specified in the second bus cycle.
Figure 2.11 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can be
read using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
Refer to “Data protect function” for the lock bit function and how to set the lock bit to “1” (unlocked
status).
Start
Write command code ‘xx7716’ to
the uppermost block address
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Lock bit program completed
Note: Write the command code and data at even number.
Figure 19.11. Lock Bit Program Command
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Read Lock Bit Status Command (User area only)
This command reads the lock bit status of a specified block.
Write ‘xx7116’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even
address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the
FMR1 register’s FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1”
(ready).
Figure 19.12 shows an example of a read lock bit status flowchart.
Start
Write the command code ‘xx7116’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
FMR16=0?
NO
YES
Block locked
Blocks not locked
Note: Write the command code and data at even number.
Figure 19.12. Read Lock Bit Status Command
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Data Protect Function (User area only)
Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit =
0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against programming and erasure. This helps to prevent data from inadvertently written to or erased from the flash
memory. The following shows the relationship between the lock bit and the block status.
• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased.
The lock bit is cleared to “0” (locked) by executing the Lock Bit Program command, and is set to “1”
(unlocked) by erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command
The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function
(lock bit data retained).
If the Block Erase or Erase All Unlocked Block command is executed while the FMR02 bit = 1, the target
block or all blocks are erased irrespective of how the lock bit is set. The lock bit for each block is set to “1”
after completion of erasure.
For details about the commands, refer to “Software Commands.”
Status Register
The status register indicates the operating status of the flash memory and whether an erase or programming operation terminated normally or in error. The status of the status register can be known by reading
bit 0, bit 6 and bit 7 of the FMR0, FMOSA0 and FMOSB0 registers.
A status register exists in each to three area of USER/OSD1/OSD2. In order to read the right result, it is
necessary to choose an object area by FMSEL0 and FMSEL1 before command execution.
Table 19.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register
command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase,
Erase All Unlocked Block, or Lock Bit Program command but before executing the Read Array
command.
Sequencer Status (SR7 and FMR00/FMOSA00/FMOSB00 Bits)
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation
finishes.
Erase Status (SR5 and FMR07/FMOSA07/FMOSB07 Bits)
Refer to “Full Status Check.”
Program Status (SR4 and FMR06/FMOSA06/FMOSB06 Bits)
Refer to “Full Status Check.”
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Table 19.5. Status Register
Status
register
bit
SR7 (D7)
"0"
"1"
Value
after
reset
Busy
Ready
1
Reserved bit
-
-
Flash memory
control
register0
Status name
bit0
Sequencer status
SR6 (D6)
Contents
SR5 (D5)
bit7
Erase status
Terminated normally
Terminated in error
0
SR4 (D4)
bit6
Program status
Terminated normally
Terminated in error
0
SR3 (D3)
Reserved bit
-
-
SR2 (D2)
Reserved bit
-
-
SR1 (D1)
Reserved bit
-
-
SR0 (D0)
Reserved bit
-
-
• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.
• SR5 and SR4 are cleared to “0” by executing the Clear Status Register command.
• When SR5 or SR4 = 1, the Program, Block Erase, Erase All Unlocked Block, and Lock Bit Program
commands are not accepted.
• Flash memory control register exists independently to each area of USER, OSD1, and OSD2, and serves
as FMR0, FMOSA0, and FMOSB0, respectively.
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Full Status Check
When an error occurs, the bit 6 to 7 of the Flash memory control register are set to “1”, indicating
occurrence of each specific error. Therefore, execution results can be verified by checking these
status bits (full status check). Table 19.6 lists errors and FMR0, FMOSA0, and FMOSB0 register
status. Figure 19.13 shows a full status check flowchart and the action to be taken when each error
occurs.
Table 19.6. Errors and the Flash Memory Control Register Status
Flash memory
control register
(status register)
status
(SR5)
(SR4)
1
1
Error
Error occurrence condition
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be written in the second bus cycle of the Lock Bit Program, Block Erase,
or Erase All Unlocked Block command (i.e., other than ‘xxD016’ or
1
0
Erase error
0
1
Program error
‘xxFF16’) (Note 1)
• When the Block Erase command was executed on locked blocks
(Notes 2, 3)
• When the Block Erase or Erase All Unlocked Block command
was executed on unlocked blocks but the blocks were not automatically erased correctly
• When the Block Erase command was executed on locked blocks
(Notes 2, 3)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not programmed correctly (Note 3)
Note 1: Writing ‘xxFF16’ in the second bus cycle of these commands places the microcomputer in read array
mode, and the command code written in the first bus cycle is nullified.
Note 2: When the 02 bit = 1 (lock bit disabled), no error will occur under this condition.
Note 3: It does not correspond, when it performs to OSD1 or OSD2 area, and error is not generated.
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M306V8FJFP
Full status check
bit6 =1
and
bit7=1?
YES
Command
sequence error
(1) Execute the Clear Status Register command to set
these status flags to “0”.
(2) Reexecute the command after checking that it is
entered correctly.
NO
bit7=
0?
NO
Erase error
YES
bit6=
0?
NO
Program error
YES
Full status check completed
(1) Execute the Clear Status Register command to set
the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the Flash Memory Control register’s 02 bit to “1”.
(3) Reexecute the Block Erase or Erase All Unlocked
Block command.
Note 1: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During programming]
(1) Execute the Clear Status Register command to set
the program status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the Flash Memory Control register’s 02 bit to “1”.
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During lock bit programming]
(1) Execute the Clear Status Register command to set
the program status flag to “0”.
(2) Set the Flash Memory Control register’s 02 bit to “1”.
(3) Execute the Block Erase command to erase the
block in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error
cannot be used.
Note 4: If bit 06 or 07 = 1, any of the Program, Block Erase, Erase All Unlocked Block, Lock
Bit Program, or Read Lock Bit Status command is not accepted. Execute the Clear
Status Register command before executing those commands.
Figure 19.13. Full Status Check and Handling Procedure for Each Error
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M306V8FJFP
Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is
mounted on-board by using a serial programmer suitable for the M16C/6V8 group. For more information
about serial programmers, contact the manufacturer of your serial programmer. For details on how to use,
refer to the user’s manual included with your serial programmer.
Table 19.7 lists pin functions (flash memory standard serial input/output mode). Figures 19.14 to 19.16
show pin connections for standard serial input/output mode.
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the
flash memory match. (Refer to the description of the functions to inhibit rewriting flash memory version.)
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Table 19.7. Pin Functions (Flash Memory Standard Serial I/O Mode)
Name
Pin
VCC1, VCC2,
VCC3, VSS
Please input the guarantee voltage of program erase into pins VCC1,
VCC2, and VCC3. Please input 0V into VSS.
Power input
CNVSS1, CNVSS2 CNVSS
Description
I/O
I
Please connect CNVSS1 to VCC and connect CNVSS2 to VSS.
RESET
Reset input
I
Reset input pin. While RESET pin is "L" level, input a 20 cycle or
longer clock to XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
BYTE
BYTE input
I
Connect this pin to Vss.
P00 to P07
Input port P0
I
Input "H" or "L" level signal or open.
P10 to P17
Input port P1
I
Input "H" or "L" level signal or open.
P20 to P27
Input port P2
I
Input "H" or "L" level signal or open.
P30 to P37
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P47
Input port P4
I
Input "H" or "L" level signal or open.
P51 to P54,
P56, P57
Input port P5
I
Input "H" or "L" level signal or open.
P50
CE input
I
Input "H" level signal.
P55
EPM input
I
Input "L" level signal.
P60 to P63
Input port P6
I
Input "H" or "L" level signal or open.
P64/RTS1
BUSY output
O
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
P65/CLK1
SCLK input
I
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P66/RXD1
RxD input
I
Serial data input pin.
P67/TXD1
TxD output
O
Serial data output pin. (Note 1)
P70 to P77
Input port P7
I
Input "H" or "L" level signal or open.
P82 to P83, P86,
P87
Input port P8
I
Input "H" or "L" level signal or open.
P90 to P91
Input port P9
I
Input "H" or "L" level signal or open.
P103 to P107
Input port P10
I
Input "H" or "L" level signal or open.
Other input pins
Input "H" or "L" level signal.
Other output pins
Please open.
___________
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET
pin is pulled low. Therefore, connect this pin to VCC1 via a resistor. Because this pin is directed for
data output after reset, adjust the pull-up resistance value in the system so that data transfers will
not be affected.
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VCC2
M306V8FJFP
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
CNVSS2
VCC3
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
M306V8MJ-XXXFP,
M306V8FJFP
116
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
CE
EPM
BUSY
SCLK
RxD
TxD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Vss
VCC1
CNVss1
RESET
Oscillation
circuit is
connected
Mode setup method
Signal
CNVSS1
EPM
RESET
CE
Value
VCC1
VSS
VSS to VCC2
VCC2
Package: 116P6A-A
Figure 19.14. Pin circuit at the time of standard serial I/O mode
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M306V8FJFP
Example of Circuit Application in the Standard Serial I/O Mode
Figure 19.15 and 19.16 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.
Microcomputer
P65/CLK1
SCLK input
P50(CE)
TXD output
P67/TXD1
BUSY output
P64/RTS1
RXD input
P66/RXD1
Reset input
RESET
P55(EPM)
CNVss1
User reset
signal
(1) Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss1 input with a switch.
(3) If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 19.15. Circuit Application in Standard Serial I/O Mode 1
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Microcomputer
P65/CLK1
TXD output
P67/TXD1
Monitor output
P50(CE)
P55(EPM)
P64/RTS1
RXD input
P66/RXD1
Reset input
RESET
CNVss1
User reset
signal
Note: In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss1 input with a switch.
Figure 19.16. Circuit Application in Standard Serial I/o Mode 2
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M306V8FJFP
Parallel I/O Mode
In parallel input/output mode, the user ROM, OSD ROM, and boot ROM areas can be rewritten by using a
parallel programmer suitable for the M16C/6V8 group. For more information about parallel programmers,
contact the manufacturer of your parallel programmer. For details on how to use, refer to the user’s manual
included with your parallel programmer.
Boot ROM Areas
In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area
contains a standard serial input/output mode based rewrite control program which was written in it when
shipped from the factory. Therefore, when using a serial programmer, be careful not to rewrite the boot
ROM area.
When in parallel output mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other
than the addresses 0FF00016 to 0FFFFF16.)
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)
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M306V8FJFP
Usage Precaution
Reset
When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must meet
the conditions of SVCC.
Symbol
SVCC
Parameter
Min.
Power supply rising gradient (VCC1)
0.05
SVCC
Power supply rising gradient
(VCC1)
V
SVCC
0V
Figure 20.1 Timing of SVCC
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Standard
Typ.
Max.
Unit
V/ms
M306V8FJFP
Bus
• The ROMless version can operate only in the microprocessor mode, connect the CNVss1 pin to VCC1.
• When resetting CNVss1 pin with “H” input, contents of internal ROM cannot be read out.
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Power Control
____________
• When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.
• Set the MR0 bit in the TAiMR register (i=0 to 4) to “0” (pulse is not output) to use the timer A to exit stop
mode.
• Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the
next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, depending on a combination of instruction and an execution timing.
• Wait the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main
clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
• Suggestions to reduce power consumption
Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A
current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
A/D converter
When A/D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no VREF connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.
However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,
this measure is not conducive to reducing the power consumption of the chip. If low speed mode or
low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral
function clock stopped when in wait mode), before changing wait mode.
Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not
requested).
Changing the interrupt generate factor refered to here means any act of changing the source, polarity or
timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to
clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 20.2 shows the procedure for changing the interrupt generate factor.
Changing the interrupt source
Disable interrupts (2, 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)
Enable interrupts (2, 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
NOTES :
1. The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
2. Use the I flag for the INTi interrupt (i = 0 to 3).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
3. Refer to 23.5.6 Rewrite the Interrupt Control Register for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 20.2 Procedure for Changing the Interrupt Generate Factor
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M306V8FJFP
DMAC
Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously(1).
Step 2: Make sure that the DMAi is in an initial state(2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
NOTES :
1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set
to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0,” “1”
should be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the
DMAS bit immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written
to the DMAS bit in order to maintain a DMA request which is generated during execution.
2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal
to a value which was written to the TCRi register before DMA transfer start, the DMAi is in an
initial state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi
register is “1”.) If the read value is a value in the middle of transfer, the DMAi is not in an initial
state.
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Timers
Timer A
(1) Timer A (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count
starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, if the counter is read at the same time it is reloaded, the value “FFFFh” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
(2) Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH
bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the
ONSF register and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi
register. However, “FFFFh” can be read in underflow, while reloading, and “0000h” in overflow. When
setting TAi register to a value during a counter stop, the setting value can be read before a counter
starts counting. Also, if the counter is read before it starts counting after a value is set in the TAi
register while not counting, the set value is read.
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(3) Timer A (One-shot Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
When setting TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger has been selected, one-cycle delay of a count source as maximum occurs between a
trigger input to TAiIN pin and output in one-shot timer mode.
The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been
made.
When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a
second trigger between occurring the previous trigger and operating longer than one cycle of a timer
count source.
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(4) Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i
= 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, TA0TGL and TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the PWM mode after reset.
• Change an operation mode from timer mode to PWM mode.
• Change an operation mode from event counter mode to PWM mode.
To use the Timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above
listed changes have been made.
When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H,” output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L,” both output level and the IR bit remains unchanged.
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Timer B
(1) Timer B (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i
= 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless whether after reset or not.
A value of a counter, while counting, can be read in TBi register at any time. “FFFFh” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
(2) Timer B (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i
= 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless whether after reset or not.
The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFFh.” If the TBi
register is read after setting a value in it while not counting but before the counter starts counting, the
read value is the one that has been set in the register.
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M306V8FJFP
(3) Timer B (Pulse Period/pulse Width Measurement Mode)
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5)
register before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while the
TBiS bit = 1 (count starts), be sure to write the same value as previously written to the TM0D0, TM0D1,
MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
The IR bit in the TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or Timer Bi is overflowed. The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
Timer B has overflowed.
To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and counting
the next count source after setting the MR3 bit to “1” (overflow).
Use the IR bit to detect only overflows. Use the MR3 bit only to determine the interrupt factor within the
interrupt routine.
When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and Timer
Bi interrupt request may be generated between a count start and an effective edge input.
For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is an “H” level width or an “L” level width.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 357 of 363
M306V8FJFP
Serial I/O
Clock Synchronous Serial I/O
(1) Transmission/reception
_______
________
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes
to “L” when the data-receivable status becomes ready, which informs the transmission side that the
________
reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So
________
________
if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and
_______
reception data with consistent timing. With the internal clock, the RTS function has no effect.
(2) Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1
(transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer
clock), the external clock is in the low state.
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = L
(3) Reception
In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
settings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TXDi pin when receiving data.
When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission
enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and
the shift clock will be generated when the external clock is fed to the CLKi input pin.
When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the RE bit in the UiC1 register (i = 0 to 2) = 1 (data present in the UiRB register), an
overrun error occurs and the OER bit in the UiRB register is set to “1” (overrun error occurred). In this
case, because the content of the UiRB register is indeterminate, a corrective measure must be taken
by programs on the transmit and receive sides so that the valid data before the overrun error occurred
will be retransmitted. Note that when an overrun error occurred, the IR bit in the SiRIC register does
not change state.
To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external
clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit in the UiC1 register= 1 (reception enabled)
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register= 0 (data present in the UiTB register)
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 358 of 363
M306V8FJFP
A/D Converter
Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a
trigger occurs).
When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref connected), start A/D conversion after passing 1 µs or longer.
When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
When setting the ADST bit in the ADCON0 register to “0” in single-sweep mode during A/D conversion and
aborting A/D conversion, disable the interrupt before setting the ADST bit to “0”.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 359 of 363
M306V8FJFP
Programmable I/O Ports
The input threshold voltage of pins differs between programmable input/output ports and peripheral functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input
level at this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor
“low”), the input level may be determined differently depending on which side—the programmable input/
output port or the peripheral function—is currently selected.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 360 of 363
M306V8FJFP
Flash Memory Version
(1) Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in
standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.
(2) Program Command
Write “xx40h” in the first bus cycle and write data to the write address in the second bus cycle, and an auto
program operation (data program and verify) will start. Make sure the address value specified in the first
bus cycle is the same even address as the write address specified in the second bus cycle.
(3) Lock Bit Program Command
Write “xx77h” in the first bus cycle and write “xxD0h” to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”. Make sure the
address value specified in the first bus cycle is the same uppermost block address that is specified in the
second bus cycle.
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 361 of 363
M306V8FJFP
Noise
Use thick and shortest possible wiring to connect bypass capacitors (0.1µF) between the VCC1 pin and VSS
pin, VCC2 pin and VSS pin, and VCC3 pin and VSS pin.
Figure 20.3 shows the bypass capacitor connection.
Bypass Capacitor
Connecting Pattern
VSS
Connecting Pattern
VCC2
M306V8 Group
VSS
Connecting Pattern
VCC1
Connecting Pattern
Bypass Capacitor
Figure 20.3 Bypass Capacitor Connection
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 362 of 363
M306V8FJFP
Package Outline
116P6A-A
MMP
Plastic 116pin 20✕20mm body LQFP
Weight(g)
1.78
JEDEC Code
–
Lead Material
Cu Alloy
MD
HD
D
ME
b2
e
EIAJ Package Code
LQFP116-P-2020-0.65
l2
116
88
Recommended Mount Pad
1
87
Symbol
E
HE
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
59
29
30
58
A
L1
F
b
x
M
L
Lp
Detail F
Rev.1.31 Apr 18, 2005
REJ03B0082-0131
page 363 of 363
c
y
A1
A2
A3
e
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.125
0.2
0.05
1.4
–
–
0.17
0.22
0.27
0.105
0.125
0.175
19.9
20.0
20.1
19.9
20.0
20.1
0.65
–
–
21.8
22.0
22.2
21.8
22.0
22.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.13
–
0.1
–
0°
8°
–
0.225
–
–
0.95
–
–
–
20.4
–
–
20.4
–
REVISION HISTORY
Rev.
M306V8FJFP
Date
Description
Summary
Page
1.30 Mar 15, 2005
–
First edition issued.
1.31 Apr 18, 2005
2
Table 1.1 revised.
25
Table 3.1 partly deleted.
265
Figure 17.5 partly deleted.
295
Table 18.1 partly deleted.
298
Table 18.7 revised.
299
Table 18.8 partly deleted.
A-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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