SPLC502B - NewHaven Display

SPLC502B
132 x 65 Dot Matrix LCD Driver
MAR. 30, 2007
Version 1.0
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SPLC502B
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4
2. FEATURES.................................................................................................................................................................................................. 4
3. ORDERING INFORMATION........................................................................................................................................................................ 5
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 5
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
5.1.
POWER SUPPLY PINS .......................................................................................................................................................................... 6
5.2.
LCD POWER SUPPLY CIRCUIT TERMINALS ........................................................................................................................................... 6
5.3.
SYSTEM BUS CONNECTION TERMINALS................................................................................................................................................ 7
5.4.
LIQUID CRYSTAL DRIVE TERMINALS ...................................................................................................................................................... 9
5.5.
TEST TERMINALS ................................................................................................................................................................................ 9
6. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 10
6.1.
THE MPU INTERFACE ........................................................................................................................................................................ 10
6.2.
THE CHIP SELECT ..............................................................................................................................................................................11
6.3.
ACCESSING THE DISPLAY DATA RAM AND THE INTERNAL REGISTERS ...................................................................................................11
6.4.
THE BUSY FLAG .................................................................................................................................................................................11
6.5.
DISPLAY DATA RAM .......................................................................................................................................................................... 12
6.6.
THE DISPLAY DATA LATCH CIRCUIT .................................................................................................................................................... 14
6.7.
THE OSCILLATOR CIRCUIT ................................................................................................................................................................. 14
6.8.
THE COMMON OUTPUT STATUS SELECT............................................................................................................................................. 14
6.9.
DISPLAY TIMING GENERATOR CIRCUIT ............................................................................................................................................... 14
6.10. THE LIQUID CRYSTAL DRIVER CIRCUITS ............................................................................................................................................. 16
6.10. THE LIQUID CRYSTAL DRIVER CIRCUITS ............................................................................................................................................. 16
6.11. THE POWER SUPPLY CIRCUITS .......................................................................................................................................................... 17
6.12. HIGH POWER MODE .......................................................................................................................................................................... 20
6.13. THE INTERNAL POWER SUPPLY SHUTDOWN COMMAND SEQUENCE ..................................................................................................... 20
6.14. REFERENCE CIRCUIT EXAMPLES ....................................................................................................................................................... 21
6.15. THE RESET CIRCUIT .......................................................................................................................................................................... 23
7. COMMANDS ............................................................................................................................................................................................. 23
7.1.
DISPLAY ON/OFF ............................................................................................................................................................................. 24
7.2.
DISPLAY START LINE SET .................................................................................................................................................................. 24
7.3.
PAGE ADDRESS SET .......................................................................................................................................................................... 24
7.4.
COLUMN ADDRESS SET ..................................................................................................................................................................... 25
7.5.
STATUS READ ................................................................................................................................................................................... 25
7.6.
DISPLAY DATA WRITE ........................................................................................................................................................................ 26
7.7.
DISPLAY DATA READ .......................................................................................................................................................................... 26
7.8.
ADC SELECT (SEGMENT DRIVER DIRECTION SELECT) ....................................................................................................................... 26
7.9.
DISPLAY NORMAL/REVERSE .............................................................................................................................................................. 26
7.10. DISPLAY ALL POINTS ON/OFF........................................................................................................................................................... 27
7.11. LCD BIAS SET .................................................................................................................................................................................. 27
7.12. READ/MODIFY/WRITE........................................................................................................................................................................ 27
7.13. END................................................................................................................................................................................................. 28
7.14. RESET ............................................................................................................................................................................................ 29
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SPLC502B
7.15. COMMON OUTPUT MODE SELECT ...................................................................................................................................................... 29
7.16. POWER CONTROLLER SET ................................................................................................................................................................ 29
7.17. V0 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO SET ................................................................................................................. 30
7.18. THE ELECTRONIC VOLUME (DOUBLE BYTE COMMAND)....................................................................................................................... 30
7.19. STATIC INDICATOR (DOUBLE BYTE COMMAND).................................................................................................................................... 31
7.20. PAGE BLINKING (DOUBLE BYTE COMMAND)........................................................................................................................................ 31
7.21. SET DRIVING MODE (DOUBLE BYTE COMMAND) ................................................................................................................................. 32
7.22. POWER SAVE (COMPOUND COMMAND) .............................................................................................................................................. 33
7.23. NOP ................................................................................................................................................................................................ 34
7.24. TEST ............................................................................................................................................................................................... 34
7.25. OSCILLATOR FREQUENCY SELECTION ................................................................................................................................................ 34
7.26. TABLE 13 TABLE OF SPLC502B COMMANDS...................................................................................................................................... 35
8. COMMAND DESCRIPTION ...................................................................................................................................................................... 37
8.1.
INSTRUCTION SETUP: REFERENCE (REFERENCE) ............................................................................................................................... 37
9. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 39
9.1.
ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................................... 39
9.2.
DC CHARACTERISTICS ...................................................................................................................................................................... 39
9.3.
DISPLAY PATTERN CHECKER.............................................................................................................................................................. 40
9.4.
DISPLAY PATTERN CHECKER.............................................................................................................................................................. 40
9.5.
TIMING CHARACTERISTICS................................................................................................................................................................. 42
9.6.
THE MPU INTERFACE (REFERENCE EXAMPLES) ................................................................................................................................. 48
9.7.
CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE)........................................................................................................ 50
9.8.
CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES)...................................................................................................... 51
10. VLCD VOLTAGE (VOLTAGE BETWEEN V0 TO VSS) RELATIONSHIP OF V0 VOLTAGE REGULATOR INTERNAL RESISTOR RATIO REGISTER AND
ELECTRONIC VOLUME CONTROL REGISTER .................................................................................................................................................. 52
11. CHIP INFORMATION ................................................................................................................................................................................ 53
11.1. PAD ASSIGNMENT ............................................................................................................................................................................. 53
11.2. PAD DIMENSION ............................................................................................................................................................................... 53
11.3. BUMP CHARACTERISTIC .................................................................................................................................................................... 53
11.4. PAD LOCATIONS ............................................................................................................................................................................... 54
11.5. COG ALIGN KEY COORDINATE .......................................................................................................................................................... 57
12. DISCLAIMER............................................................................................................................................................................................. 58
13. REVISION HISTORY ................................................................................................................................................................................. 59
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SPLC502B
132 x 65 DOT MATRIX LCD DRIVER
1. GENERAL DESCRIPTION
The SPLC502B, a single-chip dot matrix liquid crystal display
„ These chips not designed for resistance to light or Resistance
drivers, is specially designed to connect directly with a
microprocessor bus.
to radiation.
The 8-bit parallel or serial display data sent
„ High-speed 8-bit MPU interface (capability to be connected
from the microprocessor is stored in the internal display data RAM.
directly to the both the 80X86 series MPUs and the 68000
It generates a liquid crystal drive signal independent of the
series MPUs)/Serial interface are supported.
microprocessor.
Since the SPLC502B contains a 65 X 132 bits
„ Wide range of operating temperatures.
of display data RAM, a 1-to-1 correspondence between the liquid
„ CMOS process
crystal panel pixels and the internal RAM bits, it is able to enable
„ CR oscillator circuit equipped internally
displays with a high degree of flexibility.
The SPLC502B contains
(External clock can also be input).
65 common output circuits, 132 segment output circuits and
„ Abundant command functions
therefore, a single chip can drive a 65 X 132 dot display (capable
Display data Read/Write, display ON/OFF, Normal/Reverse
of displaying 8 columns X 4 rows of a 16 X 16 dot kanji font). In
display mode, page address set, display start line set, column
addition, the capacity of the display can also be extended through
address set, status read, display all points ON/OFF, LCD bias
the use of master/slave structures between chips.
The chips can
set, electronic volume, read/modify/write, segment driver
save a great amount of power because no external operating
direction select, power saver, static indicator, common output
clock is required for the display data RAM to read and write
status select, V0 voltage regulation internal resistor ratio set.
operations.
Booster ratio set
Since each chip is equipped internally with a
low-power liquid crystal driver power supply, resistors for liquid
„ Low-power liquid crystal display power supply circuit equipped
crystal driver power voltage adjustment and a display clock CR
internally.
oscillator circuit, the SPLC502B can be used for creating the
Booster circuit (with Boost ratios 2X/3X/4X/5X/6X, where
lowest power display system with the fewest components for high
the step-up voltage reference power supply can be input
performance portable devices.
externally).
High-accuracy voltage adjustment circuit
(Thermal gradient -0.05%/℃).
2. FEATURES
V0 voltage regulator resistors equipped internally,
„ Provide Reduced Capacitor of Follower (V1 ~ V4) function
V1 to V4 voltage divider resistors equipped internally, electronic
„ Direct display of RAM data through the display data RAM.
volume function equipped internally, voltage follower.
‘1’: Non-illuminated.
„ Driving Mode register provided for different size panel loading.
‘0’: Illuminated.
„ Extremely low power consumption.
Low operating power when the built-in power supply is used
„ RAM capacity.
„ Power supply
65 X 132 = 8580 bits.
Operable on the low 1.8 voltage
„ Display driver circuits.
Logic power supply VDD - VSS = 1.8V to 3.6V
SPLC502B: 65 common outputs and 132 segment outputs.
Boost reference voltage: VDD2 - VSS = 1.8V to 3.6V
„ Static drive circuit equipped internally for indicators.
Liquid crystal drive power supply (VLCD):V0 - VSS = 4V to 12V
(1 system, with variable flashing speed.)
Product Name
Duty
Bias
SED Dr
COM Dr
VREG Temperature Gradient
Shipping Forms
SPLC502B
1/65
1/9, 1/7
132
65
-0.05%/℃
Bare Chip with Gold Bump
1/55
1/8, 1/6
132
55
1/49
1/8, 1/6
132
49
1/33
1/6, 1/5
132
33
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SPLC502B
3. ORDERING INFORMATION
Product Number
Package Type
SPLC502B-C
Chip form with Gold Bump
COMS
COM63
COM0
SEG0
SEG131
4. BLOCK DIAGRAM
V0
V1
V2
V3
V4
VSS
COMS
VDD
COM
Drivers
SEG Drivers
COM output
status select
circuit
Display data RAM
132 X 65
circuit
Line address circuit
VDD2
I/O buffer
Power
supply
circuit
Display timing generation
Display data
latch circuit
Page address circuit
FRS
FR
CL
DOF
MS
Column address circuit
Oscillator
HPM
Command
decoder
Bus holder
circuit
VOUT
CAP1P
CAP1N
CAP2P
CAP2N
CAP3P
CAP4P
CAP5P
CLS
Status
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D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
RESET
PS
WR (RWP)
RD (EP)
A0P
CS2
CS1
MPU interface
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SPLC502B
5. SIGNAL DESCRIPTIONS
5.1. Power Supply Pins
Mnemonic
VDD
PIN No.
Type
Description
9, 15
P
VDD Shared with MPU power supply terminal VCC
P
0V terminal connected to the system GND.
P
A reference power supply for the step-up voltage circuit for the liquid crystal drive
P
0V terminal connected to the system GND.
P
A multi-level power supply for the liquid crystal drive.
28 - 26
63 - 62
80
VSS
6
12
34 - 32
59 - 58
74
VDDA
31 - 29
VSSA
37 – 35
61 – 60
57 - 56
V0,
73 - 72
V1,
65 - 64
liquid crystal cell, and is changed through the use of a resistive voltage divided or through
V2,
67 - 66
changing the impedance using an op. amp.
V3,
69 - 68
must maintain the relative magnitudes shown below.
V4,
71 - 70
The voltage applied is determined by the
Voltage levels are determined based on VDD, and
V0 ≧V1≧V2≧V3≧V4≧VSS
Master operation: When the power supply turns ON, the internal power supply circuits generate
the V1 to V4 voltages shown below. The voltage settings are selected by the LCD bias command.
1/65 DUTY
1/55 DUTY
1/49 DUTY
1/33 DUTY
V1
8/9*V0, 6/7*V0
7/8*V0, 5/6*V0
7/8*V0, 5/6*V0
5/6*V0, 4/5*V0
V2
7/9*V0, 5/7*V0
6/8*V0, 4/6*V0
6/8*V0, 4/6*V0
4/6*V0, 3/5*V0
V3
2/9*V0, 2/7*V0
2/8*V0, 2/6*V0
2/8*V0, 2/6*V0
2/6*V0, 2/5*V0
V4
1/9*V0, 1/7*V0
1/8*V0, 1/6*V0
1/8*V0, 1/6*V0
1/6*V0, 1/5*V0
P: Power Supply
5.2. LCD Power Supply Circuit Terminals
Mnemonic
PIN No.
Type
Description
CAP1P
49-48
O
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1N
terminal. The step-up voltage relationships are shown in Fig.7
CAP1N
47-46
O
DC/DC voltage converter. A capacitor is connected between this terminal and the
CAP1P/CAP3P/CAP5P terminal. The step-up voltage relationships are shown in Fig.7
CAP2P
51-50
O
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2N
terminal. The step-up voltage relationships are shown in Fig.7
CAP2N
53-52
O
CAP3P
45-44
O
CAP4P
41,54,55
O
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2P/CAP4P
terminal. The step-up voltage relationships are shown in Fig.7
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1N
terminal.
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP2N
terminal. The step-up voltage relationships are shown in Fig.7
CAP5P
43-42
O
DC/DC voltage converter. A capacitor is connected between this terminal and the CAP1N
terminal. The step-up voltage relationships are shown in Fig.7
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SPLC502B
Mnemonic
VOUT
PIN No.
Type
40-38
O
Description
DC/DC voltage converter. A capacitor is connected between this terminal and VSS.
5.3. System Bus Connection Terminals
Mnemonic
DB7 - 0
PIN No.
Type
23-16
I/O
(SI) (SCL)
Description
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus.
When the serial interface is selected (PS = ‘L’), DB7 serves as the serial data input terminal (SI)
and DB6 serves as the serial clock input terminal (SCL).
high impedance.
A0P
11
I
At the same time, DB5 - 0 are set to
When the chip select is inactive, DB0 to DB7 are set to high impedance.
This is connected to the least significant bit of the normal MPU address bus, and it determines
whether the data bits are data or a command.
A0P = ‘H’: Indicates DB7 - 0 is display data.
A0P = ‘L’: Indicates DB7 - 0 is control data.
RESET
10
I
When RESET is set to ‘L’, the settings are initialized.
The RESET signal level performs the reset operation.
CS1
7
CS2
8
RD (EP)
14
I
This is the chip select signal.
When CS1 = ‘L’ and CS2 = ‘H’, the chip select becomes active,
and data/command I/O is enabled.
I
When connected to an 8080 MPU, this is LOW active.
This pin is connected to the RD signal of
the 8080 MPU, and the SPLC502B data bus is in an output status when this signal is ‘L’.
When connected to a 6800 Series MPU, this is HIGH active.
This is the 68000 Series MPU
enable clock input terminal.
WR (RWP)
13
I
When connected to an 8080 MPU, this is LOW active.
This terminal connects to the 8080 MPU
WR signal. The signals on the data bus are latched at the rising edge of the WR signal.
When connected to a 6800 Series MPU:
This is the read/write control signal input terminal.
When RWP = ‘H’: Read.
When RWP = ‘L’: Write.
C86
77
I
This is the MPU interface switch terminal.
C86 = ‘H’: 6800 Series MPU interface.
C86 = ‘L’: 8080 MPU interface.
PS
78
I
This is the parallel data input/serial data input switch terminal.
PS = ‘H’: Parallel data input.
PS = ‘L’: Serial data input.
The following applies depending on the PS status:
PS
Data/Command
Data
Read/Write
Serial Clock
'H'
A0P
DB0 to DB7
RD , WR
Write only
SCL (DB6)
'L'
A0P
SI(DB7)
When PS = ‘L’, DB0 to DB5 are high impedance.
(EP) and WR (RWP) are fixed to either ‘H’ or ‘L’.
DB0 to DB5 may be ‘H’, ‘L’ or Open.
RD
With serial data input, RAM display data
reading is not supported.
CLS
76
I
Terminal to select whether to enable or disable the display clock internal oscillator circuit.
CLS = ‘H’: Internal oscillator circuit is enabled.
CLS = ‘L’: Internal oscillator circuit is disabled (requires external input).
When CLS = ‘L’, input the display clock through the CL terminal.
FR
3
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I/O
This is the liquid crystal alternating current signal I/O terminal.
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SPLC502B
Mnemonic
PIN No.
Type
Description
MS = ‘H’: Output
MS = ‘L’: Input
When the SPLC502B chip is used in master/slave mode, the various FR terminals must be
connected.
MS
75
I
This terminal selects the master/slave operation for the SPLC502B chips. Master operation
outputs the timing signals that are required for the LCD display, while slave operation inputs the
timing signals required for the liquid crystal display, synchronizing the liquid crystal display
system.
MS = ‘H’: Master operation
MS = ‘L’: Slave operation
The following is true depending on the MS and CLS status:
CLS
Oscillator
Circuit
Supply Circuit
'H'
'H'
Enabled
'L'
'L'
CL
4
I/O
Power
MS
CL
FR
FRS
DOF
Enabled
Output
Output
Output
Output
Disabled
Enabled
Input
Output
Output
Output
'H'
Disabled
Disabled
Input
Input
Output
Input
'L'
Disabled
Disabled
Input
Input
Output
Input
This is the display clock input terminal
The following is true depending on the MS and CLS status.
MS
CLS
CL
'H'
'H'
Output
'L'
Input
'H'
Input
'L'
Input
'L'
When the SPLC502B chips are used in master/slave mode, the various CL terminals must be
connected.
DOF
5
I/O
This is the liquid crystal display blanking control terminal.
MS = ‘H’: Output
MS = ‘L’: Input
When the SPLC502B chip is used in master/slave mode, the various DOF terminals must be
connected.
FRS
2
O
This is the output terminal for the static drive. This terminal is only enabled when the static
indicator display is ON when in master operation mode, and is used in conjunction with the FR
terminal.
HPM
79
I
This is the power control terminal for the power supply circuit for liquid crystal drive.
HPM = ‘H’: Normal mode.
HPM = ‘L’: High power mode.
This pin is enabled only when the master operation mode is selected.
It is fixed to either ‘H’ or
‘L’ when the slave operation mode is selected. The detailed application circuit can refer 5.14.
DSEL1-0
25-24
I
These pins can provide duty selection.
DSEL1
1
1
0
0
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DSEL0
1
0
1
0
DUTY RATIO
1/65
1/55
1/49
1/33
8
BIAS
1/9 or 1/7
1/8 or 1/6
1/8 or 1/6
1/6 0r 1/5
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SPLC502B
5.4. Liquid Crystal Drive terminals
Mnemonic
PIN No.
Type
Description
SEG131 - 0
258-127
O
These are the liquid crystal segment drive outputs. Through a combination of the contents of the
display RAM and with the FR signal, a single level is selected from V0, V2, V3, and VSS.
FR
H
H
V0
H
L
VSS
V3
L
H
V2
V0
L
L
V3
Power save
COM31 – 0
94-125
COM32-63
259-290
O
Output Voltage
RAM DATA
Normal Display
Reverse Display
V2
VSS
VSS
-
These are the liquid crystal common drive outputs.
Part No.
COM
SPLC502
COM63 - 0
Through a combination of the contents of the scan data and with the FR signal, a single level is
selected from V0, V1, V4, and Vss.
COMS
126, 291
O
Scan Data
FR
Output Voltage
H
H
H
L
V0
L
H
V1
L
L
V4
Power Save
-
VSS
VSS
These are the COM output terminals for the indicator.
Leave these pins open if they are not used.
Both terminals output the same signal.
When in master/slave mode, the same signal is
output by both master and slave.
5.5. Test Terminals
Mnemonic
PIN No.
Type
1
I
This is terminal for IC chip testing only, please tie to VSS.
TEST5, TEST6
81,82
O
These are terminals for IC chip testing only.
DUMY1~DUMY11
83~93
I
These are terminals for IC chip testing only.
TEST
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SPLC502B
6. FUNCTIONAL DESCRIPTIONS
6.1. The MPU Interface
6.1.1. Selecting the interface type
For SPLC502B, data transfers are accomplished through an 8-bit
to select either parallel data input or serial data input as shown in
bi-directional data bus (DB7 - 0) or through a serial data input (SI).
Table 1.
By selecting the PS terminal polarity to the ‘H’ or ‘L’, it is possible
Table 1
PS
CS1
CS2
A0P
RD
WR
C86
DB7
DB6
DB5 - 0
H: Parallel Input
CS1
CS2
A0P
RD
WR
C86
DB7
DB6
DB5 - 0
L: Serial Input
CS1
CS2
A0P
-
-
-
SI
SCL
(HiZ)
‘-‘ indicates fixed to either ‘H’ or to ‘L’
6.1.2. The parallel interface
When the parallel interface is selected (PS = ‘H’), it is possible to
MPU (as shown in Table 2) by selecting the C86 terminal to either
connect directly to either an 8080-system MPU or a 6800 Series
‘H’ or ‘L’.
Table 2
C86
CS1
CS2
A0P
RD
WR
DB7 - 0
H: 6800 Series MPU Bus
CS1
CS2
A0P
EP
RWP
DB7 - 0
L: 8080 MPU Bus
CS1
CS2
A0P
RD
WR
DB7 - 0
Data bus signals are recognized by a combination of A0P, RD (EP), WR (RWP) signals, shown in Table 3.
Table 3
Shared
6800 Series
8080 Series
A0P
WRP
RD
WR
1
1
0
1
Function
Read the display data
1
0
1
0
Write the display data
0
1
0
1
Read Status
0
0
1
0
Write control data (command)
6.1.3. The serial interface
When the serial interface is selected (PS = ‘L’) and when the chip
The A0P input determines whether the serial data input is display
is in active state ( CS1 = ‘L’ and CS2 = ‘H’), the serial data input (SI)
data or command data; when A0P = ‘H’, the data is display data,
and the serial clock input (SCL) can be received.
and when A0P = ‘L’, the data is command data.
The serial data
The A0P input is
is read from the serial data input pin at the rising edge of the serial
read and used for detecting every 8th rising edge of the serial
clocks DB7, DB6 through DB0 in order.
clock after the chip is active.
The data is converted to
8-bit parallel data at the rising edge of the eighth serial clock.
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SPLC502B
CS1
CS2
SI
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
8
9
10
11
12
13
14
SCL
1
2
3
4
5
6
7
A0P
Figure 1: serial interface signal chart.
Note1: When the chip is not active, the shift registers and counter are reset to their initial states.
Note2: Reading is not acceptable in serial interface mode.
Note3: Caution is required on the SCL signal when it comes to line-end reflections and external noise.
ORISE recommends that operation should be
rechecked on the actual equipment.
6.2. The Chip Select
Writing
The SPLC502B have two chip-select-terminals: CS1 and CS2.
MPU
WR
The MPU interface or the serial interface is enabled only when
Internal Timing
DATA
CS1 = ‘L’ and CS2 = ‘H’.
N
N+1
N+3
N
N+1
N+2
N+3
Write Signal
When the chip select is inactive, DB7 - 0 enter into a high
Reading
impedance state, and the A0P, RD , and WR inputs are inactive.
WR
MPU
When the serial interface is selected, the shift register and the
counter are reset.
RD
DATA
N
N
n
n+1
Address Preset
INternal Timing
6.3. Accessing the Display Data RAM and the Internal
Registers
Data transferring at a high speed is ensured since the MPU is
Read Signal
Column Address
Preset N
Bus Holder
N
required to satisfy the cycle time (tCYC) requirement alone in
accessing the SPLC502B.
N+2
Latch
BUS Holder
Address Set
#n
Increment N+1
n
Dummy
Read
N+2
n+1
Data Read
#n
n+2
Data Read
#n+1
Wait time may not be considered.
Also, in SPLC502B chips, each time data is sent from MPU.
A
Figure2
type of pipeline process between LSIs is performed through the
bus holder attached to the internal data bus.
6.4. The Busy Flag
For example, when
the MPU writes data to the display data RAM, once the data is
When the busy flag is ‘1’, it indicates that the SPLC502B is
stored in the bus holder, it is written to the display data RAM
running internal processes.
before the next data write cycle.
from a status read will be received.
The busy flag is outputted to
the display data RAM, the first data read cycle (dummy) stores the
DB7 pin with the read instruction.
If the cycle time (tCYC) is
read data in the bus holder, and then the data is read from the bus
remained, it is not necessary to check for this flag before each
holder to the system bus at the next data read cycle.
command.
Moreover, when the MPU reads
There is a
At this moment, no command aside
This makes vast improvements in MPU processing
capabilities possible.
certain restriction in the read sequence of the display data RAM.
Note that data of the specified address is not generated by the
read instruction issued immediately after the address setup. This
data is generated in data read of the second time.
Thus, a
dummy read is required whenever the addresses setup or write
cycle operation is conducted.
This relationship is shown in
Figure 2.
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SPLC502B
6.5. Display Data RAM
6.5.1. Display data RAM
6.5.3. The column addresses
The display data RAM is a RAM that stores the dot data for the
As is shown in Figure 4, the display data RAM column address is
display.
specified by the Column Address Set command.
It has a 65 (8 page x 8 bit +1) x 132-bit structure.
It is
The specified
possible to access the desired bit by specifying the page address
column address is incremented (+1) with each display data
and the column address.
read/write command.
Because, as is shown in Figure 3, the
This allows the MPU display data to be
DB7 - 0 display data from the MPU corresponds to the liquid
accessed continuously.
crystal display common direction, there are few constraints at the
addresses stops with 83H.
time of display data transfer when multiple SPLC502B chips are
depends
used.
the page address and the column address when moving, for
Therefore, display structures can be created easily and
with a high degree of freedom.
on
Moreover, the increment of column
Because the column address
the page address, it is necessary to re-specify both
example, from page 0 column 83H to page 1 column 00H.
Furthermore, as is shown in Table 4, the ADC command (segment
D0
D1
D2
D3
D4
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
driver direction select command) can be used to reverse the
COM0
COM1
COM2
COM3
0
0
0
0
0
relationship between the display data RAM column address and
the segment output.
layout when the LCD module is assembled can be minimized.
COM4
Display data RAM
Because of this, the constraints on the IC
Table 4
Liquid crystal display
SEG Output
Figure 3
Moreover, reading from and writing to the display RAM in the MPU
SEG0
SEG131
ADC ‘0’
0 (H) Æ
Column Address Æ83(H)
(DB0) ‘1’
83(H) Å
Column Address Å 0(H)
side is performed through the I/O buffer, which is an independent
operation from signal reading for the liquid crystal driver.
6.5.4.
The line address circuit
Consequently, even if the display data RAM is accessed
The line address circuit, as shown in Figure 4, specifies the line
asynchronously during liquid crystal display, it will not cause
address relating to the COM output when the contents of the
adverse effects on the display (such as flickering).
display data RAM are displayed.
Using the display start line
address set command, which is normally the top line of the display
6.5.2. The page address circuit
can be specified.
As shown in Figure 4, page address of the display data RAM is
output mode is normal and the COM63 output for SPLC502B
specified through the Page Address Set Command.
when the common output mode is reversed.
The page
This is the COM0 output when the common
The display area is
address must be specified again when changing pages to perform
a 65-line area for the SPLC502B from the display start line
access. Page address 8 (DB3, DB2, DB1, DB0 = 1, 0, 0, 0) is
address.
the page for the RAM region used only by the indicators, and only
the display start line address set command, screen scrolling, page
display data DB0 is used.
swapping, …etc. can be performed.
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If the line addresses are changed dynamically using
MAR. 30, 2007
Version: 1.0
SPLC502B
83
82
81
80
7F
7E
7D
7C
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
48 lines
54 lines
64 lines
32 lines
Column
Address
P age 8
D0
0
ADC
0
D0
0
0
1
P age 7
1
1
W h e n th e
c o m m o n o u tp u t
m o d e is n o rm a l
COM
O u tp u t
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
C O M 10
C O M 11
C O M 12
C O M 13
C O M 14
C O M 15
C O M 16
C O M 17
C O M 18
C O M 19
C O M 20
C O M 21
C O M 22
C O M 23
C O M 24
C O M 25
C O M 26
C O M 27
C O M 28
C O M 29
C O M 30
C O M 31
C O M 32
C O M 33
C O M 34
C O M 35
C O M 36
C O M 37
C O M 38
C O M 39
C O M 40
C O M 41
C O M 42
C O M 43
C O M 44
C O M 45
C O M 46
C O M 47
C O M 48
C O M 49
C O M 50
C O M 51
C O M 52
C O M 53
C O M 54
C O M 55
C O M 56
C O M 57
C O M 58
C O M 59
C O M 60
C O M 61
C O M 62
C O M 63
CMOS
R eg ard les s of th e d is p lay
s tart lin e ad d res s , th e
1 /6 5 d u ty a c e s s e s 6 4 lin e s
1 /5 5 d u ty a c e s s e s 5 4 lin e s
1 /4 9 d u ty a c e s s e s 4 8 lin e s
1 /3 3 d u ty a c e s s e s 3 2 lin e s
LCD
Out
1
83
1
82
0
P age 6
00
0
SEG131
1
81
1
01
0
P age 5
SEG130
1
80
0
02
1
SEG129
0
P age 4
7F
0
03
0
SEG128
1
7E
0
P age 3
04
1
05
1
SEG127
0
SEG126
0
P age 2
7C
0
7D
1
06
0
07
0
P age 1
SEG125
1
SEG124
0
07
0
06
0
P age 0
04
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
05
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
03
0
L in e
A d d re ss
00
0
D a ta
02
P a g e A d d re ss
D2
D1
D0
01
D3
Figure 4
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SPLC502B
6.6. The Display Data Latch Circuit
6.7. The Oscillator Circuit
The display data latch circuit temporarily stores the display data
This is a CR-type oscillator that produces the display clock.
that is output to the liquid crystal driver circuit from the display
oscillator circuit is only enabled when MS = ‘H’ and CLS = ‘H’.
data RAM.
When CLS = ‘L’, the oscillation stops, and the display clock is
Because the display normal/reverse status, display
ON/OFF status, and display all points ON/OFF commands control
The
input through the CL terminal.
only the data within the latch, they do not change the data within
the display data RAM itself.
6.8. The Common Output Status Select
In the SPLC502B chips, the COM output scan direction can be
selected by the common output status select command (See Table
5.).
Consequently, the constraints in IC layout at the time of LCD
module assembly can be minimized.
Table 5
COM Scan Direction
Status
Duty
1/65 Duty
1/55 Duty
1/49 Duty
1/33 Duty
Normal
COM0 Æ COM63
COM0 Æ COM53
COM0 Æ COM47
COM0 Æ COM31
Reverse
COM63 Æ COM0
COM53 Æ COM0
COM47 Æ COM0
COM31 Æ COM0
Common output pads
Status
COM [0:15] COM [16:23] COM [24:26] COM [27:36] COM [37:39] COM [40:47] COM [48:63]
1/65
1/55
1/49
1/33
Normal
COM [0:63]
Reverse
COM [63:0]
Normal
Reverse
COMS
COMS
COM [0:26]
NC
COM [27:53]
COM [53:27]
NC
COM [26:0]
COMS
Normal
COM [0:23]
NC
COM [24:47]
Reverse
COM [47:24]
NC
COM [23:0]
COMS
Normal
COM [0:15]
NC
COM [16:31]
Reverse
COM [31:16]
NC
COM [15:0]
COMS
6.9. Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to
data RAM is accessed asynchronously during liquid crystal display,
the line address circuit and the display data latch circuit using the
there is absolutely no adverse effect (such as flickering) on the
display clock. The display data is latched into the display data
display.
latch circuit synchronized with the display clock, and is output to
the common timing and the liquid crystal alternating current signal
the data driver output terminal.
Moreover, the display timing generator circuit generates
Reading to the display data liquid
(FR) from the display clock. It generates a drive-wave form using
crystal driver circuits is completely independent of accesses to the
a 2-frame alternating current drive method, as is shown in Figure 5,
display data RAM by the MPU.
for the liquid crystal drive circuit.
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Consequently, even if the display
14
MAR. 30, 2007
Version: 1.0
SPLC502B
Two-frame alternating current drive-wave form (SPLC502B)
64
65
1
2
3
4
5
6
60
61
62
63
64
65
1
2
3
4
5
6
CL
FR
V0
COM0
V1
V4
Vss
V0
V1
COM1
V4
Vss
RAM
DATA
V0
V2
SEGn
V3
Vss
Figure 5
When multiple SPLC502B chips are used, the slave chips must be
supplied the display timing signals (FR, CL, DOF ) from the
master chip(s).
Operating Mode
Table 6 shows the status of the FR, CL, and
FR
CL
DOF
Input
Input
Input
Input
Input
Input
Slave (MS = ‘L’):
DOF signals.
The internal oscillator circuit is
enabled (CLS = ‘H’)
The internal oscillator circuit is
Table 6
Operating Mode
FR
CL
DOF
Output
Output
Output
Output
Input
Output
disabled (CLS = ‘L’)
Master (MS = ‘H’):
The internal oscillator circuit is
enabled (CLS = ‘H’)
The internal oscillator circuit is
disabled (CLS = ‘L’)
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SPLC502B
6.10. The Liquid Crystal Driver Circuits
These are a 197-channel (SPLC502B) that generates four voltage
crystal drive voltage output.
levels for driving the liquid crystal. The combination of the display
SEG and COM output waveform.
Figure 6 shows examples of the
data, the COM scan signals, and the FR signal produces the liquid
COM0
VDD
VSS
FR
COM1
V0
V1
V2
COM2
COM3
COM0
V3
V4
VSS
COM4
COM5
COM6
V0
V1
V2
COM1
V3
V4
VSS
V0
V1
V2
COM7
COM8
COM9
COM2
V3
V4
VSS
COM10
COM11
V0
V1
V2
COM12
COM13
SEG0
V3
V4
VSS
COM14
V0
V1
V2
COM15
SEG1
V3
V4
VSS
V0
V1
V2
SEG2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
-V4
COM0-SEG0
-V2
-V1
-V0
V0
V1
V2
V3
V4
VSS
-V4
COM0-SEG1
-V2
-V1
-V0
Figure 6
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SPLC502B
6.11. The Power Supply Circuits
The power supply circuits are low-power consumption power
Table 7 The Control Details of Each Bit of the Power Control
supply circuits that generate the voltage levels for the liquid crystal
drivers.
Set Command
They comprise Booster circuits, voltage regulator circuits,
and voltage follower circuits.
operation.
The power supply circuits can turn the Booster circuits,
DB2 Booster circuit control bit
the voltage regulator circuits, and the voltage follower circuits ON
DB1 Voltage regulator circuit
or OFF independently through the use of the Power Control Set
command.
Status
Item
They are only enabled in master
(V regulator circuit) control bit
Consequently, it is possible to make an external
DB0 Voltage follower circuit
power supply and the internal power supply function in parallel.
(V/F circuit) control bit
Table 7 shows the Power Control Set Command 3-bit data control
'1'
'0'
ON
OFF
ON
OFF
ON
OFF
functions, and Table 8 shows reference combinations.
Table 8 Reference Combinations
Use Settings
Step-up
V regulator
V/F
External
Step-up Voltage
circuit
circuit
circuit
voltage input
SystemTerminal
1
O
O
O
VDD2
Used
1
1
X
O
O
VOUT, VDD2
Open
0
0
1
X
X
O
V0, VDD2
Open
0
0
0
X
X
X
V0 to V4
Open
DB0
DB1
DB0
1
1
0
Only the V/F circuit is used
Only the external power supply is used
Only the internal power supply is used
Only the V regulator circuit and
the
V/F circuit are used
Note1: The ‘step-up system terminals’ refer CAP1P, CAP1N, CAP2P, CAP2N, and CAP3N.
Note2: While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use.
6.11.1. The step-up voltage circuits
Using the step-up voltage circuits equipped within the SPLC502B
Quad step-up: Connect capacitor C1 between CAP1P and CAP1N,
chips, it is possible to product a 6 Times, 5 Times, Quad step-up, a
between CAP2P and CAP2N, between CAP1N
Triple step-up, and a Double step-up of the VDD2 - VSS voltage
and CAP3N, and between VOUT and VSS, to
levels.
produce a voltage level in the positive direction at
the VOUT terminal that is 4 times the voltage level
6 Times step-up: Connect capacitor C1 between CAP1P and
between VDD2 and VSS.
CAP1N, between CAP2P and CAP2N, between
CAP1N and CAP3N, between CAP2N and CAP4P,
Triple step-up: Connect capacitor C1 between CAP1P and CAP1N,
between CAP1N and CAP5P, and between VOUT
between CAP2P and CAP2N and between VOUT
and VSS, to produce a voltage level in the positive
and VSS, and short between CAP3P and VOUT, to
direction at the VOUT terminal that is 6 times the
produce a voltage level in the positive direction at
voltage level between VDD2 and VSS.
the VOUT terminal that is 3 times the voltage
difference between VDD2 and VSS.
5 Times step-up: Connect capacitor C1 between CAP1P and
CAP1N, between CAP2P and CAP2N, between
Double step-up: Connect capacitor C1 between CAP1P and
CAP1N and CAP3N, between CAP2N and CAP4P,
CAP1N, and between VOUT and VSS, leave
between
between
CAP2N open, and short between CAP2P and
CAP5Pand VOUT, to produce a voltage level in the
VOUT, to produce a voltage in the positive
positive direction at the VOUT terminal that is 4
direction at the VOUT terminal that is twice the
times the voltage level between VDD2 and VSS.
voltage between VDD2 and VSS.
VOUT
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and
VSS,
short
17
MAR. 30, 2007
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SPLC502B
The step-up voltage relationships are shown in Figure 7.
CAP1P
CAP1N
CAP1P
C1
CAP1P
C1
CAP1N
CAP1N
CAP3P
CAP3P
CAP3P
CAP5P
CAP5P
CAP5P
CAP2P
CAP2P
CAP2N
CAP2N
CAP4P
CAP4P
VOUT
VSS
VOUT
C1
VSS = 0V
CAP1N
CAP3P
VSS = 0V
CAP1P
CAP1N
C1
CAP3P
CAP2P
C1
CAP2N
C1
VOUT
C1
C1
C1
C1
6 X (VDD - VSS)
VOUT = 6xVDD = 12V
VOUT = 5xVDD = 10V
VSS = 0V
C1
VSS
5 X (VDD - VSS)
VDD2 = 2V
C1
CAP4P
VOUT
VSS
C1
CAP5P
CAP2P
CAP4P
VOUT = 4xVDD = 12V
VSS = 0V
C1
C1
4 X (VDD - VSS)
VDD2 = 3V
CAP5P
CAP2N
VSS
VDD2 = 3V
CAP1P
C1
VOUT
C1
VOUT = 3xVDD = 9V
VDD2 = 3V
CAP2N
CAP4P
3 X (VDD - VSS)
VOUT = 2xVDD = 6V
C1
CAP2P
C1
VSS
2 X (VDD - VSS)
C1
VDD2 =2V
VSS = 0V
Figure 7
Note: The VDD2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rate.
The Recommended C1 capacitor is 1.0u~2.2u.
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SPLC502B
6.11.2. The voltage regulator circuit
The step-up voltage generated at VOUT outputs the liquid crystal
α is set to 1 level of 64 possible levels by the electronic volume
driver voltage V0 through the voltage regulator circuit. For display
function depending on the data set in the 6-bit electronic volume
quality issue, the condition VOUT ≧ V0 + 1.0V must be satisfied
register.
for all application condition.
electronic volume register settings.
Because the SPLC502B chips have
Table 10 shows the value for depending on the
an internal high-accuracy fixed voltage power supply with a
64-level electronic volume function and internal resistors for the V0
Table 10
voltage regulator, systems can be constructed without having to
DB5
DB4
DB3
DB2
DB1
DB0
α
include high-accuracy voltage regulator circuit components.
0
0
0
0
0
0
0
Moreover, in the SPLC502B, thermal gradients have been
0
0
0
0
0
1
1
prepared as VREG approximately -0.05%/℃
0
0
0
0
1
0
2
6.11.2.1. When the V0 voltage regulator internal
:
:
:
:
:
:
:
1
1
1
1
0
1
61
Through the use of the V0 voltage regulator internal resistors and
1
1
1
1
1
0
62
the electronic volume function, the liquid crystal power supply
1
1
1
1
1
1
63
resistors are used
voltage, V0, can be controlled by commands alone (without adding
any external resistors), making it possible to adjust the liquid
Rb/Ra is the V0 voltage regulator internal resistor ratio, and can
crystal display brightness.
be set to 8 different levels through the V0 voltage regulator
The V0 voltage can be calculated
using equation A-1 over the range where | V0 | < | VOUT |.
internal resistor ratio set command.
The (1 + Rb/Ra) ratio
assumes the values shown in Table 11 depending on the 3-bit
⎧ Rb ⎫
V0 = ⎨1 +
⎬ • VEN
⎩ Ra ⎭
data settings in the V0 voltage regulator internal resistor ratio
⎧ Rb ⎫ ⎧ (69 - α) ⎫
= ⎨1+
⎬ • ⎨1− 162 ⎬ • 2.181
⎭
⎩ Ra ⎭ ⎩
[Q VEN = (1− (69 − α) 162) • 2.181]
[V
reg
= (1− (69 − 63) 162) • 2.181]
register.
Equation A-1
V0 voltage regulator internal resistance ratio register value and (1
+ Rb/Ra) ratio (Reference value)
VEN (constant voltage supply + electronic volume)
Table 11
Internal Rb
V0
SPLC502B
Register
Equipment Type by Thermal Gradient
[Units: %/℃]
Internal Ra
VSS
Figure 8
VREG is the IC-internal fixed voltage supply, and its voltage at TA =
25℃ is as shown in Table 9.
Table 9
Equipment Type
Thermal
Gradient
Internal Power Supply
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-0.05
Units
VREG
Units
[%/℃]
2.1
[V]
19
DB2
DB1
DB0
(1) -0.05
0
0
0
3.0
0
0
1
3.5
0
1
0
4.0
0
1
1
4.5
1
0
0
5.0
1
0
1
5.5
1
1
0
6.0
1
1
1
6.5
MAR. 30, 2007
Version: 1.0
SPLC502B
⎧ Rb ⎫
V0 = ⎨1 +
⎬ • VEN
⎩ Ra ⎭
⎧ Rb ⎫ ⎧ (69 - α) ⎫
= ⎨1+
⎬ • ⎨1− 162 ⎬ • 2.181
⎭
⎩ Ra ⎭ ⎩
[Q VEN = (1− (69 − α) 162) • 2.181]
[V
reg
= (1− (69 − 63) 162 ) • 2.181]
Equation B-1
VEN (constant voltage supply + electronic volume)
Internal Rb'
V0
Internal Ra'
VSS
Figure 9
using the power control set commands.
Note1: When the V0 voltage regulator internal resistors or the electronic
Moreover, it is necessary to
provide a voltage from VOUT when the Booster circuit is OFF.
volume function is used, it is necessary to at least set the voltage
regulator circuit and the voltage follower circuit to an operating mode
The V0 voltage is produced by a resistive voltage divider within
after high power mode has been set, it is necessary to add a liquid
the IC, and can be produced at the V1, V2, V3, and V4 voltage
crystal drive power supply externally.
levels required for liquid crystal driving.
Moreover, when the
voltage follower changes the impedance, it provides V1, V2, V3 and
V4 to the liquid crystal drive circuit.
6.13. The Internal Power Supply Shutdown Command
1/9 bias or 1/7 bias for
Sequence
SPLC502B can be selected.
The sequence shown in Figure 11 is recommended for shutting
down the internal power supply.
6.12. High Power Mode
First place the power supply in
power saver mode and then turn the power supply OFF.
The power supply circuit equipped in the SPLC502B chips has
very low power consumption (normal mode: HPM = ‘H’). However,
Sequence
for LCDs or panels with large loads, this low-power power supply
Step1
Display OFF
1
0 1
0
1
1 1
0
Step2
Display all points ON
1
0 1
0
0
1 0
1
may cause display quality to degrade. When this occurs, setting
Details
Command address
(Command, status)
D7 D6 D5 D4 D3 D2 D1 D0
Power saver
commands
(compound)
the HPM terminal to ‘L’ (high power mode) can improve the
END
quality of the display. We recommend that the display be checked
on actual equipment to determine whether or not to use this mode.
Internal power supply OFF
Figure 11
Moreover, if the improvement to the display is inadequate even
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6.14. Reference Circuit Examples
Figure 12 shows reference circuit examples.
Note: The C3 capacitor of V1, V2, V3 and V4 may be used or not , depending on panel loading. If the panel loading is large, the C3 capacitor and High Power
mode( HPM = ‘L’) are suggested. The Recommended C2 and C3 capacitor is 0.1u~4.7u.
6.14.1.1. When using all of the step-up circuit, voltage regulating circuit and V/F circuit
When the voltage regulator internal resistor is used
Example where VDD2 = VDD, with 4x step- up
.
VDD
MS
C
VSS
1
VOUT
1
C
CAP1N
1
CAP3P
CAP5P
C
CAP2P
1
SPLC502B
CAP1P
C
CAP2N
CAP4P
C
2
C
3
C
3
C
C
V
0
V
1
V
2
V
3
V
4
3
3
Option
VSS
Figure 12
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6.14.1.2. When the voltage regulator circuit and V/F circuit alone are used
When the voltage regulator internal resistor is used
VDD
MS
VSS
VOUT
CAP1P
External
power
supply
CAP1N
CAP5P
CAP2P
CAP2N
CAP4P
C
C
2
3
C
3
C
3
C3
V
0
V
1
V
2
V
3
V
4
SPLC502B
CAP3P
Option
VSS
Figure 13
Item
Set Value
Units
C1
1.0 to 2.2
uF
C2
0.1 to 4.7
uF
C3
0.1 to 4.7
uF
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6.15. The Reset Circuit
is ‘L.’.
While
When the RESET input comes to the ‘L’ level, these LSIs return
supply short-circuits to VDD when RESET
to the default state.
RESET is ‘L,’ the oscillator and the display timing generator stop,
Their default states are as follows:
and the CL, FR, FRS and DOF terminals are fixed to ‘H’.
The
1).
Display OFF
terminals DB7 - 0 are not affected.
2).
Normal display
from the SEG and COM output terminals.
3).
ADC select: Normal (ADC command DB0 = ‘L’)
internal resistor is connected between VDD and V0.
4).
Power control register: (DB2, DB1, DB0) = (0, 0, 0)
internal liquid crystal power supply circuit is not used on other
5).
Serial interface internal register data clear
models of SPLC502B, it is necessary that RESET is ‘L’ when the
6).
LCD power supply bias rate:
external liquid crystal power supply is turned on.
SPLC502B...............................................1/9 bias
7).
9).
It means that an
When the
While RESET
is ‘L,’ the oscillator works, but the display timing generator stops,
All-indicator lamps-on OFF (All-indicator lamps ON/OFF
and the CL, FR, FRS and DOF terminals are fixed to ‘H’.
command DB0 = ‘L’)
8).
The VDD level is output
The
terminals DB7 - 0 are not affected.
Power saving clear
V0 voltage regulator internal resistors, Ra and Rb, are
connected.
7. COMMANDS
10). Output conditions of SEG and COM terminals
The SPLC502B chips identify the data bus signals by a
SEG: VSS, COM: VSS
11). Read modify write OFF
combination of A0P, RD (EP), WR (RWP) signals.
12). Static indicator OFF
interpretation and execution do not depend on the external clock,
Command
but rather is performed through internal timing only, and thus the
Static indicator register: (DB1, DB2) = (0, 0)
13). Display start line set to first line
processing is fast enough that normally a busy check is not
14). Column address set to Address 0
required.
15). Page address set to Page 0
16). Common output status normal
In the 8080 MPU interface, commands are launched by inputting a
17). V0 voltage regulator internal resistor ratio set mode clear
low pulse to the RD terminal for reading, and inputting a low
pulse to the WR terminal for writing.
18). Electronic volume register set mode clear
In the 6800 Series MPU
Electronic volume register: (DB5, DB4, DB3, DB2, DB1, DB0)
interface, the interface is placed in a read mode when a ‘H’ signal
= (1, 0. 0, 0, 0, 0)
is input to the RWP terminal.
It is placed in a write mode when a
19). Test mode clear
‘L’ signal is input to the RWP terminal.
Then, the command is
20). Driving mode register(DB0)=(0)
launched by inputting a high pulse to the EP terminal (See ‘10.
Timing Characteristics’ regarding the timing).
Consequently, the
On the other hand, when the reset command is used, only above
6800 Series MPU interface is different from the 80x86 Series MPU
default settings from 11 to 19 are executed.
When the power is
interface in that in the explanation of commands and the display
turned on, the IC internal state becomes unstable, and it is
commands the status read and display data read RD (EP)
necessary to initialize it using the RESET terminal.
becomes ‘1(H)’.
After the
In the explanations below, the commands are
initialization, each input terminal should be controlled normally.
explained using the 8080 Series MPU interface as the example.
Moreover, when the control signal from the MPU is in the high
When the serial interface is selected, the data is inputted in the
impedance, an over-current may flow to the IC.
sequence starting from DB7.
After applying a
current, it is necessary to take proper measures to prevent the
input terminal from getting into the high impedance state.
If the
internal liquid crystal power supply circuit is not used on
SPLC502B, it is necessary that RESET is ‘H’ when the external
liquid crystal power supply is turned on.
This IC has the function
to discharge V0 when RESET is ‘L,’ and the external power
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SPLC502B
<Explanation of Commands>
7.1. Display ON/OFF
This command turns the display ON and OFF.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
1
0
1
0
1
1
1
DB0
Setting
1
Display ON
0
Display OFF
When the display OFF command is executed and when in the display all points ON mode, power saver mode is entered.
See the section
on the power saver for details.
7.2. Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4.
For further details, see the
explanation of this function in ‘The Line Address Circuit’.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Line Address
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
↓
2
↓
1
1
1
1
1
0
62
1
1
1
1
1
1
63
7.3. Page Address Set
This command specifies the page address corresponding to the
Changing the page address does not accompany a change in the
low address when the MPU accesses the display data RAM (see
status display.
Figure 4).
Description (page 12) for the detail.
Specifying the page address and column address
See the page address circuit in the Function
enables to access a desired bit of the display data RAM.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Page Address
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
↓
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2
↓
0
1
1
1
7
1
0
0
0
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SPLC502B
7.4. Column Address Set
This command specifies the column address of the display data
making it possible for the MPU to continuously read from/write to
RAM shown in Figure 4.
the display data.
The column address is split into two
The column address increment is topped at
sections (the higher 4 bits and the lower 4 bits) when it is set
83H.
(fundamentally, set continuously). Each time the display data RAM
See the function explanation in ‘The Column Address Circuit’ for
This does not change the page address continuously.
is accessed, the column address automatically incremented (+1),
details.
EP RWP
A0P RD
High bits →
0
Column
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
0
0
1
A7
A6
A5
A4
0
0
0
0
0
0
0
0
0
0
A3
A2
A1
A0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
Low bits →
DB0 A7 A6 A5 A4 A3 A2 A1 A0
↓
Address
2
↓
1
0
0
0
0
0
0
0
130
1
0
0
0
0
0
1
1
131
7.5. Status Read
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
BUSY
ADC
ON/OFF
RESET
0
0
0
0
BUSY
When BUSY = ‘1’, it indicates that either processing is occurring internally or a reset condition is in process.
While the
chip does not accept commands until BUSY = ‘0’, if the cycle time can be satisfied, there is no need to check for BUSY
condition.
ADC
This shows the relationship between the column address and the segment driver.
0: Reverse (column address 131-nÙSEG n)
1: Normal (column address nÙSEG n)
(The ADC command switches the polarity.)
ON/OFF
ON/OFF: indicates the display ON/OFF state.
0: Display ON
1: Display OFF
(This display ON/OFF command switches the polarity.)
RESET
This indicates that the chip is in the process of initialization either because of a RESET signal or because of a reset
command.
0: Operating state
1: Reset in progress
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7.6. Display Data Write
This command writes 8-bit data to the specified display data RAM
address.
by one after the write, the MPU can write the display data.
Since the column address is automatically incremented
EP
RWP
A0P
RD
WR
1
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Write data
7.7. Display Data Read
This command reads 8-bit data from the specified display data
after the column address being set.
RAM address.
in “Display Data RAM” for the explanation of accessing the internal
Since the column address is automatically
incremented by one after the read, the CPU can continuously read
registers.
multiple-word data.
data becomes unavailable.
One dummy read is required immediately
EP
RWP
A0P
RD
WR
1
0
1
DB7
DB6
DB5
See the function explanation
When the serial interface is used, reading the display
DB4
DB3
DB2
DB1
DB0
Read Data
7.8. ADC Select (Segment Driver Direction Select)
This command can reverse the correspondence between the
12) for the detail.
display RAM data column address and the segment driver output.
accompanying the reading or writing the display data is done
Thus, sequence of the segment driver output pins may be
according to the column address indicated in Figure 4.
reversed by the command.
Increment of the column address (by ‘1’)
See the column address circuit (page
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
1
0
1
0
0
0
0
DB0
Setting
0
Normal
1
Reverse
7.9. Display Normal/Reverse
This command can reverse the lit and unlit display without
done, the display data RAM contents are maintained.
overwriting the contents of the display data RAM. When this is
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
0
1
0
0
1
1
0
1
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Setting
RAM Data ‘H’
LCD ON voltage (normal
RAM Data ‘L’
LCD ON voltage (reverse)
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SPLC502B
7.10. Display All Points ON/OFF
This command makes it possible to force all display points ON
command
regardless of the content of the display data RAM. The contents of
command.
the display data RAM are maintained when this is done.
takes
priority
over
the
display
normal/reverse
This
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
0
1
0
0
1
0
0
Normal display mode
1
Display all points ON
When the display is in an OFF mode, executing the display all
Setting
For more details, see the Power Save Section.
points ON command will place the display in power save mode.
7.11. LCD Bias Set
This command selects the voltage bias ratio for the liquid crystal display.
EP
RWP
Select Status (Duty)
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
0
1
0
0
0
1
0
1/9 bias 1/8 bias 1/8 bias 1/6 bias
1
1/7 bias 1/6 bias 1/6 bias 1/5 bias
1/65
1/55
1/49
1/33
7.12. Read/Modify/Write
Once
command is inputted, the column address returns to the address
this command has been inputted, the display data read command
at when the read/modify/write command was entered. This
does not change the column address, but only the display data
function makes it possible to reduce the load on the MPU when
write command increment (+1) the column address.
there is repeating data changes in a specified display region, such
This command is used paired with the ‘END’ command.
remains until the END command is inputted.
This mode
as when there is a blanking cursor.
When the END
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
0
0
0
0
Note: Even in read/modify/write mode, other commands aside from display data read/write commands can also be used.
However, the column address set
command cannot be used.
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7.12.1. The sequence for cursor display
Page address set
Column address set
Read/modify/write
Dummy read
Data read
Data process
Data write
No
Change complete?
Yes
End
Figure 15
7.13. END
This command releases the read / modify / write mode, and returns the column address to the address at when the mode was entered.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
1
1
1
0
Return
Column address
N
N+1
N+2
N+3
Read/modify/write mode set
N+m
N
End
Figure 16
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7.14. RESET
This command initializes the display start line, the column address,
mode are released.
the page address, the common output mode, the V0 voltage
See the function explanation in “Reset” for details.
There is no impact on the display data RAM.
regulator internal resistor ratio, the electronic volume, and the
operation is performed after the reset command is entered.
The reset
static indicator are reset, and the read/modify/write mode and test
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
0
0
1
0
The initialization must be done through applying a reset signal to the RESET terminal when the power supply is applied.
7.15. Common Output Mode Select
This command can select the scan direction of the COM output
Output Mode Select Circuit”.
terminal. For details, see the function explanation in “Common
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Select Status
0
1
0
1
1
0
0
0
*
*
*
SPLC502B
Normal
1
Reverse
Note: *Disabled bit
7.16. Power Controller Set
This command sets the power supply circuit functions.
See the function explanation in “The Power Supply Circuit” for more details.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
0
1
0
0
0
1
0
1
DB2
DB1
DB0
Selected Mode
0
Booster circuit: OFF
1
Booster circuit: ON
0
Voltage regulator circuit :OFF
1
Voltage regulator circuit: ON
0
Voltage follower circuit: OFF
1
Voltage follower circuit: ON
Note: Display off command masks the power control circuits
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SPLC502B
7.17. V0 Voltage Regulator Internal Resistor Ratio Set
This command sets the V0 voltage regulator internal resistor ratio.
For details, see the function explanation in “The Power Supply
Circuits”.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
0
1
0
0
0
1
0
0
DB2
DB1
DB0
Setting
Small
0
0
0
0
0
1
1
0
0
↓
↓
1
1
0
1
1
1
Large
7.18. The Electronic Volume (Double Byte Command)
7.18.1. The electronic volume mode set
This command makes it possible to adjust the brightness of the
When this command is input, the electronic volume register set
liquid crystal display by controlling the liquid crystal drive voltage
command becomes enabled.
V0 through the output from the voltage regulator circuits of the
has been set, no other command except for the electronic volume
internal liquid crystal power supply.
register command can be used.
This command is a two bytes
Once the electronic volume mode
Once the electronic volume
command used as a pair with the electronic volume mode set
register set command has been used to set data into the register,
command and the electronic volume register set command, and
the electronic volume mode is released.
both commands must be issued one after the other.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
0
0
0
0
0
0
1
7.18.2. Electronic volume register set
By using this command to set six bits of data to the electronic
electronic volume mode is released after the electronic volume
volume register, the liquid crystal driving voltage, V0, assumes
register has been set.
one of the 64 voltage levels. When this command is input, the
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
| V0|
0
1
0
*
*
0
0
0
0
0
1
Small
0
1
0
*
*
0
0
0
0
1
0
0
1
0
*
*
0
0
0
0
1
1
0
1
0
*
*
1
1
1
1
1
0
0
1
0
*
*
1
1
1
1
1
1
↓
↓
Large
Note: *Inactive bit
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7.18.3. The electronic volume register set sequence
electrodes is connected to the FR terminal, and the other is
connected to the FRS terminal.
Electronic volume mode set
A different pattern is
recommended for the static indicator electrodes than for the
dynamic drive electrodes.
If the pattern is too close, it can result
in deterioration of the liquid crystal and of the electrodes.
Electronic volume register set
The
static indicator ON command is a double byte command paired
Electronic volume mode clear
No
with the static indicator register set command, and thus one must
execute one after the other.
Changes complete?
The static indicator OFF command
is a single byte command.
Yes
7.19.1. Static indicator ON/OFF
Figure 17
When the static indicator ON command is entered, the static
7.19. Static Indicator (Double Byte Command)
indicator register set command is enabled.
This command controls the static drive system indicator display.
indicator ON command is entered, no other command aside from
The static indicator display is controlled by this command only,
the static indicator register set command can be used.
and is independent from other display control commands.
mode is cleared when data is set in the register by the static
This
Once the static
This
indicator register set command.
is used when one of the static indicator liquid crystal drive
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Static Indicator
0
1
0
1
0
1
0
1
1
0
0
OFF
1
ON
7.19.2. Static indicator register set
This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode.
EP
RWP
A0P
RD
WR
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Static Indicator
*
*
*
*
*
*
0
0
OFF
*
*
*
*
*
*
0
1
ON (blinking at approximately one second intervals)
*
*
*
*
*
*
1
0
ON (blinking at approximately 0.5 second intervals)
*
*
*
*
*
*
1
1
ON (constantly on)
Note: *Disabled bit
7.20. Page Blinking (Double Byte Command)
7.20.1. The page blinking mode set
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
0
1
0
1
0
1
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7.20.2. Page blinking register set
Set either bit to '1' will set corresponding PAGE0 - PAGE7 to blink.
EP
RWP
A0P
RD
WR
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Blinking Page
1
0
0
0
0
0
0
0
PAGE 7 blink
0
1
0
0
0
0
0
0
PAGE 6 blink
0
0
1
0
0
0
0
0
PAGE 5 blink
0
0
0
1
PAGE 0 blink
↓
0
0
0
0
7.20.3. Page blinking indicator register set sequence
Page Blinking mode set
Blinking Page set
(Page Blinking mode clear)
No
Changes complete?
Yes
Figure 18
7.21.
Set Driving Mode (Double Byte Command)
This command makes it possible to increase the V0 voltage stability by instruction command for using different liquid crystal panel. User
can select the appropriate mode for their liquid crystal panel and display pattern. The V0 voltage stability is Mode2>Mode1(Default), and so
as the current consumption.
7.21.1. The driving mode set
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
0
1
0
0
1
0
7.21.2. Mode selection register set
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Driving Duty Selection
0
1
0
0
0
0
0
0
0
0
0
Mode 1
0
0
0
0
0
0
0
1
Mode 2
Note1: DB7 – DB1 7 bits must fill 0.
Note2: Mode1 DB0=0 is default.
Note3: Driving capability : MODE2 > MODE1.
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SPLC502B
7.22. Power Save (Compound Command)
When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered and therefore, it
reduces a great amount of power.
The power saver mode has two different modes: the sleep mode and the standby mode.
static indicator is OFF, the sleep mode is entered.
When the static indicator is ON, the standby mode is entered.
When the
In the sleep mode and
standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the
MPU is still able to access the display data RAM.
Refer to figure 19 for power save off sequence.
Static indicator OFF
Static indicator ON
Power saver (compound command)
Sleep mode
Standby mode
Power save OFF (compound command)
Display all points OFF command
Static indicator ON
(2 bytes command)
Power save OFF
(Display all points OFF command)
Sleep mode cancel
Standby mode cancel
Figure 19
7.22.1. Sleep mode
This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is
reduced to a value close to the static current.
The internal modes during sleep mode are as follows:
1). The oscillator circuit and the LCD power supply circuit are halted.
2). All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level.
7.22.2. Standby mode
The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the
minimum required consumption current for the static drive.
1). The LCD power supply circuits are halted.
The internal modes are in the following states during standby mode.
The oscillator circuit continues to operate.
2). The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs a VSS level. The static drive
system does not operate.
When a reset command is performed while in standby mode, the system enters sleep mode.
Note1: When an external power supply is used, it is recommended that the functions of the external power supply circuit should be stopped when the power
saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is
recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver
mode is in effect.
The SPLC502B chips have a liquid crystal display blanking control terminal DOF .
saver mode is launched.
This terminal enters a ‘L’ state when the power
Using the output of DOF , it is possible to stop the function of an external power supply circuit.
Note2: When the master is turned on, the oscillator circuit is operable immediately after the power on.
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7.23. NOP
Non-Operation Command
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
0
0
0
1
1
7.24. TEST
This is a command for IC chip testing.
Please do not use it. If
applying a ‘L’ signal to the RESET input by the reset command
the test command is used by accident, it can be cleared by
A0P
EP
RWP
RD
WR
DB7
DB6
or by using a NOP.
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
1
1
1
1
*
*
*
*
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
Note: The SPLC502B chips maintain their operating modes until some conditions occurred to change them.
change the internal modes of the SPLC502B chip.
Consequently, excessive external noise, etc., can
Thus, in the packaging and system design, it is necessary to suppress the noise or take
measurement to prevent the noise from influencing the chip.
Moreover, it is recommended that the operating modes be refreshed periodically to
prevent the effects.
7.25. Oscillator Frequency selection
This is a command for Oscillator frequency selection of Driver IC.
EP
RWP
A0P
RD
WR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
1
1
1
0
0
1
0
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DB0
Static Indicator
0
20KHz/ 33KHz (default)
1
16.4KHz/ 27.06KHz
MAR. 30, 2007
Version: 1.0
SPLC502B
7.26. Table 13 Table of SPLC502B Commands
Command Code
Function
Command
1). Display ON/OFF
A0P
RD
WR
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
2). Display start line set
0
1
0
0
1
3). Page address set
0
1
0
1
0
1
1
4). Column address set
0
1
0
0
0
0
1
1
0
1
0
5). Status read
0
0
1
6). Display data write
1
1
0
7). Display data read
1
0
1
8). ADC select
0
1
0
0
0
1
0
LCD display ON/OFF
1
0: OFF, 1: ON
Sets the display RAM display start line
Display start address
0
0
address
Sets the display RAM page address
Page address
upper bit
Column address set
1
Most significant
Sets the most significant 4 bits of the
column address
display RAM column address.
Least significant
Set the least significant 4 bits of the
display RAM column address.
column address
lower bit
Status
0
0
0
0
Write data
Writes to the display RAM
Read data
1
0
1
0
0
Reads the status data
Reads from the display RAM
0
0
0
Sets the display RAM address SEG
1
output correspondence
0: normal, 1:reverse
9). Display normal/reverse
0
1
0
1
0
1
0
0
1
1
0
1
0: normal, 1:reverse
10). Display
0
1
0
1
0
1
0
0
1
0
0
Display all points
1
0: normal display
all
points
ON/OFF
Sets the LCD display normal/ reverse
1: all points ON
11). LCD bias set
12). Read/modify/write
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
1
0
0
Sets the LCD driver voltage bias ratio
1
SPLC502B……….0:1/9, 1:1/7
0
Column address increment
At write: +1
At read: 0
13). End
0
1
0
1
1
1
0
1
1
1
0
Clear read/modify/write
14). Reset
0
1
0
1
1
1
0
0
0
1
0
Internal reset
15). Common output mode
0
1
0
1
1
0
0
0
*
*
*
Select COM output scan direction
select
1
0: normal direction,
1: reverse direction
16). Power control set
0
1
0
0
0
1
0
1
Operating mode
Select internal power supply operating
mode
17). V0 voltage regulator
0
1
0
0
0
1
0
0
Resistor ratio
internal resistor ratio
Select internal resistor ratio (Rb/Ra)
mode
set
18). Electronic volume
0
1
0
0
1
0
1
0
0
0
0
0
0
Set the V0 output voltage electronic
volume register
mode set
Electronic volume
1
*
*
Electronic volume value
register set
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SPLC502B
Command Code
Command
19). Static indicator
Function
A0P
RD
WR
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
1
0
1
1
0
ON/OFF
0
0: OFF, 1: ON
1
Static indicator
*
*
*
*
*
*
Mode
Set the flashing mode
Register set
20). Page Blink
Page selection
0
1
0
1
1
0
1
0
1
0
1
0
1
0
P7
P6
P5
P4
P3
P2
P1
P0
P7 - 0: 1 - blinking page
0 - no blinking, normal display
21). Driving Mode Set
Mode selection
0
1
0
1
1
0
1
0
0
1
0
Set the driving mode register
0
1
0
0
0
0
0
0
0
0
D0
Driving capability (D0): (1)>(0)
22). Power saver
Display OFF and display all points ON
compound command
23). NOP
0
1
0
1
1
1
0
0
0
1
1
Command for non-operation
24). Test
0
1
0
1
1
1
1
*
*
*
*
Command for IC test.
1
1
0
1
0
1
0
0
this command
1
1
1
0
0
1
0
0
20KHz/33KHz (Default)
1
16.4KHz/ 27.06KHz
25). Oscillator
Frequency
0
1
0
selection
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Do not use
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SPLC502B
8. COMMAND DESCRIPTION
8.1. Instruction Setup: Reference (Reference)
8.1.1. Initialization
2). When the built-in power is not being used immediately after
Note: When the power is applied, LCD driving non-selective potentials V2
turning on the power:
and V3 (SEG pin) and V1 and V4 (COM pin) are output through the
LCD driving output pins SEG and COM. When electric charge is
remaining in the smoothing capacitor connecting between the LCD
Turn ON the VDD-VSS power keeping the
RESET pin = "L".
driving voltage output pins (V0 - 1) and the VDD pin, the picture on
the display may become totally dark instantaneously when the
power is turned on.
To avoid occurrence of such a failure, we
When the power is stabilized
recommend the following flow when turning on the power.
Release the reset state. (RESET pin = "H")
1). When the built-in power is being used immediately after turning
on the power:
Initialized state (Default) *1
Arrange to start the power saver
within 5ms after releasing the
reset state. Execute the
procedures from turning on the
power to setting the power
control in 5ms.
Power saver START (multiple commands) *8
Turn ON the VDD-VSS power keeping the
RESET pin = "L".
Function setup by command input(User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
When the power is stabilized
Release the reset state. (RESET pin = "H")
Function setup by command input(User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Initialized state (Default) *1
Function setup by command input(User setup)
(11) LCD bias setting *2
(8) ADC selection *3
(15) Common output state selection *4
Arrange to execute all the
procedures from releasing the
reset state through setting the
power control within 5ms.
Execute the procedures from
turning on the power to setting
the power control in 5ms.
Power saver OFF *8
Function setup by command input(User setup)
(16) Power control setting *7
Function setup by command input(User setup)
(17) Setting the built-in resistance radio
for regulation of the V5 voltage *5
(18) Electronic volume control *6
Arrange to start power control
setting within 5ms after turning
OFF the power saver.
This concludes the initialization
Function setup by command input(User setup)
(16) Power control setting *7
Figure 21
Note1: The target time of 5ms varied depending on the panel characteristics
This concludes the initialization
and the capacitance of the smoothing capacitor.
Therefore, we
suggest users to conduct an operation check using the actual
Figure 20
equipment.
Note1: The target time of 5ms varied depending on the panel characteristics
and the capacitance of the smoothing capacitor.
Note2: Refer to respective sections or paragraphs listed below.
Therefore, we
suggest users to conduct an operation check using the actual
*1:Description of functions; Resetting circuit
equipment.
*2:Command description; LCD bias setting
*3:Command description; ADC selection
Note2: Refer to respective sections or paragraphs listed below.
*1:Description of functions; Reset circuit
*4:Command description; Common output state selection
*2:Command description; LCD bias setting
*5:Description of functions; Power circuit & Command description;
Setting the built-in resistance radio for regulation of the V0 voltage
*3:Command description; ADC selection
*6:Description of functions; Power circuit & Command description;
*4:Command description; Common output state selection
Electronic volume control
*5:Description of functions; Power circuit & Command description;
*7:Description of functions; Power circuit & Command description;
Setting the built-in resistance radio for regulation of the V0 voltage
Power control setting
*6:Description of functions; Power circuit & Command description;
*8:The power saver ON state can either be in sleep state or stand-by
Electronic volume control
state.
*7:Description of functions; Power circuit & Command description;
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Command description; Power saver START (multiple
commands)
Power control setting.
37
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SPLC502B
8.1.2. Data display
End of initialization
Function setup by command input (User setup)
(2) Display start line set *9
(3) Page address set *10
(4) Column address set *11
Function setup by command input (User setup)
(6) Display data write *12
Notes: Reference items
*9: Command Description; Display start line set
*10: Command Description; Page address set
*11:Command Description; Column address set
*12: Command Description; Display data write
*13: Command Description; Display ON/OFF
Avoid displaying all the data at the data display
start(when the display is ON) in white.
Function setup by command input (User setup)
(1) Display ON/OFF *13
End of data display
Figure 22
8.1.3. Power OFF *14
Optional status
Set the time (tL) from reset active to
turning off the VDD - VSS Power ( VDD VSS = 2.4 V) longer than the time (tH)
when the potential of V5 - 1 becomes below
the threshold voltage (approximately 1V)
of the LCD panel. For tH, refer to the
<Reference Data> of this event. When tH
is too long, insert a resistor between V5
and VDD to reduct it.
Function setup by command input (User setup)
(20) Power save *15
Reset active( RESET pin = "L")
VDD - VSS power OFF
Figure 23
Note: Reference items
*14:The logic circuit of this IC’s power supply VDD - VSS controls the
driver of the LCD power supply V0.
Therefore, if the power supply
VDD - VSS is cut off when the LCD power supply V0 has still any
residual voltage, the driver (COM. SEG) may output any uncontrolled
voltage.
When turning off the power, observe the following basic
procedures:
• After turning off the internal power supply, make sure that the
potential V0 - 1 has become below the threshold voltage of the LCD
panel, and then turn off this IC’s power supply (VDD - VSS).
Refer to “6. Description of Function, Power Circuit” for more
information.
*15: After inputting the power save command, be sure to reset the function
using the RESET terminal until the power supply VDD - VSS is
turned off.
Refer to “ 7. Command Description, (20) Power Save”
for more information.
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9. ELECTRICAL SPECIFICATIONS
9.1. Absolute Maximum Ratings
(Unless otherwise noted, VSS = 0V)
Parameter
Symbol
Conditions
Unit
VDD
-0.3 to + 3.6
V
Power Supply Voltage
Power supply voltage (2)
(VDD standard)
-0.3 to + 3.6
With Triple step-up
VDD2
-0.3 to + 3.6
With Quad step-up
V
-0.3 to + 3.0
Power supply voltage (3) (VDD standard)
V0, VLCD
-0.3 to + 12
V
Power supply voltage (4) (VDD standard)
V1, V2, V3, V4
-0.3 to V0
V
Input voltage
VIN
-0.3 to VDD +0.3
V
Output voltage
VO
-0.3 to VDD +0.3
V
TOPR
-20 to +75
℃
TSTR
-55 to +125
℃
Operating temperature
Storage temperature
Bare chip
Notes and Cautions:
1. The VDD2, V0 to V4 and VOUT are relative to the VSS = 0V reference.
2. Insure that the voltage levels of V0, V1, V2, V3, and V4 are always such that V0≧V1≧V2≧V3≧V4≧VSS(GND)
3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation
the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but
may have a negative impact on the LSI reliability as well.
9.2. DC Characteristics
(Unless otherwise specified, VSS = 0V, VDD = 3.0V±10%, TA = -20 to 75℃)
Item
Operating
Recommended
Voltage (1)
Voltage
Operating
Recommended
Voltage (2)
Voltage
Operating
Possible Operating
Voltage (3)
Voltage
Symbol
Rating
Condition
VDD
Units
Applicable
PIN
Min.
Typ.
Max.
1.8
-
3.6
V
VDD*1
VDD2
(Relative to VSS)
1.8
-
3.6
V
VDD2
V0
(Relative to VSS)
4.0
-
12.0
V
V0*2
High-level Input Voltage
VIHC
0.8 x VDD
-
VDD
V
*3
Low-level Input Voltage
VILC
VSS
-
0.2 x VDD
V
*3
High-level output Voltage
VOHC
IOH = -0.5mA
0.8 x VDD
-
VDD
V
*4
Low-level output Voltage
VOLC
IOL = 0.5mA
VSS
-
0.2 x VDD
V
*4
Input leakage current
ILI
Output leakage current
ILO
Liquid Crystal Driver ON
Resistance
Static Consumption Current
RON
VIN = VDD or VSS
TA = 25℃
V0 = 12V
(Relative To VSS)
V0 = 8.0V
ISSQ
-1.0
-
1.0
µA
*5
-3.0
-
3.0
µA
*6
-
2.0
3.5
KΩ
SEGn
-
3.2
5.4
KΩ
COMn*7
-
0.01
5.0
µA
VDD, VDD2
V0
Output Leakage Current
I0Q
V0 = 12V (Relative to VSS)
-
0.01
15
µA
Input Terminal Capacitance
CIN
TA = 25℃ f = 1.0MHz
-
5.0
8.0
pF
Oscillator
Internal Oscillator
fOSC
1/65 duty TA = 25℃
17
20
23
KHz
*8
Frequency
External Input
fCL
1/33 duty
17
20
23
KHz
CL
Internal Oscillator
fOSC
1/55 duty TA = 25℃
28
33
38
KHz
*8
External Input
fCL
1/49 duty
28
33
38
KHz
CL
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SPLC502B
Item
Symbol
Internal Power
Input Voltage
Supply Setup-up output
voltage Circuit
Voltage regulator Circuit
Operating Voltage
Units
Min.
Typ.
Max.
Application
PIN
VDD2
With Triple (Relative to VSS)
1.8
-
4.0
V
VDD2
VDD2
With Quad (Relative to VSS)
1.8
-
3.0
V
VDD2
VOUT
(Relative to VSS)
-
-
13.0
V
VOUT
VOUT
(Relative to VSS)
4.0
-
13.0
V
VOUT
V0
(Relative to VSS)
4.0
-
12.0
V
V0 *9
2.08
2.1
2.12
V
*10
Voltage Follower Circuit
Operating Voltage
Base Voltage
Rating
Condition
TA = 25℃
VREG0
-0.05%/℃
(Relative to VSS)
9.3. Display Pattern Checker
(TA = -20 to 75℃)
Item
Symbol
SPLC502B
IDD(1+2)
Rating
Condition
Min.
Typ.
Max.
-
20
25
VDD = 3.0V, V0 - VSS = 11V
Units
Notes
µA
*11
Dynamic Consumption Current (1+2), During Display, with the Internal Power Supply OFF.
Current consumed by total ICs when an external power supply is used.
9.4. Display Pattern Checker
(TA = -20 to 75℃)
Item
Symbol
SPLC502B
IDD(1+2)
Rating
Condition
VDD
=
voltage.
3.0V,
V0
Quad
Min.
Typ.
Max.
-
130
160
step-up Normal Mode
= 11.0V
Units
Notes
µA
*11
Units
Notes
Dynamic Consumption Current (1+2), During Display, with the Internal Power Supply ON
Item
Symbol
Sleep Mode SPLC502B
IDDS1
-
Item
1/65 DUTY *8
1/55 DUTY *8
1/49 DUTY *8
1/33 DUTY *8
When the internal oscillator circuit is used (20KHz)
When the internal oscillator circuit is not used
When the internal oscillator circuit is used (33KHz)
When the internal oscillator circuit is not used
When the internal oscillator circuit is used (33KHz)
When the internal oscillator circuit is not used
When the internal oscillator circuit is used (20KHz)
When the internal oscillator circuit is not used
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Rating
Condition
40
Min.
Typ.
Max.
-
0.01
5.0
µA
fCL
fFR
fOSC / 4
fOSC / (4 * 65)
External input (fCL)
fCL / 260
fOSC / 8
fOSC / (8 * 55)
External input (fCL)
fCL / 220
fOSC / 8
fOSC / (8 * 49)
External input (fCL)
fCL / 196
fOSC / 8
fOSC / (8 * 33)
External input (fCL)
fCL / 264
MAR. 30, 2007
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SPLC502B
References for items market with *
*1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is
being accessed.
*2 The operating voltage range for the VDD system and the V0 system is applied when the external power supply is being used.
*3 The A0P, DB0 to DB5, DB6 (SCL), DB7 (SI), RD (EP), WR (RWP), CS1 , CS2, CLS, CL, FR, MS, C86, PS, DOF , RES , and HPM terminals.
*4 The DB0 to DB7, FR, FRS, DOF , and CL terminals.
*5 The A0P, RD (EP), WR (RWP), CS1 , CS2, CLS, MS, C86, PS, RES , and HPM terminals.
*6 Applies when the DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, and DOF terminals are in a high impedance state.
*7 These are the resistance values for when a 0.1V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1,
V2, V3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1V/ △I (Where △I is the current that flows when 0.1V is applied while the power supply is ON.)
*8 The relationship between the oscillator frequency and the frame rate frequency.
*9 The V0 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
*10 This is the internal voltage reference supply for the V0 voltage regulator circuit. In the SPLC502B, the temperature range can come in three types as
VREG options: (1) approximately –0.05%/C.
*11 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The SPLC502B is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access
from the MPU.
V1~V4 without capacitor.
*12 It is the value on a model having the VREG option temperature gradient is –0.05%/C when the V0 voltage regulator internal resistor is used.
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9.5. Timing Characteristics
9.5.1. System bus read/write characteristics 1 (For the 8080 Series MPU)
A0P
tAW8
tAH8
CS1
(CS2="1")
tCYC8
tCCLR, tCCLW
WR, RD
tCCHR , tCCHW
tDS8
tDS8
DB7 - 0
(Write)
tOH8
tACC8
DB7 - 0
(Read)
(VDD = 3.3V to 3.6V, TA = -20 to 75℃)
Item
Address hold time
Address setup time
Signal
A0P
Symbol
Rating
Condition
Units
Min.
Max.
tAH8
0
-
ns
tAW8
0
-
ns
System cycle time
A0P
tCYC8
240
-
ns
Control L pulse width ( WR )
WR
tCCLW
80
-
ns
-
ns
Control L pulse width ( RD )
RD
tCCLR
80
Control H pulse width ( WR )
WR
tCCHW
80
-
ns
tCCHR
80
-
ns
Data setup time
tDS8
30
-
ns
Address hold time
tDH8
10
-
ns
-
70
ns
5.0
50
ns
Control H pulse width ( RD )
RD access time
Output disable time
© ORISE Technology Co., Ltd.
Proprietary & Confidential
RD
DB7 - 0
tACC8
tOH8
42
CL = 100pF
MAR. 30, 2007
Version: 1.0
SPLC502B
(VDD = 2.7V to 3.3V, TA = -20 to 75℃)
Item
Address hold time
Address setup time
System cycle time
Signal
Symbol
A0P
A0P
Rating
Condition
Units
Min.
Max.
tAH8
0
-
ns
tAW8
0
-
ns
tCYC8
400
-
ns
-
ns
Control L pulse width ( WR )
WR
tCCLW
100
Control L pulse width ( RD )
RD
tCCLR
100
-
ns
-
ns
Control H pulse width ( WR )
WR
tCCHW
100
Control H pulse width ( RD )
RD
tCCHR
100
-
ns
Data setup time
tDS8
40
-
ns
Address hold time
tDH8
15
-
ns
-
140
ns
10
100
ns
RD access time
DB7 - 0
tACC8
tOH8
Output disable time
CL = 100pF
(VDD = 1.8V to 2.7V, TA = -20 to 75℃)
Item
Address hold time
Signal
Symbol
A0P
Rating
Condition
Units
Min.
Max.
tAH8
0
-
ns
tAW8
0
-
ns
A0P
tCYC8
640
-
ns
Control L pulse width ( WR )
WR
tCCLW
200
-
ns
Control L pulse width ( RD )
RD
tCCLR
200
-
ns
Control H pulse width ( WR )
WR
tCCHW
200
-
ns
Control H pulse width ( RD )
RD
tCCHR
200
-
ns
Data setup time
tDS8
80
-
ns
Address hold time
tDH8
30
-
ns
-
280
ns
10
200
ns
Address setup time
System cycle time
RD access time
DB7 - 0
Output disable time
tACC8
tOH8
CL = 100pF
Note1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf)≦(tCYC8 - tCCLW - tCCHW) for (tr
+ tf)≦(tCYC8 - tCCLR - tCCHR) are specified.
Note2: All timing is specified using 20% and 80% of VDD as the reference.
Note3: tCCLW and tCCLR are specified as the overlap between CS1 being 'L' ( CS2 = 'H') and WR and RD being at the 'L' level.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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MAR. 30, 2007
Version: 1.0
SPLC502B
9.5.2. System bus read/write characteristics 2 (6800 series MPU)
A0P
RWP
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tEWHR, tEWHW
EP
tEWLR , tEWLW
tDS6
tDH6
DB7 - 0
(Write)
tOH6
tACC6
DB7 - 0
(Read)
(VDD = 3.3V to 3.6V, TA = -20 to 75℃)
Item
Signal
Address hold time
A0P
Address setup time
System cycle time
A0P
Symbol
Rating
Condition
Units
Min.
Max.
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
240
-
ns
Data setup time
tDS6
30
-
ns
Data hold time
tDH6
10
-
ns
tACC6
-
70
ns
tOH6
10
50
ns
DB7 - 0
Access time
Output disable time
Enable H pulse time
Enable L pulse time
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Read
Write
Read
Write
EP
EP
CL = 100pF
tEWHR
80
-
ns
tEWHW
80
-
ns
tEWLR
80
-
ns
tEWLW
80
-
ns
44
MAR. 30, 2007
Version: 1.0
SPLC502B
(VDD = 2.7V to 3.3V, TA = -20 to 75℃)
Item
Signal
Address hold time
Symbol
A0P
Address setup time
System cycle time
A0P
Rating
Condition
Units
Min.
Max.
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
400
-
ns
Data setup time
tDS6
40
-
ns
Data hold time
tDH6
15
-
ns
tACC6
-
140
ns
tOH6
10
100
ns
DB7 - 0
Access time
Output disable time
Enable H pulse time
Enable L pulse time
Read
Write
Read
Write
EP
EP
CL = 100pF
tEWHR
100
-
ns
tEWHW
100
-
ns
tEWLR
100
-
ns
tEWLW
100
-
ns
(VDD = 1.8V to 2.7V, TA = -20 to 75℃)
Item
Signal
Address hold time
Symbol
A0P
Address setup time
System cycle time
A0P
Rating
Condition
Units
Min.
Max.
tAH6
0
-
ns
tAW6
0
-
ns
tCYC6
640
-
ns
Data setup time
tDS6
80
-
ns
Data hold time
tDH6
30
-
ns
tACC6
-
280
ns
tOH6
10
120
ns
DB7 - 0
Access time
Output disable time
Enable H pulse time
Enable L pulse time
Read
Write
Read
Write
EP
EP
CL = 100pF
tEWHR
200
-
ns
tEWHW
200
-
ns
tEWLR
200
-
ns
tEWLW
200
-
ns
Note1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf)≦(tCYC6 - tEWLW - tEWHW) for
(tr + tf)≦(tCYC6 - tEWLR - tEWHR) are specified.
Note2: All timing is specified using 20% and 80% of VDD as the reference.
Note3: tEWLW and tEWLR are specified as the overlap between CS1 being 'L' (CS2 = 'H') and EP.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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MAR. 30, 2007
Version: 1.0
SPLC502B
9.5.3. The serial interface
tCSS
tCSH
CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tF
tR
tSDS
tSDH
SI
(VDD = 3.3V to 3.6V, TA = -20 to 75℃)
Item
Signal
Serial Clock Period
SCL 'H' pulse width
SCL
SCL 'L' pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
A0P
SI
CS
Symbol
Rating
Condition
Units
Min.
Max.
tSCYC
-
200
-
ns
tSHW
-
80
-
ns
tSLW
-
80
-
ns
tSAS
-
50
-
ns
tSAH
-
100
-
ns
tSDS
-
50
-
ns
tSDH
-
50
-
ns
tCSS
-
100
-
ns
tCSH
-
100
-
ns
(VDD = 2.7V to 3.3V, TA = -20 to 75℃)
Item
Signal
Serial Clock Period
Symbol
Rating
Condition
Units
Min.
Max.
tSCYC
-
250
-
ns
tSHW
-
100
-
ns
SCL 'L' pulse width
tSLW
-
100
-
ns
Address setup time
tSAS
-
150
-
ns
tSAH
-
150
-
ns
SCL 'H' pulse width
Address hold time
Data setup time
Data hold time
CS-SCL time
© ORISE Technology Co., Ltd.
Proprietary & Confidential
SCL
A0P
SI
CS
tSDS
-
100
-
ns
tSDH
-
100
-
ns
tCSS
-
150
-
ns
tCSH
-
150
-
ns
46
MAR. 30, 2007
Version: 1.0
SPLC502B
(VDD = 1.8V to 2.7V, TA = -20 to 75℃)
Item
Signal
Symbol
Serial Clock Period
Units
Min.
Max.
tSCYC
-
350
-
ns
tSHW
-
150
-
ns
SCL
SCL 'H' pulse width
Rating
Condition
SCL 'L' pulse width
tSLW
-
150
-
ns
Address setup time
tSAS
-
150
-
ns
A0P
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
CS
tSAH
-
150
-
ns
tSDS
-
60
-
ns
tSDH
-
30
-
ns
tCSS
-
250
-
ns
tCSH
-
250
-
ns
Note1: The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
Note2: All timing is specified using 20% and 80% of VDD as the standard.
9.5.4. Display control output timing
CL
(OUT)
tDFR
FR
(VDD = 3.3V to 3.6V, TA = -20 to 75℃)
Item
FR delay time
Signal
FR
Symbol
Rating
Condition
tDFR
CL = 50pF
Units
Min.
Typ.
Max.
-
10
40
ns
(VDD = 2.7V to 3.3V, TA = -20 to 75℃)
Item
FR delay time
Signal
FR
Symbol
Rating
Condition
tDFR
CL = 50pF
Units
Min.
Typ.
Max.
-
20
80
ns
(VDD = 1.8V to 2.7V, TA = -20 to 75℃)
Item
FR delay time
Signal
FR
Symbol
Rating
Condition
tDFR
CL = 50pF
Units
Min.
Typ.
Max.
-
50
200
ns
Note1: Valid only when the master mode is selected.
Note2: All timing is based on 20% and 80% of VDD.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
47
MAR. 30, 2007
Version: 1.0
SPLC502B
9.5.5. Reset timing
tRW
RESET
tR
Internal
status
During reset
Reset complete
(VDD = 3.3 V to 3.6V, TA = -20 to 75℃)
Item
Signal
Symbol
Rating
Condition
Min.
Reset time
tR
Reset 'L' pulse width
RES
-
tRW
Units
Typ.
Max.
-
-
0.5
µs
0.5
-
-
µs
(VDD = 2.7V to 3.3V, TA = -20 to 75℃)
Item
Signal
Symbol
Reset time
tR
Reset 'L' pulse width
RES
Rating
Condition
-
tRW
Units
Min.
Typ.
Max.
-
-
1.0
µs
1.0
-
-
µs
(VDD = 1.8V to 2.7V, TA = -20 to 75℃)
Item
Signal
Symbol
Reset time
tR
Reset 'L' pulse width
RES
Rating
Condition
-
t
Units
Min.
Typ.
Max.
-
-
1.5
µs
1.5
-
-
µs
Note: All timing is specified with 20% and 80% of VDD as the standard.
9.6. The MPU Interface (Reference Examples)
The SPLC502B can be connected to either 80X86 Series MPUs or
display area can be enlarged by using multiple SPLC502B chips.
to 68000 Series MPUs.
When this is done, the chip select signal can be used to select the
Moreover, The serial interface is possible
to operate the SPLC502B chips with fewer signal lines.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
The
individual ICs to access.
48
MAR. 30, 2007
Version: 1.0
SPLC502B
MPU
SPLC502B
9.6.1. 8080 series MPUs
Figure 26
9.6.2. 6800 series MPUs
VDD
VCC
VDD
A0P
VMA
CS1
Decoder
CS2
DB7 - 0
DB7 - 0
EP
E
RWP
R/W
RESET
GND
SPLC502B
MPU
A15 - 1
C86
A0P
RESET
PS
VSS
RESET
VSS
Figure 27
© ORISE Technology Co., Ltd.
Proprietary & Confidential
49
MAR. 30, 2007
Version: 1.0
SPLC502B
MPU
SPLC502B
9.6.3. Using the serial interface
Figure 28
9.7. Connections between LCD Drivers (Reference Example)
The liquid crystal display area can be enlarged with ease through the use of multiple SPLC502B chips.
Use a same equipment type.
Slave
SPLC502B
Master
SPLC502B
9.7.1. SPLC502B (Master)<->SPLC502B (Slave)
Figure 29
© ORISE Technology Co., Ltd.
Proprietary & Confidential
50
MAR. 30, 2007
Version: 1.0
SPLC502B
9.8. Connections between LCD Drivers (Reference Examples)
The liquid crystal display area can be enlarged with ease through the use of multiple SPLC502B chips. Use a same equipment type, in the
composition of these chips.
9.8.1. Single-chip structure
Figure 30
9.8.2. Double-chip structure
Figure 31
© ORISE Technology Co., Ltd.
Proprietary & Confidential
51
MAR. 30, 2007
Version: 1.0
SPLC502B
10. VLCD Voltage (Voltage between V0 to VSS) relationship of V0 Voltage Regulator Internal Resistor
Ratio Register and Electronic Volume Control Register
000
14.000
001
010
12.000
011
100
10.000
101
110
8.000
111
6.000
The V0 voltage
4.000
regulator internal
resistance ratio
2.000
registers
(D2, D1, D0)
64
61
58
55
52
49
46
43
40
37
34
31
28
25
22
19
16
13
10
7
4
1
0.000
Note: Use External VOUT Power Supply.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
52
MAR. 30, 2007
Version: 1.0
94
115
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
93
107
81
Item
PAD No.
Pad pitch
Bumped pad size
Item
Size
X
Chip Size
-
Chip thickness
483 ± 25µm
1 ~ 82
55
83 ~ 93 (Test Pins)
40
5965
270 ~ 291
116 ~ 269
34
1 ~ 82
40
100
83 ~ 93
25
63.6
270 ~ 291
135
19
116 ~ 269
19
135
Standard
Bump Hardness
50HV
±15HV
Bump Height
18µm
±3µm
Co-planarity (in Chip)
R≦ 2µm
R : Max-Min
Roughness (in Bump)
R≦ 2µm
R : Max-Min
Bump Size
“X” ± 4µm x “Y” ± 4µm
X/Y: bump size
Shear Force
>4.5g/mil^2
53
269
© ORISE Technology Co., Ltd.
Proprietary & Confidential
258
127
116
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG41
SEG40
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG74
SEG73
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG85
SEG84
SEG87
SEG86
SEG88
SEG90
SEG89
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG102
SEG101
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
TEST6
TEST5
VDD
HPM
PS
C86
CLS
MS
VSS
V0
V0
V4
V4
V3
V3
V2
V2
V1
V1
VDD
VDD
VDDA
VDDA
VSS
VSS
VSSA
VSSA
CAP4P
CAP4P
CAP2N
CAP2 N
CAP2P
CAP2P
CAP1 P
CAP1P
CAP1N
CAP1N
CAP3 P
CAP3P
CAP5P
CAP5P
CAP4P
VOUT
VOUT
VOUT
VSSA
VSSA
VSSA
VSS
VSS
VSS
VDDA
VDDA
VDDA
VDD
VDD
VDD
DSEL1
DSEL0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
EP
RWP
VSS
AOP
RESET
VDD
CS2
CS1
VSS
DOF
CL
FR
FRS
TEST
DUMY11
DUMY10
DUMY9
DUMY8
DUMY7
DUMY6
DUMY5
DUMY4
DUMY3
DUMY2
DUMY1
SPLC502B
11. CHIP INFORMATION
11.1. PAD Assignment
16
SPLC502B
1
( 0 ,0 )
COMS2 291
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43 270
11.2. PAD Dimension
Y
Unit
930
94 ~ 115
µm
94 ~ 115
Note1: Chip size included scribe line.
Note2: To ensure that the IC functions properly, please bond all of VDD, VSS, AVDD and AVSS pins.
Note3: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible.
11.3. Bump Characteristic
Note
MAR. 30, 2007
Version: 1.0
SPLC502B
11.4. PAD Locations
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
1
TEST
2552.84
344.15
49
CAP1P
-105.68
344.15
2
FRS
2497.84
344.15
50
CAP2P
-160.68
344.15
3
FR
2442.84
344.15
51
CAP2P
-215.68
344.15
4
CL
2387.84
344.15
52
CAP2N
-279.95
344.15
2332.84
344.15
53
CAP2N
-334.95
344.15
VSS
2277.84
344.15
54
CAP4P
-399.2
344.15
2222.84
344.15
55
CAP4P
-454.2
344.15
8
CS2
2167.84
344.15
56
VSSA
-509.2
344.15
9
VDD
5
6
7
2112.84
344.15
57
VSSA
-564.2
344.15
2057.84
344.15
58
VSS
-619.2
344.15
A0P
2002.84
344.15
59
VSS
-674.2
344.15
12
VSS
1947.84
344.15
60
VDDA
-729.2
344.15
13
RWP
1892.84
344.15
61
VDDA
-784.2
344.15
14
EP
1837.84
344.15
62
VDD
-841
344.15
15
VDD
1782.73
344.15
63
VDD
-896
344.15
16
DB0
1727.84
344.15
64
V1
-955.54
344.15
17
DB1
1672.84
344.15
65
V1
-1010.54
344.15
18
DB2
1617.84
344.15
66
V2
-1065.54
344.15
19
DB3
1562.84
344.15
67
V2
-1120.54
344.15
20
DB4
1507.84
344.15
68
V3
-1175.54
344.15
21
DB5
1452.84
344.15
69
V3
-1230.54
344.15
22
DB6
1397.84
344.15
70
V4
-1285.54
344.15
23
DB7
1342.84
344.15
71
V4
-1340.54
344.15
24
DSEL0
1287.84
344.15
72
V0
-1395.54
344.15
25
DSEL1
1232.84
344.15
73
V0
-1450.54
344.15
26
VDD
1177.84
344.15
74
VSS
-1505.54
344.15
27
VDD
1122.84
344.15
75
MS
-1560.54
344.15
10
11
28
VDD
1067.84
344.15
76
CLS
-1615.54
344.15
29
VDDA
1012.84
344.15
77
C86
-1670.54
344.15
30
VDDA
957.84
344.15
78
PS
-1725.54
344.15
31
VDDA
902.84
344.15
79
-1780.54
344.15
32
VSS
847.84
344.15
80
VDD
-1835.54
344.15
33
VSS
792.84
344.15
81
TEST5
-1890.55
344.15
34
VSS
737.84
344.15
82
TEST6
-1945.55
344.15
35
VSSA
682.84
344.15
83
DUMY1
-2018.99
362.35
36
VSSA
627.84
344.15
84
DUMY2
-2058.99
362.35
37
VSSA
572.84
344.15
85
DUMY3
-2098.99
362.35
38
VOUT
517.84
344.15
86
DUMY4
-2138.99
362.35
39
VOUT
462.84
344.15
87
DUMY5
-2178.99
362.35
40
VOUT
407.84
344.15
88
DUMY6
-2218.99
362.35
41
CAP4P
352.84
344.15
89
DUMY7
-2258.99
362.35
42
CAP5P
297.84
344.15
90
DUMY8
-2298.99
362.35
43
CAP5P
242.84
344.15
91
DUMY9
-2338.99
362.35
44
CAP3P
187.84
344.15
92
DUMY10
-2378.99
362.35
45
CAP3P
132.84
344.15
93
DUMY11
-2421.1
362.35
46
CAP1N
68.57
344.15
94
COM31
-2846.45
357
47
CAP1N
13.57
344.15
95
COM30
-2846.45
323
48
CAP1P
-50.68
344.15
96
COM29
-2846.45
289
© ORISE Technology Co., Ltd.
Proprietary & Confidential
54
MAR. 30, 2007
Version: 1.0
SPLC502B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
97
COM28
-2846.45
255
147
SEG20
-1547.32
-328.95
98
COM27
-2846.45
221
148
SEG21
-1513.32
-328.95
99
COM26
-2846.45
187
149
SEG22
-1479.32
-328.95
100
COM25
-2846.45
153
150
SEG23
-1445.32
-328.95
101
COM24
-2846.45
119
151
SEG24
-1411.32
-328.95
102
COM23
-2846.45
85
152
SEG25
-1377.32
-328.95
103
COM22
-2846.45
51
153
SEG26
-1343.32
-328.95
104
COM21
-2846.45
17
154
SEG27
-1309.32
-328.95
105
COM20
-2846.45
-17
155
SEG28
-1275.32
-328.95
106
COM19
-2846.45
-51
156
SEG29
-1241.32
-328.95
107
COM18
-2846.45
-85
157
SEG30
-1207.32
-328.95
108
COM17
-2846.45
-119
158
SEG31
-1173.32
-328.95
109
COM16
-2846.45
-153
159
SEG32
-1139.32
-328.95
110
COM15
-2846.45
-187
160
SEG33
-1105.32
-328.95
111
COM14
-2846.45
-221
161
SEG34
-1071.32
-328.95
112
COM13
-2846.45
-255
162
SEG35
-1037.32
-328.95
113
COM12
-2846.45
-289
163
SEG36
-1003.32
-328.95
114
COM11
-2846.45
-323
164
SEG37
-969.32
-328.95
115
COM10
-2846.45
-357
165
SEG38
-935.32
-328.95
116
COM9
-2601.32
-328.95
166
SEG39
-901.32
-328.95
117
COM8
-2567.32
-328.95
167
SEG40
-867.32
-328.95
118
COM7
-2533.32
-328.95
168
SEG41
-833.32
-328.95
119
COM6
-2499.32
-328.95
169
SEG42
-799.32
-328.95
120
COM5
-2465.32
-328.95
170
SEG43
-765.32
-328.95
121
COM4
-2431.32
-328.95
171
SEG44
-731.32
-328.95
122
COM3
-2397.32
-328.95
172
SEG45
-697.32
-328.95
123
COM2
-2363.32
-328.95
173
SEG46
-663.32
-328.95
124
COM1
-2329.32
-328.95
174
SEG47
-629.32
-328.95
125
COM0
-2295.32
-328.95
175
SEG48
-595.32
-328.95
126
COMS1
-2261.32
-328.95
176
SEG49
-561.32
-328.95
127
SEG0
-2227.32
-328.95
177
SEG50
-527.32
-328.95
128
SEG1
-2193.32
-328.95
178
SEG51
-493.32
-328.95
129
SEG2
-2159.32
-328.95
179
SEG52
-459.32
-328.95
130
SEG3
-2125.32
-328.95
180
SEG53
-425.32
-328.95
131
SEG4
-2091.32
-328.95
181
SEG54
-391.32
-328.95
132
SEG5
-2057.32
-328.95
182
SEG55
-357.32
-328.95
133
SEG6
-2023.32
-328.95
183
SEG56
-323.32
-328.95
134
SEG7
-1989.32
-328.95
184
SEG57
-289.32
-328.95
135
SEG8
-1955.32
-328.95
185
SEG58
-255.32
-328.95
136
SEG9
-1921.32
-328.95
186
SEG59
-221.32
-328.95
137
SEG10
-1887.32
-328.95
187
SEG60
-187.32
-328.95
138
SEG11
-1853.32
-328.95
188
SEG61
-153.32
-328.95
139
SEG12
-1819.32
-328.95
189
SEG62
-119.32
-328.95
140
SEG13
-1785.32
-328.95
190
SEG63
-85.32
-328.95
141
SEG14
-1751.32
-328.95
191
SEG64
-51.32
-328.95
142
SEG15
-1717.32
-328.95
192
SEG65
-17.32
-328.95
143
SEG16
-1683.32
-328.95
193
SEG66
16.68
-328.95
144
SEG17
-1649.32
-328.95
194
SEG67
50.68
-328.95
145
SEG18
-1615.32
-328.95
195
SEG68
84.68
-328.95
146
SEG19
-1581.32
-328.95
196
SEG69
118.68
-328.95
© ORISE Technology Co., Ltd.
Proprietary & Confidential
55
MAR. 30, 2007
Version: 1.0
SPLC502B
PAD No.
PAD Name
X
Y
PAD No.
PAD Name
X
Y
197
SEG70
152.68
-328.95
247
SEG120
1852.68
-328.95
198
SEG71
186.68
-328.95
248
SEG121
1886.68
-328.95
199
SEG72
220.68
-328.95
249
SEG122
1920.68
-328.95
200
SEG73
254.68
-328.95
250
SEG123
1954.68
-328.95
201
SEG74
288.68
-328.95
251
SEG124
1988.68
-328.95
202
SEG75
322.68
-328.95
252
SEG125
2022.68
-328.95
203
SEG76
356.68
-328.95
253
SEG126
2056.68
-328.95
204
SEG77
390.68
-328.95
254
SEG127
2090.68
-328.95
205
SEG78
424.68
-328.95
255
SEG128
2124.68
-328.95
206
SEG79
458.68
-328.95
256
SEG129
2158.68
-328.95
207
SEG80
492.68
-328.95
257
SEG130
2192.68
-328.95
208
SEG81
526.68
-328.95
258
SEG131
2226.68
-328.95
209
SEG82
560.68
-328.95
259
COM32
2260.68
-328.95
210
SEG83
594.68
-328.95
260
COM33
2294.68
-328.95
211
SEG84
628.68
-328.95
261
COM34
2328.68
-328.95
212
SEG85
662.68
-328.95
262
COM35
2362.68
-328.95
213
SEG86
696.68
-328.95
263
COM36
2396.68
-328.95
214
SEG87
730.68
-328.95
264
COM37
2430.68
-328.95
215
SEG88
764.68
-328.95
265
COM38
2464.68
-328.95
216
SEG89
798.68
-328.95
266
COM39
2498.68
-328.95
217
SEG90
832.68
-328.95
267
COM40
2532.68
-328.95
218
SEG91
866.68
-328.95
268
COM41
2566.68
-328.95
219
SEG92
900.68
-328.95
269
COM42
2600.68
-328.95
220
SEG93
934.68
-328.95
270
COM43
2845.81
-357
221
SEG94
968.68
-328.95
271
COM44
2845.81
-323
222
SEG95
1002.68
-328.95
272
COM45
2845.81
-289
223
SEG96
1036.68
-328.95
273
COM46
2845.81
-255
224
SEG97
1070.68
-328.95
274
COM47
2845.81
-221
225
SEG98
1104.68
-328.95
275
COM48
2845.81
-187
226
SEG99
1138.68
-328.95
276
COM49
2845.81
-153
227
SEG100
1172.68
-328.95
277
COM50
2845.81
-119
228
SEG101
1206.68
-328.95
278
COM51
2845.81
-85
229
SEG102
1240.68
-328.95
279
COM52
2845.81
-51
230
SEG103
1274.68
-328.95
280
COM53
2845.81
-17
231
SEG104
1308.68
-328.95
281
COM54
2845.81
17
232
SEG105
1342.68
-328.95
282
COM55
2845.81
51
233
SEG106
1376.68
-328.95
283
COM56
2845.81
85
234
SEG107
1410.68
-328.95
284
COM57
2845.81
119
235
SEG108
1444.68
-328.95
285
COM58
2845.81
153
236
SEG109
1478.68
-328.95
286
COM59
2845.81
187
237
SEG110
1512.68
-328.95
287
COM60
2845.81
221
238
SEG111
1546.68
-328.95
288
COM61
2845.81
255
239
SEG112
1580.68
-328.95
289
COM62
2845.81
289
240
SEG113
1614.68
-328.95
290
COM63
2845.81
323
241
SEG114
1648.68
-328.95
291
COMS2
2845.81
357
242
SEG115
1682.68
-328.95
243
SEG116
1716.68
-328.95
244
SEG117
1750.68
-328.95
245
SEG118
1784.68
-328.95
246
SEG119
1818.68
-328.95
© ORISE Technology Co., Ltd.
Proprietary & Confidential
56
MAR. 30, 2007
Version: 1.0
SPLC502B
11.5. COG Align Key Coordinate
-- Alignment Mark coordinate
Left (-2594.27, 148.43)
Right (2586.56, 148.43)
-- Alignment Mark size
© ORISE Technology Co., Ltd.
Proprietary & Confidential
57
MAR. 30, 2007
Version: 1.0
SPLC502B
12. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only.
ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement.
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
alter the specifications and prices at any time without notice.
Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders.
applications.
FURTHERMORE, ORISE Technology MAKES NO
ORISE Technology reserves the right to halt production or
Products described herein are intended for use in normal commercial
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by ORISE Technology for such applications.
Please note that
application circuits illustrated in this document are for reference purposes only.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
58
MAR. 30, 2007
Version: 1.0
SPLC502B
13. REVISION HISTORY
Date
Revision #
Description
MAR. 30, 2007
1.0
Release Version
JAN. 12, 2007
0.7
Modify temperature range
39 - 48
Modify note *11
DEC. 05, 2006
0.6
41
1. Move Ordering Information to Chapter 3
4
2. Modify 6.11.2. The voltage regulator circuit
19
3. Modify Reference Circuit Examples(Note)
JUL. 24, 2006
0.5
0.4
5. Modify 7.21 Set Driving Mode (Double Byte Command)
32
6. Add PAD Dimension
53
7. Add Bump Characteristic
53
1. Update 4.5 Test Terminals
9
2. Modify Figure 13
22
3. Modify *10.
41
1. Modify 10.1. PAD Assignment and Locations
2. Modify 10.3. PAD Locations (No. 83~93)
JUL. 18, 2006
0.3
JUL. 11, 2006
0.2
3. Remove *3 IRS & *5 IRS
41
55
1. Modify block diagram
5
2. Modify SIGNAL DESCRIPTIONS(PIN NO.)
6
19
4. Modify 5.14.1.1 (Figure 12) & 5.14.1.2 (Figure 13)
0.1
© ORISE Technology Co., Ltd.
Proprietary & Confidential
53
55,56
Modify PAD No. (5, 7, 10, 79)
3. Remove 5.11.2.2 & 5.11.2.3
APR. 07, 2006
21
21、22
4. Modify Figure 12、13
JUL. 26, 2006
Page
21,22
5. Modify 6.19.2 Table : Change (one second / 0.5 second)
31
6. Insert 6.21 Set Driving Mode (Double Byte Command)
33
7. Add 6.25 Oscillator Frequency selection
34
8. Modify 6.26 Table : Add 21). & 25)
36
9. Update 10.1 Chip Size
53
Original
56
59
MAR. 30, 2007
Version: 1.0