SPFD5408B 720-channel 6-bit Source Driver with System-on-chip for Color Amorphous TFT-LCDs Preliminary OCT. 29, 2007 Version 0.1 ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE. Preliminary SPFD5408B Table of Contents PAGE 1. GENERAL DESCRIPTION .......................................................................................................................................................................... 5 2. FEATURE .................................................................................................................................................................................................... 5 3. ORDERING INFORMATION........................................................................................................................................................................ 5 4. BLOCK DIAGRAM ...................................................................................................................................................................................... 6 4.1. BLOCK FUNCTION .................................................................................................................................................................................. 6 4.2. SYSTEM INTERFACE ............................................................................................................................................................................... 7 4.2.1. The SPFD5408B supports three high-speed system interfaces: ........................................................................................... 7 4.2.2. External Display Interface ...................................................................................................................................................... 7 4.2.3. Address Counter (AC) ............................................................................................................................................................ 7 4.2.4. Graphics RAM (GRAM).......................................................................................................................................................... 7 4.2.5. Grayscale Voltage Generating Circuit .................................................................................................................................... 7 4.2.6. Timing Controller .................................................................................................................................................................... 7 4.2.7. Oscillator (OSC) ..................................................................................................................................................................... 7 4.2.8. Source Driver Circuit .............................................................................................................................................................. 7 4.2.9. Gate Driver Circuit.................................................................................................................................................................. 7 4.2.10. LCD Driving Power Supply Circuit.......................................................................................................................................... 7 5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 8 6. INSTRUCTIONS ........................................................................................................................................................................................ 13 6.1. OUTLINE .............................................................................................................................................................................................. 13 6.2. INSTRUCTION ....................................................................................................................................................................................... 14 6.2.1. Index Register (IR) ............................................................................................................................................................... 15 6.2.2. ID Read Register (SR) ......................................................................................................................................................... 15 6.2.3. Driver Output Control Register (R01h) ................................................................................................................................. 15 6.2.4. LCD Driving Waveform Control (R02h) ................................................................................................................................ 16 6.2.5. Entry Mode (R03h) ............................................................................................................................................................... 16 6.2.6. Scaling Control register (R04h) ............................................................................................................................................ 17 6.2.7. Display Control (R07h) ......................................................................................................................................................... 17 6.2.8. Display Control 2 (R08h) ...................................................................................................................................................... 18 6.2.9. Display Control 3 (R09h) ...................................................................................................................................................... 19 6.2.10. Frame Cycle Control (R0Ah) ................................................................................................................................................ 20 6.2.11. External Display Interface Control 1 (R0Ch) ........................................................................................................................ 21 6.2.12. Frame Maker Position (R0Dh).............................................................................................................................................. 22 6.2.13. External Display Interface Control 2 (R0Fh) ........................................................................................................................ 22 6.2.14. Power Control 1 (R10h)........................................................................................................................................................ 23 6.2.15. Power Control 2 (R11h)........................................................................................................................................................ 24 6.2.16. Power Control 3 (R12h)........................................................................................................................................................ 25 6.2.17. Power Control 4 (R13h)........................................................................................................................................................ 26 6.2.18. GRAM Address Set (Horizontal Address) (R20h)................................................................................................................. 27 6.2.19. GRAM Address Set (Vertical Address) (R21h) ..................................................................................................................... 27 6.2.20. Write Data to GRAM (R22h)................................................................................................................................................. 28 6.2.21. Read Data Read from GRAM (R22h)................................................................................................................................... 31 6.2.22. NVM read data 1 (R28h) ...................................................................................................................................................... 31 6.2.23. NVM read data 2 (R29h) ...................................................................................................................................................... 31 © ORISE Technology Co., Ltd. Proprietary & Confidential 2 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.24. NVM read data 3 (R2Ah)...................................................................................................................................................... 32 6.2.25. γ Control (R30h to R3Fh) ..................................................................................................................................................... 33 6.2.26. Window Horizontal RAM Address Start (R50h) .................................................................................................................... 33 6.2.27. Window Horizontal RAM Address End (R51h) ..................................................................................................................... 33 6.2.28. Window Vertical RAM Address Start (R52h) ........................................................................................................................ 34 6.2.29. Window Vertical RAM Address End (R53h) ......................................................................................................................... 34 6.2.30. Driver Output Control (R60h) ............................................................................................................................................... 34 6.2.31. Driver Output Control (R61h) ............................................................................................................................................... 36 6.2.32. Vertical Scroll Control (R6Ah)............................................................................................................................................... 36 6.2.33. Display Position – Partial Display 1 (R80h).......................................................................................................................... 36 6.2.34. RAM Address Start – Partial Display 1 (R81h) ..................................................................................................................... 36 6.2.35. RAM Address End – Partial Display 1 (R82h) ...................................................................................................................... 37 6.2.36. Display Position – Partial Display 2 (R83h).......................................................................................................................... 37 6.2.37. RAM Address Start – Partial Display 2 (R84h) ..................................................................................................................... 37 6.2.38. RAM Address End – Partial Display 2 (R85h) ...................................................................................................................... 37 6.2.39. Panel Interface Control 1 (R90h).......................................................................................................................................... 37 6.2.40. Panel Interface Control 2 (R92h).......................................................................................................................................... 38 6.2.41. Panel Interface control 3 (R93h) .......................................................................................................................................... 39 6.2.42. Panel Interface control 4 (R95h) .......................................................................................................................................... 39 6.2.43. Panel Interface Control 5 (R97h).......................................................................................................................................... 41 6.2.44. Panel Interface Control 6 (R98h).......................................................................................................................................... 42 6.2.45. Calibration Control (RA4h) ................................................................................................................................................... 42 7. GRAM ........................................................................................................................................................................................................ 43 8. INTERFACES ............................................................................................................................................................................................ 45 8.1. SYSTEM INTERFACE ............................................................................................................................................................................. 45 8.1.1. 80-system 18-bit interface .................................................................................................................................................... 46 8.1.2. 80-system 16-bit interface .................................................................................................................................................... 46 8.1.3. 80-system 9-bit interface ...................................................................................................................................................... 46 8.1.4. 80-system 8-bit interface ...................................................................................................................................................... 46 8.1.5. Serial Peripheral interface (SPI)........................................................................................................................................... 47 8.2. VSYNC INTERFACE ............................................................................................................................................................................. 48 8.3. EXTERNAL DISPLAY INTERFACE ............................................................................................................................................................ 49 8.3.1. 6-bit RGB interface............................................................................................................................................................... 50 8.3.2. 16-bit RGB interface............................................................................................................................................................. 51 8.3.3. 18-bit RGB interface............................................................................................................................................................. 51 8.4. SEQUENCE TO SET BETWEEN SYSTEM INTERFACE AND RGB INTERFACE:................................................................................................ 52 9. DISPLAY FEATURE FUNCTION: ..................................................................................................................................................................... 53 9.1. FMARK FUNCTION: ............................................................................................................................................................................. 53 9.2. SCAN MODE FUNCTION: ....................................................................................................................................................................... 54 9.3. SCALING FUNCTION:............................................................................................................................................................................. 55 9.4. PARTIAL DISPLAY FUNCTION: ................................................................................................................................................................ 57 9.5. GAMMA CORRECTION FUNCTIONS:........................................................................................................................................................ 59 10. POWER MANAGEMENT SYSTEM: .................................................................................................................................................................. 60 11. APPLICATION CIRCUITS:............................................................................................................................................................................... 63 12. INITIAL CODE:.............................................................................................................................................................................................. 64 © ORISE Technology Co., Ltd. Proprietary & Confidential 3 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 13. POWER ON/OFF SEQUENCE ......................................................................................................................................................................... 65 13.1. POWER ON/OFF SEQUENCE DIAGRAM .................................................................................................................................................. 65 13.2. DISPLAY ON/OFF SEQUENCE: .............................................................................................................................................................. 66 13.3. SEQUENCE TO EXIT SLEEP MODE: ......................................................................................................................................................... 67 14. ELECTRICAL CHARACTERISTICS:.................................................................................................................................................................. 68 14.1. ABSOLUTE MAXIMUM RATINGS: ............................................................................................................................................................ 68 14.2. DC CHARACTERISTICS ......................................................................................................................................................................... 68 14.3. AC CHARACTERISTICS ......................................................................................................................................................................... 69 14.3.1. Clock Characteristics............................................................................................................................................................ 69 14.3.2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface).............................................................................. 69 14.3.3. Clock-synchronized Serial Interface Timing Characteristics ................................................................................................ 71 14.3.4. Reset Timing Characteristics (IOVCC=1.65~3.30V) ............................................................................................................ 71 14.3.5. RGB Interface Timing Characteristics .................................................................................................................................. 72 15. CHIP INFORMATION ................................................................................................................................................................................ 73 15.1. PAD ASSIGNMENT ............................................................................................................................................................................... 73 15.2. PAD DIMENSION .................................................................................................................................................................................. 73 15.3. BUMP DIMENSION ................................................................................................................................................................................ 73 15.3.1. Output Pads ......................................................................................................................................................................... 73 15.3.2. Input Pads ............................................................................................................................................................................ 73 15.4. BUMP CHARACTERISTICS ..................................................................................................................................................................... 73 15.5. PAD LOCATIONS .................................................................................................................................................................................. 74 15.6. ALIGNMENT MARK................................................................................................................................................................................ 82 16. REVISION HISTORY ................................................................................................................................................................................. 84 © ORISE Technology Co., Ltd. Proprietary & Confidential 4 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 720-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC) FOR COLOR AMORPHOUS TFT LCD 1. GENERAL DESCRIPTION The SPFD5408B, a 262144-color System-on-Chip (SoC) driver Line Inversion AC drive / frame inversion AC drive LSI designed for small and medium sizes of TFT LCD display, is System interfaces − High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. − Serial Peripheral Interface (SPI) The 720-channel source driver has true 6-bit resolution, which Interfaces for moving picture display − 6-, 16-, and 18-bit RGB interfaces generates 64 Gamma-corrected values by an internal D/A converter. Diverse RAM accessing for functional display − Window address function to display at any area on the The SPFD5408B is able to operate with low IO interface power screen via a moving picture display interface − Window address function to limit the data rewriting area supply up to 1.6V and incorporate with several charge pumps to generate various voltage levels that form an on-chip power and reduce data transfer − Moving and still picture can display at the same time management system for gate driver and source driver. − Vertical scrolling function − Partial screen display The built-in timing controller in SPFD5408B can support several interfaces for the diverse request of medium or small size portable Power supply display. SPFD5408B provides system interfaces, which include − Logic power supply voltage (Vcc): 2.5 ~ 3.3 V 8-/9-/16-/18-bit parallel interfaces and serial interface (SPI), to − I/O interface supply voltage (IOVcc): 1.65 ~ 3.3 V − Analog power supply voltage (Vci): 2.5 ~ 3.3 V configure system. Not only can the system interfaces be used to configure system, they can also access RAM at high speed for still picture display. In addition, the SPFD5408B incorporates 6, 16, On-chip power management system Resize function( x 1/2, x 1/4) − Power saving mode (standby / 8-color mode, etc) and 18-bit RGB interfaces for picture movement display. The − Low power consumption structure for source driver. SPFD5408B also supports a function to display eight colors and a standby mode for power control consideration. Built-in Charge Pump circuits − Source driver voltage level: DDVDH-GND=4.5V ~ 6V. − Gate driver voltage level (VGH, VGL) 2. FEATURE One-chip solution for amorphous TFT-LCD. VGH = 10.0V ~20.0V Supports resolution up to 240xRGBx320, incorporating a VGL = -4.5V ~ -13.5V VGH – VGL < 28.0V 720-channel source driver and a 320-channel gate driver − Built-in internal oscillator and hardware reset Outputs 64 γ -corrected values using an internal true 6-bit resolution D/A converter to achieve 262K colors Built-in 172800 bytes internal RAM 3. ORDERING INFORMATION Product Number Package Type SPFD5408B-C1 Chip Form with Gold Bump © ORISE Technology Co., Ltd. Proprietary & Confidential 5 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 4. BLOCK DIAGRAM 4.1. Block Function S1 OTP Memory WR*/SCL SDI SDO IM[3:1],IM0/ID CS* RS S2 S719 S720 Source Driver (720 channels) System Interface True 6-bit D/A Converter 6 6 6 6 Level Shifter (720 x 6bits) DB[17:0] 18 ENABLE DOTCLK VSYNC HSYNC RGB Interface Graphics RAM 172800 bytes 6 18 6 6 6 Data Latch (240 x 3 x 6bits) Shift Register (240 bits) Gamma Voltage Generator VCIOUT VREG1OUT Regulator Timing Signal Generator C21P/N Internal Clock CLK C22P/N Generator © ORISE Technology Co., Ltd. Proprietary & Confidential VCOM VCOMH VCOM VCOML Gate Driver G[320:1] VLOUT1 /DDVDH VCI1 C11P/N C12P/N 64 Gate Power Charge Pump VLOUT2 /VGH VLOUT3 /VGL VLOUT4 /VCL 6 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 4.2. System Interface 4.2.4. Graphics RAM (GRAM) 4.2.1. The SPFD5408B supports three high-speed SPFD5408B features a 172800-byte (240 x 320 x 18 / 8) Graphic system interfaces: RAM (GRAM). 1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 4.2.5. Grayscale Voltage Generating Circuit 2. Serial Peripheral Interface (SPI). SPFD5408B has true 6-bit resolution D/A converter, which The SPFD5408B has a 16-bit index register (IR) and two 18-bit generates 64 Gamma-corrected values and cooperates with data registers, a write-data register (WDR) and a read-data OP-AMP structure to enhance display quality. The grayscale register (RDR). voltage can be adjusted by grayscale data set in the γ-correction The IR register is used to store index information register. from control registers. The WDR register is used to temporarily store data to be written for register control and internal GRAM. The RDR register is used to temporarily store data read from the 4.2.6. Timing Controller GRAM. When graphic data is written to the internal GRAM from SPFD5408B has a timing controller, which can generate a timing MCU/graphic engine, the data is first written to the WDR and then signal for internal circuit operation such as gate output timing, automatically written to the internal GRAM in internal operation. RAM accessing timing, etc. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore, invalid data 4.2.7. Oscillator (OSC) is first read out to the data bus when the SPFD5408B executes st the 1 read operation. The SPFD5408B also features an internal oscillator to generate Thus, valid data can be read out after the RC oscillation with an internal resistor. In standby mode, RC nd SPFD5408B executes the 2 read operation. oscillation is halted to reduce power consumption. 4.2.2. External Display Interface 4.2.8. Source Driver Circuit The SPFD5408B supports external RGB interface for picture SPFD5408B consists of a 720-output source driver circuit (S1 ~ movement display. The SPFD5408B allows switching between one of the external display interfaces and the system interface via pin configuration so th S720). Data in the GRAM are latched when the 720 bit data is input. The latched data controls the source driver and generates a drive waveform. that the optimum interface is selected for still / moving picture displayed on the screen. 4.2.9. Gate Driver Circuit SPFD5408B When the RGB interface is chosen, display operations are consists of a 320-output gate driver circuit (G1~G320). The gate driver circuit outputs gate driver signals at synchronized with external supplied signals, VSYNC, HSYNC, and either VGH or VGL level. DOTCLK. Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling. 4.2.10. LCD Driving Power Supply Circuit The LCD driving power supply circuit generates the voltage levels 4.2.3. Address Counter (AC) DDVDH, VLOUT1, VLOUT2 and VCOM for driving an LCD. All this SPFD5408B features an Address Counter (AC) giving an address voltages can be adjusted by register setting. to the internal GRAM. The address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. © ORISE Technology Co., Ltd. Proprietary & Confidential 7 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 5. SIGNAL DESCRIPTIONS Signal Pin No. I/O Connected with Function System Configuration Input Signal IM3~1, IM0/ID 4 I GND/ IOVCC Select a mode to interface to an MPU. In serial interface operation, the IM0 pin is used to set the ID bit of device code. IM3 IM2 IM1 IM0/ ID Interface Mode DB Pin 0 0 0 0 Setting disabled - - 0 0 0 1 Setting disabled - - 0 0 1 0 80-system 16-bit interface 0 0 1 1 80-system 8-bit interface DB17-10 0 1 0 *(ID) Clock synchronous serial interface - 65,536 0 1 1 0 Setting disabled - - 0 1 1 1 Setting disabled - - 1 0 0 0 Setting disabled - - 1 0 0 1 Setting disabled - - 1 0 1 0 DB17-0 262,144 1 0 1 1 DB17-9 262,144 1 1 0 0 Setting disabled - - 1 1 0 1 Setting disabled - - 1 1 1 0 Setting disabled - - 1 1 1 1 Setting disabled - - 80-system 18-bit interface 80-system 9-bit interface DB17-10, DB8-1 Colors 262,144 see Note 1 262,144 see Note 2 Notes: 1. 65,536 colors in one transfer mode 2. 65,536 colors in two transfers mode /RESET 1 I MPU or RESET pin. This is an active low signal. external RC circuit Interface input Signals /CS 1 I MPU Chip select signal. Low: the SPFD5408B is accessible High: the SPFD5408B is not accessible Must connect to the GND or IOVCC level when not used. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. RS 1 I MPU Register select signal. Low: Index register or internal status is selected. High: Control register is selected. Must connect to the GND or IOVCC level when not used. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. (/WR) / (SCL) 1 I MPU (A) In 80-system interface mode, a write strobe signal can be input via this pin and initializes a write operation when the signal is low. (B) In SPI mode, served as a synchronizing clock signal. © ORISE Technology Co., Ltd. Proprietary & Confidential 8 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Signal Pin No. I/O Connected with Function This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. /RD 1 I MPU In 80-system interface mode, a read strobe signal can be input via this pin and initializes a read operation when the signal is low. Must connect to the GND or IOVCC level when not in use. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. SDI 1 I MPU Series Data is the input on the rising edge of the SCL signal in SPI mode. Must connect to the GND or IOVCC level when not in use. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. SDO 1 O MPU Series Data is the output on the rising edge of the SCL signal in SPI mode. DB0-DB17 1 I/O MPU Served as an 18-bit parallel bi-directional data bus. Data bus pin assignment corresponding to different modes are summarized in the table: Mode Pin Assignment 8-bit system interface DB17-DB10 9-bit system interface DB17-DB9 16-bit system interface DB17-DB10, DB8-DB1 18-bit system interface DB17-DB0 6-bit External (RGB) interface DB17-DB12 16-bit External (RGB) interface DB17-13, DB11-DB1 18-bit External (RGB) interface DB17-DB0 Must connect to the GND or IOVCC level when not in use. These pins have weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. VSYNC 1 I MPU In external interface mode, served as a vertical synchronize signal input Must connect to the IOVCC or GND level when not in use. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. HSYNC 1 I MPU In external interface mode, served as a horizontal synchronized signal input Must connect to the IOVCC or GND level when not used. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. ENABLE 1 I MPU In external interface mode, polarity of ENABLE signal is synchronized with valid graphic data input. Low: Valid data on DB17-DB0 High: Invalid data on DB17-DB0 Moreover, setting EPL bit can change the polarity of the ENABLE signal. Must connect to the GND or IOVCC level when not in use. This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. DOTCLK 1 I MPU In external interface mode, served as a dot clock signal. When DPL = “0”: Input data on the rising edge of DOTCLK When DPL = “1”: Input data on the falling edge of DOTCLK It is fixed to the IOVCC level when not in use. © ORISE Technology Co., Ltd. Proprietary & Confidential 9 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Signal Pin No. I/O Connected with Function This pin has weak pull high/low resistors and can be modified to high / low by metal layer change for customer’s request. FMARK 1 O MPU Frame head pulse signal, which is used when writing data to the internal RAM. Keep this pin open when not used. Charge Pump and Power Supply Signal C11P/N, 12 - C12P/N Step-up Connect boost capacitors for the internal DC/DC converter circuit to these capacitor pins. C13P/N Leave the pins open when DC/DC converter circuits are not used. C21P/N, C22P/N C23P/N VCIOUT 1 O Stabilizing Output voltage from the step-up circuit 1, generated from the reference capacitor, VCI1 voltage. VC bits set the output factor. Make sure to connect to stabilizing capacitor. VCI1 1 I/O VCIOUT Reference voltage of step-up circuit 1. Make sure the output voltage levels from VLOUT1, VLOUT2, and VLOUT3 do not exceed the respective setting ranges. VLOUT1 DDVDH 1 1 O I Stabilizing Output voltage from the step-up circuit 1, generated from VCI1. The step-up capacitor, factor is set by BT. Make sure to connect to stabilizing capacitor. DDVDH VLOUT1 = 4.5V ~ 6.0V VLOUT1 Power supply for the source driver liquid crystal drive unit and VCOM drive. Connect to VLOUT1. DDVDH = 4.5V ~ 6.0V VLOUT2 1 O Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and DDVDH. capacitor, VGH The step-up factor is set by BT. Make sure to connect to stabilizing capacitor. VLOUT2 = max 15.0V VGH 1 I VLOUT3 1 O VLOUT2 Liquid crystal drive power supply. Connect to VLOUT2. Stabilizing Output voltage from the step-up circuit 2, generated from VCI1 and DDVDH. capacitor, VGL The step-up factor is set by BT bits. Make sure to connect to stabilizing capacitor. VLOUT3 = min –12.5V VGL 1 I VCL 1 O VCILVL I VLOUT3 Liquid crystal drive power supply. Connect to VLOUT3. Stabilizing VCOML drive power supply. Make sure to connect to stabilizing capacitor. capacitor VCL = -1.9V ~ -3.0V Reference VCILVL must be at the same electrical potential as VCI. VCILVL = 2.5V ~ power supply 3.3V. Connect to external power supply. In case of COG, connect to VCI on the FPC to prevent noise. VPP2 I Power supply or Power supply. open Source/Gate Driver and VCOM Signals G1~G320 320 O LCD Output gate driver signals, which has the swing from VGH to VGL S1~S720 720 O LCD Output source driver signals. The D/A converted 64-gray-scale analog voltage is output. VREG1 OUT 1 O Stabilizing Output voltage generated from the reference voltage (VCILVL or VCIR). The capacitor factor is determined by instruction (VRH bits). VREG1OUT is used for (1) source driver grayscale reference voltage, (2) VCOMH level reference voltage, and (3) VCOM amplitude reference voltage. Connect to a stabilizing capacitor © ORISE Technology Co., Ltd. Proprietary & Confidential 10 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Signal Pin No. I/O VCOM 1 O Connected with Function when in use. VREG1OUT = 4.0V ~ (DDVDH – 0.5)V VCOMH 1 O TFT panel Power supply to TFT panel’s common electrode. VCOM alternates between common VCOMH and VCOML. The alternating cycle is set by internal register. Also, the electrode VCOM output can be started and halted by register setting. Stabilizing The High level of VCOM amplitude. The output level can be adjusted by either capacitor external resistor (VCOMR) or electronic volume. Make sure to connect to stabilizing capacitor. VCOML 1 O Stabilizing The Low level of VCOM amplitude. The output level can be adjusted by capacitor instruction (VDV bits). VCOML = (VCL+0.5) V ~ 0V. Make sure to connect to stabilizing capacitor. VCOMR 1 I Variable resistor or open Connect a variable resistor when adjusting the VCOMH level between VREG1OUT and GND. VGS 1 I GND VCC 1 - Power supply Internal logic power: VCC = 2.5V ~3.3V. VCC > IOVCC. GND 1 - Power supply Internal logic GND: GND = 0V. RGND 1 - VDD IOVCC 1 1 O - Power supply Reference level for the grayscale voltage generating circuit. Internal RAM GND. RGND must be at the same electrical potential as GND. In case of COG, connect to GND on the FPC to prevent noise. Stabilizing Internal logic regulator output, which is used as the power supply to internal capacitor logic. Connect a stabilizing capacitor. Power supply Power supply to the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOVCC = 1.65V ~ 3.3V. VCC ≥IOVCC. In case of COG, connect to VCC on the FPC if IOVCC=VCC, to prevent noise. IOGND 1 - Power supply GND for the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. AGND 1 - Power supply Analog GND (for logic regulator and liquid crystal power supply circuit): AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. VCI VCILVL 1 1 I I Power supply Power supply to the liquid crystal power supply analog circuit. Connect to an external power supply of 2.5V ~ 3.3V. Reference VCILVL must be at the same electrical potential as VCI. VCILVL = 2.5V ~ power supply 3.3V. Connect to external power supply. In case of COG, connect to VCI on the FPC to prevent noise. Misc. Signal V0T, V31T 2 VTEST 1 I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. VREFC 1 VREF 1 VDDTEST VREFD 1 1 Test pins. Leave them open. Test pins. Leave them open. Test pins. Leave them open. Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. VMON 1 Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. TESTA5 1 © ORISE Technology Co., Ltd. Proprietary & Confidential Test pins. Leave them open. SPFD5408B use these pins to do self-test. 11 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Signal Pin No. IOVCCDUM1~2 2 I/O Connected with Function No any signal on panel can cross these pins, otherwise function fail. VCCDUM1 1 IOGNDDUM1~3 3 OSC1DUM1~4 4 I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I/O Open I IOGND I IOVCC I IOVCC I IOGND I IOGND I/O Open Test pins. Leave them open. Test pins. Leave them open. Test pins. Leave them open. Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. OSC2DUM1~2 2 Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. AGNDDUM1~4 4 DUMMYR1~10 10 Test pins. Leave them open. Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. VGLDMY1~4 4 TESTO2~38 37 TEST1~2 2 TEST3 1 TEST4 1 TEST5 1 TSC 1 TS0~8 9 Test pins. Leave them open. Test pins. Leave them open. Test pins. Connect to IOGND. Test pins. Connect to IOVCC. Test pins. Connect to IOVCC. Test pins. Connect to IOGND. Test pins. Connect to IOGND. Test pins. Leave them open. SPFD5408B use these pins to do self-test. No any signal on panel can cross these pins, otherwise function fail. © ORISE Technology Co., Ltd. Proprietary & Confidential 12 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6. INSTRUCTIONS 6.1. Outline The SPFD5408B supports 18-bit data bus interface to access The instruction can be categorized into 8 groups. And the 8 groups command register to configure system. When the command are: register accessing is desired, sending the command information to 1. Specify the index of register specify which index register would be accessed and following the 2. Read a status data to that control register. Moreover, register accessing 3. Display control operation should cooperate with RS, /WR, /RD signal for 4. Power management Control SPFD5408B to recognize the control instruction. And command 5. Graphics data processing instruction can be accomplished by using all system interfaces 6. Set internal GRAM address (18-bit, 16-bit, 9-bit, 8-bit 80 system and SPI). The corresponding 7. Transfer data to and from the internal GRAM pin assignment of different system interface are shown in Figure 8. Internal grayscale γ-correction 6-1 to Figure 6-6 80-system 18-bit interface 80-system 8-bit interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 DB 9 DB 8 CB 7 DB 7 CB 6 DB 6 CB 5 DB 5 CB 4 DB 4 CB 3 DB 3 CB 2 DB 2 CB 1 DB 1 1st Transfer DB 0 CB 0 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 Figure 6-1 Figure 6-4 Serial interface Data Format 80-system 16-bit interface DB 17 CB 15 DB 16 CB 14 DB 15 CB 13 DB 14 CB 12 DB 13 DB 12 CB 11 CB 10 DB 11 CB 9 DB 10 DB 8 CB 8 CB 7 DB 7 CB 6 DB 6 CB 5 DB 5 CB 4 DB 4 CB 3 DB 3 CB 2 DB 2 CB 1 1st Transfer DB 1 2nd Transfer D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 CB 0 Figure 6-2 80-system 9-bit interface 1st Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 Figure 6-5 2nd Transfer DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 Serial interface Data Transfer Format Transfer end Transfer Start CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CS (input) CB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 1 1 0 ID RS RW D15 D14 D13 D12 D11 RS RW 14 15 16 17 18 19 D10 D9 D8 D7 D6 D5 20 21 22 23 D2 D1 24 SCL (input) MSB Figure 6-3 SDI (input) Device ID code SDO (output) D15 D14 D13 D12 D11 LSB D10 D9 D8 D7 D6 D5 D4 D4 D3 D3 D2 D1 D0 D0 Figure 6-6 © ORISE Technology Co., Ltd. Proprietary & Confidential 13 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2. Instruction Table 6-1 Instruction List Table Register No Register CB15 0 0 CB14 1 0 CB13 0 0 CB12 1 0 Upper 8-bit CB11 0 0 0 0 0 0 0 CB10 1 SM (0) 1 00h 01h ID Read Driver Output Control 02h 03h LCD Drive Waveform Control Entry Mode 04h TRIREG (0) 0 DFM (0) 0 0 0 0 BGR (0) 0 0 Scaling Control 0 0 Display Control (1) 0 0 PTDE0 (0) 0 0 0 RCV1 (0) 0 07h FP2 (0) PTS2 (0) 0 FP1 (0) PTS1 (0) 0 CB9 0 0 B/C (0) 0 Lower 8-bit CB4 CB3 0 1 0 0 CB8 0 SS (0) 0 CB7 0 0 CB6 0 0 CB5 0 0 0 0 0 0 0 ORG (0) 0 0 0 0 0 I/D1 (1) RCH1 (0) 0 RCV0 (0) BASEE (0) FP0 (0) PTS0 (0) 0 08h Display Control (2) 0 0 PTDE1 (0) 0 09h Display Control (3) 0 0 0 0 FP3 (1) 0 0Ah Frame Cycle Control 0 0 0 0 0 0Ch External Display interface control (1) Frame Maker Position 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10h External Display interface control (2) Power Control (1) 0 0 0 Power Control (2) 0 0 0 SAP (0) 0 0 11h 0 12h Power Control (3) 0 0 0 0 0 BT2 (0) DC12 (0) 0 BT1 (0) DC11 (0) 0 13h Power Control (4) 0 0 0 20h 0 0 0 VDV3 (0) 0 VDV2 (0) 0 VDV1 (0) 0 0 0 0 0 0 0 0 AD16 (0) 28h GRAM address Set Horizontal Address GRAM address Set Vertical Address Write Data to GRAM Read Data from GRAM NVM read data (1) VDV4 (0) 0 0 0 0 0 0 0 0 29h NVM read data (2) 0 0 0 0 0 0 0 2Ah NVM read data (3) 0 0 0 0 0 0 0 30h γ Control (1) 0 0 0 V1RP4 V1RP3 V1RP2 V1RP1 31h γ Control (2) 0 0 V2RP5 V2RP4 V2RP3 V2RP2 V2RP1 32h γ Control (3) 0 0 V3RP5 V3RP4 V3RP3 V3RP2 33h γ Control (4) 0 0 V4RP5 V4RP4 V4RP3 34h γ Control (5) 0 0 V5RP5 V5RP4 V5RP3 35h γ Control (6) 0 0 0 V6RP4 36h γ Control (7) 0 0 0 37h γ Control (8) 0 0 0 38h γ Control (9) 0 0 39h γ Control (10) 0 3Ah γ Control (11) 3Bh γ Control (12) 3Ch 0 0 0 0 0 0 PTG1 (0) 0 PTG0 (0) 0 DM1 (0) FMP5 (0) 0 0 0 0 0 AM (0) 0 0 0 0 0 RSZ0 (0) 0 DSTB (0) VC2 (0) VRH2 (0) 0 RSZ1 (0) D1 (0) BP1 (0) ISC1 (0) FMI1 (0) RIM1 (0) FMP1 (0) EPL (0) SLP (0) VC1 (0) VRH1 (0) 0 VC0 (0) VRH0 (0) 0 AD2 (0) AD10 (0) AD1 (0) AD9 (0) AD0 (0) AD8 (0) COL (0) BP3 (1) ISC3 (0) FMARKOE (0) 0 0 BP2 (0) ISC2 (0) FMI2 (0) 0 BP0 (0) ISC0 (0) FMI0 (0) RIM0 (0) FMP0 (0) DPL (0) 0 AP1 (0) DC01 (0) 0 0 0 0 VRH3 (0) 0 AD7 (0) AD15 (0) AD6 (0) AD14 (0) AD5 (0) AD13 (0) AD4 (0) AD12 (0) AD3 (0) AD11 (0) 0 0 0 0 0 0 0 0 0 0 0 0 V1RP0 VCMSEL (0) 0 0 0 VCM14 (0) VCM24 (0) V1RN4 UID3 (0) VCM13 (0) VCM23 (0) V1RN3 UID2 UID1 UID0 (0) (0) (0) VCM12 VCM11 VCM10 (0) (0) (0) VCM22 VCM21 VCM20 (0) (0) (0) V1RN2 V1RN1 V1RN0 V2RP0 0 0 V2RN5 V2RN4 V2RN3 V2RN2 V2RN1 V2RN0 V3RP1 V3RP0 0 0 V3RN5 V3RN4 V3RN3 V3RN2 V3RN1 V3RN0 V4RP2 V4RP1 V4RP0 0 0 V4RN5 V4RN4 V4RN3 V4RN2 V4RN1 V4RN0 V5RP2 V5RP1 V5RP0 0 0 V5RN5 V5RN4 V5RN3 V5RN2 V5RN1 V5RN0 V6RP3 V6RP2 V6RP1 V6RP0 0 0 0 V6RN4 V6RN3 V6RN2 V6RN1 V6RN0 V7RP4 V7RP3 V7RP2 V7RP1 V7RP0 0 0 0 V7RN4 V7RN3 V7RN2 V7RN1 V7RN0 V8RP4 V8RP3 V8RP2 V8RP1 V8RP0 0 0 0 V8RN4 V8RN3 V8RN2 V8RN1 V8RN0 0 0 V9RP3 V9RP2 V9RP1 V9RP0 0 0 0 0 V9RN3 V9RN2 V9RN1 V9RN0 0 0 0 V10RP3 V10RP2 V10RP1 V10RP0 0 0 0 0 V10RN3 V10RN2 V10RN1 V10RN0 0 0 0 0 V11RP3 V11RP2 V11RP1 V11RP0 0 0 0 0 V11RN3 V11RN2 V11RN1 V11RN0 0 0 0 0 V12RP3 V12RP2 V12RP1 V12RP0 0 0 0 0 V12RN3 V12RN2 V12RN1 V12RN0 γ Control (13) 0 0 0 0 V13RP3 V13RP2 V13RP1 V13RP0 0 0 0 0 V13RN3 V13RN2 V13RN1 V13RN0 3Dh γ Control (14) 0 0 0 0 V14RP3 V14RP2 V14RP1 V14RP0 0 0 0 0 V14RN3 V14RN2 V14RN1 V14RN0 3Eh γ Control (15) 0 0 0 0 V15RP3 V15RP2 V15RP1 V15RP0 0 0 0 0 V15RN3 V15RN2 V15RN1 V15RN0 3Fh γ Control (16) 0 0 0 0 V16RP3 V16RP2 V16RP1 V16RP0 0 0 0 0 V16RN3 V16RN2 V16RN1 V16RN0 50h Window Horizontal RAM Address Start Window Horizontal RAM Address End Window Vertical RAM Address Start Window Vertical RAM Address End Driver Output Control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GS (0) 0 NL5 (0) NL4 (0) NL3 (0) NL2 (0) NL1 (0) VSA8 (0) VEA8 (1) NL0 (0) HSA7 (0) HEA7 (1) VSA7 (0) VEA7 (0) 0 HSA6 (0) HEA6 (1) VSA6 (0) VEA6 (0) 0 HSA5 (0) HEA5 (1) VSA5 (0) VEA5 (1) SCN5 (0) HSA4 (0) HEA4 (0) VSA4 (0) VEA4 (1) SCN4 (0) HSA3 (0) HEA3 (1) VSA3 (0) VEA3 (1) SCN3 (0) 21h 22h 51h 52h 53h 60h © ORISE Technology Co., Ltd. Proprietary & Confidential 14 BT0 (0) DC10 (0) VCMR0 (0) VDV0 (0) 0 0 FMP6 (0) 0 CB0 0 0 DC02 (0) 0 0Fh 0 FMP7 (0) 0 CB1 0 0 DM0 (0) FMP4 (0) VSPL (0) AP0 (0) DC00 (0) 0 0Dh RM (0) FMP8 (0) 0 0 I/D0 (1) RCH0 (0) DTE (0) 0 CB2 0 0 APE (0) 0 VREG1R (0) 0 0 FMP3 (0) HSPL (0) 0 0 FMP2 (0) 0 HSA2 (0) HEA2 (1) VSA2 (0) VEA2 (1) SCN2 (0) HSA1 (0) HEA1 (1) VSA1 (0) VEA1 (1) SCN1 (0) HSA0 (0) HEA0 (1) VSA0 (0) VEA0 (1) SCN0 (0) OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 61h Driver Output Control 0 0 0 0 0 0 0 0 0 0 0 0 0 6Ah Vertical Scroll Control 0 0 0 0 0 0 0 80h Display Position Partial Display 1 RAM Address Start Partial Display 1 RAM Address End Partial Display 1 Display Position Partial Display 2 RAM Address Start Partial Display 2 RAM Address End Partial Display 2 Panel interface Control 1 Panel Interface Control 2 Panel Interface Control 3 Panel Interface Control 4 Panel Interface Control 5 Panel Interface Control 6 Calibration control 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VL7 (0) PTDP07 (0) PTSA07 (0) PTEA07 (0) PTDP17 (0) PTSA17 (0) PTEA17 (0) 0 VL6 (0) PTDP06 (0) PTSA06 (0) PTEA06 (0) PTDP16 (0) PTSA16 (0) PTEA16 (0) 0 VL5 (0) PTDP05 (0) PTSA05 (0) PTEA05 (0) PTDP15 (0) PTSA15 (0) PTEA15 (0) 0 0 0 0 0 0 VL8 (0) PTDP08 (0) PTSA08 (0) PTEA08 (0) PTDP18 (0) PTSA18 (0) PTEA18 (0) DIVI0 (0) NOWI0 (0) VEQW10 (0) DIVE0 (0) NOWE0 (0) 0 0 0 0 VL4 (0) PTDP04 (0) PTSA04 (0) PTEA04 (0) PTDP14 (0) PTSA14 (0) PTEA14 (0) RTNI4 (1) 0 VL3 (0) PTDP03 (0) PTSA03 (0) PTEA03 (0) PTDP13 (0) PTSA13 (0) PTEA13 (0) RTNI3 (0) 0 0 81h 82h 83h 84h 85h 90h 92h 93h 95h 97h 98h A4h 0 0 0 0 0 NOWI2 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOWE3 (0) 0 NOWE2 (0) 0 DIVI1 (0) NOWI1 (0) VEQW11 (0) DIVE1 (0) NOWE1 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTNE5 (0) 0 RTNE4 (1) 0 RTNE3 (1) 0 0 0 0 0 0 0 0 0 0 0 NDL (0) VL2 (0) PTDP02 (0) PTSA02 (0) PTEA02 (0) PTDP12 (0) PTSA12 (0) PTEA12 (0) RTNI2 (0) 0 VLE (0) VL1 (0) PTDP01 (0) PTSA01 (0) PTEA01 (0) PTDP11 (0) PTSA11 (0) PTEA11 (0) RTNI1 (0) 0 REV (0) VL0 (0) PTDP00 (0) PTSA00 (0) PTEA00 (0) PTDP10 (0) PTSA10 (0) PTEA10 (0) RTNI0 (0) 0 MCPI2 (0) RTNE2 (1) 0 MCPI1 (0) RTNE1 (1) 0 MCPI0 (0) RTNE0 (0) 0 MCPE2 MCPE1 MCPE0 (0) (0) (0) 0 0 CALB (0) The following are detailed explanations of instructions with illustrations of instruction bits (CB15-0) assigned to each interface. 6.2.1. Index Register (IR) R/W RS W 0 CB15 CCB14 CB13 CB12 CB11 CB10 ∗ ∗ ∗ ∗ ∗ CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 ∗ ∗ ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 ∗ The index register specifies the index (R00h ~ RFFh) of a control register. The index range is from “000_0000” to “111_1111” in binary format. 6.2.2. ID Read Register (SR) R/W RS R 0 CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 1 0 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 1 0 0 0 1 The IC code of SPFD5408B can be accessed by read operation. ‘5408H can be read out when read ID operation is executed. 6.2.3. Driver Output Control Register (R01h) R/W RS W SS: CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 SS 0 0 0 0 0 0 0 0 SM Shift direction of the source driver output selection. can cooperate with GS for different LCD panel gate line When SS = “0”, source driver shift from S1 to S720. When layout. The combination of GS and SM bit are summarized at SS = “1”, source driver shift from S720 to S1. Moreover, SS Table 6-3. can cooperate with BGR for different color filter configuration of LCD panel. The combination of SS and Table 6-3 BGR bit are summarized at Table 6-2. Table 6-2 SM GS Shift Direction (begin,…..,end) 0 0 G1, G2, G3, G4…………G317, G318, G319, G320 SS=0;BGR=0; S1 S2 S3 S718 S719 S720 0 1 G320, G319, G318, G317…………G4, G3, G2, G1 SS=0;BGR=1; S1 S2 S3 S718 S719 S720 1 0 G1, G3, G5, …G317, G319, …G2, G4,... G318, G320 SS=1,BGR=0; S1 S2 S3 S718 S719 S720 1 1 G320, G318, G316,..G4, G2, ..G319, G317,...G3, G1 SS=1,BGR=1; S1 S2 S3 S718 S719 S720 SM: Set the scan mode of the gate driver output. Moreover, SM © ORISE Technology Co., Ltd. Proprietary & Confidential 15 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.4. LCD Driving Waveform Control (R02h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 1 B/C CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 0 0 0 0 0 0 0 0 CB6 CB5 CB4 CB3 CB2 CB1 CB0 AM 0 0 0 B/C: This bit .is to set the Vcom toggle at frame rate format of N-line inversion format. B/C=0: Frame inversion. B/C=1: 1-line inversion. 6.2.5. Entry Mode (R03h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 TRIR DFM 0 BGR 0 CB9 CB8 0 0 0 CB7 ORG 0 I/D1 I/D0 EG the window start address, as normal operation case. Table 6-4 ORG=1: RAM address setting (R20h, R21h) should set to Operation ORG AM I/D1 I/D0 (00000h) no matter where the window start address is. In Function mode Mode 1 0 0 0 0 Replace horizontal data Mode2 0 1 0 1 Replace vertical data Mode3 1 0 1 0 Conditionally replace horizontal data Mode4 1 1 1 1 Conditionally replace vertical data this case, the window start position is treated as (00000h), regardless the physical location in GRAM. BGR: To set the order of RGB dot location in GRAM. BGR=0: same assignment of RGB allocation of DB17-0 BGR=1: inverse assignment of RGB allocation of DB17-0 AM: To set the update direction when writing data to GRAM. If AM=1, data will write in vertical direction. If AM=0, data will DFM: In combination with TRIREG setting to set the different data transfer mode. write in horizontal direction. Moreover, if a fixed window GRAM accessing is desired, the writing direction can be set TRIREG: to set 1–3 time transfer mode for system interface. TRI by I/D1-0 and AM bits. bit should cooperate with DFM to meet the specific transfer mode. I/D1-0: To specify address counter increment /decrement automatically function while GRAM is accessing. I/D[0] For 8-bit data bus interface mode: indicates the increment or decrement in horizontal TRIREG=0: 2 time transfer mode for 16-bit GRAM data. direction. I/D[1] indicates the increment or decrement in TRIREG=1: 3 time transfer mode for 18-bit GRAM data vertical direction. For 16-bit data bus interface mode: I/D[0]=0: decrement in horizontal direction automatically TRIREG=0: 1 time transfer mode for 16-bit GRAM data. TRIREG=1: 2 time transfer mode for 18-bit GRAM data I/D[0]=1: increment in horizontal direction automatically Note: Set TRIREG=0, when using neither 8-bit nor 16-bit. I/D[1]=0: decrement in vertical direction automatically I/D[1]=1: increment in vertical direction automatically ID[1-0] setting can cooperate with Am bit to set the data updating direction. ORG: SPFD5408B provides the option of start address definition when window function is selected. ORG=0: RAM address setting (R20h, R21h) should set to © ORISE Technology Co., Ltd. Proprietary & Confidential 16 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.6. Scaling Control register (R04h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 CB9 CB8 CB7 CB6 0 0 RCV1 RCV0 CB5 CB4 RCH1 RCH0 CB3 CB2 0 0 CB1 CB0 RSZ1 RSZ0 RSZ [1:0]: SPFD5408B provides scaling factor to give the display more flexibility to show different picture size. For detail, refer to “Scaling function”. RSZ1 RSZ0 Scaling Factor 0 0 No Scaling 0 1 1/2 times 1 0 Setting Disable 1 1 1/4 times RCH [1:0]: To set the surplus pixel number in horizontal direction when scaling mode is selected. When scaling mode is not selected, make sure RCH[1:0]= “00” RCH1 RCH0 Surplus pixel number in Horizontal direction 0 0 0 Pixel 0 1 1 Pixel 1 0 2 Pixels 1 1 3 Pixels RCH [1:0]: To set the surplus pixel number in Vertical direction when scaling mode is selected. When scaling mode is not selected, make sure RCV[1:0]= “00” RCV1 RCV0 Surplus pixel number in Vertical direction 0 0 0 Pixel 0 1 1 Pixel 1 0 2 Pixels 1 1 3 Pixels 6.2.7. Display Control (R07h) R/W RS W 1 D1-0: CB15 CB14 CB13 CB12 CB11 CB10 0 0 PTDE1 PTDE0 0 CB9 0 0 CB8 CB6 CB5 0 0 0 BASEE CB4 CB3 DTE CB2 CB1 CB0 0 D1 0 COL To set the internal operation, source driver output and COL: 8-color mode selection. When CL=1 SPFD5408B enter to VCOM output function. When D1-0=00; SPFD5408B is 8-color mode. When CL=0, SPFD5408B is in normal operation mode. set to standby mode. The combination of D1-0 and AM bit DTE: Specify the high/low level of gate driver output signal. The is summarized at Table 6-5. meaning of DTE bit is summarized at Table 6-6. Table 6-5 Source, VCOM Internal output Operation * GND Terminated 0 Non-lit display Normal Operation D1 BASEE 0 1 CB7 1 Normal display © ORISE Technology Co., Ltd. Proprietary & Confidential Normal Operation Table 6-6 FLM APE DTE Gate Output OFF 0 * VGL(=GND) ON 1 0 VGL 1 VGH/VGL ON 17 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B PTDE [0]: “0” Partial image 1 display “Off”. BASEE: To enable Base image display “1” Partial image 1 display “On”. BASEE 0 1 PTDE [1]: “0” Partial image 2 display “Off”. (1) Non-lit display (2) Partial image display “1” Partial image 2 display “On”. Base image is display on the LCD PTDE1-0: To set the partial-display enables function. 6.2.8. Display Control 2 (R08h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 FP3 FP2 CB9 FP1 CB8 FP0 CB7 CB6 CB5 CB4 0 0 0 0 CB3 CB2 BP3 CB1 BP2 CB0 BP1 BP0 FP3-0: Set the amount of blank period of front porch In external display interface mode, a back porch (BP) period starts BP3-0: Set the amount of blank period of back porch on the falling edge of the VSYNC signal, followed by a display operation period. After driving the number of lines set with NL bits, Table 6-7 summarized the function of FP3-0/BP3-0 setting. a front porch period starts. After the front porch period, a blank When setting this register, make sure that: period continues until the next input of VSYNC signal. Be aware BP + FP ≤ 16 lines that different interface mode, has different BP/ FP setting. Table FP ≥ 2 lines 6-8 summarized the setting for each interface mode. BP ≥ 2 lines Table 6-7 FP3 FP2 FP1 FP0 Number of lines for the Front Porch BP3 BP2 BP1 BP0 Number of lines for the Back Porch 0 0 0 0 Setting disabled 0 0 0 1 Setting disabled 0 0 1 0 2 lines 0 0 1 1 3 lines 0 1 0 0 4 lines 0 1 0 1 5 lines 0 1 1 0 6 lines 0 1 1 1 7 lines 1 0 0 0 8 lines 1 0 0 1 9 lines 1 0 1 0 10 lines 1 0 1 1 11 lines 1 1 0 0 12 lines 1 1 0 1 13 lines 1 1 1 0 14 lines 1 1 1 1 Setting disabled Table 6-8 Operation of Internal clock BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines RGB interface BP ≥ 2 lines FP ≥ 2 lines FP +BP ≤ 16 lines VSYNC interface BP ≥ 2 lines FP ≥ 2 lines FP +BP = 16 lines © ORISE Technology Co., Ltd. Proprietary & Confidential 18 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Figure 6-7 Front porch and back porch function diagram 6.2.9. Display Control 3 (R09h) R/W RS W ISC3-0: CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 PTS2 PTS1 PTS0 CB7 CB6 0 0 CB5 CB4 CB3 CB2 PTG1 PTG0 ISC3 CB1 ISC2 ISC1 CB0 ISC0 To set the gate driver scan cycle in non-display area. Table 6-9 summarized the function of ISC3-0 setting Table 6-9 ISC3 ISC2 ISC1 ISC0 Scan cycle fFLM=60Hz 0 0 0 1 Setting disable 0 0 1 0 3frames 50 ms 0 0 1 1 5 frames 84 ms 0 1 0 0 7 frames 117 ms 0 1 0 1 9 frames 150 ms 0 1 1 0 11 frames 184 ms 0 1 1 1 13 frames 217 ms 1 0 0 0 15 frames 251 ms 1 0 0 1 19 frames 317 ms 1 0 1 0 21 frames 351 ms 1 0 1 1 23 frames 384 ms 1 1 0 0 25 frames 418 ms 1 1 0 1 27 frames 451 ms 1 1 1 0 29 frames 484 ms 1 1 1 1 31 frames 518 ms © ORISE Technology Co., Ltd. Proprietary & Confidential 19 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B To set the gate driver scan mode in non-display area. PTG1-0: Table 6-10 summarized the function of PTG1-0 setting Table 6-10 PTG1 PTG0 0 0 0 1 1 0 1 1 Gate outputs in non- Source outputs in non- display area display area Normal scan Based on the PTS2-0 bits setting VCOM output VCOMH/VCOML Setting Disable Interval scan Based on the PTS2-0 bits setting VCOMH/VCOML Setting Disable PTS2-0: To set the source driver output level in non-display area of partial display mode. Table 6-11 summarized the function of PTS2-0 setting. Table 6-11 PTS2 0 PTS1 0 Source output in non-display area PTS0 + polarity - polarity 0 V63 V0 Operation amplifier in non-display area V0-V63 0 0 1 Invalid setting Invalid setting - 0 1 0 GND GND V0-V63 0 1 1 High impedance High impedance V0-V63 1 0 0 V63 V0 V0, V63 1 0 1 Invalid setting Invalid setting - 1 1 0 GND GND V0, V63 1 1 1 High impedance High impedance V0, V63 6.2.10. Frame Cycle Control (R0Ah) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 CB4 0 0 0 0 0 0 0 CB3 FMAR KOE CB2 CB1 FMI2 FMI1 CB0 FMI0 FMI [2:0]: SPFD5408 provide FMARK signal to prevent tearing effect. FMI [2:0] can set FMARK output interval. FMI2 FMI1 FMI0 Output interval 0 0 0 1 frame 0 0 1 2 frames 0 1 1 4 frames 1 0 1 6 frames Other Setting Setting Disable FMARKOE: Initialized the output signal FMARK from FMARK pin. FMARK=”0”: Output FMARK disable FMARK=”1”. Output FMARK enables. © ORISE Technology Co., Ltd. Proprietary & Confidential 20 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.11. External Display Interface Control 1 (R0Ch) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 CB8 0 RM CB7 CB6 0 0 CB5 DM1 CB4 CB3 CB2 0 0 DM0 CB1 CB0 RIM1 RIM0 RIM1-0: To set the different transfer modes of RGB interface. Table 6-12 summarized the function of RIM1-0 setting. Table 6-12 RIM1 RIM0 RGB Interface Mode Colors 0 0 18-bit RGB interface (one transfer/pixel) 262K DB 17-0 0 1 16-bit RGB interface (one transfer/pixel) 65K DB 17-13; DB 11-1 1 0 6-bit RGB interface (three transfers/pixel) 262K DB17-12 1 1 Setting disabled - - DM1-0: To specify the display interface mode. DM1-0 Setting can DM1 DM0 Data Bus Display Interface switch the display interface among system interface, RGB 0 0 Internal clock operation interface and VSYNC interface. 0 1 RGB interface 1 0 VSYNC interface 1 1 Setting disabled Table 6-13 summarized the function of DM1-0 setting. Table 6-13 RM: Select the interface to access the SPFD5408B’s internal GRAM. Set RM to “1” when writing display data via the RGB interface. The SPFD5408B allows for setting the RM bit not constrained by the mode used for the display operation. This means it is possible to rewrite display data via a system interface by setting RM = “0” even while display operations are performed via the RGB interface. Table 6-14Table 6-14 summarized the function of RM bit setting. Table 6-14 RM Interface for RAM Access 0 System interface/VSYNC interface 1 RGB interface © ORISE Technology Co., Ltd. Proprietary & Confidential 21 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Table 6-15 Display State Still pictures Moving pictures Operation Mode RAM Access (RM) Display Operation Mode (DM1-0) Internal clock System interface Internal clock operation operation (RM = 0) (DM1-0 = 00) RGB interface RGB interface (RM = 1) (DM1-0 = 01) System interface RGB interface (RM = 0) (DM1-0 = 01) System interface VSYNC interface (RM = 0) (DM1-0 = 10) RGB interface (1) Rewrite still picture area while RGB interface (2) displaying moving pictures. Moving pictures VSYNC interface Note1: Instructions are set only via the system interface. Note2: The RGB-I/F and the VSYNC-I/F are not used simultaneously. Note3: Do not make changes to the RGB-I/F mode setting (RIM-0) while the RGB I/F is in operation. Note4: See the “External Display Interface” section for the flowcharts to follow when switching from one mode to another. Note5: Use the high-speed write mode (HWM/LHWM = “1”) when writing data in RGB or VSYNC interface mode. 6.2.12. Frame Maker Position (R0Dh) R/W RS W 1 CB15 CB14 CB13 0 0 CB12 CB11 CB10 CB9 CB8 CB7 0 0 0 0 FMP8 FMP7 FMP6 FMP5 0 CB6 CB5 CB4 CB3 CB2 CB1 CB0 FMP4 FMP3 FMP2 FMP1 FMP0 FMP 8-0: indicates the output position of frame cycle signal (frame maker) relation with back porch. When FMP[8:0] =9’h000, FMARK is outputted at the start of back porch. When FMP[8:0] =9’h001, FMARK is outputted one line after the start of back porch. FMP [8:0] RAM data write cycle 9’h000 immediate 9’h001 1 line 9’h002 2 line ~ 9’h175 373 lines 9’h176 374 lines 9’h177 375 lines 6.2.13. External Display Interface Control 2 (R0Fh) R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 W 1 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 EPL DPL EPL: The polarity of ENABLE signal selection in RGB interface VSPL: The polarity of VSYNC signal selection in RGB interface mode. mode. EPL = “0”: ENABLE: Low active VSPL = ”0”: Low active. EPL = ”1”: ENABLE: High active VSPL = ”1”: High active. DPL: Select the data latch edge of the DOTCLK signal in RGB HSPL: The polarity of HSYNC signal selection in RGB interface interface mode. mode. DPL = ”0”: rising edge of the DOTCLK. HSPL = ”0”: Low active. DPL =”1”: falling edge of the DOTCLK. HSPL = ”1”: High active. © ORISE Technology Co., Ltd. Proprietary & Confidential 22 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.14. Power Control 1 (R10h) R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 W 1 0 0 0 SAP 0 BT2 BT1 BT0 APE 0 AP1 AP0 0 DSTB SLP 0 SLP: Sleep mode selection. When SLP =1, SPFD5408B set to AP1-0: Operational amplifier DC bias current adjustment. Set AP1-0 sleep mode. In sleep mode, all internal operations are = “00” to stop operational amplifier and DC/DC charge terminated except internal RC oscillation. Be sure that a pump circuits to reduce current consumption during no display off sequence should be executed before set SLP to display period. Table 6-16 summarized the function of “1”. In sleep mode, no instruction can be accepted except AP1-0 setting R11h, R13h, bit 3-0 of R12h and R10h (except SAP2-0). Set STB=0 can exit sleep mode. Moreover, when exit from sleep Table 6-16 mode, data in GRAM and in instruction registers are keep the AP0 AP1 same with these before set to SLP mode. Constant current in Constant current in power supply circuit Gamma circuit DSTB: Deep Standby mode selection. When DSTB =1, SPFD5408B set to deep standby mode. In this mode, all internal operations are terminated including internal RC oscillation. Be sure that a display off sequence should be executed before set DSTB to “1”. Set DSTB=0 can exit standby mode. 0 0 Halt Halt 0 1 0.5 0.62 1 0 0.75 0.71 1 1 1 1 Be sure that start oscillation following by 10ms delay should APE: Enable bit for both liquid crystal power supply and gamma be executed before set DSTB to “0”. Moreover, when exit from deep standby mode, data in GRAM and register might voltage generation circuit. be lost, reset and re-sending command and data into GRAM APE=”0”, Halt liquid crystal power supply and gamma voltage generation circuit is necessary. APE=”1”, Enable liquid crystal power supply and gamma voltage generation circuit. BT3-0: Set the voltage level of DDVDH, VGH, VGL and VCL. Table 6-17 summarized the function of BT3-0 setting BT2 BT1 BT0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 DDVDH VGH VGL VCI1 x 2 DDVDH x 3 -(VCI1+DDVDHx 2) [x2] [VCI1 x 6] [VCI1x -5] VCI1 x 2 DDVDH x 3 -(DDVDHx 2) [x2] [VCI1 x 6] [VCI1x -4] VCI1 x 2 DDVDH x 3 -(VCI1+DDVDH) [x2] [VCI1 x 6] [VCI1x -3] VCI1 x 2 DDVDH x 2 + VCI1 -(VCI1+DDVDHx 2) [x2] [VCI1 x 5] [VCI1x -5] VCI1 x 2 DDVDH x 2 + VCI1 -(DDVDHx 2) [x2] [VCI1 x 5] [VCI1x -4] VCI1 x 2 DDVDH x 2 + VCI1 -(VCI1+DDVDH) [x2] [VCI1 x 5] [VCI1x -3] VCI1 x 2 DDVDH x 2 -(DDVDHx 2) [x2] [VCI1 x 4] [VCI1x -4] VCI1 x 2 DDVDH x 2 -(VCI1+DDVDH) [x2] [VCI1 x 4] [VCI1x -3] VCL -VCI1 Capacitor connection pins C23 can be eliminated -VCI1 -VCI1 -VCI1 -VCI1 -VCI1 -VCI1 C23 can be eliminated -VCI1 C23 can be eliminated SAP: Enable bit for gamma voltage generation circuit. SAP=”0”, Halt gamma voltage generation circuit. SAP=”1”, Enable gamma voltage generation circuit © ORISE Technology Co., Ltd. Proprietary & Confidential 23 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.15. Power Control 2 (R11h) R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 W 1 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 VC1 VC0 VC2-0: Set the voltage of VCIOUT. VCIOUT is generated by DC12-10: Set DC/DC charge pump circuit 2 operating frequency. VCILVL. Table 6-18 summarized the function of VC2-0 Table 6-20 summarized the function of DC02-00 setting setting Note: Be aware that DC/DC charge pump 1 frequency ≥ DC/DC charge pump 2 frequency Table 6-18 VC2 VC1 VC0 VCIOUT 0 0 0 0.94 x VCILVL 0 0 1 0.89 x VCILVL 0 1 0 Table 6-20 Step-up circuit 2 DC12 DC11 DC10 Setting Disable 0 0 0 Oscillation clock / 16 step-up frequency (fDCDC2) 0 1 1 Setting Disable 0 0 1 Oscillation clock / 32 1 0 0 0.76 x VCILVL 0 1 0 Oscillation clock / 64 1 0 1 Setting Disable 0 1 1 Oscillation clock / 128 0 0 Oscillation clock / 256 1 1 0 Setting Disable 1 1 1 1 1.00 x VCILVL 1 0 1 Setting disabled 1 1 0 Halt Step-up Circuit 2 1 1 1 Setting disabled DC02-00: Set DC/DC charge pump circuit 1 operating frequency. Table 6-19 summarized the function of DC02-00 setting Note: Be sure fDCDC1≥fDCDC2 when setting DC02-00, DC12-10. Table 6-19 DC/DC charge pump circuit 1 DC02 DC01 DC00 0 0 0 0 0 1 Oscillation clock / 2 0 1 0 Oscillation clock / 4 0 1 1 Oscillation clock / 8 frequency (fDCDC1) Oscillation clock 1 0 0 Oscillation clock / 16 1 0 1 Invalid Setting 1 1 0 Halt Step-up Circuit 1 1 1 1 Invalid Setting © ORISE Technology Co., Ltd. Proprietary & Confidential 24 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.16. Power Control 3 (R12h) R/W RS W CB15 CB14 CB13 1 0 0 0 CB12 CB11 CB10 0 0 CB9 0 CB8 0 CB7 VCM VRE R[0] G1R CB6 CB5 CB4 0 0 0 CB3 CB2 CB1 CB0 VRH3 VRH2 VRH1 VRH0 VRH3-0: Set the voltage level of VCILVL. VCILVL is generated by VREG1OUT. Table 6-21 summarized the function of VRH3-0 setting Table 6-21 VRH3 VRH2 VRH1 VRH0 VRH3 VREG1OUT voltage VCILVL VCIR VRH2 VRH1 VRH0 VREG1OUT voltage VCILVL VCIR 0 0 0 0 Halt Halt 1 0 0 0 VCILVLx1.6 2.5Vx1.6 0 0 0 1 Halt Halt 1 0 0 1 VCILVLx1.65 2.5Vx1.65 0 0 1 0 Halt Halt 1 0 1 0 VCILVLx1.7 2.5Vx1.7 0 0 1 1 Halt Halt 1 0 1 1 VCILVLx1.75 2.5Vx1.75 0 1 0 0 1 1 0 0 VCILVLx1.8 2.5Vx1.8 1 1 0 1 VCILVLx1.85 2.5Vx1.85 1 1 1 0 VCILVLx1.9 2.5Vx1.9 1 1 1 1 0 1 0 1 0 1 1 0 0 1 1 1 Setting Setting disable disable Setting Setting disable disable Setting Setting disable disable Setting Setting disable disable Setting Setting disable disable VREG1R: Select reference voltage for VREG1OUT VREG1R = “0” (default): VCILVL (External) as reference voltage for VREG1OUT. VREG1R = ”1”: VCIR (internal) as reference voltage for VREG1OUT. VCMR[0]: Select VCOMH external resistance or internal setting for VCOMH voltage level. VCMR[0] = “0” use VCOMR (External) setting as VCOMH voltage. VCMR[0] = ”1”: use register (internal) setting as VCOMH voltage. © ORISE Technology Co., Ltd. Proprietary & Confidential 25 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.17. Power Control 4 (R13h) R/W RS W 1 CB15 CB14 0 0 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0 VDV4-0: Set the Vcom amplitude. Vcom amplitude is generated by VREG1OUT. Table 6-22 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 VREG1OUT x 0.70 0 0 0 0 1 VREG1OUT x 0.72 0 0 0 1 0 VREG1OUT x 0.74 0 0 0 1 1 VREG1OUT x 0.76 0 0 1 0 0 VREG1OUT x 0.78 0 0 1 0 1 VREG1OUT x 0.80 0 0 1 1 0 VREG1OUT x 0.82 0 0 1 1 1 VREG1OUT x 0.84 0 1 0 0 0 VREG1OUT x 0.86 0 1 0 0 1 VREG1OUT x 0.88 0 1 0 1 0 VREG1OUT x 0.90 0 1 0 1 1 VREG1OUT x 0.92 0 1 1 0 0 VREG1OUT x 0.94 0 1 1 0 1 VREG1OUT x 0.96 0 1 1 1 0 VREG1OUT x 0.98 0 1 1 1 1 VREG1OUT x 1.00 1 0 0 0 0 VREG1OUT x 1.02 1 0 0 0 1 VREG1OUT x 1.04 1 0 0 1 0 VREG1OUT x 1.06 1 0 0 1 1 VREG1OUT x 1.08 1 0 1 0 0 VREG1OUT x 1.10 1 0 1 0 1 VREG1OUT x 1.12 1 0 1 1 0 VREG1OUT x 1.14 1 0 1 1 1 VREG1OUT x 1.16 1 1 0 0 0 VREG1OUT x 1.18 1 1 0 0 1 VREG1OUT x 1.20 1 1 0 1 0 VREG1OUT x 1.22 1 1 0 1 1 VREG1OUT x 1.24 1 1 1 0 0 Setting disable 1 1 1 0 1 Setting disable 1 1 1 1 0 Setting disable 1 1 1 1 1 Setting disable © ORISE Technology Co., Ltd. Proprietary & Confidential Vcom amplitude 26 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.18. GRAM Address Set (Horizontal Address) (R20h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 0 0 CB9 CB8 0 CB7 CB6 AD7 AD6 CB5 AD5 CB4 AD4 CB3 CB2 AD3 CB1 AD2 AD1 CB0 AD0 6.2.19. GRAM Address Set (Vertical Address) (R21h) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD16–0: To set the initial address counter for GRAM address. AD9 CB0 AD8 Table 6-23 Based on AM and I/D[1:0] setting, the address counter is automatically increment or decrement while data are written to the internal GRAM There is no need to updated AD16-0 every data transfer if AD16-0 was set in the beginning of one frame graphic data. Be aware that address counter is not automatically updated if reading data from the internal AD16–AD0 GRAM Setting “00000”H – “000EF”H Bitmap data for G1 “00100”H – “001EF”H Bitmap data for G2 “00200”H – “002EF”H Bitmap data for G3 “00300”H – “003EF”H Bitmap data for G4 GRAM instruction is executed. Moreover, the address : : counter cannot be accessed when the SPFD5408B is in “13600”H – “13CEF”H Bitmap data for G317 standby mode. “13700”H – “13DEF”H Bitmap data for G318 “13800”H – “13EEF”H Bitmap data for G319 “13900”H – “13FEF”H Bitmap data for G320 Table 6-23Table 6-23 summarized the function of AD15-0 setting Note1: The address AD16-0 should be set in the address counter every frame on the falling edge of VSYNC if RGB interface mode is selected. Note2: The address AD16-0 should be set when executing an instruction if system or VSYNC interface mode is selected. © ORISE Technology Co., Ltd. Proprietary & Confidential 27 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.20. Write Data to GRAM (R22h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 RAM write data (WD17-0) The DB17-0 pin assignment is different in different interface modes. WD17-0: SPFD5408B supports 18 bits data format. However, if Data in GRAM Source Driver Grayscale Output only 16-bit (565format) is input to GRAM, SPFD5408B RGB Negative Positive will expand the 16 bit data into 18-bit format. Same case 011101 V29 V34 011110 V30 V33 011111 V31 V32 100000 V32 V31 100001 V33 V30 100010 V34 V29 100011 V35 V28 100100 V36 V27 when RGB interface is selected. Based on the graphic data in GRAM, the grayscale voltage of source driver is selected. Table 6-24 summarized the source driver grayscale voltage output versus graphic data in GRAM. Figure 6-8 ~ Figure 6-18 illustrates the pin assignment among data bus (DB17-0), R22 (WD17-0) and GRAM. Table 6-24 Data in GRAM Source Driver Grayscale Output 100101 V37 V26 RGB Negative Positive 100110 V38 V25 000000 V0 V63 100111 V39 V24 000001 V1 V62 101000 V40 V23 000010 V2 V61 101001 V41 V22 000011 V3 V60 101010 V42 V21 000100 V4 V59 101011 V43 V20 000101 V5 V58 101100 V44 V19 000110 V6 V57 101101 V45 V18 000111 V7 V56 101110 V46 V17 001000 V8 V55 101111 V47 V16 001001 V9 V54 110000 V48 V15 001010 V10 V53 110001 V49 V14 001011 V11 V52 110010 V50 V13 001100 V12 V51 110011 V51 V12 001101 V13 V50 110100 V52 V11 001110 V14 V49 110101 V53 V10 001111 V15 V48 110110 V54 V9 010000 V16 V47 110111 V55 V8 010001 V17 V46 111000 V56 V7 010010 V18 V45 111001 V57 V6 010011 V19 V44 111010 V58 V5 010100 V20 V43 111011 V59 V4 010101 V21 V42 111100 V60 V3 V61 V2 010110 V22 V41 111101 010111 V23 V40 111110 V62 V1 011000 V24 V39 111111 V63 V0 011001 V25 V38 011010 V26 V37 011011 V27 V36 011100 V28 V35 © ORISE Technology Co., Ltd. Proprietary & Confidential 28 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Figure 6-14 8-bit interface 262 colors) TRIREG = 1, DFM=0. Figure 6-8 18-bit interface (262,144 colors) Figure 6-15 8-bit interface (262K colors) TRIREG = 1, DFM=1 Figure 6-9 16-bit interface (65,536 colors) TRIREG= 0 Figure 6-16 18-bit RGB interface (262,144 colors) Figure 6-10 16-bit interface (262,144 colors) TRIREG = 1, DFM = 0 Figure 6-17 16-bit RGB interface (65,563 colors) Figure 6-11 16-bit interface (262,144 colors) TRIREG = 1, DFM = 1 Figure 6-18 6-bit RGB interface (262,144 colors) Figure 6-12 9-bit interface (262,144 colors) Figure 6-13 8-bit interface (65,536 colors) TRIREG = 0 © ORISE Technology Co., Ltd. Proprietary & Confidential 29 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B SPFD5408B supports external (RGB) interface. In RGB interface mode, all graphic data are stored in GRAM. To meet the diverse requirement of small size LCD panel, SPFD5408B also supports in a fix window using RGB interface and outside the window still use system interface. In RGB interface mode, data writing to the internal RAM is synchronized with DOTCLK during ENABLE = “Low”. Set ENABLE Figure 6-19 “High” to terminate writing data to RAM. Wait for a write/read bus cycle time. If accessing internal RAM using the RGB interface is desired after accessing the RAM via the system interface. Figure 6-19 illustrates the timing diagram while RGB and system interface are both use in the same time. © ORISE Technology Co., Ltd. Proprietary & Confidential 30 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.21. Read Data Read from GRAM (R22h) R/W R RS CB15 CB14 CB13 CB12 CB11 CB10 1 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 RAM Read data (RD17-0) The DB17-0 pin assignment is different in different interface modes. R22 also served as a register, which store the data read out from GRAM. When data are read out from the GRAM is desired, first sets the RAM address and executes first word read, and issues second word read. When first word read instruction is issued, Invalid data are sent to the data bus DB17-0. Valid data are sent to the data bus as second word data is executed. Figure 6-21 16-bit interface The LSBs of R and B dots cannot read out, when the 8 or 16-bit interface is selected, Note: This register is not available with the RGB interface. Figure 6-20 ~ Figure 6-23 illustrates the pin assignment among data bus (DB17-0), R22 (RD17-0) and GRAM in read data instruction. Figure 6-22 9-bit interface Figure 6-20 18-bit interface Figure 6-23 8-bit interface / SPI 6.2.22. NVM read data 1 (R28h) R/W W RS 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 CB4 0 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 CB4 0 0 0 0 0 CB3 CB2 UID3 CB1 UID2 UID1 CB0 UID0 6.2.23. NVM read data 2 (R29h) R/W W RS 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 © ORISE Technology Co., Ltd. Proprietary & Confidential 0 0 0 0 31 CB3 CB2 CB1 CB0 VCM VCM VCM VCM VCM 14 13 12 11 10 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.24. NVM read data 3 (R2Ah) R/W W RS CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 CB9 0 CB8 0 CB7 VCM SEL CB6 0 CB5 0 CB4 CB3 CB2 CB1 CB0 VCM VCM VCM VCM VCM 24 23 22 21 20 UID[3:0]: SPFD5408B provides a 4-bit identification code UID[3:0] for user to use. UID[3:0] can be write / read from NVM. UID can be read out via R28h when CALB(RA4h, CB0) is set to 1. VCM1 [4:0]:These pins are to set the factor for generating VCM2 [4:0]: These pins are to set the factor for generating VCOMH when VCMSEL=”0”. Table 6-25 summarized the VCOMH when VCMSEL=”1”. Table 6-26 summarized the factor of VERG1OUT factor of VERG1OUT Table 6-25 VCM1[4:0] 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 5’h07 5’h08 5’h09 5’h0A 5’h0B 5’h0C 5’h0D 5’h0E 5’h0F 5’h10 5’h11 5’h12 5’h13 5’h14 5’h15 5’h16 5’h17 5’h18 5’h19 5’h1A 5’h1B 5’h1C 5’h1D 5’h1E 5’h1F Table 6-26 VCM2[4:0] 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 5’h07 5’h08 5’h09 5’h0A 5’h0B 5’h0C 5’h0D 5’h0E 5’h0F 5’h10 5’h11 5’h12 5’h13 5’h14 5’h15 5’h16 5’h17 5’h18 5’h19 5’h1A 5’h1B 5’h1C 5’h1D 5’h1E 5’h1F VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00 VCOMH voltage VREG1OUT x 0.69 VREG1OUT x 0.70 VREG1OUT x 0.71 VREG1OUT x 0.72 VREG1OUT x 0.73 VREG1OUT x 0.74 VREG1OUT x 0.75 VREG1OUT x 0.76 VREG1OUT x 0.77 VREG1OUT x 0.78 VREG1OUT x 0.79 VREG1OUT x 0.80 VREG1OUT x 0.81 VREG1OUT x 0.82 VREG1OUT x 0.83 VREG1OUT x 0.84 VREG1OUT x 0.85 VREG1OUT x 0.86 VREG1OUT x 0.87 VREG1OUT x 0.88 VREG1OUT x 0.89 VREG1OUT x 0.90 VREG1OUT x 0.91 VREG1OUT x 0.92 VREG1OUT x 0.93 VREG1OUT x 0.94 VREG1OUT x 0.95 VREG1OUT x 0.96 VREG1OUT x 0.97 VREG1OUT x 0.98 VREG1OUT x 0.99 VREG1OUT x 1.00 VCMSEL: VCMSEL is to select VCM1 or VCM2; When VCMSEL=”0”, VCM1 is selected while VCMSEL=”1”, VCM2 is selected. © ORISE Technology Co., Ltd. Proprietary & Confidential 32 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.25. γ Control (R30h to R3Fh) Table 6-27 R/W RS CB15 CB14 CB13 CB12 CB11 CB10 CB9 R30 W 1 0 0 R31 W 1 0 R32 W 1 0 R33 W 1 R34 W 1 R35 W 1 R36 W R37 R38 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0 V1RN4 V1RN3 V1RN2 V1RN1 V1RN0 V1RP4 V1RP3 V1RP2 V1RP1 V1RP0 0 0 0 V2RP5 V2RP4 V2RP3 V2RP2 V2RP1 V2RP0 0 0 V2RN5 V2RN4 V2RN3 V2RN2 V2RN1 V2RN0 0 V3RP5 V3RP4 V3RP3 V3RP2 V3RP1 V3RP0 0 0 V3RN5 V3RN4 V3RN3 V3RN2 V3RN1 V3RN0 0 0 V4RP5 V4RP4 V4RP3 V4RP2 V4RP1 V4RP0 0 0 V4RN5 V4RN4 V4RN3 V4RN2 V4RN1 V4RN0 0 0 V5RP5 V5RP4 V5RP3 V5RP2 V5RP1 V5RP0 0 0 V5RN5 V5RN4 V5RN3 V5RN2 V5RN1 V5RN0 0 0 0 V6RP4 V6RP3 V6RP2 V6RP1 V6RP0 0 0 0 V6RN4 V6RN3 V6RN2 V6RN1 V6RN0 1 0 0 0 V7RP4 V7RP3 V7RP2 V7RP1 V7RP0 0 0 0 V7RN4 V7RN3 V7RN2 V7RN1 V7RN0 W 1 0 0 0 V8RP4 V8RP3 V8RP2 V8RP1 V8RP0 0 0 0 V8RN4 V8RN3 V8RN2 V8RN1 V8RN0 W 1 0 0 0 0 V9RP3 V9RP2 V9RP1 V9RP0 0 0 0 0 V9RN3 V9RN2 V9RN1 V9RN0 R39 W 1 0 0 0 0 V10RP3 V10RP2 V10RP1 V10RP0 0 0 0 0 V10RN3 V10RN2 V10RN1 V10RN0 R3A W 1 0 0 0 0 V11RP3 V11RP2 V11RP1 V11RP0 0 0 0 0 V11RN3 V11RN2 V11RN1 V11RN0 R3B W 1 0 0 0 0 V12RP3 V12RP2 V12RP1 V12RP0 0 0 0 0 V12RN3 V12RN2 V12RN1 V12RN0 R3C W 1 0 0 0 0 V13RP3 V13RP2 V13RP1 V13RP0 0 0 0 0 V13RN3 V13RN2 V13RN1 V13RN0 R3D W 1 0 0 0 0 V14RP3 V14RP2 V14RP1 V14RP0 0 0 0 0 V14RN3 V14RN2 V14RN1 V14RN0 R3E W 1 0 0 0 0 V15RP3 V15RP2 V15RP1 V15RP0 0 0 0 0 V15RN3 V15RN2 V15RN1 V15RN0 R3F W 1 0 0 0 0 V16RP3 V16RP2 V16RP1 V16RP0 0 0 0 0 V16RN3 V16RN2 V16RN1 V16RN0 γ Control (R30h to R3Fh): SPFD5408B provides 16 gamma registers to fine tune gamma output voltage. V1RP[4:0]: register for positive VSD0 fine tune adjustment. V1RN[4:0]: register for negative VSD0 fine tune adjustment. V2RP[5:0]: register for positive VSD1 fine tune adjustment. V2RN[5:0]: register for negative VSD1 fine tune adjustment. V3RP[5:0]: register for positive VSD2 fine tune adjustment. V3RN[5:0]: register for negative VSD2 fine tune adjustment. V4RP[5:0]: register for positive VSD61 fine tune adjustment. V4RN[5:0]: register for negative VSD61 fine tune adjustment. V5RP[5:0]: register for positive VSD62 fine tune adjustment. V5RN[5:0]: register for negative VSD62 fine tune adjustment. V6RP[4:0]: register for positive VSD63 fine tune adjustment V6RN[4:0]: register for negative VSD63 fine tune adjustment V7RP[4:0]: register for positive VSD13 fine tune adjustment V7RN[4:0]: register for negative VSD13 fine tune adjustment V8RP[4:0]: register for positive VSD50 fine tune adjustment V8RN[4:0]: register for negative VSD50 fine tune adjustment V9RP[3:0]: register for positive VSD4 fine tune adjustment V9RN[3:0]: register for negative VSD4 fine tune adjustment V10RP[3:0]: register for positive VSD8 fine tune adjustment V10RN[3:0]: register for negative VSD8 fine tune adjustment V11RP[3:0]: register for positive VSD20 fine tune adjustment V11RN[3:0]: register for negative VSD20 fine tune adjustment V12RP[3:0]: register for positive VSD27 fine tune adjustment V12RN[3:0]: register for negative VSD27 fine tune adjustment V13RP[3:0]: register for positive VSD36 fine tune adjustment V13RN[3:0]: register for negative VSD36 fine tune adjustment V14RP[3:0]: register for positive VSD43 fine tune adjustment V14RN[3:0]: register for negative VSD43 fine tune adjustment V15RP[3:0]: register for positive VSD55 fine tune adjustment V15RN[3:0]: register for negative VSD55 fine tune adjustment V16RP[3:0]: register for positive VSD59 fine tune adjustment V16RN[3:0]: register for negative VSD59 fine tune adjustment 6.2.26. Window Horizontal RAM Address Start (R50h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 0 CB8 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 6.2.27. Window Horizontal RAM Address End (R51h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 © ORISE Technology Co., Ltd. Proprietary & Confidential 0 0 0 0 CB9 0 CB8 0 33 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.28. Window Vertical RAM Address Start (R52h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 6.2.29. Window Vertical RAM Address End (R53h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 HSA7-0/HEA7-0: SPFD5408B provides window access function. Figure 6-24 illustrates the window-accessing function using R44 and R45. Set HSA7-0 and HEA7-0 represent the start address and end address of the window function in horizontal direction. To use window-accessing function, HSA and HEA bits must be set before starting RAM write operation. Be aware that “00”h ≤ HSA7-0< HEA7-0 ≤ “EF”h and HEA-HSA>=”04h”. VSA8-0/VEA8-0: SPFD5408B provides window access function. Set VSA8-0 and VEA8-0 represent the start address and end address of the window in vertical direction. To use window-accessing function, VSA and VEA bits must be set before starting RAM write operation. Be aware that “00”h ≤ VSA8-0< VEA8-0 ≤ 9’h13F. 6.2.30. Driver Output Control (R60h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 GS 0 NL5 NL4 NL3 CB9 CB8 CB7 NL1 NL0 0 NL2 SCN5-0: Set the SCN5-0 bits can specify the starting position of the gate driver. The start position of gate driver is determined by the combination of the setting of GS and CB6 0 CB5 CB4 CB3 CB2 CB1 CB0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 SC SC SC SC SC SC N5 N4 N3 N2 N1 N0 Scan Start Position (Gate line) GS = “0” GS = “1” SM. Table 6-28 summarized the starting position for 0 0 1 0 1 0 G81 G240 each SCN5-0 setting. 0 0 1 0 1 1 G89 G232 0 0 1 1 0 0 G97 G224 0 0 1 1 0 1 G105 G216 Scan Start Position 0 0 1 1 1 0 G113 G208 (Gate line) 0 0 1 1 1 1 G121 G200 0 1 0 0 0 0 G129 G192 0 1 0 0 0 1 G137 G184 0 1 0 0 1 0 G145 G176 0 1 0 0 1 1 G153 G168 0 1 0 1 0 0 G161 G160 0 1 0 1 0 1 G169 G152 0 1 0 1 1 0 G177 G144 0 1 0 1 1 1 G185 G136 0 1 1 0 0 0 G193 G128 0 1 1 0 0 1 G201 G120 0 1 1 0 1 0 G209 G112 Table 6-28 (when SM=0) SC SC SC SC SC SC N5 N4 N3 N2 N1 N0 GS = “0” GS = “1” 0 0 0 0 0 0 G1 G320 0 0 0 0 0 1 G9 G312 0 0 0 0 1 0 G17 G304 0 0 0 0 1 1 G25 G296 0 0 0 1 0 0 G33 G288 0 0 0 1 0 1 G41 G280 0 0 0 1 1 0 G49 G272 0 0 0 1 1 1 G57 G264 0 0 1 0 0 0 G65 G256 0 0 1 0 0 1 G73 G248 © ORISE Technology Co., Ltd. Proprietary & Confidential 34 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B SC SC SC SC SC SC N5 N4 N3 N2 N1 N0 Scan Start Position (Gate line) GS = “0” GS = “1” SC SC SC SC SC SC N5 N4 N3 N2 N1 N0 Scan Start Position (Gate line) GS = “0” GS = “1” 0 1 1 0 1 1 G217 G104 1 0 0 0 1 1 G281 G40 0 1 1 1 0 0 G225 G96 1 0 0 1 0 0 G289 G32 0 1 1 1 0 1 G233 G88 1 0 0 1 0 1 G297 G24 0 1 1 1 1 0 G241 G80 1 0 0 1 1 0 G305 G16 0 1 1 1 1 1 G249 G72 1 0 0 1 1 1 G313 G8 1 0 0 0 0 0 G257 G64 1 0 1 0 0 0 1 0 0 0 0 1 G265 G56 1 0 0 0 1 0 G273 G48 Setting disable Setting disable 1 1 1 1 1 1 Setting NL5-0: Set the number of gate lines for different resolution of display panel. The combination of NL5-NL0 represents the gate line number are summarized at Table 6-29. Table 6-29 NL5 NL4 NL3 NL2 NL1 NL0 0 0 0 0 0 0 Display Size Lines Driven gate lines Setting disabled Setting disabled Setting disabled 176 G1 ~ G176 Setting disable 0 1 0 1 0 1 720 x 176 dots Setting disable 0 1 1 1 0 1 720 x 240 dots 240 G1 ~ G240 0 1 1 1 1 0 720 x 248 dots 248 G1 ~ G248 0 1 1 1 1 1 720 x 256 dots 256 G1 ~ G256 1 0 0 0 0 0 720 x 264 dots 264 G1 ~ G264 1 0 0 0 0 1 720 x 272 dots 272 G1 ~ G272 1 0 0 0 1 0 720 x 280 dots 280 G1 ~ G280 1 0 0 0 1 1 720 x 288 dots 288 G1 ~ G288 1 0 0 1 0 0 720 x 296 dots 296 G1 ~ G296 1 0 0 1 0 1 720 x 304 dots 304 G1 ~ G304 1 0 0 1 1 0 720 x 312 dots 312 G1 ~ G312 1 0 0 1 1 1 720 x 320 dots 320 G1 ~ G320 Setting disable Note: Back porch and a front porch (set with BP/FP bits respectively) are inserted before/ after driving all gate lines, GS: Shift direction of the gate driver output selection. When GS=“0”, gate driver shift from G1 to G320. When GS = “1”, gate driver shift from G320 to G1. © ORISE Technology Co., Ltd. Proprietary & Confidential 35 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.31. Driver Output Control (R61h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 CB8 CB7 0 0 0 CB6 CB5 0 CB4 0 CB3 0 CB2 0 NDL CB1 VLE CB0 REV To set the grayscale corresponding to normally white or normally black LCD panel from same data input. REV: Table 6-30Table 6-30 summarized REV bit function. VLE: SPFD5408B provides vertical scrolling function which can be Table 6-30 0 1 set by VLE bit. Source Driver Output GRAM REV data Positive Polarity Negative Polarity 18’h00000 V63 V0 18’h3FFFF V0 V63 18’h00000 V0 V63 18’h3FFFF V63 V0 VLE = “1”, vertical scrolling function enable. The amount of scrolling line from the first line is determined by VL[8:0]. VLE = ”0”, normal display. NDL: set the source diver output level in non-lit area.. NDL = “1”, . NDL = ”0”, . 6.2.32. Vertical Scroll Control (R6Ah) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 0 VL8-0: SPFD5408B provides scrolling function. The start position for displaying the image is shifted vertically by the number of lines based on the setting of the VL8-0 bits. Be aware that the vertical scrolling function is not available in the external (RGB) display interface mode. Table 6-31 summarized the function of VL8-0 setting. Table 6-31 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 Scrolling lines 0 0 0 0 0 0 0 0 0 0 line 0 0 0 0 0 0 0 0 1 1 line 0 0 0 0 0 0 0 1 0 2 lines : : : : : : : : : 1 0 0 1 1 1 1 1 1 319 lines 1 0 1 0 0 0 0 0 0 320 lines Note: VL8-0 bits cannot set more than 320 lines. 6.2.33. Display Position – Partial Display 1 (R80h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTD PTD PTD PTD PTD PTD PTD PTD PTD P08 P07 P06 P05 P04 P03 P02 P01 P00 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTS PTS PTS PTS PTS PTS PTS PTS PTS A08 A07 A06 A05 A04 A03 A02 A01 A00 6.2.34. RAM Address Start – Partial Display 1 (R81h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 © ORISE Technology Co., Ltd. Proprietary & Confidential 0 0 0 0 CB9 0 36 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.35. RAM Address End – Partial Display 1 (R82h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 0 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A08 A07 A06 A05 A04 A03 A02 A01 A00 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTD PTD PTD PTD PTD PTD PTD PTD PTD P18 P17 P16 P15 P14 P13 P12 P11 P10 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTS PTS PTS PTS PTS PTS PTS PTS PTS A18 A17 A16 A15 A14 A13 A12 A11 A10 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 PTE PTE PTE PTE PTE PTE PTE PTE PTE A18 A17 A16 A15 A14 A13 A12 A11 A10 CB1 CB0 6.2.36. Display Position – Partial Display 2 (R83h) R/W RS W 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 CB9 0 0 6.2.37. RAM Address Start – Partial Display 2 (R84h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 CB9 0 6.2.38. RAM Address End – Partial Display 2 (R85h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 CB9 0 PTDP0[8:0]: Set the physical starting position of partial display 1 on the LCD panel PTDP1[8:0]: Set the physical starting position of partial display 2 on the LCD panel The partial display 1 and partial display 2 should not overlap with each other. And make sure the PTDP0[8:0] < PTDP1[8:0]. PTSA0[8:0]: Set the start line address of display RAM of partial display 1 which will be display according to PTDP0[8:0]. PTEA0[8:0]: Set the end line address of display RAM of partial display 1 which will be display according to PTDP0[8:0]. Make sure PTSA0<=PTEA0 PTSA1[8:0]: Set the start line address of display RAM of partial display2 which will be display according to PTDP1[8:0]. PTEA1[8:0]: Set the end line address of display RAM of partial display2 which will be display according to PTDP1[8:0] Make sure PTSA1<=PTEA1 6.2.39. Panel Interface Control 1 (R90h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 RTNI4-0: 0 0 0 0 0 0 CB9 CB8 CB7 CB6 CB5 0 0 0 DIVI1 DIVI0 CB4 CB3 CB2 RTNI4 RTNI 3 RTNI 2 RTNI 1 RTNI 0 Set the clock cycle per line Table 6-32 summarized the function of RTNI4-0 setting. Table 6-32 RTNI4 0 RTNI3 0 RTNI2 0 RTNI1 0 RTNI0 0 Clock Cycles per line Setting disable Setting disable 1 0 0 0 0 16 clocks 1 0 0 0 1 17 clocks 1 0 0 1 0 18 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 37 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B RTNI4 RTNI3 RTNI2 RTNI1 RTNI0 Clock Cycles per line 1 0 0 1 1 19 clocks 1 0 1 0 0 20 clocks 1 0 1 0 1 21 clocks 1 0 1 1 0 22 clocks 1 0 1 1 1 23 clocks 1 1 0 0 0 24 clocks 1 1 0 0 1 25 clocks 1 1 0 1 0 26 clocks 1 1 0 1 1 27 clocks 1 1 1 0 0 28 clocks 1 1 1 0 1 29 clocks 1 1 1 1 0 30 clocks 1 1 1 1 1 31 clocks DIVI1-0: To specified the division ratio of internal operation clock frequency. Set the RTN and DIVI bits to adjust frame frequency. Be aware of that if the number of lines for driving liquid crystal is changed, the frame frequency must also be adjusted. Moreover, In RGB interface mode, the DIVI1-0 bits are disabled. Table 6-33 summarized the function of DIVI1-0 setting. Formula to calculate frame frequency Table 6-33 Division Internal Operation Clock Ratio Frequency 0 1 fosc / 1 0 1 2 fosc / 2 1 0 4 fosc / 4 1 1 8 fosc / 8 DIVI1 DIVI0 0 fosc: frequency of RC oscillation Line: number of lines for driving liquid crystal (NL bits) Division ratio: DIVI bits Clock cycles per line: RTNI bits fosc =Frequency of RC oscillation FP: the number of lines for the front porch period BP: the number of lines for the back porch period 6.2.40. Panel Interface Control 2 (R92h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 CB9 CB8 NOWI2NOWI1NOWI0 CB7 0 CB6 0 CB5 0 CB4 0 CB3 CB2 0 CB1 0 0 CB0 0 NOWI [2:0]: Set the adjacent gate driver output non-overlap period. Table 6-34 summarized the function of NOWI2-0 setting. Table 6-34 Gate output non-overlap period NOWI2 NOWI1 NOWI0 Internal Operation (reference clock: internal oscillator) 0 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 7 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 38 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.41. Panel Interface control 3 (R93h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 0 0 CB9 0 CB8 CB7 0 0 CB6 CB5 0 0 CB4 0 CB3 0 CB2 CB1 CB0 MCP MCP MCP I2 I1 I0 CB1 CB0 MCPI[2:0]: Set source driver start output timing. The source driver output position is measure from internal reference point. MCPI2 MCPI0 Source driver start output position 0 MCPI1 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 7 clocks 6.2.42. Panel Interface control 4 (R95h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 1 0 0 0 0 0 0 CB9 CB8 DIVE1 DIVE0 CB7 CB6 0 0 CB5 CB4 CB3 CB2 RTNE5RTNE4RTNE3RTNE2RTNE1RTNE0 RTNE5-0: Set the clock cycle per line Table 6-35 summarized the function of RTNE5-0 setting. Table 6-35 RTNE5 0 RTNE4 RTNE3 0 0 RTNE2 0 RTNE1 RTNE0 0 Clock Cycles per line 0 Setting disable Setting disable 0 1 0 0 0 0 16 clocks 0 1 0 0 0 1 17 clocks 0 1 0 0 1 0 18 clocks 0 1 0 0 1 1 19 clocks 0 1 0 1 0 0 20 clocks 0 1 0 1 0 1 21 clocks 0 1 0 1 1 0 22 clocks 0 1 0 1 1 1 23 clocks 0 1 1 0 0 0 24 clocks 0 1 1 0 0 1 25 clocks 0 1 1 0 1 0 26 clocks 0 1 1 0 1 1 27 clocks 0 1 1 1 0 0 28 clocks 0 1 1 1 0 1 29 clocks 0 1 1 1 1 0 30 clocks 0 1 1 1 1 1 31 clocks 1 1 0 0 0 0 32 clocks 1 1 0 0 0 1 33 clocks 1 1 0 0 1 0 34 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 39 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 Clock Cycles per line 1 1 0 0 1 1 35 clocks 1 1 0 1 0 0 36 clocks 1 1 0 1 0 1 37 clocks 1 1 0 1 1 0 38 clocks 1 1 0 1 1 1 39 clocks 1 1 1 0 0 0 40 clocks 1 1 1 0 0 1 41 clocks 1 1 1 0 1 0 42 clocks 1 1 1 0 1 1 43 clocks 1 1 1 1 0 0 44 clocks 1 1 1 1 0 1 45 clocks 1 1 1 1 1 0 46 clocks 1 1 1 1 1 1 47 clocks 1 1 0 0 0 0 48 clocks 1 1 0 0 0 1 49 clocks 1 1 0 0 1 0 50 clocks 1 1 0 0 1 1 51 clocks 1 1 0 1 0 0 52 clocks 1 1 0 1 0 1 53 clocks 1 1 0 1 1 0 54 clocks 1 1 0 1 1 1 55 clocks 1 1 1 0 0 0 56 clocks 1 1 1 0 0 1 57 clocks 1 1 1 0 1 0 58 clocks 1 1 1 0 1 1 59 clocks 1 1 1 1 0 0 60 clocks 1 1 1 1 0 1 61 clocks 1 1 1 1 1 0 62 clocks 1 1 1 1 1 1 63 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 40 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B DIVE1-0: To specified the division ratio of internal operation clock frequency. Set the RTNE and DIVE bits to adjust frame frequency. Be aware of that if the number of lines for driving liquid crystal is changed, the frame frequency must also be adjusted. Moreover, In RGB interface mode, the DIVE1-0 bits are disabled. Table 6-36 summarized the function of DIVE1-0 setting. Table 6-36 DIVE1 DIVE0 0 0 0 1 Division Internal Operation Clock Ratio Frequency Setting disable 4 fosc / 4 1 0 8 fosc / 8 1 1 16 fosc / 16 fosc =Frequency of RC oscillation 6.2.43. Panel Interface Control 5 (R97h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 CB9 CB8 NOW NOW NOW NOW E3 E2 E1 CB7 CB6 0 0 CB5 0 CB4 0 CB3 0 CB2 0 CB1 0 CB0 0 E0 NOWE [3:0]: Set the adjacent gate driver output non-overlap period in RGB interface. Table 6-37 summarized the function of NOWE3-0 setting. Table 6-37 Gate output non-overlap period NOWE3 NOWE2 NOWE1 NOWE0 Internal Operation (reference clock: internal oscillator) 0 0 0 0 0 clock 0 0 0 1 1 clocks 0 0 1 0 2 clocks 0 0 1 1 3 clocks 0 1 0 0 4 clocks 0 1 0 1 5 clocks 0 1 1 0 6 clocks 0 1 1 1 7 clocks 1 0 0 0 8 clocks 1 0 0 1 9 clocks 1 0 1 0 10 clocks 1 0 1 1 11 clocks 1 1 0 0 12 clocks 1 1 0 1 13 clocks 1 1 1 0 14 clocks 1 1 1 1 15 clocks © ORISE Technology Co., Ltd. Proprietary & Confidential 41 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 6.2.44. Panel Interface Control 6 (R98h) R/W RS W CB15 CB14 CB13 CB12 CB11 CB10 0 1 0 0 0 0 0 CB9 0 CB8 CB7 0 0 CB6 0 CB5 0 CB4 0 CB3 0 CB2 CB1 CB0 MCP MCP MCP E2 E1 E0 MCPE[2:0]: Set source driver start output timing in RGB interface. The source driver output position is measure from internal reference point. MCPE2 MCPE1 MCPE0 Source driver start output position 0 0 0 0 clock 0 0 1 1 clocks 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 4 clocks 1 0 1 5 clocks 1 1 0 6 clocks 1 1 1 7 clocks 6.2.45. Calibration Control (RA4h) R/W W RS 1 CB15 CB14 CB13 CB12 CB11 CB10 0 0 0 0 0 0 CB9 0 CB8 CB7 0 0 CB6 0 CB5 0 CB4 0 CB3 0 CB2 0 CB1 0 CB0 CALB CALB: .the enable bit for the read function of the NVM. When CALB=”1”: Read function from NVM is enable. When CALB=”0”: Read function from NVM is disable. © ORISE Technology Co., Ltd. Proprietary & Confidential 42 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 7. GRAM DB17-0 DB17-0 S720 S719 S718 S717 S716 S715 S714 S713 S712 DB17-0 S711 S710 DB17-0 S12 …. S11 DB17-0 S10 S9 S8 DB17-0 …. S709 DB17-0 S7 S6 S5 S4 S3 S2 S/G pin S1 Table 7-1 GRAM address and display panel position (SS = “0”) GS=0 GS=1 DB17-0 G1 G320 “00000"H “00001"H “00002"H "00003"H …. "000EC"H "000ED"H "000EE"H "000EF"H G2 G319 "00100"H "00101"H "00102"H "00103"H …. "001EC"H "001ED"H "001EE"H "001EF"H G3 G318 "00200"H "00201"H "00202"H "00203"H …. "002EC"H "002ED"H "002EE"H "002EF"H G4 G317 "00300"H "00301"H "00302"H "00303"H …. "003EC"H "003ED"H "003EE"H "003EF"H G5 G316 "00400"H "00401"H "00402"H "00403"H …. "004EC"H "004ED"H "004EE"H "004EF"H G6 G315 "00500"H "00501"H "00502"H "00503"H …. "005EC"H "005ED"H "005EE"H "005EF"H G7 G314 "00600"H "00601"H "00602"H "00603"H …. "006EC"H "06ED"H "06EE"H "06EF"H G8 G313 "00700"H "00701"H "00702"H "00703"H …. “007EC"H “007ED"H “007EE"H “007EF"H G9 G312 “00800"H “00801"H “00802"H “00803"H …. “008EC"H “008ED"H “008EE"H “008EF"H G10 G311 “00900"H “00901"H “00902"H “00903"H …. “009EC"H “009ED"H “009EE"H “009EF"H G11 G310 “00E00"H “00E01"H “00E02"H “00E03"H …. “00EEC"H “00EED"H “00EEE"H “00EEF"H G12 G309 “00B00"H “00B01"H “00B02"H “00B03"H …. “00BEC"H “00BED"H “00BEE"H “00BEF"H G13 G308 “00C00"H “00C01"H “00C02"H “00C03"H …. “00CEC"H “00CED"H “00CEE"H “00CEF"H G14 G307 “00D00"H “00D01"H “00D02"H “00D03"H …. “00DEC"H “00DED"H “00DEE"H “00DEF"H G15 G306 “00E00"H “00E01"H “00E02"H “00E03"H …. “00EEC"H “00EED"H “00EEE"H “00EEF"H G16 G305 “00F00"H “00F01"H “00F02"H “00F03"H …. “00FEC"H “00FED"H “00FEE"H “00FEF"H G17 G304 “01000"H “01001"H “01002"H “01003"H …. “010EC"H “010ED"H “010EE"H “010EF"H G18 G303 “01100"H “01101"H “01102"H “01103"H …. “011EC"H “011ED"H “011EE"H “011EF"H G19 G302 “01200"H “01201"H “01202"H “01203"H …. “012EC"H “012ED"H “012EE"H “012EF"H G20 …. G301 “01300"H “01301"H “01302"H “01303"H “013EC"H “013ED"H “013EE"H “013EF"H ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： “13803"H …. “138EC"H “138ED"H “138EE"H “138EF"H G313 G8 “13800"H “13801"H “13802"H G314 G7 “13900"H “13901"H “13902"H “13903"H …. “139EC"H “139ED"H “139EE"H “139EF"H G315 G6 “13A00"H “13A01"H “13A02"H “13A03"H …. “13AEC"H “13AED"H “13AEE"H “13AEF"H G316 G5 “13B00"H “13B01"H “13B02"H “13B03"H …. “13BEC"H “13BED"H “13BEE"H “13BEF"H G317 G4 “13C00"H “13C01"H “13C02"H “13C03"H …. “13CEC"H “13CED"H “13CEE"H “13CEF"H G318 G3 “13D00"H “13D01"H “13D02"H “13D03"H …. “13DEC"H “13DED"H “13DEE"H “13DEF"H G319 G2 “13E00"H “13E01"H “13E02"H “13E03"H …. “13EEC"H “13EED"H “13EEE"H “13EEF"H G320 G1 “13F00"H “13F01"H “13F02"H “13F03"H …. “13FEC"H “13FED"H “13FEE"H “13FEF"H © ORISE Technology Co., Ltd. Proprietary & Confidential 43 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 …. S709 S12 S11 S10 S9 S8 … S7 S5 S4 S3 S2 S/G pin S1 Table 7-2 GRAM address and display panel position (SS = “1”) GS=0 GS=1 DB17-0 DB17-0 DB17-0 DB17-0 …. DB17-0 DB17-0 DB17-0 DB17-0 G1 G320 “000EF”H “000EE”H “000ED”H “000EC”H …. “00003”H “00002”H “00001”H “00000”H G2 G319 “001EF”H “001EE”H “001ED”H “001EC”H …. “00103”H “00102”H “00101”H “00100”H G3 G318 “002EF”H “002AE”H “002ED”H “002EC”H …. “00203”H “00202”H “00201”H “00200”H G4 G317 “003EF”H “003EE”H “003ED”H “003EC”H …. “00303”H “00302”H “00301”H “00300”H G5 G316 “004EF”H “004EE”H “004ED”H “004EC”H …. “00403”H “00402”H “00401”H “00400”H G6 G315 “005EF”H “005EE”H “005ED”H “005EC”H …. “00503”H “00502”H “00501”H “00500”H G7 G314 “006EF”H “006EE”H “006ED”H “006EC”H …. “00603”H “00602”H “00601”H “00600”H G8 G313 “007EF”H “007EE”H “007ED”H “007EC”H …. “00703”H “00702”H “00701”H “00700”H G9 G312 “008EF”H “008EE”H “008ED”H “008EC”H …. “00803”H “00802”H “00801”H “00800”H G10 G311 “009EF”H “009EE”H “009ED”H “009EC”H …. “00903”H “00902”H “00901”H “00900”H G11 G310 “00AEF”H “00AEE”H “00AED”H “00AEC”H …. “00E03”H “00A02”H “00A01”H “00A00”H G12 G309 “00BEF”H “00BEE”H “00BED”H “00BEC”H …. “00B03”H “00B02”H “00B01”H “00B00”H G13 G308 “00CEF”H “00CEE”H “00CED”H “00CEC”H …. “00C03”H “00C02”H “00C01”H “00C00”H G14 G307 “00DEF”H “00DEE”H “00DED”H “00DEC”H …. “00D03”H “00D02”H “00D01”H “00D00”H G15 G306 “00EEF”H “00EEE”H “00EED”H “00EEC”H …. “00E03”H “00E02”H “00E01”H “00E00”H G16 G305 “00FEF”H “00FEE”H “00FED”H “00FEC”H …. “00F03”H “00F02”H “00F01”H “00F00”H G17 G304 “010EF”H “010EE”H “010ED”H “010EC”H …. “01003”H “01002”H “01001”H “01000”H G18 G303 “011EF”H “011EE”H “011ED”H “011EC”H …. “01103”H “01102”H “01101”H “01100”H G19 G302 “012EF”H “012EE”H “012ED”H “012EC”H …. “01203”H “01202”H “01201”H “01200”H G20 G301 “013EF”H “013EE”H “013ED”H “013EC”H …. “01303”H “01302”H “01301”H “01300”H ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： ： G233 G8 “E8EF”H “138EE”H “138ED”H “138EC”H …. “13803”H “13802”H “13801”H “13800”H G234 G7 “139EF”H “139EE”H “139ED”H “139EC”H …. “13903”H “13902”H “13901”H “13900”H G235 G6 “13AEF”H “13AEE”H “13AED”H “13AEC”H …. “13A03”H “13A02”H “13A01”H “13A00”H G236 G5 “13BEF”H “13BEE”H “13BED”H “13BEC”H …. “13B03”H “13B02”H “13B01”H “13B00”H G237 G4 “13CEF”H “13CEE”H “13CED”H “13CEC”H …. “13C03”H “13C02”H “13C01”H “13C00”H G238 G3 “13DEF”H “13DEE”H “13DED”H “13DEC”H …. “13D03”H “13D02”H “13D01”H “13D00”H G239 G2 “13EEF”H “13EEE”H “13EED”H “13EEC”H …. “13E03”H “13E02”H “13E01”H “13E00”H G240 G1 “13FEF”H “13FEE”H “13FED”H “13FEC”H …. “13F03”H “13F02”H “13F01”H “13F00”H © ORISE Technology Co., Ltd. Proprietary & Confidential 44 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8. INTERFACES The SPFD5408B provides different interfaces to meet the diverse 1. System interface need of small/medium size LCD. Based on the application 2. External interface (RGB interface) requirement, there are three different display modes which are 3. VSYNC interface most used in end product. 1. Still picture display System interface is suitable for still picture display while RGB 2. Moving picture display. interface and VSYNC interface are suitable for moving picture 3. Re-writing still pictures while moving picture are display. display. Be aware that RGB or VSYNC interface still can used to display still picture and system interface can also display moving For above three different display requirements, SPFD5408B picture. Table 8-1 summarized different interfaces for different provides different interfaces to meet the requirement. display requirement. Table 8-1 Operation Mode Display Mode System Still picture RGB interface (1) Moving picture RGB interface (2) RAM Access Setting (RM) Display Operation Mode (DM1-0) System interface Internal operating clock (RM = 0) (DM1-0 = 00) RGB interface RGB interface (RM = 1) (DM1-0 = 01) Rewriting still pictures while System interface RGB interface displaying moving pictures (RM = 0) (DM1-0 = 01) System interface VSYNC interface (RM = 0) (DM1-0 = 10) VSYNC interface Moving pictures 8.1. System Interface The system interfaces of SPFD5408B can support 8-bit, 9-bit, interface can set instructions and access RAM. Table 8-2 16-bit, 18-bit 80-system Interface and Serial Peripheral Interface summarized the interface corresponding to IM3-0 setting. (SPI), which can be set by the IM3/2/1/0 pins. The system Table 8-2 IM3 IM2 IM1 IM0 0 0 0 0 Setting disabled - 0 0 0 1 Setting disabled - 0 0 1 0 80-system 16-bit interface DB17 to 10 and 8 to 1 0 0 1 1 80-system 8-bit interface DB17 to 10 0 1 0 * Serial peripheral interface (SPI) DB1 to 0 0 1 1 0 Setting disabled - 1 0 0 0 Setting disabled - 1 0 0 1 Setting disabled - 1 0 1 0 80-system 18-bit interface DB17 to 0 1 0 1 1 80-system 9-bit interface DB17 to 9 1 1 * * Setting disabled - - © ORISE Technology Co., Ltd. Proprietary & Confidential MPU-Interface Mode 45 DB Pin in use OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8.1.1. 80-system 18-bit interface 8.1.3. 80-system 9-bit interface The instruction and GRAM accessing format of 80-system 18-bit The instruction and GRAM accessing format of 80-system 9-bit interface are shown in Figure 8-1 and Figure 8-2, respectively. interface are shown in Figure 8-5 and Figure 8-6, respectively. Instruction Instructions DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 DB 9 DB 8 DB 7 CB 7 DB 6 CB 6 DB 5 CB 5 DB 4 CB 4 DB 3 CB 3 DB 2 CB 2 DB 1 CB 1 DB 0 CB 0 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 DB 9 DB 17 DB 16 CB 7 CB 6 DB 15 CB 5 DB 14 DB 13 CB 4 CB 3 DB 12 CB 2 DB 11 CB 1 DB DB 10 9 CB 0 Figure 8-5 Figure 8-1 RAM Accessing GRAM access DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 B 0 1st Transfer 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB DB 10 9 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 Figure 8-2 B 0 Figure 8-6 8.1.2. 80-system 16-bit interface 8.1.4. 80-system 8-bit interface The instruction and GRAM accessing format of 80-system 16-bit The instruction and GRAM accessing format of 80-system 8-bit interface are shown in Figure 8-3 and Figure 8-4, respectively. interface are shown in Figure 8-7 and Figure 8-8, respectively. Instruction DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 Instruction 1st Transfer CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 Figure 8-3 RAM Accessing TRI=0; DB 17 DB 16 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 Figure 8-7 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 RAM Accessing TRI=0; R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 1st Transfer B 0 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 DB 15 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB DB 13 12 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 DB 14 DB 13 DB 12 DB 17 DB 16 DB 15 DB 14 DB DB 13 12 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 RAM Accessing TRI=1;DFM1-0=10 1st Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 2nd Transfer DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB DB 17 16 B 0 RAM Accessing TRI=1, DFM1-0=10 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 B 0 1 st Transfer 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 3rd Transfer RAM Accessing TRI=1;DFM1-0=11 1st Transfer DB DB 2 1 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 G 3 B 0 RAM Accessing TRI=1, DFM1-0=11 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 G 3 G 2 G 1 G 0 B 5 B 4 B 3 B 2 B 1 B 0 1 st Transfer Figure 8-4 2nd Transfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 DB 15 G 3 3rd Transfer B 0 Figure 8-8 © ORISE Technology Co., Ltd. Proprietary & Confidential 46 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8.1.5. Serial Peripheral interface (SPI) The system interface of SPFD5408B also includes the Serial When read operation is desired In SPI mode, valid data are read Peripheral Interface (SPI). In SPI mode, /CS, SCL, SDI and SDO out as the SPFD5408B reads out the 6th byte data from the are used to transfer data between MCU and SPFD5408B. IM0/ID internal GRAM. The RAM data transfer in SPI mode, in SPI mode pin served as the ID pin. Figure 8-9 illustrates the detail timing with TRI=1/ DFM1-0=10 and status read are illustrated in Figure while using SPI. Be aware that the unused pins such as DB17-0 8-12, Figure 8-13 and Figure 8-14, respectively. pins must be fixed at either IOVCC or GND level. Transfer end Transfer Start CS (input) The instruction and GRAM accessing format of SPI interface are 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCL (input) shown in Figure 8-10 and Figure 8-11, respectively. MSB 0 SDI (input) 1 1 1 0 ID Device ID code LSB RS RW D15 D14 D13 D12 D11 RS RW D15 D14 D13 D12 D11 SDO (output) D10 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Figure 8-9 Start Byte Format Transferred bits S 1 2 Start byte format Transfer start Device ID code 0 3 1 4 1 5 1 6 0 7 8 RS R/W ID Note 1) ID bit is selected by setting the IM0/ID pin. RS R/W Function 0 0 Set an index register 0 1 Read a status 1 0 Write an instruction or RAM data Basic transfer in SPI mode Transfer end Transfer Start CS (input) 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 1 1 0 ID RS RW D15 D14 D13 D12 D11 RS RW 14 15 16 17 18 19 D10 D9 D8 D7 D6 D5 20 21 22 23 D3 D2 D1 MSB 1 1 24 SCL (input) SDI (input) Device ID code Read an instruction or RAM data SDO (output) Instruction 1st Transfer 2nd Transfer D15 D14 D13 D12 D11 LSB D10 D9 D8 D7 D6 D5 D4 D4 D3 D2 D1 D0 D0 Consecutive data transfer in SPI mode D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CB 15 CB 14 CB 13 CB 12 CB 11 CB 10 CB 9 CB 8 CB 7 CB 6 CB 5 CB 4 CB 3 CB 2 CB 1 CB 0 CS (input) SCL (input) SDI (input) Figure 8-10 RAM read out transfer RAM Accessing CS (input) 1st Transfer 2nd Transfer D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 D 7 G 3 G 2 D 6 G 1 D 5 G 0 D 4 B 5 SCL (input) D 3 B 4 D 2 B 3 D 1 B 2 D 0 B 1 SDI (input) SDO (Output) B 0 RAM Accessing TRI=1, DFM1-0=10 1 st Transfer 2nd Transfer D 23 D 22 D 21 D 20 D 19 D 18 D 15 D 14 R 5 R 4 R 3 R 2 R 1 R 0 G 5 G 4 D 13 G 3 Figure 8-12 3rd Transfer D 12 D 11 D 10 G 2 G 1 G 0 D 7 B 5 D 6 B 4 D 5 B 3 D 4 B 2 D 3 B 1 D 2 B 0 Figure 8-11 © ORISE Technology Co., Ltd. Proprietary & Confidential 47 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Status read RAM data access in SPI mode, when TRI=1, DFM1-0=10 Transfer Start CS* (input) CS (input) 1 2 3 4 5 1 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ID RS RW D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 RS RW 25 26 27 28 29 30 31 32 SCL (input) SCL (input) LSB 0 SDI (input) 1 1 Device ID code D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI (input) Start byte RAM data write D23 SDO (output) D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 SDO (Output) D0 RAM data read Figure 8-14 Consecutive data transfer in SPI mode CS (input) SCL (input) SDI (input) RAM read out transfer CS (input) SCL (input) SDI (input) SDO (Output) Figure 8-13 8.2. VSYNC Interface The SPFD5408B also supports VSYNC interface for moving picture display, which is the system interface in synchronization with the frame-synchronizing signal (VSYNC). The VSYNC interface can display a moving picture without tremendous modification. DM1-0 = “10” and RM = “0” can initialized VSYNC interface. In VSYNC interface mode, the internal display operation is synchronized with the VSYNC signal. In VSYNC interface mode, the graphic data are stored in GRAM to minimize the data transfer to overwrite on the moving picture GRAM area. Figure 8-15 illustrates moving picture data transfer through VSYNC interface. In VSYNC mode, Internal operation is executed in synchronization with the internal clock generated from internal oscillators and VSYNC input. Therefore the frame rate is determined by the frequency of VSYNC. SPFD5408B can access the internal RAM in high speed with less power consumption in VSYNC interface mode while using high-speed write mode Figure 8-15 In VSYNC interface mode, the formula for Internal clock frequency and frame rate is shown below: Input clock frequency = FrameRate x (DisplayLines) + FrontPorch + BackPorch x 16 x variance Due to the possible cause of variances while set the internal clock frequency; be sure to complete the display operation in one VSYNC cycle. © ORISE Technology Co., Ltd. Proprietary & Confidential 48 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8.3. External Display Interface SPFD5408B also includes external (RGB) interface for displaying moving picture. External interface can be set by RIM1-0 bit. Table 8-3 summarized the corresponding types of RGB interface with RIM1-0 setting. Table 8-3 RIM1 RIM0 RGB Interface DB Pin 0 0 18-bit RGB interface DB17-0 0 1 16-bit RGB interface DB17-10, 8-1 1 0 6-bit RGB interface DB17-12 1 1 Setting disabled RGB interface cab access SPFD5408B by VSYNC, HSYNC, ENABLE, DOTCLK and DB17-0 signals, where VSYNC is used for frame synchronization; HSYNC is used for line synchronization and ENABLE is served as the valid data synchronized signals. The RGB interface can be rewriting minimum necessary data to the GRAM area which need to be overwritten with use of window address function and high-speed write mode. It is necessary for RGB interface to set front and back porch periods after and before a display period, respectively. Figure 8-16 illustrates the general timing for RGB interface. There are some constrain while using RGB interface. The following summarized the conditions (a) Partial display/ scroll function / interlace and graphics operation function are not available for RGB interface (b) In RGB interface VSYNC, HSYNC, and DOTCLK signals must be input through a display operation period. (c) The setting of the NO1-0 bits, STD1-0 bits and EQ1-0 bits are based on DOTCLK in RGB interface mode. In 6-bit RGB interface mode, it takes 3 DOTCLK inputs to transfer one pixel. Be aware data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode is necessary. Set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC ENABLE, DB17-0) to input 3x clock to complete data transfer in units of pixels. (d) In RGB-I/F mode, while writing data to the internal RAM make sure to use the high-speed write mode (HWM = “1”) (e) In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame. (f) In RGB interface mode, a GRAM address (DB17-0) is set in the address counter every frame on the falling edge of VSYNC. RGB interface includes ENABLE signal served as valid data synchronized signals. Moreover, the active level for ENABLE can be set by EPL. The EPL bit inverts the polarity of ENABLE signal. Table 8-4 summarized the setting of EPL and ENABLE active level for GRAM accessing. Setting both EPL and ENABLE bits to automatically update RAM address in the AC is necessary while writing data to the GRAM. Table 8-4 Figure 8-16 © ORISE Technology Co., Ltd. Proprietary & Confidential 49 EPL ENABLE RAM Write RAM Address 0 0 Enabled Updated 0 1 Disenabled Retained 1 0 Disenabled Retained 1 1 Enabled Updated OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B SPFD5408B can support 18-bit, 16-bit and 6-bit RGB interface. The detail timing diagram for 18-bit, 16-bit and 6-bit RGB interface are shown in Figure 8-17 and Figure 8-18 respectively. Figure 8-18 Figure 8-17 The RGB interface also has the window address function to transfer only minimum necessary data on the moving picture GRAM area, which can lower the power consumption and still can use system interface to rewrite data in still picture RAM area while displaying a moving picture. Setting RM = 0 while in RGB interface mode can make GRAM access through the system interface. When RGB interface accessing GRAM is desired, wait for one read/write bus cycle following by RM = 1 setting. Figure 8-19 illustrates the timing diagram when displaying a moving picture through the RGB interface and rewriting data in the still picture GRAM area through the system interface. Figure 8-19 8.3.1. 6-bit RGB interface RAM accessing format and data transmission synchronization of 6-bit RGB interface are shown in Figure 8-20 and Figure 8-21, respectively. Figure 8-21 Figure 8-20 © ORISE Technology Co., Ltd. Proprietary & Confidential 50 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8.3.2. 16-bit RGB interface 8.3.3. 18-bit RGB interface RAM accessing format of 16-bit RGB interface are shown in RAM accessing format of 18-bit RGB interface are shown in Figure 8-22. Figure 8-23. Figure 8-22 Figure 8-23 © ORISE Technology Co., Ltd. Proprietary & Confidential 51 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 8.4. Sequence to set between system interface and RGB interface: Internal Clock Operation to RGB Interface (1) Internal clock operation HWM AM==01 and AM = 0 RAM address set Set DM1-0 = 01 and RM = 1 for RGB interface Set index register to R22h Display operation in synchronization with internal clocks *Instruction setting for the RGB interface operation is enebled from the next frame period. Wait one frame period or more Write data to RAM via RGB interface Display operation in synchronization with VSYNC, HSYNC, and DOTCLK Operation via RGB interface Note: Input the RGB interface signals before setting the DM 1-0 and RM bits to the RGB interface operation . RGB Interface (1) to Internal Clock Operation RGB interface operation Set internal clock operation mode* (DM1-0 = 00 and RM = 0) Wait one frame period or more Internal clock operation Display operation in synchronization with VSYNC, HSYNC, and DOTCLK *Instruction setting to the internal clock operation is enebled from the next frame period. Display operation in synchronization with internal clocks Note: Continue RGB interface signals at least for one frame period after setting DM1-0, RM bits to internal clock operation. © ORISE Technology Co., Ltd. Proprietary & Confidential 52 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 9. Display Feature Function: 9.1. FMARK function: SPFDF5408B provided FMARK function which output signal to alert host MCU via FMARK I/O pad so that LCD display can avoid flicker effect. FMARK output position and interval can be set by FMP[8:0] and FMI[2:0], respectively. Figure 9-1 illustrated the FMARK output position when FMP[8:0]=9’h008. FMARK output position FMP = 9'h008 Line address Back porch FMP=9'h008 NL=6'h27 320th line FP=4'h8 BP=4'h8 VL=8'h00 RAM physical line address 8 (9th line) 9 (10th line) 10 (11th line) Base image NL=6'h27 Display area AD[16:8]=9'h13F 327 (320th line) Front porch Figure 9-1 Example of FMARK signal. © ORISE Technology Co., Ltd. Proprietary & Confidential 53 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 9.2. Scan Mode function: SM GS 0 0 Scan Direction odd-number G1 G3 G2 G4 even-number G2 to G320 G1 to G319 TFT panel G318 G320 G317 G319 SPFD5408B Scan Order: 0 G1, G2, G3, G4,---------G317, G318, G319, G320 1 odd-number G1 G3 G2 G4 even-number G320 to G2 G319 to G1 TFT panel G318 G320 G317 G319 SPFD5408B Scan Order: G320, G319, G318, G317,------G4, G3, G2, G1 1 0 G1 odd-number TFT panel even-number G2 G2 to G320 G1 to G319 G319 G320 SPFD5408B Scan Order: G1, G3, G5,----G317,G319, G2, G4, G6,----G318, G320 1 1 G1 odd-number TFT panel even-number G2 G320 G320 to G2 G319 to G1 G319 SPFD5408B Scan Order: © ORISE Technology Co., Ltd. Proprietary & Confidential G320, G318, G316,-----G4, G2, G319, G317, G315,-----G3, G1 54 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 9.3. Scaling function: SPFD5408 provides scaling function to resize the display area. The Scaling factor can be set via RSZ[1:0] (register R04h, CB [1:0]). Table summarized the RSZ[1:0] function. The image after scaling can be displayed at the area set by (HSA, HEA, VSA, VFA). Table 9-1 RSZ[1:0] 00 01 10 11 Scaling Factor No scaling 1/2 scaling Setting Disable 1/4 scaling Actual resolution (original input data 240xRGbx320) 240xRGBx320 120xRGBx160 60xRGBx80 Table 9-2 illustrated the data arrangement when scaling factor is 1/2, RSZ[1:0]=’”01” 1 2 3 4 5 6 7 8 1 2 3 4 1 A1 B1 C1 D1 E1 F1 G1 H1 2 A2 B2 C2 D2 E2 F2 G2 H1 1 A1 C1 E1 G1 3 A3 B3 C3 D3 E3 F3 G3 H3 4 A4 B4 C4 D4 E4 F4 G4 H4 2 A3 C3 E3 G3 5 A5 B5 C5 D5 E5 F5 G5 H5 6 A6 B6 C6 D6 E6 F6 G6 H6 3 A5 C5 E5 G5 7 A7 B7 C7 D7 E7 F7 G7 H7 8 A8 B8 C8 D8 E8 F8 G8 H8 4 A7 C7 E7 G7 Table 9-3 data arrangement Figure 9-2 illustrated the example when scaling factor is 1/2, RSZ[1:0]=’”01” © ORISE Technology Co., Ltd. Proprietary & Confidential 55 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B The flow chart to use scaling function: Set (RSZ, RCH, RCV) Set scaling image location (HSA, HEA, VSA, VEA) RAM Address Set (AD16~0) Write Data to RAM Via R22h © ORISE Technology Co., Ltd. Proprietary & Confidential 56 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 9.4. Partial Display function: SPFD5408 has partial display function feature which can provide only partial display for power saving purpose. Partial display function can be accessed by setting BSEE=”0”,. Moreover, 2 partial display area (partial image 1/ partial image 2) can be initialized by set PTDE0=”1” and PTDE1=”1”, respectively. The partial display area for partial image 1 and partial 2 can be set by PTSA0 / PTEA0 and PTSA1/ PTEA1, respectively. Table 9-4 and Figure 9-3 summarized the full and partial display function. Table 9-4 Partial display function summary table Case Function Setting Display area setting Display Position Full display BASEE=”1” PTDE0=”x” PTDE1=”x” BASEE=”0” PTDE0=”1” PTDE1=”0” BASEE=”0” PTDE0=”0” PTDE1=”1” BASEE=”0” PTDE0=”1” PTDE1=”1” (BSA,BEA) - (PTSA0,PTEA0) PTDP0 (PTSA1,PTEA1) PTDP1 (PTSA0,PTEA0) (PTSA1,PTEA1) PTDP0 & PTDP1 Partial image1:0n Partial image2:Off Partial image1:Off Partial image2:On Partail image1:On Partial image2:On Figure 9-3 Partial display function diagram Figure 9-4 indicated the case of NL[5:0] setting is < 6’h27 which active line is less than 320. Partial display image data can stored in not active area. Figure 9-5 indicated the partial display area start position. The partial display area and start position can be set by (PTSA0, PTEA0, PTSA1, PTEA1) and (PTDP0, PTDP1), respectively. © ORISE Technology Co., Ltd. Proprietary & Confidential 57 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Display Data output order LCD panel Physical line address Display screen 1 2 3 4 5 0 (1st line) 1 (2nd line) 2 (3rd line) RAM line address Partial display BSA0=9'h000 PTSD image 1 Display area NL (n lines) NL BASE image RAM area PTSD image 2 Display area n-1 NL PTSA0 PTSA0 PTEA0 PTEA0 Partial image 1 RAM area PTSA1 PTSA1 PTEA1 PTEA1 Partial image 2 RAM area BEA=9'h13F Figure 9-4 Example of NL[5:0] setting is < 6’h27 case Figure 9-5 indicated the partial display area start position. © ORISE Technology Co., Ltd. Proprietary & Confidential 58 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 9.5. Gamma Correction functions: SPFD54508A adopt Gamma voltage generation circuit which can provide wider output voltage range to fit the different kind of liquid crystal for Gamma curve from 1.0~2.5. The Gamma output voltage can be set by R30h~R3Fh. V1RP[4:0]: register for positive VSD0 fine tune adjustment. V1RN[4:0]: register for negative VSD0 fine tune adjustment. V2RP[5:0]: register for positive VSD1 fine tune adjustment. V2RN[5:0]: register for negative VSD1 fine tune adjustment. V3RP[5:0]: register for positive VSD2 fine tune adjustment. V3RN[5:0]: register for negative VSD2 fine tune adjustment. V4RP[5:0]: register for positive VSD61 fine tune adjustment. V4RN[5:0]: register for negative VSD61 fine tune adjustment. V5RP[5:0]: register for positive VSD62 fine tune adjustment. V5RN[5:0]: register for negative VSD62 fine tune adjustment. V6RP[4:0]: register for positive VSD63 fine tune adjustment V6RN[4:0]: register for negative VSD63 fine tune adjustment V7RP[4:0]: register for positive VSD13 fine tune adjustment V7RN[4:0]: register for negative VSD13 fine tune adjustment V8RP[4:0]: register for positive VSD50 fine tune adjustment V8RN[4:0]: register for negative VSD50 fine tune adjustment V9RP[3:0]: register for positive VSD4 fine tune adjustment V9RN[3:0]: register for negative VSD4 fine tune adjustment V10RP[3:0]: register for positive VSD8 fine tune adjustment V10RN[3:0]: register for negative VSD8 fine tune adjustment V11RP[3:0]: register for positive VSD20 fine tune adjustment V11RN[3:0]: register for negative VSD20 fine tune adjustment V12RP[3:0]: register for positive VSD27 fine tune adjustment V12RN[3:0]: register for negative VSD27 fine tune adjustment V13RP[3:0]: register for positive VSD36 fine tune adjustment V13RN[3:0]: register for negative VSD36 fine tune adjustment V14RP[3:0]: register for positive VSD43 fine tune adjustment V14RN[3:0]: register for negative VSD43 fine tune adjustment V15RP[3:0]: register for positive VSD55 fine tune adjustment V15RN[3:0]: register for negative VSD55 fine tune adjustment V16RP[3:0]: register for positive VSD59 fine tune adjustment V16RN[3:0]: register for negative VSD59 fine tune adjustment Figure 9-6 illustrated 4 different Gamma Curve. Gamma Curve 1.0 0.9 0.8 Gamma = 1.0 0.7 Gamma = 2.5 0.6 Gamma = 2.2 Y 0.5 Gamma = 1.8 0.4 0.3 0.2 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 X © ORISE Technology Co., Ltd. Proprietary & Confidential 59 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 10. Power Management System: (a) VCI1=VCI direct input: VREG1OUT Amplifier 1 (VDH adjustment) VciOUT VCIOUT AMP VGH VGL REGP Source driver VcomR Vci1 Vci C11- Gate driver VcomH Adjustment circuit G1-320 S1-720 Grayscale voltage generating circuit C11+ VLOUT1 DDVDH C12- VcomH output AMP C12+ C21- VcomH Vcom C21+ C22- Vcom amplitude adjustment VcomL output AMP VcomL See Note 3 C22+ C23C23+ VCC VLOUT2 GND VGH VCILVL VCI VLOUT3 AGND VGL IOVCC IOGND VCL VDD See Note 3 SPFD5408B © ORISE Technology Co., Ltd. Proprietary & Confidential 60 GND OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B (b) VCI1=VCIOUT: VREG1OUT Amplifier 1 (VDH adjustment) VciOUT VCIOUT AMP VGH VGL REGP Source driver VcomR Vci1 C11- Gate driver VcomH Adjustment circuit G1-320 S1-720 Grayscale voltage generating circuit C11+ VLOUT1 DDVDH C12- VcomH output AMP C12+ C21- VcomH Vcom C21+ C22- Vcom amplitude adjustment VcomL output AMP VcomL See Note 3 C22+ C23C23+ VCC VLOUT2 GND VGH VCILVL VCI VLOUT3 AGND VGL IOVCC IOGND VCL VDD See Note 3 SPFD5408B © ORISE Technology Co., Ltd. Proprietary & Confidential 61 GND OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B VLOUT2 VGH (+10 ~ +20V) BT VLOUT1 DDVDH (4.5~6V) VREG1OUT Vci (2.5 ~ 3.3V) VC Vcc (2.4V ~ 3.3V ) Vci1 VREG1OUT (4.0 ~ (DDVDH-0.5)V) VCM/VcomR VRH VcomH (3.0~(DDVDH-0.5)V) VDV IOVcc (1.65 ~ 3.3V) GND (0V) VcomL ((VCL+0.5) ~ 0V) VCOMG VCL (-1.9~ -3.0)V BT VLOUT3 © ORISE Technology Co., Ltd. Proprietary & Confidential VGL (-4.5 ~ - 13.5V) 62 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 11. Application circuits: SPFD5408B ( Bump Up) 19 5 200 205 210 S714 21 5 220 S716 S718 S720 G2 G6 S715 S717 S719 DUMMY22 DUMMY21 G4 G8 225 230 23 5 G310 G314 G318 DUMMY20 G312 G316 G320 240 24 3 63 190 Proprietary & Confidential 185 m h o 5 < © ORISE Technology Co., Ltd. 180 m h o 5 < C22P 175 m h o 5 < 1uF C22N 170 m h o 5 < 1uF C21P 165 m h o 5 < C13P C21N 160 m h o 5 < 1uF C13N 155 m h o 5 < 1uF VGH 150 m h o 5 < VCI GND 145 m h o 5 < GND GND 140 m h o 5 < VGL 1uF GND 13 5 m h o 5 < 1uF C11P 130 m h o 5 < 1uF C12P C11N 12 5 m h o 5 < C12N 120 m h o 5 < VCI 1uF FPC GND 11 5 m h o 5 1 < VCI1 1uF GND 110 m h o 0 1 < DDVDH 1uF GND 10 5 m h o 0 1 < 1uF VCL 10 0 m h o 0 1 < 1uF GND 95 VCOML VREG1OUT GND 9 0 1uF m h o 5 < 1uF GND VCOMH 8 5 m h o 5 < GND 80 m h o 5 < VCOM 7 5 m h o 5 < AGND 7 0 m h o 5 < RGND GND GND GND GND VGS VGS RGND RGND RGND RGND RGND AGND AGND AGND AGND AGND DUMMY4 DUMMY5 DUMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VREG1OUT VREG1OUT VREG1OUT DUMMY7 DUMMY8 DUMMY9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI DUMMY10 DUMMY11 C12N C12N C12N C12N C12N C12P C12P C12P C12P C12P C11N C11N C11N C11N C11N C11P C11P C11P C11P C11P VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VGH VGH VGH DUMMY12 DUMMY13 C13N C13N C13N C13N C13P C13P C13P C13P C21N C21N C21N C21N C21N C21N C21N C21P C21P C21P C21P C21P C21P C21P C22N C22N C22N C22N C22N C22N C22N C22P C22P C22P C22P C22P C22P C22P DUMMY14 DUMMY15 6 5 m h o 5 < VGS 6 0 m h o 5 < GND 5 5 VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 GND GND GND GND G7 G3 DUMMY26 DUMMY25 S2 S4 S6 5 0 VDDD m h o 5 < 1uF GND S1 S3 S5 S7 4 5 m h o 5 < IOVCC G9 G5 G1 40 m h o 0 0 1 < 1uF GND 3 5 m m m mmm h o ho h o ho ho h o 0 00 0 0 00 00 0 0 0 1 1 1 1 11 < < < <<< FMARK 30 mm ho h o 00 0 0 1 1 << SDO SDI RD WR_SCL RS CS 2 5 m m m mmm h o ho h o ho ho h o 0 00 0 0 00 00 0 0 0 1 1 1 1 11 < < < <<< DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 20 m m m mm ho ho h o ho h o 0 00 0 0 00 0 0 0 1 1 1 1 1 < < < << DB12 DB11 DB10 DB9 DB8 15 m m m m m m m m mm h o h o ho ho h o ho ho h o ho h o 0 0 0 00 00 0 0 00 00 0 0 00 0 0 0 1 1 11 1 1 11 11 < < < < < < < < << RESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 1 0 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 RESET RESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 SDO SDI RD WR_SCL RS CS TESTO14 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VDDD VDDD VDDD VDDD VDDD DUMMY27 G319 G317 G315 G313 5 m mm m h o hh h o o 0 0o 0 0 0 0 0 0 1 1 1 1 < << < DUMMY1 TEST1 IOGNDDUM VPP2 TESTO2 TESTO3 IM0_ID IM1 IM2 IM3 TEST2 TESTO4 1 m h o 5 1 < VPP2 IM0/ID IM1 IM2 IM3 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 12. Initial Code: Step Register Address Register Value 1 R00h 2 R01h TBD TBD 3 R02h TBD 4 R03h TBD 5 R04h TBD 6 R08h TBD 7 R09h TBD 8 R0Ah TBD 9 R0Ch TBD 10 R0Dh TBD 11 R0Fh TBD 12 R07h TBD 13 R10h TBD 14 R11h TBD 15 R17h TBD 16 R12h TBD 17 R13h TBD 18 R29h TBD 19 R2Ah TBD 20 R50h TBD 21 R51h TBD 22 R52h TBD 23 R53h TBD 24 R60h TBD 25 R61h TBD 26 R6Ah TBD 27 R80h TBD 28 R81h TBD 29 R82h TBD 30 R83h TBD 31 R84h TBD 32 R85h TBD 33 R90h TBD 34 R92h TBD 35 R93h TBD 36 R95h TBD 37 R97h TBD 38 TBD 39 R98h RF0h 40 RF3h TBD 41 RF4h TBD 42 RF0h TBD 43 R07h TBD Note TBD Note: This initial code is not including Gamma setting. Please contact Orise Technology for desired Gamma setting. © ORISE Technology Co., Ltd. Proprietary & Confidential 64 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 13. Power On/Off Sequence 13.1. Power On/Off Sequence Diagram Power supply (Vcc, Vci, IOVcc) ON DTE=1, D1=1 Normal display Vci IOVcc Vcc Display OFF sequence 2frame or more Vcc Æ IOVcc Æ Vci or Vcc, IOVcc, Vci simultaneously Power supply OFF setting DET=0, D1=0 Power supply user setting R10h: AP=2’h0, SAP=0 LCD Power supply OFF sequence 1frame or more Power ON reset 2ms or more Power supply Halt setting R10h: APE = 0 Transfer synchronization RS=0, DB=16’h0000 RS=0, DB=16’h0000 RS=0, DB=16’h0000 RS=0, DB=16’h0000 User setting (1) NL, BP, FP, Gamma Setting, others LCD Power supply ON sequence Power supply Startup time (8 frames x 1/OSC) Power supply (Vcc, Vci, IOVcc) OFF Vci IOVcc Vcc Initial instruction setting Vci Æ IOVcc Æ Vcc or Vcc, IOVcc, Vci simultaneously Power supply user setting R10h: APE=1, AP, BT, SAP=1 R11h: VC, DC0, DC1 R12h: VRH, VCMR=1 R13h: VDV R29h: VCM1 Other mode setting instruction Display ON sequence © ORISE Technology Co., Ltd. Proprietary & Confidential 65 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 13.2. Display On/Off Sequence: Display ON sequence Display OFF sequence Display OFF LCD Power supply ON Sequence *Note1 R07h: 16’h0000 (BASEE=0, DTE=0, D1=0) Display ON R07h: 16’h0112 LCD Power supply OFF Sequence *Note1 (BASEE=1, DTE=1, D1=1) Display ON Display OFF *Note1: See power supply ON/OFF setting sequence © ORISE Technology Co., Ltd. Proprietary & Confidential 66 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 13.3. Sequence to exit sleep mode: © ORISE Technology Co., Ltd. Proprietary & Confidential 67 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 14. Electrical Characteristics: 14.1. Absolute Maximum Ratings: Table 14-1 Item Symbol Unit Value Note Power Supply Voltage1 VCC,IOVCC V -0.3 ～+4.6 Power Supply Voltage 2 VCI – AGND V -0.3 ～+4.6 Power Supply Voltage 3 DDVDH – AGND V -0.3 ～+6.5 Power Supply Voltage4 AGND – VCL V -0.3 ～+4.6 Power Supply Voltage 5 DDVDH – VCL V -0.3 ～+9.0 Power Supply Voltage7 AGND – VGL V -0.3 ～+14.0 Power Supply Voltage 8 VGH– VGL V -0.3 ～+30.0 Input Voltage Vt V -0.3 ～IOVCC + 0.3 Operating Temperature Topr ℃ -40 ～+85 Storage Temperature Tstg ℃ -55 ～+110 14.2. DC Characteristics VCC= 2.50V～3.30V，IOVCC=1.65V～ 3.30V，Ta=-40℃～+85℃ Table 14-2 Item Symbol Unit Test Condition Min. Typ. Max. Input High level voltage VIH V IOVCC=1.65V～3.30V 0.8xIOVCC - IOVCC Input Low level voltage VIL V IOVCC=1.65V～3.30V -0.3 - 0.2xIOVCC Output ”High” level voltage 1 （DB0-17） VOH V IOVCC=1.65V～3.30V， IOH=-0.1mA 0.8xIOVCC - - Output ”Low” level voltage 1 （DB0-17） VOL V IOVCC=1.65V～3.30V， IOL=0.1mA - - 0.2xIOVCC I/O leak current ILI µA Vin=0～IOVCC -1 - 1 µA fosc= tdb kHz (320line drive), IOVCC=VCC=3.00V fFLM= tbd Hz Ta=25℃ RAM data: 18’h000000 - TBD - µA fosc= tbd kHz (64-line, partial display), IOVCC=VCC=3.00V， fFLM= tbd Hz Ta=25℃ RAM data: 18h’000000 - TBD - Current Consumption (IOVCC-IOGND)+(VCC-GND) Normal operation mode (262k-colors, display operation) Current Consumption (IOVCC-IOGND)+(VCC-GND) 8-color mode, 64-line, partial display operation © ORISE Technology Co., Ltd. Proprietary & Confidential IOP1 Iop2 68 Note OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 14.3. AC Characteristics VCC= 2.50V～3.30V，IOVCC=1.65V～3.30V，Ta=-40℃～+85℃ 14.3.1. Clock Characteristics Table 14-3 Item Symbol Unit fosc kHz RC Oscillation clock Timing Diagram Min. IOVCC = VCC = 3.0V, 25°C Typ. Max. Note TBD 9 14.3.2. 80-System Bus Interface Timing Characteristics (18-/ 16- bit interface) Table 14-4 Normal write operation (HWM=0 or 1), IOVCC=1.65V~3.30V Item Symbol Unit Min. Typ. Max. Write tCYCW ns 125 - - Read tCYCR ns 450 - - Write low-level pulse width PWLW ns 45 - - Read low-level pulse width PWLR ns 170 - - Write high-level pulse width PWHW ns 70 - - Read high-level pulse width PWHR ns 250 - - Write/Read rise/ fall time tWRr， WRf ns - - 25 ns 0 - - ns 10 - - Bus cycle time Write (RS to CS*,WR*) Setup time tAS Read (RS to CS*, RD*) Address Hold Time tAH ns 2 - - Write data setup time tDSW ns 25 - - Write data hold time tH ns 10 - - Read data delay time tDDR ns - - 150 Read data hold time tDHR ns 5 - - © ORISE Technology Co., Ltd. Proprietary & Confidential 69 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B Figure 14-1 80-System Bus Interface RESET* VIH VIL VIL Figure 14-2 Reset Operation © ORISE Technology Co., Ltd. Proprietary & Confidential 70 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 14.3.3. Clock-synchronized Serial Interface Timing Characteristics Normal Write Function (HWM=0), High-speed Write Function (HWM=1), IOVCC=1.65~3.30V) Table 14-5 Item Symbol Serial Time Clock Cycle Unit Min. Typ. Max. Write (received) tSCYC ns 100 - 20.000 Read (transmitted) tSCYC ns 350 - 20.000 Write (received) tSCH ns 40 - - Read (transmitted) tSCH ns 150 - - Write (received) tSCL ns 40 - - Read (transmitted) tSCL ns 150 - - Serial clock rise/fall time tSCr，tSCf ns - - 20 Chip select setup time tCSU ns 20 - - Chip select hold time tCH ns 60 - - Serial input data setup time tSISU ns 30 - - Serial input data hold time tSIH ns 30 - - Serial Clock high-level width Serial Clock low-level width Serial output data delay time Serial output data hold time tSOD tSOH ns - - 130 ns 5 - - Max. 14.3.4. Reset Timing Characteristics (IOVCC=1.65~3.30V) Table 14-6 Item Symbol Unit Min. Typ. Reset low-level width tRES ms 1 － － － 10 Reset rise time © ORISE Technology Co., Ltd. Proprietary & Confidential trRES µs 71 － OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 14.3.5. RGB Interface Timing Characteristics 18-/ 16- bit RGB interface (HWM=0 or 1), IOVCC=1.65~3.30V Table 14-7 Item Symbol Unit Min. Typ. Max. VSYNC/HSYNC Setup time TSYNCS clock 0 - 1 ENABLE Setup time TENS ns 10 - - ENABLE Hold time TENH ns 20 - - DOTCLK low-level pulse width PWDL ns 40 - - DOTCLK high-level pulse width PWDH ns 40 - - DOTCLK cycle time TCYCD ns 100 - - Data setup time TPDS ns 10 - - Data hold time TPDH ns 40 - - DOTCLK, VSYNC and HSYNC rise/fall time Trgbr Trgbf ns - - 25 Item Symbol Unit Min. Typ. Max. VSYNC/HSYNC setup time TSYNCS clock 0 - 1 ENABLE setup time TENS ns 10 - - ENABLE hold time TENH ns 25 - - DOTCLK low-level pulse width PWDL ns 25 - - DOTCLK high-level pulse width PWDH ns 25 - - DOTCLK cycle time TCYCD ns 60 - - Data setup-time TPDS ns 10 - - Data hold time TPDH ns 25 - - DOTCLK, VSYNC, and HSYNC rise/fall time Trgb Ttrgbf ns - - 25 6-bit RGB interface (HWM=0 or 1), IOVCC=1.65~3.30V Table 14-8 © ORISE Technology Co., Ltd. Proprietary & Confidential 72 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 15. CHIP INFORMATION 15.1. PAD Assignment TBD. 15.2. PAD Dimension Item Size PAD No. Unit X Chip Size - Chip thickness - Pad pitch Bumped pad size Y 17770 ± 25 815 ± 25 300 ± 25 1~243 70 - 244~1291 16 117 1~243 50 80 244~1291 14.4 98 µm Note1: Chip size included scribe line. 15.3. Bump Dimension 15.3.1. Output Pads 15.3.2. Input Pads 15.4. Bump Characteristics Item Standard Note Bump Hardness 75Hv ± 25Hv Bump Height 15µm ± 3µm Co-planarity (in Chip) R≦ 2µm R : Max-Min Roughness (in Bump) R≦ 2µm R : Max-Min Bump Size “X” ± 3µm x “Y” ± 3µm X/Y: bump size Shear Force >4.5g/mil^2 © ORISE Technology Co., Ltd. Proprietary & Confidential 73 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 15.5. PAD Locations No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 DUMMY1 TEST1 IOGNDDUM VPP2 TESTO2 TESTO3 IM0_ID IM1 IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 RESET RESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 SDO SDI RD WR_SCL RS CS TESTO14 -8610 -8540 -8470 -8400 -8330 -8260 -8190 -8120 -8050 -7980 -7910 -7840 -7770 -7700 -7630 -7560 -7490 -7420 -7350 -7280 -7210 -7140 -7070 -7000 -6905 -6825 -6745 -6665 -6585 -6495 -6405 -6325 -6245 -6165 -6085 -5990 -5920 -5825 -5745 -5665 -5585 -5505 -5425 -5345 -5265 -5180 -5110 -5040 -4970 -4900 -4830 -4760 -4690 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 GND GND GND GND GND GND GND GND VGS VGS RGND RGND RGND RGND RGND AGND AGND AGND AGND AGND DUMMY4 DUMMY5 -4620 -4550 -4480 -4410 -4340 -4270 -4200 -4130 -4060 -3990 -3920 -3850 -3780 -3710 -3640 -3570 -3500 -3430 -3360 -3290 -3220 -3150 -3080 -3010 -2940 -2870 -2800 -2730 -2660 -2590 -2520 -2450 -2380 -2310 -2240 -2170 -2100 -2030 -1960 -1890 -1820 -1750 -1680 -1610 -1540 -1470 -1400 -1330 -1260 -1190 -1120 -1050 -980 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 DUMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VREG1OUT VREG1OUT VREG1OUT DUMMY7 DUMMY8 DUMMY9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 2030 2100 2170 2240 2310 2380 2450 2520 2590 2660 2730 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 74 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 VCI VCI VCI DUMMY10 DUMMY11 C12N C12N C12N C12N C12N C12P C12P C12P C12P C12P C11N C11N C11N C11N C11N C11P C11P C11P C11P C11P VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VGH VGH VGH DUMMY12 DUMMY13 C13N C13N C13N C13N C13P C13P C13P C13P C21N 2800 2870 2940 3010 3080 3150 3220 3290 3360 3430 3500 3570 3640 3710 3780 3850 3920 3990 4060 4130 4200 4270 4340 4410 4480 4550 4620 4690 4760 4830 4900 4970 5040 5110 5180 5250 5320 5390 5460 5530 5600 5670 5740 5810 5880 5950 6020 6090 6160 6230 6300 6370 6440 6510 6580 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 C21N C21N C21N C21N C21N C21N C21P C21P C21P C21P C21P C21P C21P C22N C22N C22N C22N C22N C22N C22N C22P C22P C22P C22P C22P C22P C22P DUMMY14 DUMMY15 DUMMY20 G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300 G298 G296 G294 G292 G290 G288 G286 G284 G282 G280 G278 G276 G274 G272 6650 6720 6790 6860 6930 7000 7070 7140 7210 7280 7350 7420 7490 7560 7630 7700 7770 7840 7910 7980 8050 8120 8190 8260 8330 8400 8470 8540 8610 8659 8643 8627 8611 8595 8579 8563 8547 8531 8515 8499 8483 8467 8451 8435 8419 8403 8387 8371 8355 8339 8323 8307 8291 8275 8259 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 G170 G168 G166 G164 G162 8243 8227 8211 8195 8179 8163 8147 8131 8115 8099 8083 8067 8051 8035 8019 8003 7987 7971 7955 7939 7923 7907 7891 7875 7859 7843 7827 7811 7795 7779 7763 7747 7731 7715 7699 7683 7667 7651 7635 7619 7603 7587 7571 7555 7539 7523 7507 7491 7475 7459 7443 7427 7411 7395 7379 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 75 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 7363 7347 7331 7315 7299 7283 7267 7251 7235 7219 7203 7187 7171 7155 7139 7123 7107 7091 7075 7059 7043 7027 7011 6995 6979 6963 6947 6931 6915 6899 6883 6867 6851 6835 6819 6803 6787 6771 6755 6739 6723 6707 6691 6675 6659 6643 6627 6611 6595 6579 6563 6547 6531 6515 6499 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 DUMMY21 DUMMY22 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 6483 6467 6451 6435 6419 6403 6387 6371 6355 6339 6323 6307 6291 6275 6259 6243 6227 6211 6195 6179 6163 6147 6131 6115 6099 6083 6047 6031 6015 5999 5983 5967 5951 5935 5919 5903 5887 5871 5855 5839 5823 5807 5791 5775 5759 5743 5727 5711 5695 5679 5663 5647 5631 5615 5599 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 S692 S691 S690 S689 S688 S687 S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 S651 S650 S649 S648 S647 S646 S645 S644 S643 S642 S641 S640 S639 S638 5583 5567 5551 5535 5519 5503 5487 5471 5455 5439 5423 5407 5391 5375 5359 5343 5327 5311 5295 5279 5263 5247 5231 5215 5199 5183 5167 5151 5135 5119 5103 5087 5071 5055 5039 5023 5007 4991 4975 4959 4943 4927 4911 4895 4879 4863 4847 4831 4815 4799 4783 4767 4751 4735 4719 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 76 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 S637 S636 S635 S634 S633 S632 S631 S630 S629 S628 S627 S626 S625 S624 S623 S622 S621 S620 S619 S618 S617 S616 S615 S614 S613 S612 S611 S610 S609 S608 S607 S606 S605 S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587 S586 S585 S584 S583 4703 4687 4671 4655 4639 4623 4607 4591 4575 4559 4543 4527 4511 4495 4479 4463 4447 4431 4415 4399 4383 4367 4351 4335 4319 4303 4287 4271 4255 4239 4223 4207 4191 4175 4159 4143 4127 4111 4095 4079 4063 4047 4031 4015 3999 3983 3967 3951 3935 3919 3903 3887 3871 3855 3839 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 S536 S535 S534 S533 S532 S531 S530 S529 S528 3823 3807 3791 3775 3759 3743 3727 3711 3695 3679 3663 3647 3631 3615 3599 3583 3567 3551 3535 3519 3503 3487 3471 3455 3439 3423 3407 3391 3375 3359 3343 3327 3311 3295 3279 3263 3247 3231 3215 3199 3183 3167 3151 3135 3119 3103 3087 3071 3055 3039 3023 3007 2991 2975 2959 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 2943 2927 2911 2895 2879 2863 2847 2831 2815 2799 2783 2767 2751 2735 2719 2703 2687 2671 2655 2639 2623 2607 2591 2575 2559 2543 2527 2511 2495 2479 2463 2447 2431 2415 2399 2383 2367 2351 2335 2319 2303 2287 2271 2255 2239 2223 2207 2191 2175 2159 2143 2127 2111 2095 2079 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 77 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 2063 2047 2031 2015 1999 1983 1967 1951 1935 1919 1903 1887 1871 1855 1839 1823 1807 1791 1775 1759 1743 1727 1711 1695 1679 1663 1647 1631 1615 1599 1583 1567 1551 1535 1519 1503 1487 1471 1455 1439 1423 1407 1391 1375 1359 1343 1327 1311 1295 1279 1263 1247 1231 1215 1199 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 1183 1167 1151 1135 1119 1103 1087 1071 1055 1039 1023 1007 991 975 959 943 927 911 895 879 863 847 831 815 799 783 767 751 735 719 703 687 671 655 639 623 607 591 575 559 543 527 511 495 479 463 447 431 415 399 383 367 351 335 319 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 S362 S361 DUMMY23 DUMMY24 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 303 287 271 -271 -287 -303 -319 -335 -351 -367 -383 -399 -415 -431 -447 -463 -479 -495 -511 -527 -543 -559 -575 -591 -607 -623 -639 -655 -671 -687 -703 -719 -735 -751 -767 -783 -799 -815 -831 -847 -863 -879 -895 -911 -927 -943 -959 -975 -991 -1007 -1023 -1039 -1055 -1071 -1087 202.5 319.5 202.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 78 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 -1103 -1119 -1135 -1151 -1167 -1183 -1199 -1215 -1231 -1247 -1263 -1279 -1295 -1311 -1327 -1343 -1359 -1375 -1391 -1407 -1423 -1439 -1455 -1471 -1487 -1503 -1519 -1535 -1551 -1567 -1583 -1599 -1615 -1631 -1647 -1663 -1679 -1695 -1711 -1727 -1743 -1759 -1775 -1791 -1807 -1823 -1839 -1855 -1871 -1887 -1903 -1919 -1935 -1951 -1967 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 -1983 -1999 -2015 -2031 -2047 -2063 -2079 -2095 -2111 -2127 -2143 -2159 -2175 -2191 -2207 -2223 -2239 -2255 -2271 -2287 -2303 -2319 -2335 -2351 -2367 -2383 -2399 -2415 -2431 -2447 -2463 -2479 -2495 -2511 -2527 -2543 -2559 -2575 -2591 -2607 -2623 -2639 -2655 -2671 -2687 -2703 -2719 -2735 -2751 -2767 -2783 -2799 -2815 -2831 -2847 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 -2863 -2879 -2895 -2911 -2927 -2943 -2959 -2975 -2991 -3007 -3023 -3039 -3055 -3071 -3087 -3103 -3119 -3135 -3151 -3167 -3183 -3199 -3215 -3231 -3247 -3263 -3279 -3295 -3311 -3327 -3343 -3359 -3375 -3391 -3407 -3423 -3439 -3455 -3471 -3487 -3503 -3519 -3535 -3551 -3567 -3583 -3599 -3615 -3631 -3647 -3663 -3679 -3695 -3711 -3727 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 79 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 -3743 -3759 -3775 -3791 -3807 -3823 -3839 -3855 -3871 -3887 -3903 -3919 -3935 -3951 -3967 -3983 -3999 -4015 -4031 -4047 -4063 -4079 -4095 -4111 -4127 -4143 -4159 -4175 -4191 -4207 -4223 -4239 -4255 -4271 -4287 -4303 -4319 -4335 -4351 -4367 -4383 -4399 -4415 -4431 -4447 -4463 -4479 -4495 -4511 -4527 -4543 -4559 -4575 -4591 -4607 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 -4623 -4639 -4655 -4671 -4687 -4703 -4719 -4735 -4751 -4767 -4783 -4799 -4815 -4831 -4847 -4863 -4879 -4895 -4911 -4927 -4943 -4959 -4975 -4991 -5007 -5023 -5039 -5055 -5071 -5087 -5103 -5119 -5135 -5151 -5167 -5183 -5199 -5215 -5231 -5247 -5263 -5279 -5295 -5311 -5327 -5343 -5359 -5375 -5391 -5407 -5423 -5439 -5455 -5471 -5487 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY25 DUMMY26 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 -5503 -5519 -5535 -5551 -5567 -5583 -5599 -5615 -5631 -5647 -5663 -5679 -5695 -5711 -5727 -5743 -5759 -5775 -5791 -5807 -5823 -5839 -5855 -5871 -5887 -5903 -5919 -5935 -5951 -5967 -5983 -5999 -6015 -6031 -6047 -6083 -6099 -6115 -6131 -6147 -6163 -6179 -6195 -6211 -6227 -6243 -6259 -6275 -6291 -6307 -6323 -6339 -6355 -6371 -6387 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 80 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B No. Pad Name X Y No. Pad Name X Y No. Pad Name X Y 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 -6403 -6419 -6435 -6451 -6467 -6483 -6499 -6515 -6531 -6547 -6563 -6579 -6595 -6611 -6627 -6643 -6659 -6675 -6691 -6707 -6723 -6739 -6755 -6771 -6787 -6803 -6819 -6835 -6851 -6867 -6883 -6899 -6915 -6931 -6947 -6963 -6979 -6995 -7011 -7027 -7043 -7059 -7075 -7091 -7107 -7123 -7139 -7155 -7171 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193 G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 -7187 -7203 -7219 -7235 -7251 -7267 -7283 -7299 -7315 -7331 -7347 -7363 -7379 -7395 -7411 -7427 -7443 -7459 -7475 -7491 -7507 -7523 -7539 -7555 -7571 -7587 -7603 -7619 -7635 -7651 -7667 -7683 -7699 -7715 -7731 -7747 -7763 -7779 -7795 -7811 -7827 -7843 -7859 -7875 -7891 -7907 -7923 -7939 -7955 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 G235 G237 G239 G241 G243 G245 G247 G249 G251 G253 G255 G257 G259 G261 G263 G265 G267 G269 G271 G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 DUMMY27 -7971 -7987 -8003 -8019 -8035 -8051 -8067 -8083 -8099 -8115 -8131 -8147 -8163 -8179 -8195 -8211 -8227 -8243 -8259 -8275 -8291 -8307 -8323 -8339 -8355 -8371 -8387 -8403 -8419 -8435 -8451 -8467 -8483 -8499 -8515 -8531 -8547 -8563 -8579 -8595 -8611 -8627 -8643 -8659 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 © ORISE Technology Co., Ltd. Proprietary & Confidential 81 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 15.6. Alignment Mark --Alignment Mark coordinate Left (-8751, 269) Right (8751, 269) --Alignment Mark size © ORISE Technology Co., Ltd. Proprietary & Confidential 82 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. normal commercial applications. FURTHERMORE, ORISE Technology MAKES ORISE Technology reserves the right to halt Products described herein are intended for use in Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © ORISE Technology Co., Ltd. Proprietary & Confidential 83 OCT. 29, 2007 Preliminary Version: 0.1 Preliminary SPFD5408B 16. REVISION HISTORY Date Revision # OCT. 29, 2007 0.1 © ORISE Technology Co., Ltd. Proprietary & Confidential Description Original version Page 84 84 OCT. 29, 2007 Preliminary Version: 0.1