NT39016 D One Chip TFT LCD Driver IC with Timing Controller For S960xG240 TFT LCD V0.7 Preliminary Spec. 1 Preliminary Spec. for NT39016D TFT LCD Driver Revise History Version 0.7 0.6 0.5 0.4 NT39016 Specification Revision History Content Modify DC Electrical Characteristics Modify pin description Remove CPMPDB function Modify Analog Supply Voltage Modify 3-Wire Control Register Modify STBYB initial value 0.3 Modify Digital Operating Current value Modify Analog Operating Current value 0.2 0.1 Source Driver Output Timing Diagram New Spec. Mar 10,2008 2 Page 29 28 8 14 29 12 14 28 29 33 -- 、 Date 2008/3/10 2008/2/18 2008/2/4 2008/1/14 2007/11/26 2007/11/16 2007/10/22 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Index Revise History ................................................................................................................................................... 2 Index ................................................................................................................................................................. 3 Features ............................................................................................................................................................ 4 General Description ........................................................................................................................................... 4 Function Block Diagram ..................................................................................................................................... 5 System Block Diagram................................................................................................................................ 5 Charge Pump Circuit Block Diagram ........................................................................................................... 6 Pad Sequence (Bump Side)............................................................................................................................... 7 Pad Description ................................................................................................................................................. 8 3-Wire Serial Port Interface (Default Register Map) .......................................................................................... 11 3-Wire Command Format.......................................................................................................................... 11 3-Wire Control Registers (Default)............................................................................................................. 12 3-Wire Registers Function Description ...................................................................................................... 14 Function Description ........................................................................................................................................ 23 Power On/Off Sequence ........................................................................................................................... 23 External Reset (RSTB).............................................................................................................................. 23 Input Data VS Output Voltage ................................................................................................................... 24 Input Data and Output Voltage Reference Table (VSET = “0”)................................................................... 25 Data Input Format ............................................................................................................................................ 26 1. RGB input Data format .......................................................................................................................... 26 2. YUV input Data format .......................................................................................................................... 26 3. CCIR_656 Mode Data format ................................................................................................................ 26 4. Data Active Area ................................................................................................................................... 26 5. YUV_601/656 to RGB conversion ......................................................................................................... 27 6. Brightness / Contrast Adjustment .......................................................................................................... 27 Absolute Maximum Ratings.............................................................................................................................. 28 DC Electrical Characteristics ............................................................................................................................ 28 AC Electrical Characteristics ............................................................................................................................ 30 Timing Table.................................................................................................................................................... 31 CCIR601 Mode A/B * ................................................................................................................................ 31 CCIR656 Mode A/B * ................................................................................................................................ 31 8 Bit RGB 960 CH Mode ........................................................................................................................... 31 24 Bit RGB Mode (@ SEL[3:0] = 1100 or 1101) ........................................................................................ 31 Timing Diagram ............................................................................................................................................... 32 Clock and Data Input Timing Diagram ....................................................................................................... 32 3-Wire Timing Diagram ............................................................................................................................. 32 Source Driver Output Timing Diagram....................................................................................................... 33 Gate Driver Output Timing Diagram .......................................................................................................... 33 Vertical Timing Diagram (HV Mode) .......................................................................................................... 34 Vertical Timing Diagram (DE Mode) .......................................................................................................... 34 Input Data Timing (24 bit RGB mode for 960 x 240 @ SEL[3:0] = 1100b) .................................................. 39 Pad Location.................................................................................................................................................... 36 Alignment Mark................................................................................................................................................ 37 Pad Information ............................................................................................................................................... 37 Application Notes............................................................................................................................................. 38 PWM for LED Backlight Control ................................................................................................................ 38 Appendix A: Pad Coordinate ............................................................................................................................ 39 Mar 10,2008 3 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Features One-Chip solution for 960 x 240 dot TFT LCD Driver 8-bit resolution 256 gray scale with Dithering Support 8-bit / 24-bit digital (RGB) or CCIR_601/656 input timing Support two sets of 3-Wire commands for internal parameters setting Build-In DC2DC power supplies (VGH/VGL/VCOMAC/VCOMDC voltage supply) Configurable color filter type for both Delta and Stripe type 3.0 ~ 3.6V digital supply voltage with Build-In 1.8V LDO for internal circuit 3.0 ~ 3.6V charge pump supply voltage Configurable VCOMAC : 4.6V~6.1V Configurable VCOMDC : 1.0V~2.26V Source output deviation: 20mV(max) Source output settling time: 30uS(max) Operating frequency: 30MHz(max) Right/Left shift, Up and Down scan function selectable Support VCOM swing driving output Support Cs on Common structure Build-In PWM circuit for LED Back-light Support stand-by mode for low power consumption Frame / One Line / Two Line Inversion driving method selectable Built-in Auto Test Pattern COG package General Description NT39016 is a single-chip solution for 960x240 dot color TFT-LCD panel, which integrated source driver, gate driver, timing controller, power generator and 3-wire interface for system function control. With highly integration technology, NT39016 integrate 960 channels source driver and 240 channels gate driver on single silicon. Data Input support 8 bit digital image data with standard CCIR601/656, serial 8-bit RGB data format or parallel 24-bit RGB data format. Source outputs support 8-bit resolution (256 gray scales) with dithering function on. Custom parameters can be set by using 3-wire commands. Special circuit architecture is designed for system lower power dissipation. NT39016 is designed for wide voltage supply range and small output deviation for better display quality. Power dissipation for internal 5 sections reference voltage resistors for 64-level gamma resistors are also concerned. Supporting multiple input timings make this chip more suitable to various applications of small size TFT-LCD panel. Mar 10,2008 4 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Function Block Diagram System Block Diagram Mar 10,2008 5 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Charge Pump Circuit Block Diagram NT39016 built in charge pump circuit for gate driver VGH / VGL voltage and panel VCOMAC/VCOMDC voltage. Following block diagram illustrate how the charge pump circuit works. <Value of wiring resistance and Cap.> Pin name C1P C1M C2P C2M C3P C3M C4P C4M C1AP C1AM Resistor of wiring (ohm) Cap no. < 10 C1 < 10 < 10 C2 < 10 < 10 C3 < 10 < 10 C4 < 10 < 10 C1A < 10 *Note: Others Cap. Suggest value > 4.7 uF CAP (uF) >1uF Schottky diode turn-on voltage=0.2V Mar 10,2008 6 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Pad Sequence (Bump Side) Mar 10,2008 7 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Pad Description NT39016 Pad Description: Designation I/O DIN[23..0] I CLKIN I HSD VSD I I I (Pull Low) DEN DATSEQ O POL O V1 ~ V7 I/O SPENB SPDA SPCK SPSW RSTB I (Pull High) I/O I I (Pull Low) I (Pull High) PINCTLB I (Pull High) SO1~SO960 GO1~GO240 ALIGN_T/B O O M TP15 I TP0~14 TP16~18 T I VPSW I (Pull Low) Mar 10,2008 Description Data Input. For 8/24-bit digital (RGB) or 8-bit CCIR601/656 image data input 8-bit mode: DIN7: MSB; DIN0: LSB; the remainder should be connect to GND. 24-bit mode: DIN[7:0] = R[7:0] data; DIN[15:8] = G[7:0] data; DIN[23:16] = B[7:0] data. For 18bit RGB interface, connect two LSB bits of all the R/G/B data bus to GND. Clock for Input Data. Data latched at rising/falling edge of this signal. Default Negative polarity. Horizontal Sync input. Default Negative polarity, can be change by HSDPOL register. Vertical Sync input. Default Negative polarity, can be change by VSDPOL register. Data Input Enable. Active High to enable the data input Bus under “DE Mode”. Normally pull low. Data sequence control pin for external T-CON. Output “1”: for Odd line, “0”: for Even line Frame polarity output. Amplitude of signal is from 0V to 3.3V. Gamma correction reference voltage. When VSET=”1” is used. The voltage of pins V1 ~ V7 must be swing and must be AVDD-0.1V > V1 > V2 > V3 V5 > V6 > V7 > AGND+0.1V when POL=”1” and AGND+0.1V < V1’ < V2’ < V3’ V5’ < V6’ < V7’ < AVDD-0.1V when POL=”0”, Where V1-V2=V2’-V1’, V2-V3=V3’-V2’, …V5-V6=V6’-V5’, V6-V7=V7’-V6’. Note: V1~V7 must be supplied voltage external when VSET=”1”. Vx is external power of positive polarity and Vx’ is external power of negative polarity 3-Wire Communication Enable. Active Low. Normally pull high. Please pull high or floating under PINCTLB=0 mode. 3-Wire Communication Data input/output. 3-Wire Communication Clock input. Rising edge latch. 3-Wire register map select. ”0” for default 3-Wire register map, “1” for optional 3-Wire register map. Global reset pin. Active Low to enter Reset State. Suggest connecting with a RC reset circuit for stability. Normally pull high. Enable pin control function. Normally pull high PINCTLB = “0”, Enable pin control function. TP0~14 and TP16~18 active as input pin for function control propose. Refer to the TP0~18 description for more information. PINCTLB = “1”, Default mode. TP0~14 and TP16~18 active as unknown state ; Don’t connect TP0~14 and TP16~18 to any state under this mode. Note: The 3-wire control register will be disabled under PINCTLB = 0 mode. Source Driver Output Signals. Gate Driver Output Signals. For assembly alignment. Charge pump on/off control pin.TP15=CPMPDB CPMPDB = “0”, internal charge pump will be shut down CPMPDB = “1”, internal charge pump normal operating TP15 active as input pin under any state of PINCTLB. If floating TP15,the charge pump will turn off TEST Pin / Function control pin. When PINCTLB = “1”, TP0~14, TP16~18 act as test pin. Floating those pins for normal operation. When PINCTLB = “0”, TP0~14, TP16~18 act as function control input pin. All the input pin should be connect to GND or VDD. Floating those pins will result in input unknown problem. Voltage control switch. Normally pull low. VPSW = “0” .Default mode. VGH VGL VCOMAC and VCOMDC active as normal use and control by 3-wire. VPSW = “1”.Voltage fix mode. VGH = 18V VGL = -7V VCOMAC = 5.4V and VCOMDC 、 、 、 8 、 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver VPP_OTP VGH VGL VCOMAC VCOM P PS PS PS PS VCOMOUT O VDDA GNDA VDD GND VDDP GNDP PO PI PI PI PI PI VCC C C1P/M C1AP/M C2P/M C3P/M C4P/M Vint1/2 FB_P C I = 1.7V. Under the mode voltage can't control by 3-wire Customer OTP power input pin Capacitor pin. Positive power supply for Gate Driver output Capacitor pin. Negative power supply for Gate Driver output Capacitor pin. Power supply for VCOMOUT output VCOM DC voltage output pin for DC re-construction Frame polarity output for panel VCOM. Amplitude of signal is from GNDA1 to VDDA1 The polarity of VCOMOUT is inversed with internal signal “POL” when “FPOL” = 0 Power supply for source driver and gamma circuit Ground pins for source driver and gamma circuit Power supply for digital circuits Ground pins for digital circuits Power supply for charge pump circuits Ground pins for charge pump circuits Capacitor connect pin for internal regulator Refer to the section of “Power Circuit” for the application. Capacitor connect pin for internal charge pump Refer to the section of “Power Circuit” for the application. FB_N O FB DRV COM1_L/R COM2_L/R VI O S S Internal power switch current input pad. Note: Voltage on this pad should be < 5.5V. Pull low in more than one LED case. Internal power switch current output pad. Note: Voltage on this pad should be < 5.5V. Pull low in more than one LED case. PWM controller feedback input. FB threshold is 0.6 V nominal PWM output driver signal for the boost converter The internal link together between input side and Output side. The internal link together between input side and Output side. DUM D Don’t connect to any signal or pull high/low. Note: I: Input, O: Output, P: Power, D: Dummy, S: Shorted line, M: Mark, PI: Power input, PO: Power output, T: Testing I/ O: Input / Output. PS: Power Setting, C: Capacitor pin. NT39016 Align Mark: ALIGN_T ALIGN_B M For assembly alignment. M For assembly alignment. NT39016 Pass Line Description: Pass Line No: 1 2 Mar 10,2008 Pad Name COM1_L COM2_L COM1_R COM2_R 9 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver TP0 ~ TP14 and TP16~TP18 Function Control Pin Mapping Table (When PINCTLB = “0”): TPx PINCTLB = “0” Input control function (Related to 3-wire control register) STBYB UPDN SHLR SEL0 SEL1 SEL2 SEL3 FRAD0 FRAD1 PAL PALM SKIPMOD HDNC0 HDNC1 FPOL PWMPDB AVGY Auto Test Pattern Enable 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 Note 1: PINCTLB function has higher priority then the 3-wire command. The 3-wire control register will be disabled when PINCTLB = “0”. Please pull high or floating SPENB under PINCTLB=0 mode. Remark: TP15=CPMPDB Charge pump on/off control pin. CPMPDB = “0”, internal charge pump will be shut down CPMPDB = “1”, internal charge pump normal operating TP15 active as input pin under any state of PINCTLB. ， Mar 10,2008 10 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver 3-Wire Serial Port Interface (Default Register Map) 3-Wire Command Format NT39016 uses the 3-wire serial port as communication interface for all the function and parameter setting. 3-Wire communication can be bi-directional controlled by the “R/W” bit in address field. NT39016 3-Wire engine act as a “slave mode” for all the time, and will not issue any command to the 3-Wire bus itself. Under read mode, 3-Wire engine will return the data during “Data phase”. The returned data should be latched at the rising edge of SPCK by external controller. Data in the “Hi-Z phase” will be ignored by 3-Wire engine during write operation, and should be ignored during read operation also. During read operation, external controller should float SPDA pin under “Hi-Z phase” and “Data phase”. Refer to the section of “3-Wire Timing Diagram” for the detail timing, please. W Hi-Z / R Address[5:0] SPENB SPDA D15 D14 D13 D12 D11 D10 D9 D8 Data[7:0] D7 D6 D5 D4 D3 Delay D2 D1 D0 Next Transfer D15 SPCK 3-Wire Command Format: Bit D15-D10 D9 D8 D7-D0 Description Register Address [5:0]. W/R control bit. “1” for Write; “0” for Read Hi-Z bit during read mode. Any data within this bits will be ignored during write mode Data for the W/R operation to the address indicated by Address phase 3-Wire Writer Format: MSB D15 D14 D13 D12 D11 Register Address [5:0] D10 D9 1 D8 X D7 D6 D5 D4 D3 D2 D1 DATA (Issue by external controller) D10 D9 0 D8 Hi-Z D7 D6 LSB D0 3-Wire Read Format: MSB D15 D14 D13 D12 D11 Register Address [5:0] Mar 10,2008 11 D5 D4 D3 D2 DATA (Issue by NT39016) D1 LSB D0 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver 3-Wire Control Registers (Default) Following table list the default 3-Wire control registers and bit name definition for NT39016. Refer to the next section for detail register function description, please. NT39016 3-Wire Control Register List (Default) 3-Wire Registers D[15:10] Name 000000b R00 000001b R01 000010b R02 000011b R03 000100b R04 000101b R05 000110b R06 000111b R07 001000b R08 001001b R09 001010b R0A 001011b R0B 001100b R0C 001101b R0D 001110b R0E 001111b R0F 010000b R10 010001b R11 010010b R12 011110b R1E 100000b R20 Mar 10,2008 Init. 07h 00h 03h CCh 46h 0Dh 00h 00h 08h 40h 88h 88h 20h 20h 10h A4h 04h 24h 24h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Description Function Description System control register Timing Controller function register Operation control register Input data Format control register Source Timing delay control register Gate Timing delay control register Reserved Internal function control register RGB Contrast control register RGB Brightness control register Hue / Saturation control register R / B Sub-Contrast control register R Sub-Brightness control register B Sub-Brightness control register VCOMDC Level Control Register VCOMAC Level Control Register VGAM2 level control register VGAM3/4 level control register VGAM5/6 level control register VCOMDC Trim function control register Wide and narrow display mode control register 12 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver NT39016 3-Wire Register Bit Definition (Default) Reg. Bit [7] Bit [6] 3-Wire Control Register Bit Map Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] R00 PAT3 PAT2 PAT1 PAT0 PWMPDB X STBYB R01 X X X SWD2 SWD1 SWD0 DITHB R02 SKIPMOD HDNC1 HDNC0 X FPOL VSET UPDN R03 DENPOL CLKPOL HSDPOL VSDPOL SEL3 SEL2 SEL1 R04 DDLY7 DDLY6 DDLY5 DDLY4 DDLY3 DDLY2 DDLY1 R05 X HDLY6 HDLY5 HDLY4 HDLY3 HDLY2 HDLY1 R06 X X X X X X X R07 FRAD1 FRAD0 INVSL1 INVSL0 PAL PALM R08 X X X CON4 CON3 CON2 CON1 R09 X BRI6 BRI5 BRI4 BRI3 BRI2 BRI1 R0A HUE3 HUE2 HUE1 HUE0 SAT3 SAT2 SAT1 R0B SCONB1 SCONB0 SCONR1 SCONR0 R0C X X SBRIR5 SBRIR4 SBRIR3 SBRIR2 SBRIR1 R0D X X SBRIB5 SBRIB4 SBRIB3 SBRIB2 SBRIB1 R0E X OTP_BYPS VCDCSL5 VCDCSL4 VCDCSL3 VCDCSL2 VCDCSL1 R0F VGLSL1 VGLSL0 VGHSL1 VGHSL0 VCACSL3 VCACSL2 VCACSL1 R10 X X X GAMEN X V2GAM2 V2GAM1 R11 X X V4GAM2 V4GAM1 V4GAM0 V3GAM2 V3GAM1 R12 X X V6GAM2 V6GAM1 V6GAM0 V5GAM2 V5GAM1 R1E TRMEN7 TRMEN6 TRMEN5 TRMEN4 TRMEN3 TRMEN2 TRMEN1 R20 X X X X X X WNSEL1 Note: Register function active at the falling edge of VSD except STBYB, RESETB register bits. Registers require Vsync trigger table DITHB CFTYP SKIPMOD HDNC PAL PALM AVGY CON Mar 10,2008 FPOL BRI VSET HUE UPDN SAT 13 SHLR SCONB DDLY SCONR HDLY SBRIR Bit [0] RESETB CFTYP SHLR SEL0 DDLY0 HDLY0 X AVGY CON0 BRI0 SAT0 SBRIR0 SBRIB0 VCDCSL0 VCACSL0 V2GAM0 V3GAM0 V5GAM0 TRMEN0 WNSEL0 FRAD SBRIB INVSL Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver 3-Wire Registers Function Description R00: System Control Register Bit Name Initial R/W Bit [7:4] PAT[3:0] 0000b R/W Bit [3] PWMPDB 0b (R) R/W Bit [2] - - - Bit [1] STBYB 1b (R) R/W Bit [0] RESETB 1b R/W Description Internal Test Pattern Selection PAT[3:0] : Select chip embedded test pattern. Internal PWM controller Power Down bit PWMPDB = “0”, internal PWM controller will be shut down PWMPDB = “1”, internal PWM controller normal operating Reserve Standby Mode function control. STBYB = “0”, TCON, Source output will turn off and outputs are High-Z. STBYB = “1”, Normal operation Global Reset Register. Write “0” to reset whole chip. This bit will set to “1” automatically after chip was reset. PAT[3:0] : Embedded Auto Test Pattern Selection Register PAT[3:0] 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Test Pattern Disable Internal Test Pattern Function White Black Red Green Blue Yellow Cyan Magenta Gray Level 8 Gray Level 16 Color Bar Checker Board Cross Talk Pattern Horizontal Flick Pattern Test Pattern Auto Run Mode Note Default Note: WNSEL[1:0] will be disabled under Internal Test Pattern mode. Mar 10,2008 14 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver R01: Timing Controller Function Register Bit Name Initial R/W Bit [4:2] SWD[2:0] 000b Bit [1] DITHB 0b Bit [0] CFTYP 0b Description Control and switch the relationship between the R,G,B and outputs. R/W This register is used to match different types of color filters on LCD panel Dithering enable. Active low DITHB = “0”, Dithering on, (Pseudo 8-bits resolution). (Default mode) R/W DITHB = “1”, Dithering off, (6-bits resolution, truncation last 2-bits of the input data) Note 1: Recommend user to enable this function under all modes except for 18 bit RGB input application. Color Filter Type Select. Select Delta or Stripe mode for data arrangement. CFTYP = “0”, Stripe mode, Data arrangement keep in the “odd line” state of R/W SWD[2:0] selection. CFTYP = “1”, Delta mode, Data arrangement controlled by SWD[2:0] setting. SWD[2:0] function control: SWD2 SWD1 SWD0 0 0 0 0 0 1 0 1 X 1 0 0 1 0 1 1 1 X 3n+1 R G G B B R G R B G R B Output (n=0 to 319) 3n+2 3n+3 G B B R R G B G R B G R B R R G G B R B G R B G Condition Odd Line Even Line Odd Line Even Line Odd Line Even Line Odd Line Even Line Odd Line Even Line Odd Line Even Line SHLR=”1” UPDN=”1” Note 1: X = Don’t care Note 2: Data arrangement will keep in the “odd line” state when CFTYP = 0 for stripe mode. Mar 10,2008 15 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver R02: Operation Control Register Bit Name Initial R/W Bit [7] SKIPMOD 0b Bit [6:5] HDNC[1:0] 00b (R) R/W Bit [4] - - (R) R/W - Bit [3] FPOL 0b R/W Bit [2] VSET 0b R/W Bit [1] UPDN 1b (R) R/W Bit [0] SHLR 1b (R) R/W Description Horizontal data processing algorithms select register. SKIPMOD = “0”: Horizontal data weighting skip mode. (Default mode) SKIPMOD = “1”: Horizontal data direct skip mode. Horizontal Data scaling mode select register. This function is active under CCIR601 and CCIR656 mode only. Reserve VCOMOUT polarity inverse control. FPOL = ”0”: VCOMOUT normal polarity (Default mode). FPOL = ”1”: VCOMOUT inverse polarity. Gamma correction source select. VSET = ”0”, used internal Gamma Reference voltage (VDDA). (Default mode) VSET = ”1”, used external Gamma Reference Input (V1~V7). Gate Driver Up/down scan control of gate driver. UPDN = “0”, Shift from down to up, First line=L240->L239->,,->L2->L1= Last line UPDN = “1”, Shift from up to down, First line=L1->L2->,,->239->240= Last line (Default mode) Right/Left sequence control of source driver. SHLR = “0”, shift left: Last data = S1 S2 S3.......... S960 =First data. SHLR = “1”, shift right: First data = S1 S S3........ S960 = Last data. ← ← →→ ← → HDNC[1:0] function setting for different horizontal data skip mode HDNC1 HDNC0 Source Data Data Skip Mode 1440 clock -> 720 RGB -> (scale down) 320 RGB 0 0 1440 / 1280 clock 1280 clock -> 640 RGB -> (scale down) 320 RGB 1440 clock -> 720 RGB -> (Skip Right/Left 10 RGB) 700 RGB -> 0 1 1440 clock (scale down) 320 RGB 1440 clock -> 720 RGB -> (Skip Right/Left 20 RGB) 680 RGB -> 1 0 1440 clock (scale down) 320 RGB 1440 clock -> 720 RGB -> (Skip Right/Left 40 RGB) 640 RGB -> 1 1 1440 clock (scale down) 320 RGB Note: HDNC function is active under CCIR601/656 mode only R03: Input Data Format Control Register Bit Name Bit [7] DENPOL 1b R/W Bit [6] CLKPOL 1b R/W Bit [5] HSDPOL 0b R/W Bit [4] VSDPOL 0b R/W Bit [3:0] SEL[3:0] 1100b (R) R/W Mar 10,2008 Initial R/W Description DEN input pin polarity control. DENPOL = “0”, DEN negative polarity. DENPOL = “1”, DEN positive polarity. (Default mode) CLKIN pin polarity control. CLKPOL = “0”, CLKIN negative edge latch data. CLKPOL = “1”, CLKIN positive edge latch data. (Default mode) HSD pin polarity control. HSDPOL = “0”, HSD negative polarity. (Default mode) HSDPOL = “1”, HSD positive polarity. VSD pin polarity control. VSDPOL = “0”, VSD negative polarity. (Default mode) VSDPOL = “1”, VSD positive polarity Input data format selection. Note: Different SEL [3:0] setting resolute in different AC timing. 16 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver SEL[3:0]: Data input mode SEL3 SEL2 SEL1 SEL0 Data input format Operating frequency 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 24.54 MHz 24.54 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 27 MHz 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 CCIR601 YUV 1280 input format (YUV mode A) CCIR601 YUV 1280 input format (YUV mode B) CCIR601 YUV 1440 input format (YUV mode A) CCIR601 YUV 1440 input format (YUV mode B) CCIR656 YCbCr input format (YcbCr mode A) CCIR656 YCbCr input format (YcbCr mode B) 8-bit digital RGB input format HV Mode (NTSC only) 8-bit digital RGB input format DE Mode (NTSC only) 8-bit digital RGB through mode input format HV Mode (NTSC only) 8-bit digital RGB through mode input format DE Mode (NTSC only) 24-bit digital RGB input format HV Mode (NTSC only) 24-bit digital RGB input format DE Mode (NTSC only) - ： 27 MHz 27 MHz 6.4 MHz 6.4 MHz - Note Hsync and Vsync will be floated in CCIR656 and DE mode Remark: YUV mode A: Data sequence are “Cb_Y_Cr_Y…”. YUV mode B: Data sequence are “Cr_Y_Cb_Y…”. RGB through mode will bypass 3-wire SWD[2:0] function;TCON will not arrange data color mapping. R04: Source Timing Delay Control Register Bit Bit [7:0] Name DDLY[7:0] Initial R/W 46h Description Select the HSD signal to 1’st input data delay timing Under CCIR601 mode, Ths = DDLY[7:0] + 128, (Unit = CLKIN) Under CCIR656 mode, Ths = DDLY[7:0] + 136, (Unit = CLKIN) R/W Under RGB 8/24 bit mode, Ths = DDLY[7:0] , (Unit = CLKIN) The register value will be update to the different default value each time when SEL[3:0] changed. Read the section of “Timing Table” for the detail, please. Note: DDLY function will be disabled under 8/24bit DE mode and PINCTLB = 0 condition. The default value list in the timing table will be used when PINCTLB = 0. R05: Gate Timing Delay Control Register Bit Bit [7] Name - Bit [6:0] HDLY[6:0] Initial R/W - Reserve 0Dh R/W Description Select the Gate start pulse output delay timing Tvs = HDLY[6:0], (Unit = HSD) The register value will be update to the different default value each time when SEL[3:0] changed. Read the section of “Timing Table” for the detail, please. Note: HDLY function will be disabled under 8/24bit DE mode and PINCTLB = 0 condition. The default value list in the timing table will be used when PINCTLB = 0. R06: Reserved Bit Name Bit [7:0] - Mar 10,2008 Initial R/W - - Description Reserve 17 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver R07: Internal Function Control Register Bit Name Bit [7:6] Bit [5:4] FRAD[1:0] INVSL[1:0] Initial R/W 00b 00b Bit [3] PAL 0b Bit [2] PALM 0b Bit [1] - - Bit [0] AVGY 0b Description R/W Odd frame or Even frame advance control R/W Source Driving Mode Selection Register NTSC or PAL mode selection. Only for 601 and 656 mode. (R) PAL = “0”, Select NTSC interface mode. (Default mode) R/W PAL = “1”, Select PAL interface mode. PAL mode input data format selection (R) PALM = “0”, Select PAL 280 line mode. (Default mode) R/W PALM = “1”, Select PAL 288 line mode Reserve Average YUV interface Luminance Y. AVGY = “0”; Only used odd Y sample for YUV conversion, R/W AVGY = “1”; Used odd and even Y sample for YUV conversion. This function active under YUV mode only! INVSL[1:0] INVSL1 0 0 1 1 INVSL0 0 1 0 1 Driving Mode 1 - Line Inversion 2 - Line Inversion Frame Inversion Reserved Notes Default FRAD[1:0] FRAD1 0 0 1 1 FRAD0 0 1 0 1 Advance Frame Default Odd frame Even frame Reserve Notes Odd/Even frame Tstv are the same Even frame Tstv = HDLY setting +1 ODD frame Tstv = HDLY setting +1 Reserve Unit: H Note: Remark: This function is available under CCIR601 and CCIR656 mode only. R08: Contrast Control Register Bit Bit [7:5] Name - Bit [4:0] CON[4:0] Initial R/W Description - Reserve Display Contrast level adjustment register. (0.125/Step) 08h R/W Adjust range from 0x00(level = 0) to 0x1F(level = 3.875) Default value 08h(level = 1.0) R09: Brightness Control Register Bit Bit [7] Name - Bit [6:0] BRI[6:0] Initial R/W Description - Reserve Display Brightness level adjustment register. (2/Step) 40h R/W Adjust range from 0x00(level = -128) to 0x7F(level = +126) Default value 0x40(level = +0) R0A: Hue and Saturation Control Register Bit Name Bit [7:4] HUE[3:0] Initial R/W 08h Description YUV Hue level adjustment register. (5 Deg/Step) Adjust range from 0x00(level = -40 Deg) to 0x0F(level = +35 Deg) R/W Default value 0x08(level = 0 Deg) Cb’ = Cb * cos + Cr * sin Cr’ = Cr * cos + Cb * sin θ θ θ θ YUV saturation level adjustment register. (0.125/Step) R/W Adjust range from 0x00(level = 0) to 0x0F(level = 1.875) Default value 0x08(level = 1.00) Note: Hue and Saturation function was available under YUV input mode only. Bit [3:0] SAT[3:0] Mar 10,2008 08h 18 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver R0B: R / B Sub-Contrast Control Register Bit Name Initial R/W Bit [7:6] SCONB[1:0] 02h Bit [3:2] SCONR[1:0] 02h Description B Data Contrast level adjustment register. (0.125/Step) R/W Adjust range from 0x00(level = 0.75) to 0x0F(level = 1.125) Default value 08h(level = 1.0) R Data Contrast level adjustment register. (0.125/Step) R/W Adjust range from 0x00(level = 0.75) to 0x0F(level = 1.125) Default value 08h(level = 1.0) R0C: R Sub-Brightness Control Register Bit Bit [7:6] Name - Bit [5:0] SBRIR[5:0] Initial R/W Description - Reserve R Data Brightness level adjustment register. (1/Step) 20h R/W Adjust range from 0x00(level = -32) to 0x3F(level = +31) Default value 20h(level = 0) R0D: B Sub-Brightness Control Register Bit Bit [7:6] Name - Bit [5:0] SBRIB[5:0] Initial R/W Description - Reserve B Data Brightness level adjustment register. (1/Step) 20h R/W Adjust range from 0x00(level = -32) to 0x3F(level = +31) Default value 20h(level = 0) R0E: VCOMDC Level Control Register Bit Bit [7] Bit [6] Bit [5:0] Name - Initial R/W Description - Reserve VCDCSL[5:0] data source selection register OTP_BYPS =”0”, VCDCSL[5:0] is read from OTP memory. OTP_BYPS 0h R/W OTP_BYPS =”1”, VCDCSL[5:0] is switch to the 3-wire register memory when user want to adjust the VCOMDC level for test propose. Refer to the “TRMEN” control register for the proper OTP write operation. VCOMDC level control register (20mV/Step @ VDDA = 5.0V) VCDCSL[5:0] = 00h, VCOMDC = 1.00V VCDCSL[5:0] = 01h, VCOMDC = 1.02V ….. VCDCSL 10h R/W [5:0] VCDCSL[5:0] = 10h, VCOMDC = 1.32V ….. VCDCSL[5:0] = 3eh, VCOMDC = 2.24V VCDCSL[5:0] = 3fh, VCOMDC = 2.26V ： .VCOMDC always keep 1.7V When VPSW = “1” . The OTP value effect in VPSW=0. Note The offset value is equal to 50mV in default level R0F VCOMAC Level Control Register Bit Name Bit [7:6] VGLSL 10 Bit [5:4] VGHSL 10 Bit [3:0] Initial R/W VCACSL[3: 0100 0] Mar 10,2008 Description VGLSL level control register R/W VGLSL Level = 1V / Step VGHSL level control register R/W VGHSL Level = 1V / Step VCOMAC level control register R/W VCOMAC Level = 0.1V / Step @ VDDA = 5.0V 19 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver VCACSL [3:0] VCSL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ： VCSL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VCSL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VCSL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Level (V) 4.6 4.7 4.8 4.9 5.0 (Default) 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 Note When VPSW = “1” .The register can’t be used The offset value is equal to 100mV in default level VGHSL[5:4] VGHSL1 0 0 1 1 VGHSL0 0 1 1 0 VGH(V) 12 13 14 15 When VPSW = “1” .The register can’t be used VGLSL[7:6] VGHSL1 0 0 1 1 VGHSL0 0 1 1 0 VGL(V) -7 -8 -9 -10 When VPSW = “1” .The register can’t be used R10: VGAM2 Level Control Register Bit Bit [7:5] Name - Bit [4] GAMEN Bit [3] V2GAM [2:0] Bit [2:0] Initial R/W Description - Reserve GAMMA adjustment enable control register.(adjustable voltage for V2-V6) 0b R/W GAEN=”0” or VSET = 1, Gamma correction disabled. GAEN=”1” & VSET=”0”, Gamma correction enabled - Reserve V2 GAMMA voltage level setting. Function enabled when VSET=”0” 100b R/W Adjust level = 22mV / Step R11: VGAM3/4 Level Control Register Bit Bit [7:6] Bit [5:3] Bit [2:0] Name V4GAM [2:0] V3GAM [2:0] Mar 10,2008 Initial R/W Description - Reserve V4 GAMMA voltage level setting. Function enabled when VSET=”0” 100b R/W Adjust level = 22mV / Step V3 GAMMA voltage level setting. Function enabled when VSET=”0” 100b R/W Adjust level = 22mV / Step 20 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver R12: VGAM5/6 Level Control Register Bit Bit [10:6] Bit [5:3] Bit [2:0] Name V6GAM [2:0] V5GAM [2:0] Initial R/W Description - Reserve V6 GAMMA voltage level setting. Function enabled when VSET=”0” 100b R/W Adjust level = 22mV / Step V5 GAMMA voltage level setting. Function enabled when VSET=”0” 100b R/W Adjust level = 22mV / Step V2GAM/ V3GAM/ V4GAM/ V5GAM./ V6GAM Level Control Register Setting Table VxGMA2 VxGMA1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Note: x = 2, 3, 4, 5, 6 VxGMA0 0 1 0 1 0 1 0 1 Voltage level +88 +66 +44 +22 +0(Default) -22 -44 -66 Unit mV mV mV mV mV mV mV mV Note Refer to the Gamma Table for the default voltage level of V2 ~ V6 R1E: VCOMDC Trim Function Control Register Bit Name Description VCOMDC Trim function control register Write the follow command sequentially to enable the VCOMDC trim function. Adjust VCDC level: TRMEN Bit [7:0] 00b R/W Set TRMEN[7:0]=00h and write proper VCDCSL[5:0] value using 3-wire cmd. [7:0] Programming the VCDCSL value into OTP memory: Set TRMEN[7:0] as following sequence A0h->5Fh -> EEh -> 00h OTP_BYPS will be clear to 0b after the programming procedure Note: The Trim Block can be writing for only “2” times. Trim command exceed the limit may cause the VCOMDC output unknown value. Mar 10,2008 Initial R/W 21 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Procedure 0 Set VPP_OTP= 7.5V Procedure 1 Set OTP_BYPS = 1 Procedure 2 Update VCDCSL value in R0E Bit[5:0] Procedure 3 Set TRMEN[7:0] as following sequence A0h->5Fh -> EEh -> 00h Programming the VCDCSL value into OTP memory: Procedure 4 OTP_BYPS will be clear to 0b after the programming procedure Procedure 5 Set VPP_OTP= 0V R20: Wide and narrow display mode Control Register Bit Bit [7:2] Bit [1:0] Name WNSEL [1:0] Initial R/W - Reserve 00b Description R/W Wide and narrow display mode select register WNSEL[1:0]: Wide and narrow display mode select register WNSEL1 0 0 1 1 WNSEL0 0 1 0 1 Display Mode Normal display (Default) Narrow display Wide display 234-Line Note: This function will be enabled under CCIR601 and CCIR656 mode Mar 10,2008 22 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Function Description Power On/Off Sequence To prevent IC from power on reset fail, the rising time (TPOR) of digital power supply VDD, should be control within the specification. Refer to the “AC Characteristic” for the detail timing, please. Power-On Timing Sequence: Power-off Timing Sequence: External Reset (RSTB) To prevent from abnormal reset condition, a glitch filter for RSTB is embedded in this chip. The external reset signal should keep active for large then reset time (TRSTB). Refer to the AC/DC Specification for the requirement. Mar 10,2008 23 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Input Data VS Output Voltage Source Driver data output sequence can be control by “SHLR”. Output SO1 SHLR=”1” SHLR=”0” First data Last data SO2 SO3 -- SO958 SO959 SO960 Last data First data Gate Driver scan output sequence can be control by “UPDN”. Scan UPDN=”1” UPDN=”0” GO1 First scan Last scan GO2 GO3 -- GO238 GO239 GO240 Last scan First scan The figure below shows the relationship between the input data and the output voltage. Refer to the following pages to get the relative resistor value and voltage calculation method, please. 5.000 Postive (VCOM = L) 4.500 4.000 3.500 3.000 ) (V tu 2.500 o V 2.000 1.500 1.000 0.500 0.000 H 00 H 30 H 60 H 9 0 H C 0 H F 0 H 2 1 H 5 1 5.000 H 8 1 H B 1 H E 1 H 1 2 H 4 2 H A 2 H 7 2 INPUT H D 2 H 0 3 H 3 3 H 6 3 H 9 3 H C 3 H F 3 Negative (VCOM = H) 4.500 4.000 3.500 3.000 ) V t(u o V 2.500 2.000 1.500 1.000 0.500 0.000 H 00 H 40 Mar 10,2008 H 80 H C 0 H 01 H 41 H 81 H C 1 INPUT H 02 H 42 H 82 H C 2 24 H 03 H 43 H 83 H C 3 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Input Data and Output Voltage Reference Table (VSET = “0”) @ VDDA = 5 V, VCOMOUT=L, POL=H Vno. Unit = V V1 4.610 V2 3.680 V3 3.115 V4 2.585 V5 2.185 V6 1.790 V7 0.390 @ VDDA = 5 V, VCOMOUT=H, POL=L Vno. Unit = V V1 0.390 V2 1.320 V3 1.885 V4 2.415 V5 2.815 V6 3.210 V7 4.610 Data (V1) 00H 01H 02H 03H 04H (V2) 05H 06H 07H 08H 09H 0AH 0BH (V3) 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H (V4) 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H (V5) 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H (V6) 38H 39H 3AH 3BH 3CH 3DH 3EH (V7) 3FH VCOMOUT=H, POL=L VDDA X 0.078 VDDA X 0.107 VDDA X 0.153 VDDA X 0.201 VDDA X 0.236 0.264 VDDA X VDDA X 0.288 VDDA X 0.308 VDDA X 0.325 VDDA X 0.340 VDDA X 0.354 VDDA X 0.366 VDDA X 0.377 VDDA X 0.388 VDDA X 0.398 VDDA X 0.408 VDDA X 0.416 VDDA X 0.424 VDDA X 0.431 VDDA X 0.438 VDDA X 0.446 VDDA X 0.453 VDDA X 0.459 VDDA X 0.465 VDDA X 0.472 VDDA X 0.478 VDDA X 0.483 VDDA X 0.488 VDDA X 0.493 VDDA X 0.499 VDDA X 0.505 VDDA X 0.510 VDDA X 0.514 VDDA X 0.519 VDDA X 0.525 VDDA X 0.530 VDDA X 0.535 VDDA X 0.540 VDDA X 0.545 VDDA X 0.550 VDDA X 0.554 VDDA X 0.558 VDDA X 0.563 VDDA X 0.568 VDDA X 0.573 VDDA X 0.578 VDDA X 0.583 VDDA X 0.588 VDDA X 0.593 VDDA X 0.598 VDDA X 0.603 VDDA X 0.609 VDDA X 0.615 VDDA X 0.621 VDDA X 0.626 VDDA X 0.632 VDDA X 0.642 VDDA X 0.648 VDDA X 0.656 VDDA X 0.665 VDDA X 0.677 VDDA X 0.693 VDDA X 0.719 VDDA X 0.922 Data (V1) 00H 01H 02H 03H 04H (V2) 05H 06H 07H 08H 09H 0AH 0BH (V3) 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H (V4) 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H (V5) 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H (V6) 38H 39H 3AH 3BH 3CH 3DH 3EH (V7) 3FH VCOMOUT=L, POL=H VDDA X 0.922 VDDA X 0.893 VDDA X 0.847 VDDA X 0.799 VDDA X 0.764 VDDA X 0.736 VDDA X 0.712 VDDA X 0.692 VDDA X 0.675 VDDA X 0.660 VDDA X 0.646 VDDA X 0.634 VDDA X 0.623 VDDA X 0.612 VDDA X 0.602 VDDA X 0.592 VDDA X 0.584 VDDA X 0.576 VDDA X 0.569 VDDA X 0.562 VDDA X 0.554 VDDA X 0.547 VDDA X 0.541 VDDA X 0.535 VDDA X 0.528 VDDA X 0.522 VDDA X 0.517 VDDA X 0.512 VDDA X 0.507 VDDA X 0.501 VDDA X 0.495 VDDA X 0.490 VDDA X 0.486 VDDA X 0.481 VDDA X 0.475 VDDA X 0.470 VDDA X 0.465 VDDA X 0.460 VDDA X 0.455 VDDA X 0.450 VDDA X 0.446 VDDA X 0.442 VDDA X 0.437 VDDA X 0.432 VDDA X 0.427 VDDA X 0.422 VDDA X 0.417 VDDA X 0.412 VDDA X 0.407 VDDA X 0.402 VDDA X 0.397 VDDA X 0.391 VDDA X 0.385 VDDA X 0.379 VDDA X 0.374 VDDA X 0.368 VDDA X 0.358 VDDA X 0.352 VDDA X 0.344 VDDA X 0.335 VDDA X 0.323 VDDA X 0.307 VDDA X 0.281 VDDA X 0.078 Note: Gamma Table will be difference for each custom. Contact to Novatek for the detail information, please. Mar 10,2008 25 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Data Input Format 1. RGB input Data format HSD CLKIN (RGB HV mode ) Ths DIN[7:0] DIN[7:0] (RGB DE mode) DEN 0 1 2 3 4 5 6 7 8 R G B R G B R G - - - - - - - - - R G B R G B R G - - - - - - - - - Active Area Total Area 2. YUV input Data format HSD CLKIN Ths YUV mode DIN[7:0] 0 1 2 3 4 5 6 7 8 Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 - - - - - - - - - Active Area Total Area 3. CCIR_656 Mode Data format Next Line CLKIN // EAV code CCIR_656 Dataformat Blanking // SAV Code // FFh 00h 00h XY 80h 10h 80h 10h // 80h 10h 80h 10h FFh 00h 00h XY 0 1 2 3 4 5 6 7 8 Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 - - - Cr // 4 4 Y FFh Digital Video Stream Active 4. Data Active Area CCIR_601 CCIR_656 CCIR_601 27 1 24.54 1 Total Area (CLKIN) 1716 1728 1560 8bit RGB 8 bit RGB 27 1 1716 960 24bit RGB 24 bit RGB 6.4 1 408 320 Input Format Format Standard CLKIN (MHz) HSD (CLKIN) YUV Mar 10,2008 26 Active Area (CLKIN) Note 1440 1280 960x240 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver 5. YUV_601/656 to RGB conversion AVGY=0: Rn = 1.164(Y2n-16) +1.596(Crn -128) Gn = 1.164(Y2n-16) -0.813(Crn -128) -0.392(Cbn -128); [Y=16~235,Cr & Cb=16~240] Bn = 1.164(Y2n-16) +2.017(Cbn-128) AVGY=1: Rn = 1.164((Y2n +Y2n+1)/2 -16)+1.596(Crn-128) Gn = 1.164((Y2n +Y2n+1)/2 -16)-0.813(Crn-128)-0.392(Cbn-128) ; [Y=16~235,Cr & Cb=16~240] Bn = 1.164((Y2n +Y2n+1)/2 -16)+2.017(Cbn-128) 6. Brightness / Contrast Adjustment Contrast: Gn = G[7:0] x Contrast( 0 to 3.875) Rn = R[7:0] x Contrast( 0 to 3.875) x Sub-Contrast R( 0.8 to 1.175) Bn = B[7:0] x Contrast( 0 to 3.875) x Sub-Contrast B( 0.8 to 1.175) Brightness: Gn = G[7:0] + Brightness( -128 to +126) Rn = R[7:0] + Brightness ( -128 to +126) + Sub-Brightness R( -32 to +31) Bn = B[7:0] + Brightness ( -128 to +126) + Sub-Brightness B( -32 to +31) Mar 10,2008 27 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Absolute Maximum Ratings Logic supply voltage, VDD Analog supply voltage, VDDA Supply voltage, VDDP Supply voltage, V1~ V6 VGH~VGL Storage temperature Operating temperature -0.5V to +5V -0.5V to +7.5V -0.5V to +5.5V -0.3 ~VDDA+0.3 -0.3~ +25V -55 to +125 to +85 -20 ℃ ℃ ℃ ℃ Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or under any other conditions above those indicated in the operational sections of this specification are not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (For the digital circuit: Test Condition: VDD=VDDP=3.3V , VDDA=5.0V, GND=GNDA=GNDP= 0V, TA=25 Parameter Digital Block Circuit Digital Supply Voltage Symbol Min. Typ. Max. Unit Conditions VDD 3.0 3.3 3.6 V Low Level Input Voltage Vil GND - 0.2xVDD V High Level Input Voltage Vih 0.8xVDD - VDD V Low Level Input Voltage Vil GND - 0.2xVDD V High Level Input Voltage Vih 0.8xVDD - VDD V Low Level Input Voltage Vil GND - 0.1xVDD V High Level Input Voltage Vih 0.9xVDD - VDD V Input Leakage Current Ii - - ±1 ℃ Digital input pins TA=85℃ Digital input pins TA=25℃ Digital input pins TA=25℃ Digital input pins TA= -20℃ Digital input pins TA= -20℃ µA Digital input pins Pull-high/low Impedance High Level Output Voltage Low Level Output Voltage Rin Voh Vol VDD-0.4 VDD GND 200K - GND+0.4 ohm V V Digital control input pins Digital output pins; Ioh = 400 uA Digital output pins; Iol = -400 uA Digital Stand-by Current Digital Operating Current Iddst Idd1 - (50) 2 (100) - uA mA No load, CLKIN/VSD/HSD stopped CLKIN = 27 MHz (CCIR601mode) Charge Pump Supply Voltage VDDP 3.0 3.3 3.6 V VCOMAC output level VCOMAC 4.6 - 6.1 V VCOMDC output level VCOMDC 1.0 - 2.26 V Positive power supply Negative power supply Base drive current DRV output voltage VGH VGL IDRV VDRV 15 -10 - VFB 15.5 -11 10 VDD -0.1 0.65 V V mA V Feed back voltage 14.5 -9 GND +0.1 0.55 ℃) Digital power Digital input pins TA=85 Power Circuit Mar 10,2008 0.6 28 V For VGH/VGL power and Source Driver power, must in this range By VCSL[2:0] setting VCOMAC = V(VCSL[2:0]) +- 100mV By VCDCSL[5:0] setting VCOMDC = V(VCDCSL[5:0]) +- 50mV Gate driver load + procard load Gate driver load + procard load VDDP=3.3V, DRV=0.7 V DC/DC operating, VBL current=20 mA Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Parameter Analog Block Circuit Analog Supply Voltage Voltage Deviation of Outputs Symbol Min. Typ. Max. Unit Conditions VDDA 5.0 5.2 6.0 V - ±20 ±35 mV Analog circuit power from Power Block Vo=0.1V ~ 0.5V & VDDA - 0.5 ~ VDDA - 0.1V ±15 ±25 mV Vvd Vo=0.5V ~ VDDA-0.5V Force VCOMAC = 6.0V VCOMOUT output = 0V V.S. 0.9V Force VCOMAC = 6.0V VCOMOUT output = 6.0V V.S 5.1V Low-Level Output Current of VCOMOUT IOLF - -10 - mA High-Level Output Current of VCOMOUT IOHF - 10 - mA IOLS - -30 - uA Son = Vo V.S. (Vo+0.9) IOHS - 30 - uA Son = Vo V.S. (Vo-0.9) IOLG - -250 - µA GOn; Vo=VGL V.S. (VGL +0.5) Source Low-Level Output Current Source High-Level Output Current Gate Low-Level Output Current Gate High-Level Output Current Analog Stand-by Current IOHG - 250 - µA GOn; Vo=VGH V.S. (VGH -0.5) Iddast - - 100 µA STBYB = ”0”, all function are shutdown Analog Operating Current Idda - 10 - mA No load, CLKIN = 27MHz, Fld=15KHz Mar 10,2008 29 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver AC Electrical Characteristics Test Condition: (VDD=VDDP=3.3V, VDDA=5.0V, GND=GNDA=GNDP=0V, TA= 25 Parameter System Operation Timing VDD power source slew time RSTB active pulse width Input Output Timing CLKIN clock time HSD to CLKIN HSD width VSD width HSD period time VSD setup time VSD hold time HSD setup time HSD hold time Data set-up time Data hold time Symbol Min. Typ. TPOR ℃) Max. Unit Conditions 1000 us From 0V to 90% VDD us VDD = 3.3V ns CLKIN CLKIN Th us ns ns ns ns ns ns CLKIN = 28MHz TRSTB 40 Tclk Thc Thwh Tvwh Th Tvst Tvhd Thst Thhd Tdsu Tdhd 1 1 60 12 12 12 12 12 12 63.56 - Tesd 12 - Tvs 2 13 127 Th Tvs 12 20 28 Th Tvs 17 25 33 Th @CCIR656 PAL mode Control by HDLY[6:0] setting Tvs = HDLY[6:0] Time that VSD to 1 line data input Tvs 2 13 127 Th @24bit RGB HV mode Control by HDLY[6:0] setting Tvs = HDLY[6:0] Source output stable time 1 Tst DEN setup time 35.7 1 67 - ns st Time that VSD to 1 line data input st Time that CCIR_V to 1 line data input st Time that CCIR_V to 1 line data input st Gate output stable time Tgst VCOMOUT output stable Tcst time 3-wire serial communication AC timing Serial clock Tspck DEN to CLKIN @CCIR601 / 8bit RGB HV mode Control by HDLY[6:0] setting Tvs = HDLY[6:0] @CCIR656 NTSC mode Control by HDLY[6:0] setting Tvs = HDLY[6:0] - 25 30 us 96% final, CL=30pF, RL=2K - 500 1000 ns 96% final, CL=40pF - 4 8 us 96% final, CL=33nF, RL=100ohm 320 - - ns SPCK pulse duty Tscdut 40 50 60 % Serial data setup time Serial data hold time Serial clock high/low Chip select distinguish SPENA to VSD Tisu Tihd Tssw Tcd Tcv 120 120 120 1 1 - - ns ns ns us us Mar 10,2008 DIN[23:0] to CLKIN DIN[23:0] to CLKIN 30 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Timing Table CCIR601 Mode A/B * Parameter Symbol CLKIN frequency Fclk CLKIN cycle time CLKIN pulse duty Time from HSD to VCOMOUT Time from HSD to DATSEQ Time from HSD to Gate output n line Time from HSD to Gate output n+1 line Time from HSD to 1’st data input (PAL) Time from HSD to 1’st data input (NTSC) Tclk Tcwh Thvcm Thseq Thgz Thgo Ths Ths Min. 40 - 128 128 Typ. 24.54 /27 40/37 50 66 60 30 100 264 244 Max. Typ. 27 37 50 66 60 30 100 288 276 Max. Typ. 27 37 50 25 20 5 45 70 Max. 60 - Unit Conditions MHz VDD = 3.0 ~3.6V ns % CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN Tclk DDLY = 136, Offset = 128 (fixed) DDLY = 116, Offset = 128 (fixed) CCIR656 Mode A/B * Parameter CLKIN frequency CLKIN cycle time CLKIN pulse duty Time from EAV to VCOMOUT Time from EAV to DATSEQ Time from HSD to Gate output n line Time from HSD to Gate output n+1 line Time from EAV to 1’st data input (PAL) Time from EAV to 1’st data input (NTSC) Symbol Fclk Tclk Tcwh Thvcm Thseq Thgz Thgo Ths Ths Min. 40 - Symbol Fclk Tclk Tcwh Thvcm Thseq Thgz Thgo Ths Min. 40 - 128 128 60 - Unit MHz ns % CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN Conditions VDD = 3.0 ~3.6V Tclk DDLY = 152, Offset = 128 (fixed) DDLY = 140, Offset = 128 (fixed) 8 Bit RGB 960 CH Mode Parameter CLKIN frequency CLKIN cycle time CLKIN pulse duty Time from HSD to VCOMOUT Time from HSD to DATSEQ Time from HSD to Gate output n line Time from HSD to Gate output n+1 line Time that HSD to 1’st data input(NTSC) 35 60 255 Unit MHz ns % CLKIN CLKIN CLKIN CLKIN CLKIN Conditions VDD = 3.0 ~3.6V Tclk DDLY = 70, Offset = 0 (fixed) 24 Bit RGB Mode (@ SEL[3:0] = 1100 or 1101) Parameter CLKIN frequency CLKIN cycle time CLKIN pulse duty Time from HSD to VCOMOUT Time from HSD to DATSEQ Time from HSD to Gate output n line Time from HSD to Gate output n+1 line Time that HSD to 1’st data input(NTSC) Mar 10,2008 Symbol Fclk Tclk Tcwh Thvcm Thseq Thgz Thgo Ths Min. 40 - 40 Typ. 6.4 156 50 30 20 5 45 70 31 Max. 60 255 Unit MHz ns % CLKIN CLKIN CLKIN CLKIN CLKIN Conditions VDD = 3.0 ~3.6V Tclk DDLY =70, Offset = 0 (fixed) Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Timing Diagram Clock and Data Input Timing Diagram Tclk Tcwh CLKIN Tcwl First Last // Tdsu Tdhd // DIN[7:0] First data 2nd data Last data // // Tesu DEN // CLKIN Tvst Tvhd // VSD Thwh Thhd // HSD Th Thst CLKIN Last // // Last-1 data DIN[7:0] Last data // Thc // HSD 3-Wire Timing Diagram VSD Teck Tcv Tcke // SPENB Tcd Tisu SPDA // D15 D14 D13 D2 D1 D0 D15 // D14 D1 D0 // Tihd Tckh Tckl // // SPCK Tspck Mar 10,2008 32 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Source Driver Output Timing Diagram Gate Driver Output Timing Diagram VSD HSD G1 or G240 G2 or G239 1 2 Tstv 1 2 G239 or G2 239 G240 or G1 240 VCOMOUT (Odd frame, FPOL="L") VCOMOUT (Even frame, FPOL="L") VCOMOUT (Odd frame, FPOL="H") VCOMOUT (Even frame, FPOL="H") Mar 10,2008 33 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Vertical Timing Diagram (HV Mode) VSD HSD 1 2 Tvs 1 Data STV Tstv 2 3 4 5 6 N-2 N-1 N 1 CLKV OEV VCOMOUT (Odd frame, FPOL="L") VCOMOUT (Even frame, FPOL="L") VCOMOUT (Odd frame, FPOL="H") VCOMOUT (Even frame, FPOL="H") Vertical Timing Diagram (DE Mode) Mar 10,2008 34 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Input Data Timing (24 bit RGB mode for 960 x 240 @ SEL[3:0] = 1100b) VSD HSD 1 2 13 14 253 254 1 2 Default = 13 lines Valid Line Display lines = 240 lines Total lines = 263 lines HSD CLKIN (6.4 MHz) 1 2 70 71 Default = 70 DIN[7:0] R R R R R R R R R R R R R R R R R DIN[15:8] G G G G G G G G G G G G G G G G G DIN[23:16] B B B B B B B B B B B B B B B B B DEN (DE Mode) Active Area = 320 (RGB) Total Area = 408 CLKIN Mar 10,2008 35 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Pad Location Mar 10,2008 36 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Alignment Mark Pad Information Symbol B B3 C C1 C2 C4 D2 E1 E2 E4 E5 Dimension (um) 17 110 100 127 27 115 30 21310 760 65 65 *Remark: Chip dimension include scribe line Mar 10,2008 37 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Application Notes PWM for LED Backlight Control NT39016 using continuous analog type PWM control architecture for better performance. An auto protect detection feature was also integrated. The PWM circuit will enter power down state when the internal CKV signal is below 1KHz. Only one LED Vz=5.5v More than one LED s Mar 10,2008 38 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Appendix A: Pad Coordinate Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y 1 Alignment -10532.5 -257.5 89 TP7 635 -257.5 177 GO018 10411.5 120 265 GO194 8915.5 120 353 SO060 7307.5 120 2 DUM -10412 -257.5 90 TP6 762 -257.5 178 GO020 10394.5 260 266 GO196 8898.5 260 354 SO061 7290.5 260 3 C4M -10287 -257.5 91 TP5 889 -257.5 179 GO022 10377.5 120 267 GO198 8881.5 120 355 SO062 7273.5 120 4 C4M -10160 -257.5 92 DUM 1016 -257.5 180 GO024 10360.5 260 268 GO200 8864.5 260 356 SO063 7256.5 260 5 C4P -10033 -257.5 93 TP4 1143 -257.5 181 GO026 10343.5 120 269 GO202 8847.5 120 357 SO064 7239.5 120 6 C4P -9906 -257.5 94 TP3 1270 -257.5 182 GO028 10326.5 260 270 GO204 8830.5 260 358 SO065 7222.5 260 7 VGH -9779 -257.5 95 DUM 1397 -257.5 183 GO030 10309.5 120 271 GO206 8813.5 120 359 SO066 7205.5 120 8 VGH -9652 -257.5 96 TP2 1524 -257.5 184 GO032 10292.5 260 272 GO208 8796.5 260 360 SO067 7188.5 260 9 VGH -9525 -257.5 97 TP1 1651 -257.5 185 GO034 10275.5 120 273 GO210 8779.5 120 361 SO068 7171.5 120 10 C3M -9398 -257.5 98 DUM 1778 -257.5 186 GO036 10258.5 260 274 GO212 8762.5 260 362 SO069 7154.5 260 11 C3M -9271 -257.5 99 TP0 1905 -257.5 187 GO038 10241.5 120 275 GO214 8745.5 120 363 SO070 7137.5 120 12 C3P -9144 -257.5 100 VDDA 2032 -257.5 188 GO040 10224.5 260 276 GO216 8728.5 260 364 SO071 7120.5 260 13 C3P -9017 -257.5 101 VDDA 2159 -257.5 189 GO042 10207.5 120 277 GO218 8711.5 120 365 SO072 7103.5 120 14 C2P -8890 -257.5 102 VDDA 2286 -257.5 190 GO044 10190.5 260 278 GO220 8694.5 260 366 SO073 7086.5 260 15 C2P -8763 -257.5 103 GNDA 2413 -257.5 191 GO046 10173.5 120 279 GO222 8677.5 120 367 SO074 7069.5 120 16 C2M -8636 -257.5 104 GNDA 2540 -257.5 192 GO048 10156.5 260 280 GO224 8660.5 260 368 SO075 7052.5 260 17 C2M -8509 -257.5 105 GNDA 2667 -257.5 193 GO050 10139.5 120 281 GO226 8643.5 120 369 SO076 7035.5 120 18 COM1_L -8382 -257.5 106 GND 2794 -257.5 194 GO052 10122.5 260 282 GO228 8626.5 260 370 SO077 7018.5 260 19 COM1_L -8255 -257.5 107 GND 2921 -257.5 195 GO054 10105.5 120 283 GO230 8609.5 120 371 SO078 7001.5 120 20 DUM -8128 -257.5 108 GND 3048 -257.5 196 GO056 10088.5 260 284 GO232 8592.5 260 372 SO079 6984.5 260 21 C1AP -8001 -257.5 109 VDD 3175 -257.5 197 GO058 10071.5 120 285 GO234 8575.5 120 373 SO080 6967.5 120 22 C1AP -7874 -257.5 110 VDD 3302 -257.5 198 GO060 10054.5 260 286 GO236 8558.5 260 374 SO081 6950.5 260 23 C1AM -7747 -257.5 111 VDD 3429 -257.5 199 GO062 10037.5 120 287 GO238 8541.5 120 375 SO082 6933.5 120 24 C1AM -7620 -257.5 112 RSTB 3556 -257.5 200 GO064 10020.5 260 288 GO240 8524.5 260 376 SO083 6916.5 260 25 C1M -7493 -257.5 113 DUM 3683 -257.5 201 GO066 10003.5 120 289 COM2_R 8485.5 260 377 SO084 6899.5 120 26 C1M -7366 -257.5 114 SPDA 3810 -257.5 202 GO068 9986.5 260 290 COM2_R 8451.5 260 378 SO085 6882.5 260 27 C1P -7239 -257.5 115 SPSW 3937 -257.5 203 GO070 9969.5 120 291 COM2_R 8417.5 260 379 SO086 6865.5 120 28 C1P -7112 -257.5 116 PINCTLB 4064 -257.5 204 GO072 9952.5 260 292 COM2_R 8383.5 260 380 SO087 6848.5 260 29 GNDP -6985 -257.5 117 SPCK 4191 -257.5 205 GO074 9935.5 120 293 COM2_R 8349.5 260 381 SO088 6831.5 120 30 GNDP -6858 -257.5 118 SPENB 4318 -257.5 206 GO076 9918.5 260 294 SO001 8310.5 260 382 SO089 6814.5 260 31 GNDP -6731 -257.5 119 DEN 4445 -257.5 207 GO078 9901.5 120 295 SO002 8293.5 120 383 SO090 6797.5 120 32 VDDP -6604 -257.5 120 HSD 4572 -257.5 208 GO080 9884.5 260 296 SO003 8276.5 260 384 SO091 6780.5 260 33 VDDP -6477 -257.5 121 VSD 4699 -257.5 209 GO082 9867.5 120 297 SO004 8259.5 120 385 SO092 6763.5 120 34 VDDP -6350 -257.5 122 CLKIN 4826 -257.5 210 GO084 9850.5 260 298 SO005 8242.5 260 386 SO093 6746.5 260 35 DUM -6223 -257.5 123 DIN23 4953 -257.5 211 GO086 9833.5 120 299 SO006 8225.5 120 387 SO094 6729.5 120 36 VGL -6096 -257.5 124 DIN22 5080 -257.5 212 GO088 9816.5 260 300 SO007 8208.5 260 388 SO095 6712.5 260 37 VGL -5969 -257.5 125 DIN21 5207 -257.5 213 GO090 9799.5 120 301 SO008 8191.5 120 389 SO096 6695.5 120 38 VGL -5842 -257.5 126 DIN20 5334 -257.5 214 GO092 9782.5 260 302 SO009 8174.5 260 390 SO097 6678.5 260 39 DUM -5715 -257.5 127 DIN19 5461 -257.5 215 GO094 9765.5 120 303 SO010 8157.5 120 391 SO098 6661.5 120 40 Vint2 -5588 -257.5 128 DIN18 5588 -257.5 216 GO096 9748.5 260 304 SO011 8140.5 260 392 SO099 6644.5 260 41 Vint2 -5461 -257.5 129 DIN17 5715 -257.5 217 GO098 9731.5 120 305 SO012 8123.5 120 393 SO100 6627.5 120 42 Vint2 -5334 -257.5 130 DIN16 5842 -257.5 218 GO100 9714.5 260 306 SO013 8106.5 260 394 SO101 6610.5 260 43 DUM -5207 -257.5 131 DIN15 5969 -257.5 219 GO102 9697.5 120 307 SO014 8089.5 120 395 SO102 6593.5 120 44 GNDA -5080 -257.5 132 DIN14 6096 -257.5 220 GO104 9680.5 260 308 SO015 8072.5 260 396 SO103 6576.5 260 45 GNDA -4953 -257.5 133 DIN13 6223 -257.5 221 GO106 9663.5 120 309 SO016 8055.5 120 397 SO104 6559.5 120 46 GNDA -4826 -257.5 134 DIN12 6350 -257.5 222 GO108 9646.5 260 310 SO017 8038.5 260 398 SO105 6542.5 260 47 DUM -4699 -257.5 135 DIN11 6477 -257.5 223 GO110 9629.5 120 311 SO018 8021.5 120 399 SO106 6525.5 120 48 VCOMOUT -4572 -257.5 136 DIN10 6604 -257.5 224 GO112 9612.5 260 312 SO019 8004.5 260 400 SO107 6508.5 260 49 VCOMOUT -4445 -257.5 137 DIN9 6731 -257.5 225 GO114 9595.5 120 313 SO020 7987.5 120 401 SO108 6491.5 120 50 VCOMOUT -4318 -257.5 138 DIN8 6858 -257.5 226 GO116 9578.5 260 314 SO021 7970.5 260 402 SO109 6474.5 260 51 Vint1 -4191 -257.5 139 DIN7 6985 -257.5 227 GO118 9561.5 120 315 SO022 7953.5 120 403 SO110 6457.5 120 52 Vint1 -4064 -257.5 140 DIN6 7112 -257.5 228 GO120 9544.5 260 316 SO023 7936.5 260 404 SO111 6440.5 260 53 Vint1 -3937 -257.5 141 DIN5 7239 -257.5 229 GO122 9527.5 120 317 SO024 7919.5 120 405 SO112 6423.5 120 54 DUM -3810 -257.5 142 DIN4 7366 -257.5 230 GO124 9510.5 260 318 SO025 7902.5 260 406 SO113 6406.5 260 55 VCOMAC -3683 -257.5 143 DIN3 7493 -257.5 231 GO126 9493.5 120 319 SO026 7885.5 120 407 SO114 6389.5 120 56 VCOMAC -3556 -257.5 144 DIN2 7620 -257.5 232 GO128 9476.5 260 320 SO027 7868.5 260 408 SO115 6372.5 260 57 VCOMAC -3429 -257.5 145 DIN1 7747 -257.5 233 GO130 9459.5 120 321 SO028 7851.5 120 409 SO116 6355.5 120 58 DUM -3302 -257.5 146 DIN0 7874 -257.5 234 GO132 9442.5 260 322 SO029 7834.5 260 410 SO117 6338.5 260 59 VCOM -3175 -257.5 147 DATSEQ 8001 -257.5 235 GO134 9425.5 120 323 SO030 7817.5 120 411 SO118 6321.5 120 60 VCOM -3048 -257.5 148 VCC 8128 -257.5 236 GO136 9408.5 260 324 SO031 7800.5 260 412 SO119 6304.5 260 61 VCOM -2921 -257.5 149 VCC 8255 -257.5 237 GO138 9391.5 120 325 SO032 7783.5 120 413 SO120 6287.5 120 62 POL -2794 -257.5 150 VCC 8382 -257.5 238 GO140 9374.5 260 326 SO033 7766.5 260 414 SO121 6270.5 260 63 DUM -2667 -257.5 151 GND 8509 -257.5 239 GO142 9357.5 120 327 SO034 7749.5 120 415 SO122 6253.5 120 64 VPSW -2540 -257.5 152 GND 8636 -257.5 240 GO144 9340.5 260 328 SO035 7732.5 260 416 SO123 6236.5 260 65 DUM -2413 -257.5 153 GND 8763 -257.5 241 GO146 9323.5 120 329 SO036 7715.5 120 417 SO124 6219.5 120 66 TP18 -2286 -257.5 154 COM2_L 8890 -257.5 242 GO148 9306.5 260 330 SO037 7698.5 260 418 SO125 6202.5 260 67 TP17 -2159 -257.5 155 COM2_L 9017 -257.5 243 GO150 9289.5 120 331 SO038 7681.5 120 419 SO126 6185.5 120 68 TP16 -2032 -257.5 156 DRV 9144 -257.5 244 GO152 9272.5 260 332 SO039 7664.5 260 420 SO127 6168.5 260 69 TP15 -1905 -257.5 157 DRV 9271 -257.5 245 GO154 9255.5 120 333 SO040 7647.5 120 421 SO128 6151.5 120 70 DUM -1778 -257.5 158 FB_P 9398 -257.5 246 GO156 9238.5 260 334 SO041 7630.5 260 422 SO129 6134.5 260 71 TP14 -1651 -257.5 159 FB_P 9525 -257.5 247 GO158 9221.5 120 335 SO042 7613.5 120 423 SO130 6117.5 120 72 TP13 -1524 -257.5 160 FB 9652 -257.5 248 GO160 9204.5 260 336 SO043 7596.5 260 424 SO131 6100.5 260 73 DUM -1397 -257.5 161 FB_N 9779 -257.5 249 GO162 9187.5 120 337 SO044 7579.5 120 425 SO132 6083.5 120 74 TP12 -1270 -257.5 162 FB_N 9906 -257.5 250 GO164 9170.5 260 338 SO045 7562.5 260 426 SO133 6066.5 260 75 TP11 -1143 -257.5 163 VPP_OTP 10033 -257.5 251 GO166 9153.5 120 339 SO046 7545.5 120 427 SO134 6049.5 120 76 DUM -1016 -257.5 164 VPP_OTP 10160 -257.5 252 GO168 9136.5 260 340 SO047 7528.5 260 428 SO135 6032.5 260 77 TP10 -889 -257.5 165 VPP_OTP 10287 -257.5 253 GO170 9119.5 120 341 SO048 7511.5 120 429 SO136 6015.5 120 78 TP9 -762 -257.5 166 DUM 10412 -257.5 254 GO172 9102.5 260 342 SO049 7494.5 260 430 SO137 5998.5 260 79 TP8 -635 -257.5 167 Alignment 10532.5 -257.5 255 GO174 9085.5 120 343 SO050 7477.5 120 431 SO138 5981.5 120 80 DUM -508 -257.5 168 DUM 10581.5 260 256 GO176 9068.5 260 344 SO051 7460.5 260 432 SO139 5964.5 260 81 V1 -381 -257.5 169 GO002 10547.5 120 257 GO178 9051.5 120 345 SO052 7443.5 120 433 SO140 5947.5 120 82 V2 -254 -257.5 170 GO004 10530.5 260 258 GO180 9034.5 260 346 SO053 7426.5 260 434 SO141 5930.5 260 83 V3 -127 -257.5 171 GO006 10513.5 120 259 GO182 9017.5 120 347 SO054 7409.5 120 435 SO142 5913.5 120 84 V4 0 -257.5 172 GO008 10496.5 260 260 GO184 9000.5 260 348 SO055 7392.5 260 436 SO143 5896.5 260 85 V5 127 -257.5 173 GO010 10479.5 120 261 GO186 8983.5 120 349 SO056 7375.5 120 437 SO144 5879.5 120 86 V6 254 -257.5 174 GO012 10462.5 260 262 GO188 8966.5 260 350 SO057 7358.5 260 438 SO145 5862.5 260 87 V7 381 -257.5 175 GO014 10445.5 120 263 GO190 8949.5 120 351 SO058 7341.5 120 439 SO146 5845.5 120 88 DUM 508 -257.5 176 GO016 10428.5 260 264 GO192 8932.5 260 352 SO059 7324.5 260 440 SO147 5828.5 260 Mar 10,2008 39 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y 441 SO148 5811.5 120 529 SO236 4315.5 120 617 SO324 2819.5 120 705 SO412 1323.5 120 793 SO491 -337.5 120 442 SO149 5794.5 260 530 SO237 4298.5 260 618 SO325 2802.5 260 706 SO413 1306.5 260 794 SO492 -354.5 260 443 SO150 5777.5 120 531 SO238 4281.5 120 619 SO326 2785.5 120 707 SO414 1289.5 120 795 SO493 -371.5 120 444 SO151 5760.5 260 532 SO239 4264.5 260 620 SO327 2768.5 260 708 SO415 1272.5 260 796 SO494 -388.5 260 445 SO152 5743.5 120 533 SO240 4247.5 120 621 SO328 2751.5 120 709 SO416 1255.5 120 797 SO495 -405.5 120 446 SO153 5726.5 260 534 SO241 4230.5 260 622 SO329 2734.5 260 710 SO417 1238.5 260 798 SO496 -422.5 260 447 SO154 5709.5 120 535 SO242 4213.5 120 623 SO330 2717.5 120 711 SO418 1221.5 120 799 SO497 -439.5 120 448 SO155 5692.5 260 536 SO243 4196.5 260 624 SO331 2700.5 260 712 SO419 1204.5 260 800 SO498 -456.5 260 449 SO156 5675.5 120 537 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Preliminary Spec. for NT39016D TFT LCD Driver Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y Pad No. Name X Y 881 SO579 -1833.5 120 969 SO667 -3329.5 120 1057 SO755 -4825.5 120 1145 SO843 -6321.5 120 1233 SO931 -7817.5 120 882 SO580 -1850.5 260 970 SO668 -3346.5 260 1058 SO756 -4842.5 260 1146 SO844 -6338.5 260 1234 SO932 -7834.5 260 883 SO581 -1867.5 120 971 SO669 -3363.5 120 1059 SO757 -4859.5 120 1147 SO845 -6355.5 120 1235 SO933 -7851.5 120 884 SO582 -1884.5 260 972 SO670 -3380.5 260 1060 SO758 -4876.5 260 1148 SO846 -6372.5 260 1236 SO934 -7868.5 260 885 SO583 -1901.5 120 973 SO671 -3397.5 120 1061 SO759 -4893.5 120 1149 SO847 -6389.5 120 1237 SO935 -7885.5 120 886 SO584 -1918.5 260 974 SO672 -3414.5 260 1062 SO760 -4910.5 260 1150 SO848 -6406.5 260 1238 SO936 -7902.5 260 887 SO585 -1935.5 120 975 SO673 -3431.5 120 1063 SO761 -4927.5 120 1151 SO849 -6423.5 120 1239 SO937 -7919.5 120 888 SO586 -1952.5 260 976 SO674 -3448.5 260 1064 SO762 -4944.5 260 1152 SO850 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-3006.5 260 1038 SO736 -4502.5 260 1126 SO824 -5998.5 260 1214 SO912 -7494.5 260 1302 GO171 -9102.5 260 951 SO649 -3023.5 120 1039 SO737 -4519.5 120 1127 SO825 -6015.5 120 1215 SO913 -7511.5 120 1303 GO169 -9119.5 120 952 SO650 -3040.5 260 1040 SO738 -4536.5 260 1128 SO826 -6032.5 260 1216 SO914 -7528.5 260 1304 GO167 -9136.5 260 953 SO651 -3057.5 120 1041 SO739 -4553.5 120 1129 SO827 -6049.5 120 1217 SO915 -7545.5 120 1305 GO165 -9153.5 120 954 SO652 -3074.5 260 1042 SO740 -4570.5 260 1130 SO828 -6066.5 260 1218 SO916 -7562.5 260 1306 GO163 -9170.5 260 955 SO653 -3091.5 120 1043 SO741 -4587.5 120 1131 SO829 -6083.5 120 1219 SO917 -7579.5 120 1307 GO161 -9187.5 120 956 SO654 -3108.5 260 1044 SO742 -4604.5 260 1132 SO830 -6100.5 260 1220 SO918 -7596.5 260 1308 GO159 -9204.5 260 957 SO655 -3125.5 120 1045 SO743 -4621.5 120 1133 SO831 -6117.5 120 1221 SO919 -7613.5 120 1309 GO157 -9221.5 120 958 SO656 -3142.5 260 1046 SO744 -4638.5 260 1134 SO832 -6134.5 260 1222 SO920 -7630.5 260 1310 GO155 -9238.5 260 959 SO657 -3159.5 120 1047 SO745 -4655.5 120 1135 SO833 -6151.5 120 1223 SO921 -7647.5 120 1311 GO153 -9255.5 120 960 SO658 -3176.5 260 1048 SO746 -4672.5 260 1136 SO834 -6168.5 260 1224 SO922 -7664.5 260 1312 GO151 -9272.5 260 961 SO659 -3193.5 120 1049 SO747 -4689.5 120 1137 SO835 -6185.5 120 1225 SO923 -7681.5 120 1313 GO149 -9289.5 120 962 SO660 -3210.5 260 1050 SO748 -4706.5 260 1138 SO836 -6202.5 260 1226 SO924 -7698.5 260 1314 GO147 -9306.5 260 963 SO661 -3227.5 120 1051 SO749 -4723.5 120 1139 SO837 -6219.5 120 1227 SO925 -7715.5 120 1315 GO145 -9323.5 120 964 SO662 -3244.5 260 1052 SO750 -4740.5 260 1140 SO838 -6236.5 260 1228 SO926 -7732.5 260 1316 GO143 -9340.5 260 965 SO663 -3261.5 120 1053 SO751 -4757.5 120 1141 SO839 -6253.5 120 1229 SO927 -7749.5 120 1317 GO141 -9357.5 120 966 SO664 -3278.5 260 1054 SO752 -4774.5 260 1142 SO840 -6270.5 260 1230 SO928 -7766.5 260 1318 GO139 -9374.5 260 967 SO665 -3295.5 120 1055 SO753 -4791.5 120 1143 SO841 -6287.5 120 1231 SO929 -7783.5 120 1319 GO137 -9391.5 120 968 SO666 -3312.5 260 1056 SO754 -4808.5 260 1144 SO842 -6304.5 260 1232 SO930 -7800.5 260 1320 GO135 -9408.5 260 Mar 10,2008 41 120 260 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. Preliminary Spec. for NT39016D TFT LCD Driver Pad No. Name X Y 1321 GO133 -9425.5 120 1322 GO131 -9442.5 260 1323 GO129 -9459.5 120 1324 GO127 -9476.5 260 1325 GO125 -9493.5 120 1326 GO123 -9510.5 260 1327 GO121 -9527.5 120 1328 GO119 -9544.5 260 1329 GO117 -9561.5 120 1330 GO115 -9578.5 260 1331 GO113 -9595.5 120 1332 GO111 -9612.5 260 1333 GO109 -9629.5 120 1334 GO107 -9646.5 260 1335 GO105 -9663.5 120 1336 GO103 -9680.5 1337 GO101 -9697.5 120 1338 GO99 -9714.5 260 1339 GO97 -9731.5 120 1340 GO95 -9748.5 260 1341 GO93 -9765.5 120 1342 GO91 -9782.5 260 1343 GO89 -9799.5 120 1344 GO87 -9816.5 260 1345 GO85 -9833.5 120 1346 GO83 -9850.5 260 1347 GO81 -9867.5 120 1348 GO79 -9884.5 260 1349 GO77 -9901.5 120 1350 GO75 -9918.5 260 1351 GO73 -9935.5 120 1352 GO71 -9952.5 260 1353 GO69 -9969.5 1354 GO67 -9986.5 260 1355 GO65 -10003.5 120 1356 GO63 -10020.5 260 1357 GO61 -10037.5 120 1358 GO59 -10054.5 260 1359 GO57 -10071.5 120 1360 GO55 -10088.5 260 1361 GO53 -10105.5 120 1362 GO51 -10122.5 260 1363 GO49 -10139.5 120 1364 GO47 -10156.5 260 1365 GO45 -10173.5 120 1366 GO43 -10190.5 260 1367 GO41 -10207.5 120 1368 GO39 -10224.5 260 1369 GO37 -10241.5 120 1370 GO35 -10258.5 260 1371 GO33 -10275.5 120 1372 GO31 -10292.5 260 1373 GO29 -10309.5 120 1374 GO27 -10326.5 260 1375 GO25 -10343.5 120 1376 GO23 -10360.5 260 1377 GO21 -10377.5 120 1378 GO19 -10394.5 260 1379 GO17 -10411.5 120 1380 GO15 -10428.5 260 1381 GO13 -10445.5 120 1382 GO11 -10462.5 260 1383 GO9 -10479.5 120 1384 GO7 -10496.5 260 1385 GO5 -10513.5 120 1386 GO3 -10530.5 260 1387 GO1 -10547.5 120 1388 DUM -10581.5 260 Mar 10,2008 260 120 42 Version 0.7 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information.