RENESAS HD74ALVCH16501

HD74ALVCH16501
18-bit Universal Bus Transceivers with 3-state Outputs
REJ03D0036-0300Z
(Previous ADE-205-168A(Z))
Rev.3.00
Oct.02.2003
Description
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and
LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a
high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the low to high
transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in
the high impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and
CLKBA. The output enables are complementary (OEAB is active high, and OEBA is active low). Active
bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
Rev.3.00, Oct.02.2003, page 1 of 11
HD74ALVCH16501
Function Table *3
Inputs
Output B
OEAB
LEAB
CLKAB
A
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B0 *1
H
L
L
X
B0 *2
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Output level before the indicated steady state input conditions were established, provided that
CLKAB was high before LEAB went low.
3. A to B data flow is show; B to A flow is similar but uses OEBA, LEBA, and CLKBA.
Rev.3.00, Oct.02.2003, page 2 of 11
HD74ALVCH16501
Pin Arrangement
OEAB 1
56 GND
LEAB 2
55 CLKAB
54 B1
A1 3
53 GND
GND 4
A2 5
52 B2
A3 6
VCC 7
51 B3
A4 8
49 B4
A5 9
48 B5
A6 10
47 B6
50 VCC
GND 11
46 GND
A7 12
45 B7
A8 13
44 B8
A9 14
43 B9
A10 15
42 B10
A11 16
41 B11
A12 17
40 B12
GND 18
39 GND
A13 19
38 B13
A14 20
37 B14
A15 21
36 B15
VCC 22
35 VCC
A16 23
34 B16
A17 24
33 B17
GND 25
32 GND
A18 26
31 B18
OEBA 27
30 CLKBA
LEBA 28
29 GND
(Top view)
Rev.3.00, Oct.02.2003, page 3 of 11
HD74ALVCH16501
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
–0.5 to VCC +0.5
Conditions
Except I/O ports
I/O ports
Output voltage *1, 2
VO
–0.5 to VCC +0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
TSSOP
±100
Maximum power dissipation
*3
at Ta = 55°C (in still air)
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended DC Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
IOH
—
–12
mA
—
–12
—
–24
—
12
—
12
VCC = 2.7 V
—
24
VCC = 3.0 V
Low level output current
IOL
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.3.00, Oct.02.2003, page 4 of 11
Conditions
VCC = 2.3 V
HD74ALVCH16501
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
To seventeen other channels
Rev.3.00, Oct.02.2003, page 5 of 11
54
B1
HD74ALVCH16501
Electrical Characteristics
(Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Min
Max
Unit
Input voltage
VIH
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
VIL
Output voltage
VOH
IOH = –100 µA
Min to Max VCC–0.2
—
2.3
2.0
—
IOH = –6 mA, VIH = 1.7 V
2.3
1.7
—
IOH = –12 mA, VIH = 1.7 V
2.7
2.2
—
IOH = –12 mA, VIH = 2.0 V
3.0
2.4
—
IOH = –12 mA, VIH = 2.0 V
3.0
2.0
—
IOH = –24 mA, VIH = 2.0 V
Min to Max —
0.2
IOL = 100 µA
2.3
—
0.4
IOL = 6 mA, VIL = 0.7 V
2.3
—
0.7
IOL = 12 mA, VIL = 0.7 V
2.7
—
0.4
IOL = 12 mA, VIL = 0.8 V
3.0
—
0.55
IOL = 24 mA, VIL = 0.8 V
IIN
3.6
—
±5
IIN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
VOL
Input current
V
Test Conditions
µA
VIN = VCC or GND
3.6
—
±500
Off state output current *2
IOZ
3.6
—
±10
µA
VIN = 0 to 3.6 V
VOUT = VCC or GND
Quiescent supply current
ICC
3.6
—
40
µA
VIN = VCC or GND
∆ICC
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6) V,
other inputs at VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. For I/O ports, the parameter IOZ includes the input leakage current.
Rev.3.00, Oct.02.2003, page 6 of 11
HD74ALVCH16501
Switching Characteristics
(Ta = 40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
Maximum clock frequency
fmax
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
tPLH
2.5±0.2
1.2
—
4.8
tPHL
2.7
—
—
4.5
3.3±0.3
1.0
—
3.9
2.5±0.2
1.6
—
5.7
2.7
—
—
5.3
3.3±0.3
1.3
—
4.6
2.5±0.2
1.7
—
6.1
2.7
—
—
5.6
3.3±0.3
1.4
—
4.9
tZH
2.5±0.2
1.1
—
5.8
tZL
2.7
—
—
5.3
3.3±0.3
1.0
—
4.6
2.5±0.2
1.4
—
6.3
2.7
—
—
6.0
3.3±0.3
1.1
—
5.0
tHZ
2.5±0.2
2.2
—
6.2
tLZ
2.7
—
—
5.7
3.3±0.3
1.4
—
5.0
Propagation delay time
Output enable time
Output disable time
2.5±0.2
2.0
—
5.3
2.7
—
—
4.6
3.3±0.3
1.3
—
4.2
ns
ns
ns
FROM
(Input)
TO
(Output)
A or B
B or A
LE
A or B
CLK
A or B
OEAB
B
OEBA
A
OEAB
B
OEBA
A
Input capacitance
CIN
3.3
—
4.0
—
pF
Control inputs
Output capacitance
CIN / O
3.3
—
8.0
—
pF
A or B ports
Rev.3.00, Oct.02.2003, page 7 of 11
HD74ALVCH16501
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Symbol Vcc=2.5±0.2 V
t PLH / t PHL
OPEN
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Vcc = 2.7 V,
3.3±0.3 V
OPEN
GND
GND
4.6 V
6.0 V
Note: 1. C L includes probe and jig capacitance.
Rev.3.00, Oct.02.2003, page 8 of 11
HD74ALVCH16501
• Waveforms – 1
tr
tf
VIH
90 %
Vref
90 %
Input
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
Rev.3.00, Oct.02.2003, page 9 of 11
HD74ALVCH16501
• Waveforms – 3
Output
Control
tf
tr
90 %
Vref
VIH
90 %
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.3.00, Oct.02.2003, page 10 of 11
HD74ALVCH16501
Package Dimensions
As of January, 2003
14.0
14.2 Max
56
Unit: mm
6.10
29
1
*0.19 ± 0.05
0.50
28
0.08 M
1.0
8.10 ± 0.20
0.65 Max
*Ni/Pd/Au plating
Rev.3.00, Oct.02.2003, page 11 of 11
0.10 ± 0.05
0.10
*0.15 ± 0.05
1.20 Max
0˚ – 8˚
0.50 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-56DAV
—
—
0.23 g
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