RENESAS HD74ALVCH162830

HD74ALVCH162830
1-bit to 2-bit Address Driver with 3-state Outputs
REJ03D0040-0200Z
(Previous ADE-205-197(Z))
Rev.2.00
Oct.02.2003
Description
This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V VCC operation. To ensure the high
impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold
circuitry is provided to hold unused or floating inputs at a valid logic level. All outputs, which are designed
to sink up to 12 mA, include equivalent 26 Ω resistors to reduce overshoot and undreshoot.
Features
•
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±12 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26 Ω series resistors, so no external resistors are required
Rev.2.00, Oct.02.2003, page 1 of 10
HD74ALVCH162830
Function Table
Inputs
Outputs
OE1
OE2
A
1Yn
2Yn
L
H
H
H
Z
L
H
L
L
Z
H
L
H
Z
H
H
L
L
Z
L
L
L
H
H
H
L
L
L
L
L
H
H
X
Z
Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
Rev.2.00, Oct.02.2003, page 2 of 10
HD74ALVCH162830
Pin Arrangement
2Y2
1Y2
GND
2Y1
1Y1
VCC
A1
A2
GND
A3
A4
GND
A5
A6
VCC
A7
A8
GND
A9
OE1
OE2
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
GND
A17
A18
VCC
2Y18
1Y18
GND
2Y17
1Y17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
(Top view)
Rev.2.00, Oct.02.2003, page 3 of 10
1Y3
2Y3
GND
1Y4
2Y4
VCC
1Y5
2Y5
GND
1Y6
2Y6
GND
1Y7
2Y7
VCC
1Y8
2Y8
GND
1Y9
2Y9
1Y10
2Y10
GND
1Y11
2Y11
VCC
1Y12
2Y12
GND
1Y13
2Y13
GND
1Y14
2Y14
VCC
1Y15
2Y15
GND
1Y16
2Y16
HD74ALVCH162830
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VCC
–0.5 to 4.6
V
Input voltage *1
VI
–0.5 to 4.6
V
VO
–0.5 to VCC +0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
ICC or IGND
±100
mA
Maximum power dissipation
*3
at Ta = 55°C (in still air)
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Output voltage
*1, 2
Conditions
TVSOP
Notes: Stresses beyond those listed under “absolute
e maximum ratings” may cause permanent damage to
the device. These are stress ratings only, and functional
unctional operation of the device at these or any
other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
IOH
—
–6
mA
—
–8
VCC = 2.7 V
—
–12
VCC = 3.0 V
—
6
—
8
VCC = 2.7 V
—
12
VCC = 3.0 V
Low level output current
IOL
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.2.00, Oct.02.2003, page 4 of 10
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH162830
Logic Diagram
OE2
21
OE1
20
5
A1
1Y1
7
4
2Y1
To seventeen other channels
nnels
Rev.2.00, Oct.02.2003, page 5 of 10
HD74ALVCH162830
Electrical Characteristics
(Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Max
Unit
Input voltage
VIH
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
2.3 to 3.6
VCC–0.2
—
2.3
1.9
—
IOH = –4 mA, VIH = 1.7 V
2.3
1.7
—
IOH = –6 mA, VIH = 1.7 V
3.0
2.4
—
IOH = –6 mA, VIH = 2.0 V
2.7
2.0
—
IOH = –8 mA, VIH = 2.0 V
3.0
2.0
—
IOH = –12 mA, VIH = 2.0 V
2.3 to 3.6
—
0.2
IOL = 100 µA
2.3
—
0.4
IOL = 4 mA, VIL = 0.7 V
2.3
—
0.55
IOL = 6 mA, VIL = 0.7 V
3.0
—
0.55
IOL = 6 mA, VIL = 0.8 V
2.7
—
0.6
IOL = 8 mA, VIL = 0.8 V
VIL
Output voltage
VOH
VOL
V
Test Conditions
IOH = –100 µA
3.0
—
0.8
IIN
3.6
—
±5
IIN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V *1
IOZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current ICC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6) V,
other inputs at VCC or GND
Input current
Off state output current
∆IICC
Note:
IOL = 12 mA, VIL = 0.8 V
µA
VIN = VCC or GND
1. This is the bus hold maximum dynamic current required to switch the input from one state to
another.
Rev.2.00, Oct.02.2003, page 6 of 10
HD74ALVCH162830
Switching Characteristics
(Ta = –40 to 85°C)
Item
Symbol VCC (V)
Propagation delay time
tPLH
tPHL
Output enable time
Output disable time
Input capacitance
Output capacitance
Min
Typ
Max
Unit
FROM
(Input)
TO
(Output)
2.5±0.2 1.2
—
3.8
ns
A
Y
2.7
—
4.0
ns
OE
Y
ns
OE
Y
pF
Control inputs
—
3.3±0.3 1.7
—
3.5
tZH
2.5±0.2 1.0
—
5.7
tZL
2.7
—
5.7
3.3±0.3 1.0
—
4.8
tHZ
2.5±0.2 1.5
—
6.2
tLZ
2.7
—
5.4
CIN
CO
—
—
3.3±0.3 1.7
—
5.2
3.3
—
4.5
—
3.3
—
5.0
—
3.3
—
7.5
—
Rev.2.00, Oct.02.2003, page 7 of 10
Data inputs
pF
HD74ALVCH162830
Test Circuit
See the table below
500 Ω
S1
OPEN
GND
*1
500 Ω
CL
Load Circuit for Outputs
Symbol
t PLH / t PHL
Note:
1.
= 2.7 V,
Vc= 2.5±0.2 V Vcc
3.3±0.3 V
OPEN
t ZH/ t HZ
t ZL / t LZ
GND
GND
2 × VCC
6.0 V
CL
30 pF
50 pF
CL includes probe and jig capacitance.
Rev.2.00, Oct.02.2003, page 8 of 10
OPEN
HD74ALVCH162830
Waveforms - 1
tf
tr
Input
VIH
90 %
Vref
90 %
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
Waveforms - 2
tr
tf
90 %
Vref
Output
Control
VIH
90 %
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
Vref1
VOL
t HZ
VOH
Vref2
Vref
≈VOL1
TEST
VIH
Vref
Vref1
Vref2
VOH1
VOL1
Notes:
1.
2.
3.
4.
Vcc=2.5±0.2V
Vcc = 2.7 V,
3.3±0.3 V
VCC
2.7 V
1/2 VCC
1.5 V
VOL +0.15 V VOL +0.3 V
VOH–0.15 V VOH–0.3 V
VCC
3.0 V
GND
GND
All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct.02.2003, page 9 of 10
HD74ALVCH162830
Package Dimensions
As of January, 2003
17.0
17.2 Max
41
6.10
80
Unit: mm
1
40
0.40
0.07 M
1.0
8.10 ± 0.20
0.08
*Ni/Pd/Au plating
Rev.2.00, Oct.02.2003, page 10 of 10
0˚ – 8˚
*0.15 ± 0.05
1.20 Max
0.85 Max
0.10 ± 0.05
*0.18 ± 0.05
0.50 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-80DV
—
—
0.27 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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