HS9403

H S9403
16-Channel, 12-Bit D ata Acquisition System
D ata Converter Line
FEATURES
• M ultiplexer, instrumentation amp, S/H, A /D and
control logic in a 62-pin package
• Three state output buffer
• Instrumentation amp with selectable gain
ranging 1 to 1,0 0 0
• Single-ended (-16) and differential (-8) inputs
• 50 kHz minimum throughput
DESCRIPTION
The HS9403-8 and 9403-16 provide complete 12-bit
data acquisition functionality in a single, 62-pin
package. The 9403 includes 8- or 16-channel
multiplexing, a programmable gain instrumentation
amplifier, sample-hold circuit, 10V buffered reference,
12-bit 10- sec A /D and three-state output buffers.
The 9403 is packaged in a 62-pin, hermetically sealed
ceramic package. Temperature ranges available are
0ºC to 70ºC for commercial versions and –55ºC to
+125ºC with M IL-STD-883C screening for military
grades.
The 9403 is flexible enough to accept full-scale input
ranges from ±10 mV to ±10V . Three-state output
buffers allow output data to be accessed in any
combination of three 4-bit bytes. Expansion to 32
single-ended or 16 differential inputs can be achieved
with the addition of only 2 ICs.
FUNCTIONAL DIAGRAM
M UX
ENA BLE
(5)
GA IN
SETTING
RESISTOR
(48)
(47)
AMP
INPUT
+
–
(49) (50)
EXTERNA L
HOLD
CA PA CITOR
(45)
(46)
S/H
OUT
(39)
BIPOLA R
INPUT
(38)
OFFSET
(37) A DJUST
CHO(+)/CHO
CH1(+)/CH1
CH2(+)/CH2
CH3(+)/CH3
CH4(+)/CH4
CH5(+)/CH5
CH6(+)/CH6
CH7(+)/CH7
CH0(+)/CH8
CH1(+)/CH9
CH2(+)/CH10
CH3(+)/CH11
CH4(+)/CH12
CH5(+)/CH13
CH6(+)/CH14
CH7(+)/CH15
M UX
A DDRESS
OUTPUTS
A1
A1
A1
A1
(4)
(3)
(2)
(1)
(62)
(61)
(60)
(59)
(58)
(57)
(56)
(55)
(54)
(53)
(52)
(51)
(36) GA IN A DJUST
+
INSTRU.
AMP
–
S/H
16 CHA NNEL
SINGLES
OR
8 CHA NNEL
DIFFERENTIA L
M UX
12 BIT
A /D
CONV ERTER
(12)
(12)
(12)
(12)
M UX A DDRESS
REGISTER
(19) (16) (15) (14) (13) (20)
LOA D RA 1 RA 2 RA 4 RA 8 CLEA R
M UX A DDRESS INPUTS
(8)
(6)
(35)
(34)
(33)
(32)
BIT 1 (M SB)
BIT 2
BIT 3
BIT 4
ENA
BLE
(31)
(BITS 1-4)
3-STA TE
BUFFER
(30)
(29)
(28)
(27)
3-STA TE
BUFFER
(25)
(24)
(23)
(22)
BIT 5
BIT 6
BIT 7
BIT 8
(26) ENA BLE
(BITS 5-8)
BIT 9
BIT 10
BIT 11
BIT 12 (LSB)
ENA
BLE
(21)
(BITS 9-12)
(7)
TIM ING A ND
CONTROL LOGIC
STROBE R DELA Y
3-STA TE
BUFFER
+ 10V REF
(41)
A NG
SIGNA L
GND
(41)
A NG
POW ER
GND
(17)
DIG
GND
(18)
+5 V DC
EOC
(40) +10V
REF OUT
(44)
– 15 V DC
165Cedar Hill Street,Marlborough,MA01752 Tel:508.485.6350 Fax: 508.485.5168
www.SpectrumMicrowave.com
(43)
+15 V DC
HS9403
SPECIFICATIO N S
(Typical @ + 25ºC and nominal power supplies unless otherwise specified)
A NA LOG INPUTS
Number of Input Channels
HS 9403-8
HS 9403-16
Input V oltage Range 1
Unipolar
Bipolar
Common M ode V oltage Range
CM RR
G=1 (1 kHz)
G=1000 (60 Hz)
Input Bias Current
Bias Current Drift
Input Offset Current
Offset Current Drift
Input Offset V oltage
Offset V oltage Drift
V oltage Noise (RTI)2
G=1
G=1000
Input Resistance
Input Capacitance
OFF Channel
ON Channel 9403-8
9403-16
DIGITA L INPUTS
Logic Levels
Logic “ 1”
Logic “ 0”
Logic Loading
Logic “ 1”
Logic “ 0”
STA TIC PERFORM A NCE 4
No M issing Codes
Integral Linearity Error
Differential Linearity Error
Unipolar Offset Errors
Bipolar Zero Error 5
HS 9403
8 Differential
16 Single-Ended
0 to +10V
±10V
± 11V min
74 dB
110 dB
±50 pA typ
Doubles every 10ºC
±25 pA typ.
Doubles every 10ºC
±2 mV
(20 + 7G)µ V /ºC
150 µ V (RM S) 3
1.6 µ V (RM S) 3
10 12
10 pF
50 pF
100 pF
+2V min,+5.5V max
–0.3V min,+0.8V max
20 µA
–0.2 mA
Guaranteed over operating
temperature range
±1/4LSB typ. ±1/2LSB max
±1/4LSB typ. ±1/2LSB max
±0.025% FSR typ.
±0.1% FSR 6 max
±0.025% FSR typ.
±0.1% FSR 6 max
Gain Error 5
±0.025% typ. ±0.2% max
+ 10V REFERENCE
Output V oltage
Output V oltage Drift
+ 10.000V ± 10 mV
± 3 ppm/ºC typ, ± 8 ppm/ºC max
DY NA M IC PERFORM A NCE
Throughput Rate
50K Hz min
S/H A cquisition Time 7.11
9µsec typ. 10µsec max.
A /D Conversion Time
10µsec max.
A perture Delay
25 nsec typ.
Sample-Hold Droop
0.1µV /µsec
Feedthrough (@ 1 kHz) 8.11
±0.01% max.
M UX Crosstalk (@1 kHz) 11
–80dB min.
Strobe Command Pulse W idth 11
40 nsec min.
Setup time Digital Inputs to Strobe 11 50 nsec min.
Hold Time Digital Inputs From Strobe 11 50 nsec max.
ENA BLE
Tri-State to V alid 11
40 nsec max.
V alid to Teh-State 11
30 nsec max.
DRIFT CHA RA CTERISTICS 10
Integral Linearity
Differential Linearity
Unipolar Offset
Bipolar Zero
Gain
±1ppm/ºC
±1ppm/ºC
±3ppm/ºC
±3ppm/ºC
±8ppm/ºC
typ,
typ,
typ,
typ,
typ,
±2 ppm/ºC max
±2 ppm/ºC max
±7 ppm/ºC max
±10 ppm/ºC max
±20ppm/ºC max
DIGITA L OUTPUTS
Logic Levels
Logic " 1"
Logic " 0"
Logic Coding
Unipolar Ranges
Bipolar Ranges
Fanout
2.4V min
0.4V max
Straight binary
Offset binary
5 TTL Loads
POW ER SUPPLIES
Power Supply Range
±15V
+5V
Current Drains
+15V
–15V
+5V
Power Dissipation
P.S.R.R. for 3 supplies
P.S.R.R.(+10V ref)
55 mA typ. 60 mA max
60 mA typ, 68 mA max
32 mA typ, 45 mA max
1.4W typ.2.0W max
0.005% /% max
0.01 % /% max
TEM PERA TURE RA NGE
Operating C-Option
Operating B-Option
Storage
0ºCto +70ºC
–55ºCto +125ºC
–65ºCto +150ºC
A BSOLUTE M A XIM UM RA TINGS
+V CC
–V CC
V DD
A nalog Input Channels
Digital Inputs
–0.5V to +18V
+ 0.5V to -18V
–0.3 to +7V
±35V
–0.3toV DD +0.3V
± 14.5V to ± 15.5V
+ 4.5V to +5.5V
Notes:
1. For unity gain.
2. Referred to input.
3. M easured at output of S/H.
4. Specifications refer to entire system from M UX input to A /D output
with instrumentation amplifier G= 1.
5. Initial offset and gain errors are adjustable to zero with optional external
6. FSR s full scale range. Unipolar FSR = 10V . Bipolar FSR = 20V . For a 12-bit
system.1 LSB = 0.024% FSR
7. Includes M UX switching and setting time. instrumentation amp unity gain
settling time and S/H acquisition time. Specified for 10V step setting
to 0.01 % FSR
8. M easured at S/H output with S/H in hold mode.
9. Includes M UX address. M UX enable, dear and load inputs.
10.Unipolar 10V FSR is the basis for parts per million specifications.
11.Guaranteed but not tested.
PA CK A GE OUTLINE
2.300 TY P
0.160 TY P
0.200
0.0040
20 SPA CES A T 0.100 EA CH
0.035
TY P
52
0.150
0.250
32
1.250
BOTTOM V IEW
62
0.150
9
SPA CES
A T 0.100
EA CH
1.400
TY P
DOT ON TOP
REFERENCES
PIN 1
1
PIN SPA CING IS 0.100
INCHES ±0.005 NONCUM ULA TIV E
21
M A XIM UM PIN DIM ENSIONS
A RE 0.012 X 0.022 INCHES
Continued on next page.
HS9403
PIN A SSIGNM ENTS
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
FUNCTION
FUNCTION
HS 9403-16
HS 9403-8
CH3 IN
CH3(+)IN
CH2 IN
CH2(+)IN
CH1 IN
CH1(+)IN
CH0 IN
CHO(+)IN
M UX ENA BLE
R DELA Y
EOC
STROBE
A8
A 4 M UX A DDRESS OUT
A2
A1
RA 8
RA 4 M UX A DDRESS IN
RA 2
RA 1
DIGITA L GROUND
+5V
LOA D ENA BLE
CLEA R ENA BLE
ENA BLE (BITS 9-12)
BIT12 OUT(LSB)
BIT 11 OUT
BIT 10 OUT
BIT 9 OUT
ENA BLE (BITS 5.8)
BIT 8 OUT
BIT 7 OUT
BIT 6 OUT
BIT 5 OUT
ENA BLE (BITS 1-4)
BIT 4 OUT
BIT 3 OUT
BIT 2 OUT
BIT 1 OUT (M SB)
GA IN A DJ
OFFSET A DJ
BIPOLA R INPUT
SA M PLE/HOLD OUT
+ 10V REFERENCE OUT
A NA LOG SIGNA L GROUND
A NA LOG POW ER GROUND
+15V
–15V
EXTERNA L HOLD CA P HIGH
EXTERNA L HOLD CA P LOW
R GA IN LOW
R GA IN HIGH
INSTRU. A M P (+) INPUT
INSTRU. A M P (–) INPUT
CH151N
CH7(-)IN
CH14 IN
CH6(-)IN
CH13IN
CH5(-)IN
CH121N
CH4(-)IN
CH11IN
CH3(-)IN
CH10IN
CH2(-)IN
CH9 IN
CH1(-)IN
CH8 IN
CHO(-)IN
CH7 IN
CH7(+)lN
CH6 IN
CH6(+)IN
CH5 IN
CH5(+)IN
CH4 IN
CH4(+)IN
DIGITA L PIN FUNCTIONS
FUNCTION
LOGIC
PIN NO STA TE
DESCRIPTION
M UX ENA BLE
5
“ 0”
“ 1”
Disables internal M UX
Enables internal M UX
EOC
7
“ 0”
8
“ 1”
“ 0” to“ 1”
“ 1” to“ 0”
Signal acquisition cycle in
progress
A /D conversion in progress
Conversion complete
Initiates acquisition and
conversion of analog signal
Output of M UX address
register. Straight binary
coding
Selects M UX for random
address mode. Straight
binary coding
Random address mode
initiated on falling edge of
STROBE
Sequential address mode
Forces M UX address to
CH0 on next falling edge
of STROBE regardless of
LOA D and M UX address
inputs
Enables three-state outputs
bits 9-12
Disables three-state out
puts bits 9-12
Enables three-state outputs
bits 5-8
Disables three-state out
puts bits 5-8
Enables three-state outputs
outputs bits 1-4
Disables three-state out
puts bits 1-4
STROBE
M UX A DDRESS
OUT
9-12
M UX A DDRESS
IN
13-16
LOA D
19
“ 0”
CLEA R
20
“ 1”
“ 0”
ENA BLE
(BITS 9-12)
21
“ 0”
“ 1”
ENA BLE
(BITS 5-8)
26
“ 0”
“ 1”
ENA BLE
(BITS 1-4)
31
“ 0”
“ 1”
A NA LOG PIN FUNCTIONS
FUNCTION
PIN NO.
R DELA Y
6
GA IN A DJUST
OFFSET A DJUST
BIPOLA R INPUT
36
37
38
S/H OUTPUT
+10V REFOUT
EXTERNA L HOLD
CA PA CITOR
39
40
45.46
RGA IN
47.48
INSTRUM ENTA TION
A M P INPUTS
49.50
DESCRIPTION
Connect external resistor to
lengthen S/H acquisition time
when instrumentation A M P is
set for high gain (for normal
operation, R DELA Y tied to
+5V ).
External gain adjust (optional)
External offset adjust(optional)
For unipolar operation (0 to
+ 10V ). connect to pin 39 (S/H
OUT). For Bipolar operation
(± 10V ). connect to pin 40
(+10V REF OUT)
Sample-Hold output
Buffered + 10V reference output
A dd external polypropylene,
polystyrene or teflon hold
capacitor to improve S/H droop
rate (optional)
Optional gain selection point.
R = 20k/(G-1). Leave open for G=1
Use when adding additional
external multiplexers for
expanded single-ended or
differential operation (see
A pplications Information).
Connect pin 50 to analog
common for HS 9403-16
Continued on next page.
HS9403
ORDERING INFORM A TION
M ODEL
NUM BER
TEM PERA TURE
RA NGE
DESCRIPTION
HS 9403C-8
0ºC to +70ºC
8 differential input, 12-bit. data
acqusition system (DA S)
HS9403C-16
0ºC to +70ºC
16 single-ended input, 12-bit, DA S
HS 9403B-8
–55ºCto+125ºC
8 differential input, 12-bit, DA S
M IL-STD-883C
HS9403B-16
–55ºCto+125ºC
16 single-ended input, 12-bit,.
DA S M IL-STD-883C
HS9403C-16
FP
0ºCto+70ºC
16 single-ended input in flat
pack
HS9403B-16
FP
–55ºCto+125ºC
16 single-ended input, in flat
pack. M IL-STD-883C
Specifications subject to change without notice.
Consult factory for application information.