® SDM862 SDM863 SDM872 SDM873 FPO 46% FPO 43% 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS FEATURES ● POWER PLANT MONITORING ● COMPLETE 12-BIT DATA ACQUISITION SYSTEM IN A MINIATURE PACKAGE ● SECURITY SYSTEMS MONITORING ● AUTOMATIC TEST EQUIPMENT ● INPUT RANGES SELECTABLE FOR UNIPOLAR OR BIPOLAR OPERATION 872/3 ● THROUGHPUT RATES: 862/3 8-BIT ACCURACY: 45kHz 67kHz 12-BIT ACCURACY: 33kHz 50kHz DESCRIPTION 16 Single-Ended Inputs: 8 Differential Inputs: 33kHz Throughput Rate: 50kHz Throughput Rate: ● SELECTABLE GAINS OF 1, 10, AND 100 ● FULL MICROPROCESSOR COMPATIBLE INTERFACE ● GUARANTEED NO MISSING CODES OVER TEMPERATURE ● SURFACE-MOUNT OR PIN GRID ARRAY PACKAGE OPTIONS ● HIGH RELIABILITY SCREENED VERSIONS AVAILABLE ● FULL SPECIFICATION OVER THREE TEMPERATURE RANGES: 0 to +70°C, –25 to +85°C, –55 to +125°C ● EVERY UNIT SUPPLIED WITH ELECTRICAL TEST DATA SDM862 SDM863 SDM862 SDM872 SDM872 SDM873 SDM863 SDM873 The SDM components are complete, pin-compatible, data acquisition systems housed in a hermetically sealed 1"-square leadless chip carrier or a 1.1"-square pin grid array. The small package outlines and low power consumption provide an ideal data acquisition solution when space is at a premium. The devices comprise of an input multiplexer, instrumentation amplifier with selectable gains, sample/hold amplifier and A/D converter with microprocessor interface and three-state buffers. The SDM family will accept unipolar or bipolar voltage inputs in the range 0 to +10V, ±5V and ±10V. For lowlevel signals, jumper-selectable gains of 10 or 100 can be applied. The number of input channels can be expanded by the addition of multiplexers. System integration is simplified by the microprocessor interface and the facility of the sample/hold amplifier being controlled directly by the A/D converter. APPLICATIONS ● INDUSTRIAL PROCESS MONITORING ● AIRBORNE SYSTEMS MONITORING ● ENGINE MONITORING ANALOG DIGITAL 8 CH 16 CH MUX S/H INA ADC 12 Bits 8 CH 862/872 863/873 International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1988 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-686F Printed in U.S.A. August, 1993 Input Range Bipolar Offset Reference In Reference Out S/H Output Hold Capacitor S/H Output Amp Output S/H Input Reference Sense Gain Select + – – CH0 + 16 Single-Ended or 8 Differential Input Multiplexer + CH7 CH0 – 12-Bit A/D Converter S/H Amp Inst Amp – Digital Data Outputs S/H Common S/H Control Enable *(Output MUX Minus) Only on SDM863/873 Data Mode Byte Select Chip Select Chip Enable Read/Convert Status CH7 Input Channel Select CH 15 Input Amp Output MUX* SDM863, SDM873 or SDM862, SDM872 CH0 SPECIFICATIONS ELECTRICAL At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. All grades are burned-in at +125°C for 48 hours min. SDM862/863/872/873 J, A, R PARAMETER MIN TYP SDM862/863/872/873 K, B, S MAX RESOLUTION MIN TYP 12 MAX UNITS * Bits INPUT ANALOG Voltage Ranges: Bipolar Unipolar Input Impedance: On Channel Off Channel Input Capacitance: On Channel Off Channel CMRR (20VDC to 1kHz) Crosstalk (20Vp-p, 1kHz) (1) Feedthrough (at 1kHz) (1) Offset (channel to channel) G = 1 (2) Input Bias Current/Channel Input Voltage Range (3) DIGITAL (7, 8) MUX Input Channel Select: Logic ‘1’ Logic ‘0’ MUX Input: Logic High Logic Low S/H Command: Logic ‘1’ Logic ‘0’ ADC Section: Logic ‘1’ Logic ‘0’ ±5, ±10 0-10 80 +10 –10 1010 1010 20 20 85 –85 –85 30 1 +11 –15 * –80 –80 100 5 * * 5 5 30 30 4.0 * * * * * * * * * * * * * * * * * * * * µA µA V V nA µA µA µA ±0.012 * %FSR %FSR * * % % mV mV * * mVp-p µV/ms 15 25 35 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C * * * 0.8 0.2 5 30 10 10 * * * V V Ω Ω pF pF dB dB dB µV nA V V TRANSFER CHARACTERISTICS ACCURACY Integral Linearity (4) Differential Linearity (4) No Missing Codes Gain Error (5): G = 1 G = 100 Unipolar Offset Error (5) Bipolar Offset Error (5) Noise Error (Measured at S/H Output) G = 1 Droop Rate Temperature Coefficients: Unipolar Offset Bipolar Offset Full-Scale Calibration ±0.024 ±0.024 Over Operating Temperature Range 0.5 0.9 16 50 0.5 50 1 500 20 30 60 ® SDM862/863/872/873 2 * * * * SPECIFICATIONS ELECTRICAL At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. SDM862/863/872/873 J, A, R PARAMETERS SDM862/863/872/873 K, B, S MIN TYP MAX MIN TYP MAX UNITS 9 9 20 12 50 2 25 15 * * * * * * * * µs µs ns ns 22 28 * * kHz kHz 33 50 * * kHz kHz * * µs µs µs µs SYSTEM TIMINGS ADC Conversion Time: SDM862/SDM863 SDM872/SDM873 S/H Aperture Delay S/H Aperture Uncertainty TIMING Throughput (Serial Mode) SDM862/SDM863 SDM872/SDM873 (Overlap Mode): SDM862/SDM863 SDM872/SDM873 MULTIPLEXER (6) Switching Time (between channels) Settling Time (10V step to 0.02%) Enable Time ‘ON’ ‘OFF’ INSTRUMENTATION AMPLIFIER (6) Settling Time (20V step to 0.01%) G=1 G = 10 G = 100 Slew Rate +1.5 2.5 1 0.25 12 S/H AMPLIFIER (6) Acquisition (10V step to 0.01%) Aperture Delay Hold Mode Settling Time Slew Rate * * * * 2 0.5 5 3 4 17 12.5 7.5 7.5 * 5 50 1.5 10 * * * * * * * µs µs µs V/µs µs ns µs V/µs * * * * OUTPUT DIGITAL DATA Output Codes: Unipolar Bipolar Logic Levels: Logic 0 (Sink = 1.6mA) Logic 1 (Source = 500µA) Leakage (Data Bits Only), High-Z State +2.4 –5 0.1 Unipolar Straight Binary (USB) Bipolar Offset Binary (BOB) +0.4 * +5 * * * * V V µA * * * * * * * * * * * * VDC VDC mA mA mA mW * * * * °C °C °C °C POWER SUPPLY REQUIREMENTS Rated Voltage: Analog (±VCC) Digital (VDD) Supply Drain: +15V –15V +5V Power Dissipation 14.25 4.5 15 5 13 22 11 580 15.75 5.5 22 30 15 855 * * 70 +85 +125 +150 * * * * TEMPERATURE RANGE Operating Temperature Range JH, KH/JL, KL AH, BH/AL, BL RH, SH/RL, SL Storage Temperature Range 0 –25 –55 –65 * Specification same as SDM862/863/872/873J, A, R grades. NOTES: (1) Measured at the same and hold output. (2) Measured with all input channels grounded. (3) The range of voltage on any input with respect to common over which accuracy and leakage current is guaranteed. (4) Applicable over full operating temperature range. NO MISSING CODES GUARANTEED OVER TEMPERATURE RANGE. (5) Adjustable to zero using external potentiometer or select-on-test resistor. (6) Specifications are at +25°C and measured at 50% level of transition. (7) When using TTL drivers a 1kΩ pull-up resistor should be used. (8) Muxes operate in a break-before-make manner. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 SDM862/863/872/873 ABSOLUTE MAXIMUM RATINGS(1) DIGITAL TIMING SYMBOL PARAMETER CONVERT MODE tdsc Status Delay from CE thec CE Pulse Width tssc CS to CE Setup thsc CS Low During CE High tsrc R/C to CE Setup thrc R/C Low During CE High tsac Byte Select to CE Setup thac Byte Selected Valid During CE High tc 86X Conversion Time: 12 Bit Cycle 8 Bit Cycle tc 87X Conversion Time: 12 Bit Cycle 8 Bit Cycle READ MODE tdd Access Time from CE thd Data Valid after CE Low thl Output Float Delay tssr CS to CE Setup tsrr R/C to CE Setup tsar Byte Select to CE Setup thsr CS Valid after CE Low thrr R/C High after CE Low thar Byte Select Valid after CE Low ths 86X Status Delay after Data Valid ths 87X Status Delay after Data Valid MIN TYP MAX UNITS 100 30 20 20 0 20 0 20 20 13 12 8 200 50 50 50 50 50 0 50 9 6 9 6 75 35 100 0 0 25 0 0 25 500 300 150 25 50 0 50 0 0 50 100 100 25 17 15 10 150 1000 600 +VCC to ACOM .................................................................... –0.5V to +16V –VCC to ACOM ....................................................................... +0.5 to –16V +VDD to DCOM ................................................................... –0.5V to +7.0V Analog Input Signal Range ................................ +VCC +20V to –VCC –20V Digital Input Signal ............................................................... –0.5V to +VDD ACOM to DCOM .................................................................................. ±1V ns ns ns ns ns ns ns ns µs µs µs µs NOTE: (1) Absolute maximum ratings are limiting values applied individually, beyond which the serviceability of the circuit may be impaired. Functions operation under any of these conditions is not necessarily implied. /QM HIGH RELIABILITY SCREENING High Power Internal Visual Inspection .......................................... Burr-Brown Spec. QC2010 Stabilization Bake ............................................................. 24Hr at +150°C Temperature Cycling ...................................... 10 Cycles –65°C to +150°C Constant Acceleration .......................................................... 30kG, Y1 axis Hermeticity Fine Leak ................................................. Helium 5 x 10–8cc/s Hermeticity Gross Leak ......................................................... Fluorocarbon Burn-In ............................................................................ 160Hr at +125°C ns ns ns ns ns ns ns ns ns ns ns CONVERSION CYCLE TIMING READ CYCLE TIMING t HEC CE CE tSSC tSSR CS tSRC tHSC R/C tHRR R/C tSRR tHRC Byte Select tHSR CS Byte Select tSAC tHAR tSAR tHAC STS STS tDSC DB11– DBO tC High Impedance tHS DB11– DBO High-Z tDD ® SDM862/863/872/873 4 tHD Data Valid tHL ORDERING INFORMATION(1) LCC, PGA Accuracy Package (% FSR) Product Input SDM862J SDM862K SDM862A SDM862B SDM862R SDM862S 16SE 16SE 16SE 16SE 16SE 16SE L,H L,H L,H L,H L,H L,H SDM872J SDM872K SDM872A SDM872B SDM872R SDM872S 16SE 16SE 16SE 16SE 16SE 16SE L,H L,H L,H L,H L,H L,H Throughput Temperature Range (°C) Product Input LCC, PGA Accuracy Package (% FSR) ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 33kHz 33kHz 33kHz 33kHz 33kHz 33kHz 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 SDM863J SDM863K SDM863A SDM863B SDM863R SDM863S 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF L, H L, H L, H L, H L, H L, H ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 50kHz 50kHz 50kHz 50kHz 50kHz 50kHz 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 SDM873J SDM873K SDM873A SDM873B SDM873R SDM873S 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF L,H L,H L,H L,H L,H L,H Throughput Temperature Range (°C) ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 33kHz 33kHz 33kHz 33kHz 33kHz 33kHz 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 50kHz 50kHz 50kHz 50kHz 50kHz 50kHz 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 NOTE: (1) 16 single-ended inputs, LCC package, with accuracy of 0.24% FSR. Temp Range of 0°C to +70°C and throughput of 33kHz = SDM862JL. PACKAGE INFORMATION PRODUCT PC862/863-1 PC862/863-2 DESCRIPTION PACKAGE DRAWING NUMBER(1) LCC (Socketed) Evaluation PCB(2) PGA Evaluation PCB 907 906 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Socket is MC0068-1. ® 5 SDM862/863/872/873 AMP SENSE NC AMP IN– MUX OUT +/AMP IN+ G100 G10 RG CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 DCOM (1) MUX ADD3 PIN CONFIGURATIONS 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 MUX ADD2 51 1 AMP OUT MUX ADD1 50 2 AMP REF MUX ADD0 49 3 +15V (1) MUX ENABLE 48 4 –15V (1) CH0 47 5 +5V (2) CH1 46 6 STATUS CH2 45 7 D11 CH3 44 8 D10 CH4 43 9 D9 CH5 42 10 D8 CH6 41 11 D7 CH7 40 12 D6 S/H IN 39 13 D5 NC 38 14 D4 S/H OUT 37 15 D3 HOLD CAP 36 16 D2 S/H OUT 35 17 D1 MUX INA PIN GROUPING BY FUNCTION S/H DOTTED LINE SHOWS SUPPLY SEPARATION A/D TOP VIEW SDM862/SDM872 AMP SENSE MUX OUT– AMP IN– MUX OUT +/AMP IN+ G100 G10 RG CH7– CH6– CH5– CH4– CH3– CH2– CH1– D0 DCOM (2) CH0– DCOM (1) –15V (2) ADC IN (20V) NC ADC IN (10V) BIP OFF REF IN ACOM (2) REF OUT +15V (2) CE R/C DATA MODE CS BYTE SELECT S/H CONT S/H COM (2) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 MUX ADD2 51 1 AMP OUT MUX ADD1 50 2 AMP REF MUX ADD0 49 3 +15V (1) MUX ENABLE 48 4 –15V (1) CH0+ 47 5 +5V (2) CH1+ 46 6 STATUS CH2+ 45 7 D11 CH3+ 44 8 D10 TOP VIEW CH4+ 43 9 D9 SDM863/SDM873 CH5+ 42 10 D8 CH6+ 41 11 D7 CH7+ 40 12 D6 S/H IN 39 13 D5 NC 38 14 D4 S/H OUT 37 15 D3 HOLD CAP 36 16 D2 S/H OUT 35 17 D1 MUX INA PIN GROUPING BY FUNCTION S/H DOTTED LINE SHOWS SUPPLY SEPARATION A/D ® SDM862/863/872/873 6 D0 DCOM (2) –15V (2) ADC IN (20V) ADC IN (10V) BIP OFF REF IN ACOM (2) REF OUT +15V (2) CE R/C DATA MODE CS BYTE SELECT S/H CONT S/H COM (2) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 PIN DESIGNATION DEFINITION COMMENTS CH0 to CH15 CH0 to CH7 (+, –) (PINS 40 to 47, 54 to 61) Channel Inputs Analog Inputs (Total 16) for single-ended and differential operation. Unused inputs must be connected to analog common. MUX OUT+/AMP IN+ MULTIPLEXER “HI” OUTPUT On the SDM8X2 this is the multiplexer output. On the SDM8X3 it is the output of the positive selected inputs. It is connected internally to the positive input of the instrumentation amplifier. MUXOUT (Pin 67) MULTIPLEXER “LO” OUTPUT This pin is used on the SDM8X3 only. It should be connected to the negative input of the instrumentation amplifier. AMP IN (Pin 66) Negative input of instrumentation amplifier On the SDM8X2 this should be connected to analog common. On the SDM8X3 it should be connected to Muxout—(Pin 67). (PIN 65) SDM8X2 = SDM862 OR SDM872 AMP OUT (Pin 1) Output of instrumentation amplifier This pin should be connected to the input of the S/H amplifier (Pin 39). AMP SENSE (Pin 68) Output sense line of instrumentation amplifier This pin will normally be connected direct to AMP OUT (Pin 1). AMP REF (Pin 2) Reference for amplifier output This pin will normally be connected to analog common. Care should be taken to minimize tracking and contact resistance to analog common to optimize system accuracy. S/H OUT (Pins 35/37) Output of sample/hold amplifier Two pins are provided to facilitate a guard ring around the hold capacitor pin. These pins should be connected to either ADC in (20V) or ADC in (10V) depending on the desired range. HOLD CAP (Pin 36) Connection for hold capacitor on S/H amplifier The tracking to the hold capacitor should be as short as possible and a guard ring employed using Pins 35 and 37. ADC IN (20V); ADC IN (10V) (Pins 21, 22) Inputs to A/D converter Connect to S/H amplifier output. Use appropriate pin for desired range. RG, G10, G100 (Pins 62, 63, 64) Gain settling pins on instrumentation amplifier For Gain = 1, no connections. For Gain = 10, connect G10 to RG. For Gain = 100, connect G100 to RG. REF OUT (PIN 26) 10V Reference voltage This is the reference voltage for the A/D converter. REF IN, BIP OFF (Pins 24, 23) Reference input and offset input to A/D converter Connect trim potentiometers (or select-on-test resistors) to these pins for unipolar or bipolar operation as shown in Figures 12, 13. S/H IN (Pin 39) Input to sample/hold amplifier Connect to amp out (Pin 1). MUX ENABLE (Pin 48) Multiplex enable/disable Logic ‘1’ on this pin will enable a selected channel on the internal multiplexer. Logic ‘0’ de-selects all channels. MUX ADD0 to MUX ADD3 (Pins 49 to 52) Address inputs for channel selection These address lines select a particular channel as specified in Figure 24. S/H CONT (Pin 33) Track/Hold control on S/H amplifier Logic ‘1’ holds an analog value for conversion by the A/D converter. This line may be controlled by the status (Pin 6) of the converter to simplify external timing control. S/H COM (Pin 34) Reference for S/H logic control Connect to digital common. D0 to D11 (Pins 7 to 18) 3-state digital outputs The 12- or 8-bit result of a conversion is available as output on these pins (D0-LSB, D11-MSB). STATUS (Pin 6) Status of A/D conversion This output is at logic ‘1’ while the internal A/D converter is carrying out a conversion. This pin may be used to directly control the S/H amplifier. CE (Pin 28) Chip enable This input must be at logic ‘1’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). CS (Pin 31) Chip select This input must be at logic ‘0’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). R/C (Pin 29) Read/convert Data can be read when this pin is logic ‘1’ or a conversion can be initiated when this pin is logic ‘0’. This pin is typically connected to the R/W control line of a microprocessor-based system (see Figures 10, 17, 18, 19, 20). DATA MODE (Pin 30) Select 12- or 8-Bit Data When data mode is at logic ‘1’ all 12 output data bits are enabled simultaneously. When data mode is at logic ‘0’ MSBs and LSBs are controlled by byte select (Pin 32). BYTE SELECT (Pin 32) Byte address, short cycle When reading output data, byte select at logic ‘0’ enables the 8 MSBs. Byte select at logic ‘1’ enables the 4 LSBs. The 4 LSBs can therefore be connected to four of the MSB lines for inter-connection to an 8-bit bus. In start convert mode, logic ‘0’ enables a 12-bit conversion while logic ‘1’ will short cycle the conversion to 8 bits (see Figure 10). +15V(1), +15V(2)(Pins 3, 27) Power Supply Connect to +15V supply using decoupling as indicated in Figures 15, 16. –15V(1), –15V(2)(Pins 4, 20) Power Supply Connect to –15V supply using decoupling as indicated in Figures 15, 16. ACOM(2) (Pin 25) Analog Common Analog common connection. Note that a common (including digital common) should be connected together at one point close to the device. DCOM (1) (Pin 53) Reference for MUX logic control. Connect to digital common. +5V (Pin 5) Logic power supply Connect to +5V digital supply line with decoupling as in Figures 15, 16. DCOM(2) (Pin 19) Reference for A/D converter control lines Connect to S/H common at one point close to device. NC (Pin 38) No internal connection ® 7 SDM862/863/872/873 SYSTEM DESCRIPTION to ensure that neither of the differential inputs exceed the maximum input range. Otherwise, signal distortion will result. A return path for the input bias currents must always be provided. This prevents the charging of stray capacitances in applications using floating sources, such as transformers and thermocouples. Multiplexer inputs are protected from overvoltage, as indicated in the electrical specifications, and should be current limited to 20mA. The SDM comprises four circuit elements—an input-protected multiplexer, an instrumentation amplifier, a sample/ hold amplifier, and an analog-to-digital converter. INSTALLATION MULTIPLEXER Where high-speed operation is required and channels require rapid sampling, then it is important to buffer the inputs against the effect of current sharing between the MUX output capacitance and the input filter capacitance. See Figure 2. The SDM family has a choice of input multiplexers (MUX). SDM862 and SDM872: SDM863 and SDM873: 16 single-ended inputs 8 differential inputs On all models, the analog inputs may be expanded using the enable control. See Figure 1. When the enable is at a logic “0,” the internal MUX is disabled, allowing additional multiplexers to be connected in parallel. The limiting factor for the number of additional multiplexers is the cumulative effect of leakage current flowing in the signal source impedance, causing offset errors. MUX Cf Cf Differential inputs will generally eliminate the noise associated with common system grounds, but care must be taken D-Com EN MUX Extern SDM8X2 Out A0 A1 A2 A3 53 A0 A1 A2 A3 A4 49 50 51 52 48 65 All data acquisition systems using a MUX require consideration of the errors that may be introduced by MUX output capacitance. The applications information explains this more fully in the input filtering section. Shown in Figure 3 is an application that demonstrates the flexibility of signal conditioning and gives the opportunity to use a higher bandwidth filter. Diodes shown are low leakage types (1na). The low output impedance of the amplifiers reduces the time taken to charge MUX capacitance CM. D-Com EN INA MUX Extern Out A0 A1 A2 A3 +Out –Out A0 A1 A2 D-Com EN SDM8X3 FIGURE 2. Filter and MUX Capacitance. 66 MUX Intern 53 INSTRUMENT AMPLIFIER The instrument amplifier (INA) presents a very high input impedance to the signal source, eliminating gain errors introduced by voltage divider action between the source output impedance and SDM input impedance. Where the differential models are used, the INA performs the differential to single-ended conversion required to drive the sample/ hold amplifier. Gains may be set by using external jumpers, to values of 1 (no jumper), 10 and 100. For gains other than these presets, the following formula may be used to find an external resistor value to add in series with the G = 10 or G = 100 jumpers. A0 A1 A2 A3 49 50 51 48 65 67 66 MUX Intern INA D-Com EN +Out – Out A0 A1 A2 Rext = FIGURE 1. External Multiplexer Connections for Differential and Single-Ended Operation. 40kΩ G–1 – Ri Where Ri = 4444Ω, G = 10 input. 404Ω, G = 100 input. It should be noted that the internal gain set resistors have a ±20% tolerance and ±20ppm/°C drift. ® SDM862/863/872/873 CM 8 MUX FET Input 10kΩ 10kΩ A1 Cf – Rf Rf 10V + Cf R1 20kΩ 4.44kΩ A3 20kΩ 10V 404Ω Rf Ri R2 10kΩ – A2 10kΩ + FET Input R3 Rf + Cf – FIGURE 5. Increasing Output Amplifier Gain. Rf + Matching of R1 and R3 is required to maintain high common-mode rejection (CMR), R2 sets the gain and may be varied without effect on CMR. Cf – To ensure that the effects of temperature are minimized when altering the gain with external components, it is very important to use low tempco resistors. When connecting the output sense, ensure that series resistance is minimized because resistance present will degrade CMR. +V Rf + Cf CM – –V SETTLING TIME vs GAIN (0.01%, 20V Step) FIGURE 3. Example Application Illustrating Flexible Signal Conditioning. FET Input 10kΩ 10kΩ A1 4.44kΩ Settling Time (µs) –In 10 Sense 20kΩ 5 X10 A3 20kΩ X100 Output 404Ω REXT 0 RG 1 10kΩ A2 +In 10 100 Gain (V/V) Ref 10kΩ FET Input CMR vs FREQUENCY 120 Common-Mode Rejection (dB) FIGURE 4. Use External Gain Set Resistor. Where it is necessary to keep the input amplifiers from saturating or increasing the overall gain, then the gain of the output amplifier can be increased from unity by using the circuit in Figure 5. The values of the resistors in Figure 5 are in the following table. O/P GAIN R1 and R3 Ω R2 Ω 2 5 1200 1000 2740 511 10 1500 340 100 80 Gain = 100 60 Gain = 10 40 Gain = 1 20 0 1 10 100 1k 10k 100k 1M Frequency (Hz) FIGURE 6. Typical INA Settling Time and CMR. ® 9 SDM862/863/872/873 acquisition time and droop rate, as the hold capacitor is increased in value it takes longer to charge, and hence there is a corresponding increase in acquisition time and reduction in droop rate. The droop rate is determined by the amount of leakage present in the SDM, board leakage and the dielectric absorption of the hold capacitance. The hold capacitor is also a compensation element for the S/H and should not be reduced below 2nf for good stability. The offset error in sample mode is not affected by the hold capacitor. However, during the transition to hold mode there is approximately 5pC of charge injected into the hold capacitor, causing an offset error that has been nulled for use with a 5nf hold capacitor. Any other value for the hold capacitor will cause a minor but fixed hold mode offset to be introduced, and is proportional to the change in value from 5nf. Therefore, the SDM should be offset nulled with the S/H in hold mode. Some applications may require programmable gains. This may be realized with Figure 7. Gain Sel TTL/CMOS 1-10-100 1 2 6 7 8 PGA 102 3 15 67 SDM8X3 66 MUX INA FIGURE 7. Setting Programmable Gains. SAMPLE/HOLD AMPLIFIER The Sample/Hold amplifier (S/H) is used to track the incoming signal and “hold” the required instantaneous value so that it does not change while the ADC is carrying out its conversion. Timing for the S/H may be derived from the STATUS output of the ADC, with care being taken to comply with the SDM timing considerations. ANALOG-TO-DIGITAL CONVERTER This circuit element converts the analog voltage presented by the sample/hold amplifier to a digital number in binary format under control of the digital signals detailed in Figure 9. The converter can convert unipolar and bipolar signals in the range 10V and 20V. It can be calibrated to remove gain and offset errors from the entire system. The converter contains its own clock, voltage reference, and microprocessor interface with 3-state outputs. The converter will normally be used to digitize signals to 12-bit resolution, but it can be short-cycled to provide 8-bit resolution at higher speed. The digital output is compatible with 8- or 16-bit data buses, the data format being selected by control signals as detailed in Figure 9. Capacitors with high insulation resistance and low dielectric absorption such as Teflon™, polystyrene or polypropylene should be used as storage elements. (Polystyrene should not be used above +80°C.) Teflon™ is recommended for high temperature operation. Care should be taken in the printed circuit layout to minimize stray capacitance and leakage currents from the capacitor to minimize charge offset and droop errors. The use of a guard ring driven by the S/H output around the pin connecting to the hold capacitor is recommended. (Refer to the application board layout for an example of this.) The value of the external hold capacitor determines the droop rate, charge offset and acquisition time of the S/H, Figure 8. Droop rate for the SDM is specified with a hold capacitor value of 4700pf. There is a trade-off between ACQUISITION TIME vs HOLD CAPACITANCE For a 10V Step to ±10mV of Final Value 10 CE CS R/C DATA MODE BYTE SELECT 0 X ◊ ◊ 1 1 1 1 1 1 1 X 1 0 0 ◊ ◊ 0 0 0 0 0 X X 0 0 0 0 ◊ ◊ 1 1 1 X X X X X X X X 1 0 0 X X 0 1 0 1 0 1 X 0 1 Acquisition Time (µs) 9 8 OPERATION None None Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Enable 12-bit output Enable 8 MSBs only Enable 4 LSBs plus 4 trailing zeros FIGURE 9. Control Input Truth Table. 7 LINEARITY ERROR 6 Linearity error is defined as the deviation of actual code transition values from the ideal transition values. Ideal transition values lie on a line drawn through zero (or minus full scale for bipolar operation) and plus full scale. The zero value is located at an analog input value 1/2LSB before the first code transition (000H to 001H). The full-scale value is located at an analog value 3/2LSB beyond the last code transition (FFEH to FFFH) (see Figure). Thus, with the SDM connected for bipolar operation and with a full-scale range (or span) of 20V (±10V), the zero value of –10V is 2.44mV 5 4 3 4 6 8 10 12 14 16 Hold Capacitance (nF) FIGURE 8. Acquisition Time vs Hold Capacitance for a 10V Step Settling to ±10mV of Final Value. ® SDM862/863/872/873 10 below the first code transition (000H to 001H at –9.99756V) and the plus full-scale value of +10V is 7.32mV above the last code transition (FFEH to FFFH at +9.99268) (see Figure 13). scale value. The SDM specification, however, follows the terminology defined for the 574 converter several years ago. Thus, bipolar offset is located near the midscale value of 0V (bipolar zero) at the output code transition 7FFH to 800H. Bipolar offset error for the SDM is defined as the deviation of the actual transition value from the ideal transition value located 1/2LSB below 0V. The bipolar offset temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. NO MISSING CODES (DIFFERENTIAL LINEARITY ERROR) A specification which guarantees no missing codes requires that every code combination appear in a monotonicallyincreasing sequence as the analog input is increased throughout the range. Thus, every input code width (quantum) must have a finite width. If an input quantum has a value of zero (a differential linearity error of –1LSB), a missing code will occur. FULL SCALE CALIBRATION ERROR The last output code transition (FFEH to FFFH) occurs for an analog input value 3/2LSB below the nominal full-scale value. The full-scale calibration error is the deviation of the actual analog value at the last transition point from the ideal value. The full-scale calibration temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. The SDM is guaranteed to have no missing codes to 12-bit resolution over it’s respective specification temperature ranges. UNIPOLAR OFFSET ERROR OPERATING INSTRUCTIONS An SDM connected for unipolar operation has an analog input range of 0V to plus full scale. The first output code transition should occur at an analog input value 1/2LSB above 0V. Unipolar offset error is defined as the deviation of the actual transition value from the ideal value. The unipolar offset temperature coefficient specifies the change of this transition value versus a change in ambient temperature. OPERATING MODES The SDM can operate in one of two modes, namely serial and overlap, as shown in Figure 10. In serial mode, control of the device is such that a multiplexer channel X is first selected, time is then allowed for the instrumentation amplifier to settle, the sample/hold amplifier is set to HOLD mode and finally a conversion is carried out. This procedure is then repeated for channel Y. Faster throughput can be obtained using overlap mode. While a conversion is being BIPOLAR OFFSET ERROR A/D converter specifications have historically defined bipolar offset as the first transition value above the minus full- SERIAL MODE Signal Acquisition MUX Selection (X) Instrumentation Amp Settling Conversion Sample/ Hold Acquisition A/D Conversion Data Valid MUX Selection (Y) Time OVERLAP MODE MUX Selection (X) Instrumentation Amp Settling Sample/ Hold Acquisition MUX Selection (Y) Signal Acquisition Instrumentation Amp Settling Sample/ Hold Acquisition MUX Selection (Z) Signal Acquisition Conversion A/D Conversion on Channel (X) Data Valid A/D Conversion on Channel (Y) Time FIGURE 10. Serial and Overlap Modes of Operation. ® 11 SDM862/863/872/873 CALIBRATION - GENERAL carried out by the ADC on a voltage from channel X held on the sample/hold, channel Y is selected and the multiplexer and instrumentation amplifier allowed to settle. In this way, the total throughput time is limited only by the sum of the sample/hold acquisition time and the ADC conversion time. The input voltage ranges of the ADC are 0-10V, ±5V and ±10V. Calibration in all ranges is achieved by adjusting the offset and gain potentiometers (indicated in Figures 11 and 12) such that the 000 to 001 code transition takes place at +1/2LSB from full-scale negative (–FS) and the FFE to FFF transition takes place at –3/2LSB from full-scale positive (+FS). The procedure is therefore to select the required range from Figure 13, apply the specified (–FS+1/2LSB) voltage to any selected input channel and adjust the offset potentiometer for the 000 to 001 transition. The (+FS–3/2LSB) voltage should then be applied to the same channel and the gain potentiometer adjusted for the FFE to FFF transition. The offset should always be made before the gain adjustment. CALIBRATION – UNIPOLAR If adjustment of unipolar offset and gain are not required, then the gain set potentiometer in Figure 11 (Unipolar operation) may be replaced with a 50Ω, 1% metal film resistor, and the offset network replaced with a connection from pin 23 to ground. SDM 21 22 23 24 000 TO 001 TRANSITION VOLT. 0–10V ±5V ±10V +0.0012V –4.9988V –9.9976V 10V Span FFDH 100kΩ 802H Digital Output 100kΩ (Offset) –15V 100Ω (Gain) 20V Span Offset Error Shifts The Line 001H 000H 1/2LSB Zero (–Full Scale) (Bipolar Offset Transaction) Midscale (Bipolar Zero) Zero 1/2LSB (–Full-Scale Calibration Transition) Analog Input 3/2LSB +Full +Full-Scale Scale Calibration Transition FIGURE 14. SDM Transfer Characteristic Terminology. SDM 23 800H 7FFH 002H CALIBRATION - BIPOLAR If adjustment of bipolar offset and gain are not required then the gain set and offset potentiometers in Figure 12 (Bipolar operation) may both be replaced with 50Ω, 1% metal film resistors. 22 801H 7FEH FIGURE 11. Unipolar Calibration. 21 2.44mV 2.44mV 4.88mV Full-Scale Calibration Error Rotates The Line FFEH +15V Inputs +9.9963V +4.9963V +9.9927V FIGURE 13. Code Transition Ranges. FFFH 20V Span FFE TO FFF 1LSB TRANSITION VOLT. EQUALS 26 100Ω (Gain) 160Ω FULL-SCALE RANGE 24 GROUNDING, DECOUPLING AND LAYOUT CONSIDERATIONS 26 It should be noted that the multiplexer/instrumentation amplifier section and sample/hold plus ADC section of the SDM have separate power connections. This is to enable more flexible grounding techniques to be implemented, Figures 15, 16. It also facilitates the use of independent decoupling of the analog front-end power supply, and the ADC plus associated digital circuitry power supply if desired. In this way, a separately decoupled analog front-end can be made to be substantially more immune to power supply noise generated by the ADC circuitry than if the 100Ω (Offset) 10V Span Inputs FIGURE 12. Bipolar Calibration. ® SDM862/863/872/873 12 power supplies to the two sections were directly connected. This feature is important where low-level signals are in use or high input signal noise immunity is desired. via one track to a single point as close as possible to the SDM. To check that the grounding structure is correct, the ground tracking should be sketched and a grounding “tree” should result whereby all grounds route to a central point. The output section has three grounds: In general, layout should be such that analog and digital tracks are separated as much as possible with coupling between analog and digital lines minimized by careful layout. For instance, if the lines must cross they should do so at right angles to each other. Parallel analog and digital lines should be separated from each other by a pattern connected to common. Pin 25 Analog Common, A/D Converter Pin 34 S/H Amp Digital Input Reference Pin 19 Digital Common, A/D Converter The input section has one ground: Pin 53 Common for digital MUX-inputs and power supply decoupling. 66 53 4 3 2 34 25 19 27 +5V –15V +15V DCOM (2) ACOM (2) SHC GND Output-Ref +V –V DCOM (1) Signal-Ref (Single-Ended) All grounds have to be interconnected externally to the SDM, and it is recommended that all grounds are connected 20 5 +5V 100µH –15V Signal-Ref (1) (1) +15V 100µH (1) (1) (1) NOTE: (1) 10µF tantalum in parallel with 100nF ceramic. FIGURE 15. Recommended Decoupling of Power Supplies. 1/2 SDM 1/2 SDM ISO100 1 INA 39 2 –V 4 0 53 +V 3 –V 0 +V 0 +5V 20 25 27 19 5 100µH 100µH +5V 100µH PWR305 100µH 5V 100µH +5V MUX-Address MUX-Address 4 Opto-Couplers FIGURE 16. Galvanic Isolation Between Analog and Digital Signals. ® 13 SDM862/863/872/873 FIGURE 17. The SDM Connected to an Input/Output Port. ® SDM862/863/872/873 14 1kΩ +5V 8(0) 9(1) 10(2) 11(3) 12(4) 13(5) 14(6) 15(7) 54 55 56 57 58 59 60 61 53 48 EN 67 65 66 49 50 51 52 A1 A0 A2 A3 Out (Out) +5V DCOM CH0 1 2 3 4 5 6 7 47 46 45 44 43 42 41 40 MUX Analog-Ref 63 64 68 4 +In VEE 3 VCC 2 RG –In G10 G100 Sense Out INA Ref 62 1 34 33 6 25 19 27 20 5 +5V (12 Bit) +5V –15V +15V C4 C5 C6 C7 28 29 30 31 32 CE R/C Data M. CS Byte S. +15V –15V +5V AGND DGND A0 A1 A2 A3 A4 A5 A6 A7 C0 C1 C2 C3 10 9 8 7 Status D8 D9 D10 MSB D11 B0 B1 B2 B3 B4 B5 B6 B7 18 17 16 15 14 13 12 11 In(20V) Bip Off D4 D5 D6 D7 ADC R 100Ω 23 LSB D0 D1 D2 D3 R 100Ω 24 Ref In SHC Out Gnd Cont Ref Out 26 In(10V) 22 In Hold Cap S/H 44.7nF 39 35 36 37 21 8255 Port FIGURE 18. The SDM Connected to a 16-Bit-BUS. 34 33 Cont SHC Gnd Out Hold Cap In S/H 39 35 36 .47nF 6 25 19 37 2122 Ref In Ref Out 10 9 8 7 D8 D9 D10 MSB D11 27 20 5 +5V MUX +15V (12 Bit) 28 29 30 31 32 14 13 12 11 D4 D5 D6 D7 +15V –5V DGND Status AGND In (20V) In (10V CE R/C Data M. CS Byte S. 18 17 16 15 Bip Off 23 R 50Ω D0 D1 D2 D3 ADC 24 26 R 50Ω Fully Controlled Mode A0 A1 A2 A3 1G 2G 74244 1G 2G 74244 G OC D Q 74373 D4 D5 D6 D7 D0 D1 D2 D3 CS Status G OC D Q D0 D1 D2 D3 D4 SDM862/863/872/873 CS WR CS A0 A1 A2 A3 D15 CS MUX +15V (12 Bit) S/H Cont 5 1G 2G D8 D9 D10 D11 WR RD +5V 1G 2G D4 D5 D6 D7 D0 D1 D2 D3 WR D15 28 29 30 31 32 10 9 8 7 D8 D9 D10 MSB D11 CE R/C Data M. CS Byte S. 14 13 12 11 D4 D5 D6 D7 D4 D5 D6 D7 D8 D9 D10 D11 18 17 16 15 D0 D1 D2 D3 D0 D1 D2 D3 Bip Off 23 Stand Alone Mode 74244 74244 74373 15 ® RD CS R 100Ω 4.7nF 39 35 36 37 21 22 26 24 Ref Out R 100Ω 23 Ref In Bip Off D0 D1 D2 D3 18 17 16 15 ADC Hold Cap D4 D5 In D6 In (10V) D7 14 D0 13 D1 12 D2 11 D3 S/H Out In (20V) D8 D9 SHC Gnd D10 MSB D11 Status Cont 10 D4 9 D5 8 Z80 D6 7 D7 AGND CE DGND R/C DATAM. WR 28 RD 29 30 31 CS 32 Bytes +15V –15V AO +5V Address Decode 34 6 33 25 19 27 20 A1 – A7 5 MUX A0 A1 A2 A3 IORQ D0 D1 D2 D3 74LS175 Reset FIGURE 19a. SDM on the Z80 Interface. R 100Ω 4.7nF 39 35 36 37 21 22 26 24 Ref Out R 100Ω 23 Ref In Bip Off D0 D1 D2 D3 18 LS 374 17 16 15 Data Bus ADC SDM Status Pin 6 Hold Cap D4 D5 In D6 In (10V) D7 14 13 12 LS 374 11 S/H Out In (20V) D8 D9 SHC Gnd D10 MSB D11 Status Cont 9 8 7 Address Decode AGND 68000 Address Bus +5V CE DGND R/C DATAM 28 29 –15V R/W 30 31 CS 32 Bytes +15V SDM Status 10 UDS LOS +5V DTACK 34 33 6 25 19 27 20 5 FIGURE 19b. 68000/SDM Interface. ® SDM862/863/872/873 16 R 100Ω 4.7nF 39 35 36 37 21 22 26 24 Ref Out R 100Ω 23 Ref In Bip Off 18 D0 17 D1 16 D2 15 D3 ADC Hold Cap 14 D4 In D1 12 D6 In (10V) D0 13 D5 D2 11 D7 D3 S/H Out In (20V) 10 D8 MSB D11 Status D5 8 D10 Cont D4 9 D9 SHC Gnd D6 7 D7 IBM PC or XT Card Slot AGND CE DGND R/C DATAM IOW 28 IOR 29 30 31 CS 32 Bytes +15V –15V +5V 20 5 AO Adress Decode 34 33 6 25 19 27 MUX A0 A1 A2 A3 A1 - A9 AEN D0 D1 D2 D3 Reset FIGURE 19c. IBM PC SDM Interface. R 100Ω 4.7nF 39 35 36 37 21 22 26 24 Ref Out R 100Ω 23 Ref In Bip Off D0 D1 D2 D3 18 17 16 15 ADC Hold Cap D4 D5 In D6 In (10V) D7 BUS 14 D0 13 D1 12 D2 11 D3 S/H Out In (20V) D8 D9 SHC GND D10 MSB D11 Status Cont 10 D4 9 D5 8 D6 7 D7 AGND CE DGND R/C DATAM 28 ø2 29 R/W 30 31 CS 32 Bytes +15V 34 33 6 25 19 27 –15V +5V 20 5 A0 A4 Select 8 Bit A0 A1 A2 A3 74LS 175 D0 D1 D2 D3 Reset FIGURE 20. SDM on the 6502 BUS. ® 17 SDM862/863/872/873 CONTROLLING THE SDM The Burr-Brown SDM family can be easily interfaced to most microprocessor systems, as shown in Figures 17-20. The microprocessor may control each conversion, or the converter may operate in a stand-alone mode controlled only by the R/C input. SYMBOL PARAMETER MIN tHRL tDS tHDR tHS 86X tHS 87X tHRH tDDR Low R/C Pulse Width STS Delay from R/C Data Valid After R/C Low STS Delay After Data Valid 50 High R/C Pulse Width Data Access Time TYP MAX UNITS ns ns ns ns ns ns ns 200 25 300 100 150 500 300 1000 600 150 TABLE I. Stand-Alone Mode Timing. STAND-ALONE OPERATION The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. tHRL R/C Control of the converter is accomplished by a single control line connected to R/C. In this mode CS and BYTE SELECT are connected to LOW and CE and DATA MODE are connected to HIGH. The output data are presented as 12-bit words. tDS Status tC tHDR Conversion is initiated by a High-to-Low transition of R/C. The three-state data output buffers are enabled when R/C is high and STATUS is low. Thus, there are two possible modes of operation; conversion can be initiated with either positive or negative pulses. In each case the R/C pulse must remain low for a minimum of 50ns. DB11–DB0 Data Valid tHS High-Z State Data Valid FIGURE 21. R/C Pulse Low—Outputs Enabled After Conversion. Figure 21 illustrates timing when conversion is initiated by an R/C pulse which goes low and returns to the high state during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of R/C and are enabled for external access of the data after completion of the conversion. Figure 22 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode the output data from the previous conversion is enabled during the positive portion of R/C. A new conversion is started on the falling edge of R/C, and the three-state outputs return to the high impedance state until the next occurrence of a high R/C pulse. Table I lists timing specifications for stand-alone operation. R/C tHRH tDS Status tDDR DB11– High-Z DB0 tC tHDR High-Z State Data Valid FIGURE 22. R/C Pulse High—Outputs Enabled Only Where R/C is High. Conversion Start FULLY CONTROLLED OPERATION Conversion Length A conversion is initiated by a transition on any of three logic inputs (CE, CS, and R/C)—refer to Figure 9. The last of the three to reach the required state start the conversion and thus all three may be dynamically controlled. If necessary, they may change state simultaneously, and the nominal delay time is independent of which input actually starts the conversion. If it is desired that a particular input establish the actual start of conversion, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing relationships for start of conversion timing are illustrated in Conversion Cycle Timing of the Digital Specifications. Conversion length (8-bit or 12-bit) is determined by the state of the BYTE SELECT input, which is latched upon receipt of a conversion start transition. BYTE SELECT is latched because it is also involved in enabling the output buffers. No other control inputs are latched. If BYTE SELECT is latched high, the conversion continues for 8 bits. The full 12-bit conversion will occur if BYTE SELECT is low. If all 12 bits are read following an 8-bit conversion, the 3LSBs (DB0DB2) will be low (logic 0) and DB3 will be high (logic 1). Word 1 Word 2 Processor DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDM DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 FIGURE 23. 12-Bit Data Format for 8-Bit Systems (connected as Figures 18 and 19). ® SDM862/863/872/873 18 1. DIRECT SURFACE MOUNT ONTO PCB The STATUS output indicates the state of the converter by being high only during a conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore, data is not valid. During this period additional transitions of the three control inputs will be ignored, so that conversion cannot be prematurely terminated or restarted. However, if BYTE SELECT changes state after the beginning of conversion, any additional start conversion transition will latch the new state of BYTE SELECT, possibly resulting in an incorrect conversion length (8 bit versus 12 bits) for that conversion. ADVANTAGES DISADVANTAGES Ease of assembly Low cost Low weight Small footprint size Difficult to inspect solder joints Difficult to clean Choice of board material important in wide temperature range applications In wide temperature applications it is important to match the coefficients of thermal expansion of the board and the SDM8XXL. Below is a list of materials and their approximate coefficients of linear thermal expansion. (ppm/°C) MATERIAL Alumina (96%) - SDM Package Copper-clad-Invar (50% Cu) (30% Cu) (10% Cu) Epoxy-Kevlar (60% Kevlar) Polyimide-Kevlar (40% Kevlar) Beryllia Polyimide-glass (x-axis) (y-axis) READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance state until the following four conditions are met: R/C high, STATUS low, CE high, and CS low. In this condition the data lines are enabled according to the state of the inputs DATA MODE and BYTE SELECT. See Read Cycle Timing for timing relationships and specification. 6-7 9 6 3 6 6 5 12 14 Kevlar™ E.I. du Pont de Nemours & Co. In most applications the DATA MODE input will be hardwired in either the high or low condition, although it is fully TTL- and CMOS-compatible and may be actively driven if desired. When DATA MODE is high, all 12 outputs lines (DB0-DB11 ) are enabled simultaneously for full data word transfer to a 12-bit or 16-bit bus and the state of the BYTE SELECT is ignored. 2. ATTACHMENT OF SURFACE MOUNT EDGE CLIPS ADVANTAGES DISADVANTAGES Ease of Inspection Easy cleaning Thermal expansion taken up by the flexing of the edge clips When DATA MODE is low, the data is presented in the form of two 8-bit bytes, with selection of each byte by the state of BYTE SELECT during the read cycle. Extra cost Extra assembly ASSEMBLY The edge clips are attached to the edges of the SDM8XXL as in Figure 24 before the device is mounted on to the board. The BYTE SELECT input is usually driven by the least significant bit of the address bus, allowing storage of the output data word in two consecutive memory locations. When BYTE SELECT is low, the byte addressed contains the 8MSBs. When BYTE SELECT is high, the byte addressed contains the 4LSBs from the conversion followed by four zeros that have been forced by the control logic. The left-justified formats of the two 8-bit bytes are shown in Figure 23. The design of the SDM guarantees that the BYTE SELECT input may be toggled at any time without damage to the output buffers occurring. SDM EDGE CLIP In the majority of applications, the read operation will be attempted only after the conversion is complete and the status output has gone low. In those situations requiring the fastest possible access to the data, the read may be started as much as (tDD max + tHS max) before STATUS goes low. Refer to Read Cycle Timing for these timing relationships. FIGURE 24. Edge Clip Assembly. SUPPLIERS OF EDGE CLIPS APPLICATIONS INFORMATION ASSEMBLY OF SURFACE MOUNT PACKAGES There are several assembly methods for the LCC versions of the SDM8XX. The associated advantages and disadvantages of three methods are outlined below. USA USA DIE-TECH INC., R.D. 1, Sipe Road, York Haven, PA 17370 USA PHONE: (717) 938-6771 NAS Electronics, 381 Park St., Hackensack, NJ 07602 USA PHONE: (201) 343-3156 EUROPE EUROPE SEMI-DICE (UK) Ltd, Buckingham House, Mineral Lane, Chesham, Bucks. HP5 2AU UK PHONE: 0494 771275 NASBRIT Ltd, Wester Goudi Ind. Est. Dundee DD2 4UX UK PHONE: 0382 622222 ® 19 SDM862/863/872/873 3. SURFACE MOUNT SOCKET ADVANTAGES However, in following the application guidelines illustrated by the circuitry and accompanying notes, the designer will be able to select and adapt the solutions most suited to their won particular application or problem area. DISADVANTAGES Board thermal expansion not so critical Ease of component replacement Cost Extra height (if critical) Provisions for the following are made on the LCC PC board: —68 pin LCC socket (Burr-Brown Part No. MC0068). —8 differential or 16 single-ended inputs. —Input filtering with overvoltage protection for each channel. —Socket for quad D-type flip-flop 74175 (MUX address latches). —7 additional I.C. sockets for easy interfacing to various BUS systems (connection by wire wrap techniques). —2 voltage regulators (15V). —LC power supply decoupling. Below is the name and address of a supplier of a 68-pin surface mountable socket. The part number is: Socket 212-068-012 Spring cover CCS-004 USA EUROPE Methode Electronics INC, Interconnect Products Div. 1700 Hick Road, Rolling Meadows, TX 75050 USA PHONE: (312) 392-3500 Lucas Methode Connectors Ltd, Halifax Road Ingrow Bridge, Keighley, Yorkshire BD21 5HR UK PHONE: 0535 603282 The layout pays particular attention to the requirements when operating with precision analog signals. This requires strict separation of the analog and digital areas. Analog and digital commons are totally separated and connected together only at the commons of the supply voltage. All common lines are low resistance and low inductance. General Comments The advantages and disadvantages of all the methods mentioned above are for general use of surface mount components. Every user will find that the importance of these factors will depend on his application and situation. SUPPLY VOLTAGES EVALUATION BOARD In order to avoid coupling between the external supply voltage 15V supplies, 2 voltage regulators (78M15, 79L15) are provided on the PC board. The unregulated supply voltage may vary from ±17V to ±25V. For the engineer who wishes to evaluate the SDM family, Burr-Brown has designed printed circuit boards on a single ‘Eurocard’ (shown here for LCC only). These boards enable the design engineer to experiment with various accuracy improvement techniques which are described below. Special consideration has been given to the grounding and circuit layout techniques required when dealing with 12-bit analog signals. The MUX/INA section and SHC/ADC section of the SDM have separate supply lines which can be inductively decoupled. This is recommended in order to suppress the high frequency noise which comes from the ADC during conversion. The printed circuit board has been designed so that the solutions to several of the problems likely to be encountered by the user can be examined. The power supply rejection of the instrumentation amplifier reduces with increasing frequency. If high frequency noise on the supplies is not decoupled it will be injected into the signal path and cause errors. This effect can be particularly pronounced when using the ‘overlap’ mode since the instru- It should not be thought that every user is required to adopt all of the techniques used on the circuit board. In many applications very few external components will be required. SDM862/872 SDM863/873 MUX ADD3 MUX ADD2 MUX ADD1 MUX ADD0 MUX Enable Channel Selected MUX ADD2 MUX ADD1 MUX ADD0 MUX Enable Channel Pair Selected X L L L L L L L L H H H H H H H H X L L L L H H H H L L L L H H H H X L L H H L L H H L L H H L L H H X L H L H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H NONE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X L L L L H H H H X L L H H L L H H X L H L H L H L H – – – – – – – – L H H H H H H H H NONE 0 1 2 3 4 5 6 7 FIGURE 25. Channel Select Truth Table. ® SDM862/863/872/873 20 mentation amplifier is settling to a new analog value while the ADC is still carrying out the previous conversion. Analog In Mux Rf The digital supply voltage is +5V and is also LC-filtered. Cm Cg All supply lines are bypassed with a 10µF tantalum and a 100nF ceramic capacitor situated as close as possible to the package. INA FIGURE 26. If the voltage regulators for the ±15V are not used, small inductors for decoupling of the supply voltages are recommended. If inductors are not fitted a dynamic ground loop will be created from supply lines via bypass capacitors to analog common. Single-Ended Measurement Rf limits the maximum input current through the protection diodes. In this case, Rf has been chosen as 10kΩ and together with the capacitor Cg, forms the input filter time constant (Cg = 0.47µF). The time constant must be chosen according to the requirements of the input signal bandwidth and noise rejection. The multiplexer capacitance (Cm) is discharged mainly by Cg. This means Cg has to be sufficiently large compared with Cm or charged via Rf prior to resampling of the signal. INPUT PROTECTION The multiplexer is protected up to an input voltage which can exceed the supply voltage by a maximum of 20V. This means, that with ±15V supply voltage, the input voltage can be ±35V without damage. This is also the case when the supply voltages are switched off (0V). The maximum input voltage can then be ±20V. For higher overvoltage protection a series resistor has to be used. The current via the multiplexer should be limited to 20mA absolute maximum, 1mA is preferred. For example, a 10kΩ series resistor would give an additional 10V overprotection. Cg Mux Analog In Rf Analog In Rf For much higher overvoltages (e.g. 100V), high value series resistors cannot be used as offset errors would result. In practice, a combination of series resistors and diodes is used. The diodes are connected to ±15V and will conduct whenever the input voltage exceeds the ±15V supply voltage. The diodes are selected by signal source impedance, as well as filter resistance, as the diode leakage current across the series resistor can cause offset and linearity errors. In this circuit, IN4148 together with 10kΩ are used. Cm Cf INA Cg FIGURE 27. Differential Measurement Capacitor Cf, is used for limiting the input signal frequency. The bandwidth is calculated as follows: 1 Ff = 4π R C IF Cf > > Cg f f When selecting the value of Cf, it should be noted that Cm has to be discharged when switching the multiplexer channels. This means that the voltage error of Cf (induced by ‘charge sharing’ with Cm) has to be smaller than 1LSB. Therefore, Cf should have a minimum value of a 0.47µF. The resistors Rf, together with the source impedance, have to be sufficiently small in order to recharge Cf prior to signal sampling. This prevents errors in the signal value caused by the charge stored on Cm by the previously selected channel. INPUT FILTER Processor noise can be induced in the analog ground. Input filtering is therefore recommended for analog data acquisition. Such high frequency noise signals can cause dynamic overload of the instrumentation amplifier resulting in nonlinear behavior. This leads directly to digitizing errors. The design of the filter takes into account the characteristics of the SDM and of the signal source. The following points have to be considered: The 2 capacitors Cg form together with Rf a common-mode filter. This filter greatly improves accuracy in a noisy environment (decrease of common-mode rejection of instrumentation amplifier with increasing frequency). —The stray capacitance, output capacitance of the multiplexer and input capacitance of the instrument amplifier (up to 80pf in some cases) has to be discharged in order to minimize errors caused by ‘charge sharing.’ For good common-mode filter operation, both time constants Rf and Cg should match each other within 2%. Additional errors will be induced by a mismatch. —The series resistor limits the current in the protection diodes, but it also has to be selected for the required filter time constant. Selected values are: Cf = 0.47µF, Cg = 10nF, Rf = 10kΩ. The filter reduces the signal slew rate so that the instrumentation amplifier can follow the voltage variation of the signal with the noise component eliminated. —The noise rejection of the filter has to be >80db in order to satisfy a 12-bit A/D conversion. As well as considering the above, different calculations have to be carried out for single and differential input signals. In general, all measurements which require more than a gain of 10 should be done in differential mode. Single ended ® 21 SDM862/863/872/873 measurements should be limited to applications where current sources are measured via shunts or where signal voltages in the range of some volts are available. (b) Differential inputs —Use SDM8X3 —Consider differential filtering —Connect J3 (pin 66) to pin 67 (c) Analog input ±10V Connect J1 to pin 21 Connect J2 to pot P2 (100Ω) ±5V Connect J1 to pin 22 Connect J2 to pot P2 (100Ω) 0 to +10V: Connect J1 to pin 22 Connect J2 to junction of R1/R2 (d) Gain of instrumentation amplifier G=1 Jumper J4 open G = 10 Jumper J4 to pin 63 G = 100 Jumper J4 to pin 64 Other gains: use additional resistor between pin 62 and pin 63 (see section on Instrumentation Amplifier) as low tempco resistor is recommended in order to minimize gain drift. Bus-Interface As the outputs of the SDM are BUS compatible, only a few ICs are necessary to interface to various BUS systems. For such interfacing, 20-pin IC sockets are provided. Wiring is by wire wrap to the BUS connector. Setting of Various Modes Circuit Board positions are provided for the connection of ‘jumpers’ as follows: J1, J2—ADC analog input volt age settings. J3—Set for differential (SDM8X3) or single ended (SMD8X2) operation. J4—Instrumentation amplifier gain settings. (a) 16 input channels, single ended: —Use SDM8X2 —Consider single-ended filtering —Connect J3 (pin 66) to common ® SDM862/863/872/873 22 INPUT FILTER AND PROTECTION CIRCUITRY SINGLE-ENDED DIFFERENTIAL 26-Pin Connector Channel Numbers 0 14 15 26-Pin Connector 14 Rf +15V Rf R3 –15V +15V 0.47µF SDM Pins Cg 47 C1 C17 17 45 11 10nF 1% 0.47µF R11 C9 54 19 46 21 55 44 1 7 43 R7 5 –15V Cf 10k Ω 0 R6 4 R3 C2 R5 3 15 1% 46 D3 D4 23 Channel Numbers 47 D1 D2 19 R4 2 Cg C1 10kΩ 1 SDM Pins 23 3 42 45 R5 R8 6 4 2 41 R9 7 25 10 40 8 D15D16 17 11 C8 R10 R13 56 44 R6 54 3 R11 9 21 55 13 7 R12 10 25 56 57 9 9 58 15 58 42 R8 5 5 59 R16 14 R15 3 R15 13 43 4 13 R14 12 57 R7 R13 11 R14 5 6 60 R17 C15 R18 C16 R16 4 59 41 R9 12 61 6 D31D32 6 R17 10 60 40 R10 7 61 12 R18 Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common ® 23 SDM862/863/872/873 R10 C3 R3 D14 D30 D13 D29 R16 C5 C13 C15 C4 R7 R17 R6 C12 R14 C1 C9 R11 R4 C2 C10 R12 R5 C23 C7 C16 R18 R8 ©Burr-Brown Ltd 1989 PC862/863-1 REV B D16 D32 D15 D31 C8 C24 R9 C C C15 D22 D20 D18 C19 C18 C17 D6 D4 D2 C20 C22 D21 D19 D17 D24 D5 D3 D1 D8 C21 J4 D33 S/H S/H OUT IN RG J3 S/H BS CS DM R/C CE 33 32 31 30 29 28 A A A A A A A A A A A AAA A AA LCC Package 74/75 Pin Out For LCC Socket C27 R2 R1 P1 BIP UNI P2 P3 10V L3 J1 20V C30 + C38 L2 IC3 C35 IC2 + C37 C36 L1 E 79 E 78 C39 + C40 IC6 ST 11 10 9 8 7 6 5 4 3 2 1 0 C29 C28 A A AA A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A AA A A A A A A AA SDM INAMUX- C26 A A A A A A A A A A A A A A 10 G 100 D34 C25 + C11 C6C14 D26 D7 D10 D23 D9 D12 D28 D11 D27 IC7 D25 A0 A2 A1 A3 CL + J2 24 C42 SDM862/863/872/873 IC4 ® IC5 IC1 C41 R13 B C33 C34 +V + +5V –V B + B C31 C32 B B B B B B B B D D PCB COMPONENT LAYOUT NOTE: (1) NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 (2) NOT DRAWN TO SCALE P.C.B. LAYOUT NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 ® 25 SDM862/863/872/873 –V = Wirewrap Posts C30 C38 ACOM DCOM + C29 C37 –15V 20 27 31 CS +15V CE RC 28 Status BS Data M 6 SHC/COM 34 36 C25 4700pF 33 CH Out 1kΩ +5V INA G100 +5V +5V 8 5 12 CL 91 74175 A3 A2 A1 A0 +5V 43 44 4 13 15 210 7 51 50 49 EN A0 A1 2 1 0 45 46 47 48 15 14 Out– 13 12 11 10 9 8 MUX 7 6 5 Out+ 4 3 61 60 59 58 57 56 55 54 40 41 42 A3 A2 52 16 C26 IN+ Ref INX– RG G10 2 62 63 64 68 67 65 66 25 53 DCOM ACOM RG J3 In Out SH 1 39 C35 + 5 35 37 21 C36 100µH L1 Sense J1, J2 = ±10V J3 = 8 Diff Inputs J4 = (G = 10) 29 19 32 30 7 D11 8 9 10 11 12 20V In 10V In ADC 24 26 22 J1 L1 13 14 15 16 17 18 D0 4 –15V J2 +15V 23 P2 P1 C32 C31 Ref In Ref Out + Bip Off R2 3 R1 P3 C27 + C39 + C40 L3 L2 C28 +5V 78 79 +V C34 C33 CIRCUIT DIAGRAM—SDM PC BOARD P.C.B. COMPONENTS PARTS LIST R1 R2 R3...R18 C1...C16 C17...C24 C25 100Ω For 0–10V Settling 100kΩ 10kΩ 1% 0.47µF—Single Ended Input Mode 10nF 1%—Differential Input Mode 0.47µF—Differential Input Mode 4.700pF (Polypropylene, Polystyrene or TeflonTM) C26 C27, C29, C35 C32, C38, C39 C28, C30, C31 C36, C37, C40 C33, C34 P1 P2 10nF Ceramic 10µF Tantalum (Decoupling) 100nF Ceramic (Decoupling) 0.33µF Tantalum 100Ω 100Ω ±5V, ±10V Range Only P3 L1...L3 D1...D32 D33, D34 78 79 74175 LCC Socket 100kΩ 0–10V Range Only 100µH (Decoupling) 1N4148 (Input Protection Diodes) 1N4007 MC78M15CG MC79L15CG 74LS175 MC0068 UNLESS OTHERWISE MARKED—RESISTORS ARE 1/4W, 5%, CAPACITORS ARE 10% Teflon™ E.I. du Pont de Nemours & Co. ® SDM862/863/872/873 26 MECHANICAL (P.G.A.) Package Number 906 TOP VIEW Bottom VIEW A Pin 1 Identifier B E 67 65 63 61 59 57 55 53 1 68 66 64 62 60 58 56 54 52 51 50 2 3 49 48 4 5 47 46 6 7 45 44 8 9 43 42 10 11 41 40 12 13 39 38 14 15 37 36 16 17 20 22 24 26 28 30 32 34 35 18 19 21 23 25 27 29 31 33 C DIM A B C D E F G H J INCHES MIN MAX 1.087 1.109 1.087 1.109 .095 .120 .162 .198 .045 .055 .045 .055 .016 .020 .100 BASIC .100 BASIC MILLIMETERS MIN MAX 27.610 28.169 27.610 28.169 2.413 3.048 4.115 5.029 1.143 1.397 1.143 1.397 .406 .508 2.540 BASIC 2.540 BASIC NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. TERMINATION: Gold plated KOVAR. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 9 grms (0.32 oz) DIM A B C D E F G H J K L INCHES MIN MAX .945 .965 .945 .965 .076 .094 .841 .859 .841 .859 .755 .785 .755 .785 .800 BASIC .027 .033 .045 BASIC .050 BASIC MILLIMETERS MIN MAX 24.003 24.511 24.003 24.511 1.934 2.388 21.361 21.819 21.361 21.819 19.177 19.939 19.177 19.939 20.320 BASIC .686 .838 1.143 BASIC 1.270 BASIC NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. J H D F G MECHANICAL (L.C.C.) Package Number 907 — TOP VIEW A D F Pin 1 Identification 67 66 68 L 1 2 3 G EB J H K TERMINATION: Gold plated nickel on refractory metallization. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 4.37 grms (0.124 oz) C ® 27 SDM862/863/872/873