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DELIVERY SPECIFICATIONS
Orderer (Customer) Part Number
Panasonic Global Part Number
Vendor Issue Number
AN44071A-VF
1203001
ORDERER (CUSTOMER)
Confirmation of Security Control
We confirm and certify that the products of these specifications shall not be supplied so as to be used for Military Purpose (defined herein
below). "Military Purpose" in this statement means the design, development, manufacture, storage or use of any weapons, including
without limitation nuclear weapons, biological weapons, chemical weapons and missiles.
Receipt Date:
/
/
VENDOR
"Changes in the description of Delivery Specifications" and "changes that affect performance, quality or environment" are implemented
according to advance consultation.
2012. 3.12
Issuance Date:
/
/
Industrial Devices Company, Panasonic Corporation
SMART Puniness distraction
S423141-01#01
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or
provided to non-residents, the laws and regulations of the exporting country, especially, those with
regard to security export control, must be observed.
(2)The technical information described in this book is intended only to show the main characteristics
and application circuit examples of the products. No license is granted in and to any intellectual
property right or other right owned by Panasonic Corporation or any other company. Therefore, no
responsibility is assumed by our company as to the infringement upon any such right owned by any other
company which may arise as a result of the use of technical information de-scribed in this book.
(3)The products described in this book are intended to be used for general applications (such as
office equipment, communications equipment, measuring instruments and household appliances), or for
specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
・Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling
equipment, combustion equipment, life support systems and safety devices) in which exceptional quality
and reliability are required, or if the failure or malfunction of the products may directly jeopardize
life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a
result of or in connection with your using the products described in this book for any special
application, unless our company agrees to your using the products in this book for any special
application.
(4)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed
operating conditions (operating power supply voltage and operating environment etc.). Especially,
please be careful not to exceed the range of absolute maximum rating on the transient state, such as
power-on, power-off and mode-switching. Other-wise, we will not be liable for any defect which may
arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence
of break down and failure mode, possible to occur to semiconductor products. Measures on the systems
such as redundant design, arresting the spread of fire or preventing glitch are recommended in order
to prevent physical injury, fire, social damages, for example, by using the products.
(5)Comply with the instructions for use in order to prevent breakdown and characteristics change due
to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting
or at customer's process. When using products for which damp-proof packing is required, satisfy the
conditions, such as shelf life and the elapsed time since first opening the packages.
(6)This book may be not reprinted or reproduced whether wholly or partially, without the prior written
permission of our company.
Reprint from WARNING LABEL STANDARDS SC3-11-00007
This delivery specifications may include old company names such as “Matsushita Electronics Corporation” or
“Semiconductor Company, Matsushita Electric Industrial Co., Ltd .“”Semiconductor Company, Panasonic
Corporation ” Please interpret these old company names as Industrial Devices Company, Panasonic
Corporation” as of January 1, 2012.
Regulations
No.
Total Pages
Page
52
1
IC3F5544
Product Standards
Part No.
AN44071A
Package Code No.
HSOP056-P-0300B
Semiconductor Company
Panasonic Corporation
Established by
Applied by
Checked by
Prepared by
M.Hiramatsu
J.Kaneda
T.Yokouchi
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
2
Contents
Overview …………………………………………………….……………………………………………………… 3
Features ………………………………………………….………………………………………………………… 3
Applications ………………………………………………….……………………………………………………… 3
Package ………………………………………………….…………………………………………………………. 3
Type ……………………………………………………….…………………………………………………………. 3
Application Circuit Example ……………………………………………………………………………………… 4
Block Diagram ……………………………………………….……………………………………………………… 5
Pin Descriptions ………………………………………….………………………………………………………… 6
Absolute Maximum Ratings ……………………………….……………………………………………………… 8
Operating Supply Voltage Range …………………….…………………………………………………………… 8
Allowable Current and Voltage Range ……………………………………………………………………………
9
Electrical Characteristics …………….…………………………………………………………………………… 10
Electrical Characteristics (Reference values for design) …………….…………………………………………. 13
Test Circuit Diagram …………………………….………………………………………………………………… 14
Electrical Characteristics Test Procedures ………….……………………………………………………………. 16
Technical Data ………………………………………….…………………………………………………………… 25
1. I/O block circuit diagrams and pin function descriptions ……………………………………………………. 25
2. Control mode……….……………………………………………………………………………………………… 32
3. Each phase current value ……………………………………………………………………………………… 33
4. Each phase current value (timing chart) …………………………………………………………………………35
5. Timing chart when DIR switches ……………………………………………………………………………………39
6. Home Position function (TEST = High) ………………………………………………………………………… 40
7. Step detection output function (TEST = Low) ………………………………………………………………… 44
8. Over-current protection function ………………………………………………………………………………… 44
9. About inputting the supply voltage to IF pins when VM power supply is not applied ……………………… 44
Usage Notes ………………………………………….……………………………………………………………. 45
1. Special attention and precaution in using ………………………………………………………………………. 45
2. Notes of Power LSI ………………………………………………………………………………………………. 46
3. Notes of this IC ……………………………………………………………………………………………………. 47
2010-08-20
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Revised
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AN44071A
Product Standards
Total Pages
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52
3
AN44071A
Driver IC for Stepping Motor
Overview
AN44071A is a quad channel H-bridge driver IC. Two bipolar stepping motor can be controlled by a single driver IC. Interface
control is 1CLK_type, it can be selected 2-phase excitation, half- step, 1-2 phase excitation, W1-2 phase excitation and 2W1-2 phase
excitation.
Features
y 2-channel stepping motor driver
→ A signal driver controls 2 stepping motors
y Built-in decoder for micro steps (2-phase, half step, 1-2 phase, W1-2 phase and 2W1-2 phase excitation)
→ Stepping motor can be driven by only external clock signal.
y PWM can be driven by built-in CR (3-value can be selected during PWM OFF period.)
→ The selection of PWM OFF period enables the best PWM drive.
y Mix Decay control (4-value can be selected for Fast Decay ratio)
→ Mix Decay control can improve accuracy of motor current waveform.
y Built-in over-current protection (OCP)
→ If the current flows to motor output more than the setup value due to ground-fault etc., the OCP operates and all
motor outputs are turned OFF.
y Built-in under voltage lockout (UVLO)
→ If supply voltage falls to less than the operating supply voltage range, the UVLO operates and all motor outputs
are turned OFF.
y Built-in thermal protection (TSD)
→ If chip junction temperature rises and reaches to the setup temperature, all motor outputs are turned OFF.
y Built-in abnormal detection output function
→ If OCP or TSD operates, an abnormal detection signal is output.
y Built-in standby function
→ The operation of standby function can lower current consumption of this IC.
y Built-in Home Position function
→ Home Position function can detect the position of motor.
y Built-in step detection output function
→ If step detection output function detects clock input signal, it outputs a signal.
y Built-in 5 V power supply (accuracy : ±5%)
Applications
y Stepping motor drive
Package
y 56 pin Plastic Small Outline Package With Heat Sink (SOP Type)
Type
y Bi-CDMOS IC
2010-08-20
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Revised
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AN44071A
Product Standards
Total Pages
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4
Application Circuit Example
40
23
34
ENABLEAB
DECAY1AB
DECAY2AB
29
AOUT2
20
R
39
CLKAB
DIRAB
ST1AB
ST2AB
ST3AB
38
35
Micro
Step
Decoder
36
37
21
VREFAB
22
PWMSWAB
VPUMP
0.01 μF
S Q
10 kΩ STPHAB
31
RCSA
DACA
DACB
OSC
1/10
Gate
Circuit
33
AOUT1
BLANK
24
PWMSW
BOUT2
26
18
0.01 μF
BC2 17
CHARGE
PUMP
10
TjmonABCD
S5VOUT 13
0.1 μF
Q S
R
RCSB
BC1 16
TSD
AMP
BG
VM
41
VM2
0.1 μF
100 kΩ
OCP
STBY
10 kΩ
BOUT1
S5VOUT
AOUT1
44
28
47 μF
UVLO
DOUT2
STBY
11
43
NFAULT
VM1
7
PWMSWCD
8
VREFCD
R
TEST
OSC
1/10
47
50
49
48
Micro
Step
Decoder
DACC
DACD
RCSC
52
COUT1
9
5
DOUT2
3
Q S
DIRCD
ST1CD
ST2CD
ST3CD
10 kΩ
54
Gate
Circuit
R
46
COUT2
PWMSW
BLANK
CLKCD
56
S Q
TEST 12
RCSD
STPHCD
45
6
51
ENABLECD
DECAY1CD
DECAY2CD
1
DOUT1
GND 14
Notes) y This application circuit is shown as an example but does not guarantee the design for mass production set.
y VM1 and VM2 should be connected outside.
2010-08-20
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Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
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5
Block Diagram
ENABLEAB 40
DECAY1AB 23
DECAY2AB 34
VREFAB
PWMSWAB
39
38
35
Micro
Step
Decoder
36
37
21
22
S Q
CLKAB
DIRAB
ST1AB
ST2AB
ST3AB
29
20
R
STPHAB
31
OSC
1/10
Gate
Circuit
33
24
BLANK
BC2
TjmonABCD
R
16
CHARGE
PUMP
28
10
S5VOUT 13
41
TSD
AMP
BG
VM
VM2
UVLO
DOUT2
STBY
11
43
12
R
TEST
S Q
56
TEST
BOUT1
100 kΩ
OCP
STBY 44
RCSB
S5VOUT
AOUT1
NFAULT
BOUT2
PWMSW
18
17
AOUT1
Q S
BC1
RCSA
DACA
DACB
26
VPUMP
AOUT2
VM1
COUT2
54
RCSC
PWMSWCD 7
52
BLANK
46
DIRCD 47
50
ST1CD 49
ST2CD
48
ST3CD
STPHCD
OSC
1/10
9
Micro
Step
Decoder
Gate
Circuit
DACC
DACD
ENABLECD 45
DECAY1CD 6
51
DECAY2CD
GND
5
3
Q S
CLKCD
8
R
VREFCD
PWMSW
1
COUT1
DOUT2
RCSD
DOUT1
14
Note) This block diagram is for explaining functions. Part of the block diagram may be omitted, or it may be simplified.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
6
Pin Descriptions
Pin No.
Pin name
1
DOUT1
2
N.C.
3
RCSD
4
N.C.
5
DOUT2
6
Type
Output
—
Input/Output
—
Description
Phase D motor drive output 1
N.C.
Phase D motor current detection
N.C.
Output
Phase D motor drive output 2
DECAY1CD
Input
Phase C/D Mix Decay setup 1
7
PWMSWCD
Input
Phase C/D PWM OFF period selection input
8
VREFCD
Input
Phase C/D Torque reference voltage input
9
STPHCD
Output
Phase C/D Home Position / Step detection signal output
10
TjmonABCD
Output
Phase A/B, C/D VBE monitor
11
NFAULT
Output
Abnormal detection output
12
TEST
13
S5VOUT
Output
Internal reference voltage (output 5 V)
14
GND
Ground
Ground
15
COM1
16
BC1
Output
Capacitor connection 1 for charge pump
17
BC2
Output
Capacitor connection 2 for charge pump
18
VPUMP
Output
Charge pump circuit output
19
N.C.
20
STPHAB
Output
21
VREFAB
Input
Phase A/B Torque reference voltage input
22
PWMSWAB
Input
Phase A/B PWM OFF period selection input
23
DECAY1AB
Input
Phase A/B Mix Decay setup 1
24
BOUT2
Output
Phase B motor drive output 2
25
N.C.
26
RCSB
27
N.C.
28
BOUT1
Output
Phase B motor drive output 1
29
AOUT2
Output
Phase A motor drive output 2
30
N.C.
31
RCSA
32
N.C.
33
AOUT1
34
DECAY2AB
Input
—
—
—
Input/Output
—
—
Input/Output
—
Test mode setup
Die pad ground 1
N.C.
Phase A/B Home Position / Step detection signal output
N.C.
Phase B motor current detection
N.C.
N.C.
Phase A motor current detection
N.C.
Output
Phase A motor drive output 1
Input
Phase A/B Mix Decay setup 2
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
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52
7
Pin Descriptions (continued)
Pin No.
Pin name
Type
Description
35
ST1AB
Input
Phase A/B excitation selection 1
36
ST2AB
Input
Phase A/B excitation selection 2
37
ST3AB
Input
Phase A/B excitation selection 3
38
DIRAB
Input
Phase A/B rotation direction setup
39
CLKAB
Input
Phase A/B clock input
40
ENABLEAB
Input
Phase A/B Enable / disable CTL
41
VM2
42
COM2
43
VM1
Power supply
44
STBY
Input
Standby
45
ENABLECD
Input
Phase C/D Enable / disable CTL
46
CLKCD
Input
Phase C/D clock input
47
DIRCD
Input
Phase C/D rotation direction setup
48
ST3CD
Input
Phase C/D excitation selection 3
49
ST2CD
Input
Phase C/D excitation selection 2
50
ST1CD
Input
Phase C/D excitation selection 1
51
DECAY2CD
Input
Phase C/D Mix Decay setup 2
52
COUT1
Output
Phase C motor drive output 1
53
N.C.
54
RCSC
55
N.C.
56
COUT2
Power supply
—
—
Input/Output
—
Output
Power supply 2 for motor
Die pad ground 2
Power supply 1 for motor
N.C.
Phase C motor current detection
N.C.
Phase C motor drive output 2
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
8
Absolute Maximum Ratings
Note) Absolute maximum ratings are limit values which do not result in damages to this IC, and IC operation is not guaranteed at these limit values.
A No.
Parameter
Symbol
Rating
Unit
Notes
1
Supply voltage (Pin 41, 43)
VM
37
V
*1
2
Power dissipation
PD
448
mW
*2
3
Operating ambient temperature
Topr
–20 to +85
°C
*3
4
Storage temperature
Tstg
–55 to +150
°C
*3
5
Output pin voltage (Pin 1, 5, 24, 28, 29, 33, 52, 56)
VOUT
37
V
*4
6
Motor drive current 1 (Pin 24, 28, 29, 33)
IOUT1
±1.0
A
*5
7
Motor drive current 2 (Pin 1, 5, 52, 56)
IOUT2
±1.7
A
*5
8
Flywheel diode current 1(Pin 24, 28, 29, 33)
If1
±1.0
A
*5
9
Flywheel diode current 2 (Pin 1, 5, 52, 56)
If2
±1.7
A
*5
Notes) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2 : The power dissipation shown is the value at Ta = 85°C for the independent (unmounted) IC package without a heat sink.
When using this IC, refer to the PD-Ta diagram of the package standard and design the heat radiation with sufficient margin so that the
allowable value might not be exceeded based on the conditions of power supply voltage, load, and ambient temperature.
*3 : Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.
*4 :This is a rated value of output voltage, and do not apply input voltage from outside to these pins. Set not to exceed the allowable range at any
time.
*5 :Do not apply external current to any pin specially mentioned. For circuit currents, (+) denotes current flowing into the IC and (–) denotes
current flowing out of the IC.
Operating Supply Voltage Range
Parameter
Supply voltage range
Symbol
Range
Unit
Notes
VM
10.0 to 34.0
V
*1
Note) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
9
Allowable Current and Voltage Range
Notes) y Allowable current and voltage ranges are limit ranges which do not result in damages to this IC, and IC operation is not guaranteed within
these limit ranges.
y Voltage values, unless otherwise specified, are with respect to GND.
y Do not apply external currents or voltages to any pin not specifically mentioned.
y For the circuit currents, "+" denotes current flowing into the IC, and "−" denotes current flowing out of the IC.
Pin No.
Pin name
Rating
Unit
Notes
Pin No.
Pin name
Rating
Unit
Notes
3
RCSD
2.5
V
—
9
STPHCD
2
mA
*1
6
DECAY1CD
−0.3 to 6
V
—
11
NFAULT
2
mA
*1
7
PWMSWCD
−0.3 to 6
V
—
13
S5VOUT
−7 to 0
mA
—
8
VREFCD
−0.3 to 6
V
—
20
STPHAB
2
mA
*1
9
STPHCD
−0.3 to 6
V
*1
11
NFAULT
−0.3 to 6
V
*1
12
TEST
−0.3 to 6
V
—
17
BC2
(VM – 1) to 43
V
*2
18
VPUMP
(VM – 2) to 43
V
*2
20
STPHAB
−0.3 to 6
V
*1
21
VREFAB
−0.3 to 6
V
—
22
PWMSWAB
−0.3 to 6
V
—
23
DECAY1AB
−0.3 to 6
V
—
26
RCSB
2.5
V
—
31
RCSA
2.5
V
—
34
DECAY2AB
−0.3 to 6
V
—
35
ST1AB
−0.3 to 6
V
—
36
ST2AB
−0.3 to 6
V
—
37
ST3AB
−0.3 to 6
V
—
38
DIRAB
−0.3 to 6
V
—
39
CLKAB
−0.3 to 6
V
—
40
ENABLEAB
−0.3 to 6
V
—
44
STBY
−0.3 to 6
V
—
45
ENABLECD
−0.3 to 6
V
—
46
CLKCD
−0.3 to 6
V
—
47
DIRCD
−0.3 to 6
V
—
48
ST3CD
−0.3 to 6
V
—
49
ST2CD
−0.3 to 6
V
—
50
ST1CD
−0.3 to 6
V
—
51
DECAY2CD
−0.3 to 6
V
—
2.5
V
54
RCSC
Notes) *1 : This pin is connected to open drain circuit inside. Connect a
resistor in series with power supply.
Do not exceed the rated value at any time. Refer to page 4 for
the recommended value.
*2 : External voltage must not be applied to this pin. Do not exceed
—
the rated value at any time.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
10
Electrical Characteristics at VM = 24.0 V
Note)
Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Test
circuits
Limits
Conditions
Min
Typ
Max
Unit
Notes
Power block
1
Output saturation voltage 1 High
VOH1
2
I = –0.5 A (Pin 24, 28, 29, 33)
VM
– 0.5
VM
– 0.3
—
V
—
2
Output saturation voltage 1 Low
VOL1
2
I = 0.5 A (Pin 24, 28, 29, 33)
—
0.48
0.75
V
—
3
Output saturation voltage 2 High
VOH2
2
I = –0.8 A (Pin 1, 5, 52, 56)
—
V
—
4
Output saturation voltage 2 Low
VOL2
2
I = 0.8 A (Pin 1, 5, 52, 56)
—
0.64
0.97
V
—
5
Flywheel diode forward voltage 1
VDI1
2
I = 0.5 A (Pin 24, 28, 29, 33)
0.5
1
1.5
V
—
6
Flywheel diode forward voltage 2
VDI2
2
I = 0.8 A (Pin 1, 5, 52, 56)
0.5
1
1.5
V
—
7
Upper-side output OFF current
IOUTOFF1
2
VM = 37 V, VRCS = 0 V,
OUT = 0 V
−10
—
—
μA
*1
8
Lower-side output OFF current
IOUTOFF2
2
VM = 37 V, VRCS = 0 V,
OUT = 37 V
—
—
100
μA
*1
VM
VM
– 0.55 – 0.35
Supply current
9
Supply current (Active)
IM
1
ENABLEAB = ENABLECD =
Low, STBY = High
—
10
19
mA
—
10
Supply current (STBY)
IMSTBY
1
STBY = Low
—
22
40
μA
—
I/O block
11
STBY High-level input voltage
VSTBYH
1
—
2.1
—
5.5
V
—
12
STBY Low-level input voltage
VSTBYL
1
—
0
—
0.6
V
—
13
STBY High-level input current
ISTBYH
1
STBY = 5 V
25
50
100
μA
—
14
STBY Low-level input current
ISTBYL
1
STBY = 0 V
−2
—
2
μA
—
15
CLK High-level input voltage
VCLKH
1
—
2.1
—
5.5
V
*2
16
CLK Low-level input voltage
VCLKL
1
—
0
—
0.6
V
*2
17
CLK High-level input current
ICLKH
1
CLK = 5 V
25
50
100
μA
*2
18
CLK Low-level input current
ICLKL
1
CLK = 0 V
−2
—
2
μA
*2
19
CLK maximum input frequency
fCLK
1
—
50
—
—
kHz
*2
20
ENABLE High-level input voltage
VENABLEH
1
—
2.1
—
5.5
V
*3
21
ENABLE Low-level input voltage
VENABLEL
1
—
0
—
0.6
V
*3
22
ENABLE High-level input current
IENABLEH
1
ENABLE = 5 V
25
50
100
μA
*3
23
ENABLE Low-level input current
IENABLEL
1
ENABLE = 0 V
−2
—
2
μA
*3
Notes) *1 : OUT represents AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and DOUT2.
*2 : CLK represents CLKAB and CLKCD.
*3 : ENABLE represents ENABLEAB and ENABLECD.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
11
Electrical Characteristics (continued) at VM = 24.0 V
Note)
Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Limits
Test
circuits
Conditions
Min
Typ
Max
Unit
Notes
I/O block (continued)
24
PWMSW High-level input voltage VPWMSWH
1
—
2.3
—
5.5
V
*4
25
PWMSW Middle-level input
voltage
VPWMSWM
1
—
1.3
—
1.7
V
*4
26
PWMSW Low-level input voltage
VPWMSWL
1
—
0
—
0.6
V
*4
27
PWMSW High-level input current
IPWMSWH
1
PWMSW = 5 V
40
83
150
μA
*4
28
PWMSW Low-level input current
IPWMSWL
1
PWMSW = 0 V
–70
–36
–18
μA
*4
29
PWMSW open voltage
VPWMSWO
1
—
1.3
1.5
1.7
V
*4
30
DECAY High-level input voltage
VDECAYH
1
—
2.1
—
5.5
V
*5
31
DECAY Low-level input voltage
VDECAYL
1
—
0
—
0.6
V
*5
32
DECAY High-level input current
IDECAYH
1
DECAY = 5 V
25
50
100
μA
*5
33
DECAY Low-level input current
IDECAYL
1
DECAY = 0 V
−2
—
2
μA
*5
34
DIR High-level input voltage
VDIRH
1
—
2.1
—
5.5
V
*6
35
DIR Low-level input voltage
VDIRL
1
—
0
—
0.6
V
*6
36
DIR High-level input current
IDIRH
1
DIR = 5 V
25
50
100
μA
*6
37
DIR Low-level input current
IDIRL
1
DIR = 0 V
−2
—
2
μA
*6
38
ST High-level input voltage
VSTH
1
—
2.1
—
5.5
V
*7
39
ST Low-level input voltage
VSTL
1
—
0
—
0.6
V
*7
40
ST High-level input current
ISTH
1
ST = 5 V
25
50
100
μA
*7
41
ST Low-level input current
ISTL
1
ST = 0 V
−2
—
2
μA
*7
Torque control block
42
Input bias current 1
IREFH
1
VREFAB = VREFCD = 5 V
−2
—
2
μA
—
43
Input bias current 2
IREFL
1
VREFAB = VREFCD = 0 V
−2
—
2
μA
—
44
PWM OFF time 1
TOFF1
1
PWMSW = Low
16.8
28
39.2
μs
*4
45
PWM OFF time 2
TOFF2
1
PWMSW = High
9.1
15.2
21.3
μs
*4
46
PWM OFF time 3
TOFF3
1
PWMSW = Middle
4.9
8.1
11.3
μs
*4
47
Pulse blanking time
TB
1
VREFAB = VREFCD = 0 V
0.4
0.7
1.0
μs
—
48
Comp threshold
VTCMP
1
VREFAB = VREFCD = 5 V
475
500
525
mV
—
Reference voltage block
49
Reference voltage
VS5VOUT
1
IS5VOUT = 0 mA
4.75
5.0
5.25
V
—
50
Output impedance
ZS5VOUT
1
IS5VOUT = –7 mA
—
—
10
Ω
—
Notes) *4 : PWMSW represents PWMSWAB and PWMSWCD.
*5 : DECAY represents DECAY1AB, DECAY2AB, DECAY1CD and DECAY2CD.
*6 : DIR represents DIRAB and DIRCD.
*7 : ST represents ST1AB, ST2AB, ST3AB, ST1CD, ST2CD and ST3CD.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
12
Electrical Characteristics (continued) at VM = 24.0 V
Note)
Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Test
circuits
Limits
Conditions
Min
Typ
Max
Unit
Notes
Abnormal detection output block
51
NFAULT pin output Low-level
voltage
52
NFAULT pin output leak current
VNFAULTL
1
INFAULT = 1 mA
—
—
0.2
V
—
INFAULT(leak)
1
VNFAULT = 5 V
—
—
5
μA
—
VSTPHL
1
ISTPH = 1 mA
—
—
0.2
V
*8
ISTPH(leak)
1
VSTPH = 5 V
—
—
5
μA
*8
Home Position/ STEP detection output block
53
STPH pin output Low-level
voltage
54
STPH pin output leak current
Test input block
55
TEST High-level input voltage
VTESTH
1
—
4.0
—
5.5
V
—
56
TEST Low-level input voltage
VTESTL
1
—
0
—
0.6
V
—
57
TEST High-level input current
ITESTH
1
TEST = 5 V
25
50
100
μA
—
58
TEST Low-level input current
ITESTL
1
TEST = 0 V
−2
—
2
μA
—
Note) *8 : STPH represents STPHAB and STPHCD.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
13
Electrical Characteristics (Reference values for design) at VM = 24.0 V
Notes) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, we will respond in good faith to user concerns.
B
No.
Parameter
Symbol
Test
circuits
Reference values
Conditions
Min
Typ
Max
Unit
Notes
Output block
59
Output slew rate 1
VTr
—
At the rising edge of output
voltage, sink side of motor
current
—
350
—
V/μs
*9
60
Output slew rate 2
VTf
—
At the falling edge of output
voltage, sink side of motor
current
—
−400
—
V/μs
*9
61
Dead time
TD
—
—
—
0.8
—
μs
*9
TSDon
—
—
—
150
—
°C
—
Thermal shutdown protection
62
Thermal shutdown protection
operating temperature
Under voltage lockout
63
Protection start voltage
VUVLO1
—
—
—
7.5
—
V
—
64
Protection stop voltage
VUVLO2
—
—
—
8.5
—
V
—
Note) *9 : The characteristics of all outputs of AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and DOUT2 are shown.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
S17
2
1
Established
10 kΩ
15 Ω
V
330 μH
V
A
V
V
1 2 3
A
V
S12
1 2 3
V
36 ST2AB
35 ST1AB
34 DECAY2AB IDECAY2AB
VREFAB 21
PWMSWAB 22
DECAY1AB 23
IPWMSWAB
IDECAY1AB
A
V
S3
V
A
2
S18
1
1 2 3
29 AOUT2
30 N.C.
VRCSA
VAOUT2
VAOUT1
V
BOUT1 28
N.C. 27
31 RCSA
RCSB 26
5.6 Ω
1 kΩ
VDECAY2AB
VST1AB
VST2AB
75 Ω 12 V
1
5.6 Ω
32 N.C.
N.C. 25
IST1AB
IST2AB
VST3AB
S6
1 kΩ
VRCSB
IVREFAB
IST3AB
A
75 Ω
1 2 3
A
33 AOUT1
37 ST3AB
STPHAB 20
VDIRAB
VCLKAB
3 2 1
330 μH
75 Ω 12 V
2
VBOUT1
A
A
BOUT2 24
38 DIRAB
N.C. 19
VVPUMP
IDIRAB
ICLKAB
39 CLKAB
VPUMP 18
0.01 μF
VENABLEAB
15 Ω
S19
VBOUT2
41 VM2
BC1 16
24 V
75 Ω 12 V
10 kΩ
12 V
S11
A
VDECAY1AB
42 COM2
COM1 15
40 ENABLEAB IENABLEAB
V
BC2 17
0.01 μF
A
75 Ω
VVREFAB
43 VM1
GND 14
VSTBY
VENABLECD
VCLKCD
VDIRCD
VST3CD
VST2CD
VST1CD
VDECAY2CD
75 Ω 12 V
Product Standards
VPWMSWAB
ISTBY
44 STBY
S5VOUT 13
IVM1
45 ENABLECD IENABLECD
TEST 12
S9
A A
12 V
S10
A
5 V 2.5 kΩ
V
IS5VOUT
VS5VOUT
ITEST
ICLKCD
A A
ISTPHAB
A
VSTPHAB
A A A
A
5V
1 2 3
A
5V
46 CLKCD
NFAULT 11
IDIRCD
A
5 V 2.5 kΩ
VTEST
47 DIRCD
TjmonABCD 10
IST3CD
A
INFAULT
48 ST3CD
STPHCD 9
IST2CD
49 ST2CD
VREFCD 8
IVREFCD
A
VNFAULT
S2
VVREFCD
1 2 3
IST1CD
S13
50 ST1CD
S16
IPWMSWCD PWMSWCD 7
3 2 1
VPWMSWCD
A A
5V
1 2 3
S7
51 DECAY2CD IDECAY2CD
VCOUT1
V
IDECAY1CD DECAY1CD 6
VRCSC
V
52 COUT1
53 N.C.
N.C. 4
3 2 1
DOUT2 5
54 RCSC
RCSD 3
VCOUT2
330 μH
VDECAY1CD
1 kΩ
5.6 Ω
1 kΩ
1
5 V 2.5 kΩ
V
5.6 Ω
55 N.C.
56 COUT2
N.C. 2
DOUT1 1
S8
VDOUT2
VRCSD
2
ISTPHCD
S1
VDOUT1
S20
VSTPHCD
12 V 75 Ω
12 V 75 Ω
AN44071A
Total Pages
Page
52
14
Test Circuit Diagram
1. Test Circuit 1
10 kΩ
15 Ω
3 2 1
V
3 2 1
S5
3 2 1
S15
S14
1 2 3
V
S4
1 2 3
10 kΩ
15 Ω
330 μH
2010-08-20
Revised
Semiconductor Company, Panasonic Corporation
VSDOUT1
Established
V
V
0.01 μF
S2
2
41 VM2
BC1 16
0.6 V
37 ST3AB
STPHAB 20
1
A
DECAY1AB 23
0.6 V
V
S3
2
1
A
30 N.C.
N.C. 27
29 AOUT2
31 RCSA
RCSB 26
0.6 V
0.6 V
1
BOUT1 28
32 N.C.
N.C. 25
33 AOUT1
34 DECAY2AB
PWMSWAB 22
0.6 V
S7
BOUT2 24
35 ST1AB
VREFAB 21
VVREFAB
0.6 V
0.6 V
38 DIRAB
N.C. 19
36 ST2AB
VCLKAB
39 CLKAB
VPUMP 18
VENABLEAB
ISCOUT1
VCOUT1
Page
52
15
A
2
S6
IAOUT2
VSAOUT2
ISAOUT2
VAOUT2
IAOUT1
VSAOUT1
ISAOUT1
VAOUT1
ICOUT1 VSCOUT1
Total Pages
VBOUT1
42 COM2
COM1 15
40 ENABLEAB
VM
43 VM1
GND 14
BC2 17
2.1 V
44 STBY
S5VOUT 13
S9
0.01 μF
VCLKCD
VENABLECD
2
V
ISBOUT1
46 CLKCD
NFAULT 11
0.6 V
S10
A
IBOUT1
47 DIRCD
TjmonABCD 10
0.6 V
0.6 V
0.6 V
1
VBOUT2
48 ST3CD
STPHCD 9
45 ENABLECD
49 ST2CD
VREFCD 8
TEST 12
50 ST1CD
PWMSWCD 7
S8
VTEST
VVREFCD
0.6 V
0.6 V
2
V
VSBOUT1
A
51 DECAY2CD
ICOUT2
VSCOUT2
ISCOUT2
VCOUT2
Product Standards
ISBOUT2
1
A
IBOUT2
2
VDOUT2
S1
DECAY1CD 6
1
ISDOUT2
0.6 V
52 COUT1
53 N.C.
N.C. 4
DOUT2 5
54 RCSC
RCSD 3
2
IDOUT2
VDOUT1
55 N.C.
56 COUT2
A
V
VSBOUT2
A
ISDOUT1
1
N.C. 2
DOUT1 1
V
VSDOUT2
IDOUT1
AN44071A
Test Circuit Diagram (continued)
2. Test Circuit 2
1
S5
S4
2
V
2010-08-20
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
16
Electrical Characteristics Test Procedures
1. Test Circuit 1
C
No.
Measuring
pin
S1
to
S8
S10 S13 S17
to
to
S9 to
S12 S16 S20
VCLK
VDECAY1
VSTBY VENABLE VPWMSW VRCS
VDECAY2
*1
*2
*3
*4
*5
VDIR
*6
VST1
VST2 VTEST VVREF VVPUMP IS5VOUT
VST3
*7
*8
9, 11
41, 43, 44
1
ON
1
1
—
0.6 V
0.6 V
2.1 V
0.6 V
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
Hi-Z
Hi-Z
10
41, 43
1
ON
1
1
—
0.6 V
0.6 V
0.6 V
0.6 V
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
Hi-Z
Hi-Z
12
13, 44
1
ON
1
1
—
0.6 V
0.6 V
0.6 V
2.1 V
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
Hi-Z
Hi-Z
49
13
1
ON
1
1
—
0.6 V
0.6 V
2.1 V
2.1 V
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
Hi-Z
Hi-Z
50
13
1
ON
1
1
—
0.6 V
0.6 V
2.1 V
2.1 V
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
Hi-Z
–7 mA
13, 17, 6, 7, 12, 22,
22, 27, 23, 34 to
32, 36,
40,
40, 57
44 to 51
1
ON
1
1
—
5V
5V
5V
5V
5V
0V
5V
5V
5V
5V
Hi-Z
Hi-Z
18,
6, 7, 12, 22,
23, 28, 23, 34 to
33, 37,
40,
41, 58
45 to 51
1
ON
1
1
—
0V
0V
5V
0V
0V
0V
0V
0V
0V
5V
Hi-Z
Hi-Z
14
44
1
ON
1
1
—
0V
0V
0V
0V
0V
0V
0V
0V
0V
5V
Hi-Z
Hi-Z
42
8, 21
1
ON
1
1
—
0V
0V
2.1 V
0V
0V
0V
0V
0V
0V
5V
Hi-Z
Hi-Z
43
8, 21
1
ON
1
1
—
0V
0V
2.1 V
0V
0V
0V
0V
0V
0V
0V
Hi-Z
Hi-Z
20, 21
33, 52,
40, 45
1
OFF
1
1
—
0.6 V
0.6 V
2.1 V
Sweep
0.6 V
0V
0.6 V 0.6 V 0.6 V
5V
29V
Hi-Z
48
29, 24, 56,
5, 3, 26,
31, 54
3
ON
1
1
2
0.6 V
0.6 V
2.1 V
2.1 V
0.6 V
0.475
V,
0.6 V 0.6 V 0.6 V
0.525
V
5V
Hi-Z
Hi-Z
15, 16,
19
33, 29, 28,
24, 52, 56,
1, 5
2
ON
1
1
—
0.6 V
/ 2.1 V
50 kHz
pulse
0.6 V
2.1 V
2.1 V
5V
0V
5V
Hi-Z
Hi-Z
29
7, 22
1
ON
1
1
—
0V
0V
2.1 V
0V
Hi-Z
0V
0V
Hi-Z
Hi-Z
55
9, 20
1
ON
2
1
—
Pulse
input
0.6 V
2.1 V
2.1 V
0.6 V
0V
0.6 V 0.6 V 4.0 V
5V
Hi-Z
Hi-Z
56
9, 20
2
ON
2
1
—
Pulse
input
0.6 V
2.1 V
2.1 V
1.7 V
0V
0.6 V 2.1 V 0.6 V
5V
Hi-Z
Hi-Z
0.6 V 0.6 V 0.6 V
0V
0V
0V
Notes) *1 : CLK represents CLKAB and CLKCD.
*2 : DECAY1 represents DECAY1AB and DECAY1CD.
DECAY2 represents DECAY2AB and DECAY2CD.
*3 : ENABLE represents ENABLEAB and ENABLECD.
*4 : PWMSW represents PWMSWAB and PWMSWCD.
*5 : RCS represents RCSA, RCSB, RCSC and RCSD.
*6 : DIR represents DIRAB and DIRCD.
*7 : ST1 represents ST1AB and ST1CD.
ST2 represents ST2AB and ST2CD.
ST3 represents ST3AB and ST3CD.
*8 : VREF represents VREFAB and VREFCD.
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
17
Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
20) ENABLE High-level input voltage VENABLEH
21) ENABLE Low-level input voltage VENABLEL
Sweep ENABLE voltage, and check that VAOUT1 and VCOUT1 switch as follows.
VAOUT1
/VCOUT1
24 V
SPEC
SPEC
0V
VENABLEL
VENABLEH
0.6 V
48) Comp threshold
VENABLE
2.1 V
VTCMP
Measure the voltages of VAOUT2, VBOUT2, VCOUT2 and VDOUT2. when input voltage is set to 0.475 V and 0.525 V respectively.
VAOUT2
/VBOUT2
/VCOUT2
/VDOUT2
24 V
(A) area
(B) area
(A) area : Always output Low-level
(B) area : Output High-level as measurement value
(Average)
SPEC
12 V
SPEC
0V
VRCSA / VRCSB /VRCSC /VRCSD
0.475 V
50) Output impedance
0.525 V
ZS5VOUT
VS5OUT
ZS5VOUT =
VS5VOUT – VA
7 mA
VS5VOUT
VA
0 mA
–7 mA
IS5VOUT
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
18
Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
15) CLK High-level input voltage VCLKH
16) CLK Low-level input voltage VCLKL
19) CLK maximum input frequency fCLK
Input the pulse of 50 kHz as CLK as follows.
Low-level voltage = 0.6 V
High-level voltage = 2.1 V
When the frequency of VAOUT1, VCOUT1, VAOUT2, VCOUT2, VBOUT1, VDOUT1, VBOUT2 and VDOUT2 is 25 kHz, measure CLK Highlevel input voltage, CLK Low-level input voltage and CLK maximum input frequency.
50 kHz
2.1 V
VCLKAB
/VCLKCD
0.6 V
24 V
VAOUT1 12 V
/VCOUT1
0V
24 V
VAOUT2
12 V
/VCOUT2
0V
fAOUT1/fCOUT1
fAOUT2/fCOUT2
24 V
VBOUT1 12 V
/VDOUT1
0V
24 V
VBOUT2
12 V
/VDOUT2
0V
55) TEST High-level input voltage
56) TEST Low-level input voltage
fBOUT1/fDOUT1
fBOUT2/fDOUT2
VTESTH
VTESTL
Check that the output status is as follows when Low-level input voltage (0.6 V) and High-level input voltage (4.0 V) are applied
to TEST pin, Low-level / High-level input voltage to TEST pin.
Table
Output status at TEST Low / High-level input voltage
Parameter
TEST pin voltage
conditions
TEST Low-level input voltage
0.6 V
STPH pin = Step detection output (Refer to page 44 for details.)
TEST High-level input voltage
4.0 V
STPH pin = Home Position output (Refer to page 40 to 43 for details.)
Status
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
19
Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
C Measure
No. ment pin
S1
to
S8
S9
S10 S13 S17
to to to
S12 S16 S20
33, 29, 28,
34,
24, 52, 56,
35,
2
1, 5,
38,
35 to 38,
39
47 to 50
OFF
2
1
—
24,
25,
33, 29, 28,
26,
24, 52, 56,
3
44,
1, 5,
45,
7, 22
46,
47
ON
1
3
1
33, 29, 28,
30, 24, 52, 56,
2
31 1, 5, 6, 23,
34, 51
OFF
2
3
—
VCLK
VDECAY1
VSTBY VENABLE VPWMSW VRCS
VDECAY2
Pattern Pattern
Pulse
input
2.1 V
0.6 V
2.1 V
Pattern Pattern
2.1 V
34) DIR High-level input voltage
35) DIR Low-level input voltage
38) ST1/ST2/ST3 High-level input voltage
39) ST1/ST2/ST3 Low-level input voltage
VDIR
VST1
VST2
VST3
VTEST
VVREF VVPUMP IS5VOUT
Pattern Pattern Pattern Pattern Pattern Pattern Pattern
30 V
Hi-Z
0.5 V
Hi-Z
Hi-Z
Pattern Pattern Pattern Pattern Pattern Pattern Pattern
30 V
Hi-Z
2.1 V
0.6 V
1.3 V
1.7 V
2.3 V
—
0.6 V
0.6 V
0.6 V
VDIRH
VDIRL
VSTH
VSTL
Check the logic related to the operation of each excitation mode in page 35 to 38 under the conditions that the input voltage of
DIR, ST1, ST2 and ST3 is set as follows. Confirm Low-level / High-level of DIR, ST1, ST2 and ST3 by checking the logic.
DIR
ST1
ST2
ST3
0.6 V
0.6 V
0.6 V
0.6 V
2-phase excitation drive (4-step sequence) / Forward
0.6 V
0.6 V
2.1 V
0.6 V
Half step drive (8-step sequence) / Forward
0.6 V
2.1 V
0.6 V
0.6 V
1-2 phase excitation drive (8-step sequence) / Forward
0.6 V
2.1 V
2.1 V
0.6 V
W1-2 phase excitation drive (16-step sequence) / Forward
0.6 V
0.6 V
2.1 V
2.1 V
2W1-2 phase excitation drive (32-step sequence) / Forward
2.1 V
0.6 V
0.6 V
0.6 V
2-phase excitation drive (4-step sequence) / Reverse
2.1 V
0.6 V
2.1 V
0.6 V
Half step drive (8-step sequence) / Reverse
2.1 V
2.1 V
0.6 V
0.6 V
1-2 phase excitation drive(8-step sequence) / Reverse
2.1 V
2.1 V
2.1 V
0.6 V
W1-2 phase excitation drive (16-step sequence) / Reverse
2.1 V
0.6 V
2.1 V
2.1 V
2W1-2 phase excitation drive (32-step sequence) / Reverse
Excitation mode
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
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20
Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
24) PWMSW High-level input voltage
25) PWMSW Middle-level input voltage
26) PWMSW Low-level input voltage
44) PWM OFF time 1
45) PWM OFF time 2
46) PWM OFF time 3
47) Pulse blanking time
VPWMSWH
VPWMSWM
VPWMSWL
TOFF1
TOFF2
TOFF3
TB
Each parameter is obtained by the timing chart of VAOUT1, VBOUT1 , VCOUT1, VDOUT1, VAOUT2,VBOUT2, VCOUT2 and VDOUT2 at
VREF = 0.5 V.
The timing chart is shown as follows.
x For 24) to 26), 44) to 47), measure TOFF1, TOFF2 and TOFF3 under the input conditions of PWMSW pin in the below chart.
x For 47), measure the Low-level interval of VAOUT1, VBOUT1, VCOUT1 and VDOUT1 : TB in the below chart.
24 V
VAOUT1 /VBOUT1
VCOUT1 /VDOUT1
TOFF1 / TOFF2 / TOFF3
0V
t[μs]
24 V
VAOUT2 /VBOUT2
VCOUT2 /VDOUT2
0V
t[μs]
TB
Table
TB
PWMSW input voltage vs. TOFF
Voltage conditions
Input pin
Status
VPWMSWH / VPWMSWM / VPWMSWL
PWMSW
0.6 V
TOFF1 = 28 μs
1.3 V
TOFF3 = 8.1 μs
1.7 V
TOFF3 = 8.1 μs
2.3 V
TOFF2 = 15.2 μs
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Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
30) DECAY High-level input voltage
31) DECAY Low-level input voltage
VDECAYH
VDECAYL
Perform the logic test under the conditions that Low-level input voltage of DECAY1/DECAY2 is 0.6 V and High-level input
voltage is 2.1 V.
The timing chart of VAOUT1, VBOUT1 , VCOUT1, VDOUT1, VAOUT2, VBOUT2, VCOUT2 and VDOUT2 is as follows at the logic test.
Measure TDECAY and TOFF-R, and check Low-level / High-level input voltage of DECAY1/DECAY2.
24 V
VAOUT1 /VBOUT1
VCOUT1 /VDOUT1
12 V
TOFF-R
0V
24 V
t[μs]
TDECAY
VAOUT2 /VBOUT2
TDECAY
12 V
VCOUT2 /VDOUT2
0V
t[μs]
Table
DECAY1/2 input voltage vs. Decay control
Decay control (TDECAY / TOFF-R)
DECAY1
DECAY2
0.6 V
0.6 V
0% mode (Slow Decay)
0.6 V
2.1 V
25% mode
2.1 V
0.6 V
50% mode
2.1 V
2.1 V
100% mode
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Electrical Characteristics Test Procedures (continued)
1. Test Circuit 1 (continued)
51) NFAULT pin output Low-level voltage
VNFAULTL
Input 1 mA to NFAULT pin under the condition that the output of NFAULT pin is Low, and measure the voltage of NFAULT
pin.
52) NFAULT pin output leak current
INFAULT(leak)
Input 5 V to NFAULT pin under the condition that the output of NFAULT pin is Hi-Z, measure the leak current.
53) STPH pin output Low-level voltage
VSTPHL
Input 1 mA to STPH pin under the condition that the output of STPH pin is Low, measure the voltage of STPH pin.
54) STPH pin output leak current
ISTPH (leak)
Input 5 V to STPH pin under the condition that the output of STPH pin is Hi-Z, measure the leak current.
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Electrical Characteristics Test Procedures (continued)
2. Test Circuit 2
1)
2)
3)
4)
Output saturation voltage 1 High
Output saturation voltage 1 Low
Output saturation voltage 2 High
Output saturation voltage 2 Low
VOH1
VOL1
VOH2
VOL2
2-phase excitation drive (4-step sequence)
(ST1AB/ST1CD = Low, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low), (DIRAB/DIRCD = Low)
CLKAB/
CLKCD
1
2
3
4
1
2
3
4
1
+100%
VAOUT1/
VCOUT1
0%
–100%
+100%
VAOUT2/
VCOUT2
0%
–100%
+100%
VBOUT1/
VDOUT1
0%
–100%
+100%
VBOUT2/
VDOUT2
0%
–100%
(a) (d)
(b) (c)
FWD
Measure the output saturation voltage High and the output saturation voltage Low under the below conditions.
Measurement
parameter
(a)
B No.1/No.3
(b)
B No.2/No.4
(c)
B No.1/No.3
(d)
B No.2/No.4
Applied pin
AOUT1/BOUT1
COUT1/DOUT1
AOUT1/BOUT1
COUT1/DOUT1
AOUT2/BOUT2
COUT2/DOUT2
AOUT2/BOUT2
COUT2/DOUT2
Measured voltage
VAOUT1/VBOUT1
VCOUT1/VDOUT1
VAOUT1/VBOUT1
VCOUT1/VDOUT1
VAOUT2/VBOUT2
VCOUT2/VDOUT2
VAOUT2/VBOUT2
VCOUT2/VDOUT2
Applied condition
ISAOUT1/ISBOUT1 = −0.5 A
ISCOUT1/ISDOUT1 = −0.8 A
ISAOUT1/ISBOUT1 = +0.5 A
ISCOUT1/ISDOUT1 = +0.8 A
ISAOUT2/ISBOUT2 = −0.5 A
ISCOUT2/ISDOUT2 = −0.8 A
ISAOUT2/ISBOUT2 = +0.5 A
ISCOUT2/ISDOUT2 = +0.8 A
S1 to S8
2
2
2
2
S9
ON
ON
ON
ON
S10
OFF
OFF
OFF
OFF
VM
24 V
24 V
24 V
24 V
VVREFAB /VVREFCD
6V
6V
6V
6V
VTEST
4V
4V
4V
4V
VENABLEAB
/VENABLECD
2.1 V
2.1 V
2.1 V
2.1 V
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Electrical Characteristics Test Procedures (continued)
2. Test Circuit 2 (continued)
5) Flywheel diode forward voltage 1
6) Flywheel diode forward voltage 2
VDI1
VDI2
Measure the Flywheel diode forward voltage 1 and the Flywheel diode forward voltage 2 under the below conditions.
Measurement
parameter
B No.5 (upper-side)
B No.5 (lower-side)
B No.6 (upper-side)
B No.6 (lower-side)
Applied pin
AOUT1/BOUT1
AOUT2/BOUT2
AOUT1/BOUT1
AOUT2/BOUT2
COUT1/DOUT1
COUT2/DOUT2
COUT1/DOUT1
COUT2/DOUT2
Measured voltage
VAOUT1/VBOUT1
VAOUT2/VBOUT2
VAOUT1/VBOUT1
VAOUT2/VBOUT2
VCOUT1/VDOUT1
VCOUT2/VDOUT2
VCOUT1/VDOUT1
VCOUT2/VDOUT2
Applied condition
ISAOUT1/ISBOUT1 = +0.5 A
ISAOUT2/ISBOUT2 = +0.5 A
ISAOUT1/ISBOUT1 = −0.5 A
ISAOUT2/ISBOUT2 = −0.5 A
ISCOUT1/ISDOUT1 = +0.8 A
ISCOUT2/ISDOUT2 = +0.8 A
ISCOUT1/ISDOUT1 = −0.8 A
ISCOUT2/ISDOUT2 = −0.8 A
S1 to S8
2
2
2
2
S9
ON
ON
ON
ON
S10
OFF
OFF
OFF
OFF
VM
0V
0V
0V
0V
VENABLEAB
/VENABLECD
0.6 V
0.6 V
0.6 V
0.6 V
7) Upper-side output OFF current
IOUTOFF1
Measure the output OFF current (IOUTOFF1) in each output pin under the below conditions.
8) Lower-side output OFF current
IOUTOFF2
When the pattern is input to ENABLE pin as follows, and AOUT1, AOUT2, BOUT1, BOUT2, COUT1, COUT2, DOUT1 and
DOUT2 output High, measure the output OFF current (IOUTOFF2) in each output pin.
Measurement
parameter
B No.7
B No.8
Applied pin
Measurement
current
AOUT1/AOUT2
BOUT1/BOUT2
COUT1/COUT2
DOUT1/DOUT2
AOUT1/AOUT2
BOUT1/BOUT2
COUT1/COUT2
DOUT1/DOUT2
Applied
conditions
VSAOUT1 = VSBOUT1 = VSCOUT1 = VSDOUT1
VSAOUT1 = VSBOUT1 = VSCOUT1 = VSDOUT1
= VSAOUT2 = VSBOUT2 = VSCOUT2 = VSDOUT2 = 0 V
= VSAOUT2 = VSBOUT2 = VSCOUT2 = VSDOUT2 = 37 V
S1 to S8
1
1
S9
ON
OFF
S10
OFF
ON
VM
37 V
37 V
VVREFAB /VVREFCD
5V
5V
VTEST
0.6 V
Pattern
VENABLEAB
/VENABLECD
0.6 V
Pattern
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Technical Data
1. I/O block circuit diagrams and pin function descriptions
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Impedance
Description
Pin 10
TjmonABCD
800
10
—
800
—
Pin10 : VBE monitor
—
Pin 1 : Phase D motor drive output 1
3 : Phase D motor current
detection
5 : Phase D motor drive output 2
24 : Phase B motor drive output 2
26 : Phase B motor current
detection
28 : Phase B motor drive output 1
29 : Phase A motor drive output 2
31 : Phase A motor current
detection
33 : Phase A motor drive output 1
52 : Phase C motor drive output 1
54 : Phase C motor current
detection
56 : Phase C motor drive output 2
Pin 18 VPUMP
Phase A/B 2k
Phase C/D 1.5k
1
3
5
24
26
28
29
31
33
52
54
56
Pin
100k
—
100k
1 DOUT1
5 DOUT2
24 BOUT2
28 BOUT1
Pin 29 AOUT2
33 AOUT1
52 COUT1
56 COUT2
Pin 3 RCSD
26 RCSB
31 RCSA
54 RCSC
4k
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Impedance
Description
150
BC1
16
16
—
200
—
Pin 16 : Capacitor connection 1 for
charge pump
—
Pin 17 : Capacitor connection 2 for
charge pump
18 : Charge pump circuit output
125
300k
17
18
—
BC2
VPUMP
17
18
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
35
36
37
38
39
40
45
46
47
48
49
50
Internal circuit
Pin 40
Pin 39
Pin 37
Pin 36
Pin 35
Pin 38
ENABLEAB, Pin 45
CLKAB,
Pin 46
ST3AB,
Pin 48
ST2AB,
Pin 49
ST1AB,
Pin 50
DIRAB,
Pin 47
Impedance
Description
100 kΩ
Pin 40, 45 : Enable / disable CTL
Pin 39, 46 : Clock input
Pin 37, 48 : Excitation selection 3
Pin 36, 49 : Excitation selection 2
Pin 35, 50 : Excitation selection 1
Pin 38, 47 : Rotation direction setup
100 kΩ
Pin 44 : Standby
ENABLECD
CLKCD
ST3CD
ST2CD
ST1CD
DIRCD
152k
—
Pin
4k
100k
STBY
44
32k
44
—
68k
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Impedance
Description
6k
8
21
—
Pin 21 VREFAB
Pin 8 VREFCD
6k
—
Pin 21, 8 :
Torque reference voltage input
—
Pin 13 : Internal reference voltage
(output 5 V)
50k
100
S5VOUT
13
13
—
50k
48k
1k
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Pin 12
TEST
12
—
Impedance
Description
4k
100 kΩ
12
Pin 12 : Test mode setup
100k
Pin 7
PWMSWCD
Pin 22
PWMSWAB
7
22
140k
4k
—
—
Pin 7, 22 : PWM OFF period setup
60k
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Impedance
Description
Pin 9 STPHCD
Pin 11 NFAULT
Pin 20 STPHAB
9
11
20
—
—
Pin 9, 20 : Home Position /
Step detection signal
output
Pin 11 : Abnormal detection output
Pin 6 DECAY1CD
Pin 23 DECAY1AB
Pin 34 DECAY2AB
Pin 51 DECAY2CD
6
23
34
51
30k
—
10k
100 kΩ
Pin 6, 23, 34, 51 :
Mix DECAY setup
70k
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Technical Data (continued)
1. I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Impedance
Description
—
—
S5VOUT (Pin13)
VM(Pin41, Pin43)
—
Diode
—
Zener diode
Ground
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Technical Data (continued)
2. Control mode
Note) * is AB or CD.
1) Truth table (Excitation select)
ENABLE*
DIR*
ST1*
ST2*
ST3*
Low
—
—
—
—
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
Low
High
High
High
Low
High
Low
Low
Low
High
Low
—
—
High
2W1-2 phase excitation drive (32-step sequence)
High
High
Low
Low
Low
2-phase excitation drive (4-step sequence)
High
High
High
High
High
High
High
High
Low
High
High
—
High
Low
High
—
Low
Low
Low
High
Output excitation mode
—
Output OFF
2-phase excitation drive (4-step sequence)
Phase B/D 90°
delay to phase
A/C
Half step drive (8-step sequence)
1-2 phase excitation drive (8-step sequence)
W1-2 phase excitation drive (16-step sequence)
Phase B/D 90° Half step drive (8-step sequence)
advance to phase 1-2 phase excitation drive (8-step sequence)
A/C
W1-2 phase excitation drive (16-step sequence)
2W1-2 phase excitation drive (32-step sequence)
2) Truth table (Control / Charge pump circuit)
STBY
ENABLE*
Low
High (*3)
High (*3)
—
Low
High
Control / Charge
pump circuit
OFF
ON
ON
3) Truth table (PWM OFF period
selection)
Output transistor
PWMSW* PWM OFF period (*5)
Low
28.0 μs
All channel output : OFF
OFF (*4)
ON
4) Truth table (Decay selection)
DECAY1*
Low
Low
High
High
DECAY2*
Low
High
Low
High
Middle
8.1 μs
High
15.2 μs
5) Truth table (STPH output
selection)
Decay control (*6)
Slow Decay
25%
50%
100%
TEST
Low
STPH* output
STEP detection output
High
Home Position output
Note) The above rate is applied to Fast Decay every PWM OFF period.
6) Truth table (NFAULT output)
TSD (*1)
Thermal shutdown
protection start
OCP (*2)
NFAULT
Output transistor
－
Low
All channel output : OFF
－
Over-current detection
start
Low
All channel output : OFF
Thermal shutdown
protection stop
Over-current detection stop
Hi-Z
ON
Notes) *1 : TSD is a latch type protection
→ The protection operation starts at 150°C. (All motor outputs are turned off , and latched.) / The latch is released by Standby or UVLO.
*2 : OCP is a latch type protection
→ All motor outputs are turned off by over-current detection, and be latched. / The latch is released by Standby or UVLO.
In addition, All motor outputs are turned off at under UVLO.
*3 : Input external signals to STBY pin in order to set STBY signal to High-level.
Because, STBY pin cannot be set to High-level when it is connected to S5VOUT(Pin13).
*4 : The output transistors of AB/CD channel are controlled by ENABLEAB/CD respectively.
*5 : The PWM OFF intervals of AB/CD channel are set by PWMSWAB/CD respectively.
*6 : The Decay controls of AB/CD channel are set by DECAY1AB/CD ( DECAY2AB/CD) respectively.
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Technical Data (continued)
3. Each phase current value
1) 1-2 phase, W1-2 phase, 2W1-2 phase
DIRAB / DIRCD = Low
Note) The definition of Phase A, B, C and D current "100%" : (VREFAB(VREFCD) × 0.1) / Motor current detection resistance
1-2 phase
(8-Step)
W1-2 phase
(16- Step)
2W1-2 phase
(32-Step)
A/C phase current
(%)
B/D phase current
(%)
1
1
1
70.7
–70.7
—
—
2
83.2
–55.6
—
2
3
92.4
–38.3
—
—
4
98.1
–19.5
2
3
5
100
0
—
—
6
98.1
19.5
—
4
7
92.4
38.3
—
—
8
83.2
55.6
3
5
9
70.7
70.7
—
—
10
55.6
83.2
—
6
11
38.3
92.4
—
—
12
19.5
98.1
4
7
13
0
100
—
—
14
–19.5
98.1
—
8
15
–38.3
92.4
—
—
16
–55.6
83.2
5
9
17
–70.7
70.7
—
—
18
–83.2
55.6
—
10
19
–92.4
38.3
—
—
20
–98.1
19.5
6
11
21
–100
0
—
—
22
–98.1
–19.5
—
12
23
–92.4
–38.3
—
—
24
–83.2
–55.6
7
13
25
–70.7
–70.7
—
—
26
–55.6
–83.2
—
14
27
–38.3
–92.4
—
—
28
–19.5
–98.1
8
15
29
0
–100
—
—
30
19.5
–98.1
—
16
31
38.3
–92.4
—
—
32
55.6
–83.2
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Technical Data (continued)
3. Each phase current value (continued)
2) 1-2 phase, W1-2 phase, 2W1-2 phase
DIRAB / DIRCD = High
Note) The definition of Phase A, B, C and D current "100%" : (VREFAB(VREFCD) ×0.1) / Motor current detection resistance
1-2 phase
(8-Step)
W1-2 phase
(16-Step)
2W1-2 phase
(32-Step)
A/C phase current
(%)
B/D phase current
(%)
1
1
1
70.7
–70.7
—
—
2
55.6
–83.2
—
2
3
38.3
–92.4
—
—
4
19.5
–98.1
2
3
5
0
–100
—
—
6
–19.5
–98.1
—
4
7
–38.3
–92.4
—
—
8
–55.6
–83.2
3
5
9
–70.7
–70.7
—
—
10
–83.2
–55.6
—
6
11
–92.4
–38.3
—
—
12
–98.1
–19.5
4
7
13
–100
0
—
—
14
–98.1
19.5
—
8
15
–92.4
38.3
—
—
16
–83.2
55.6
5
9
17
–70.7
70.7
—
—
18
–55.6
83.2
—
10
19
–38.3
92.4
—
—
20
–19.5
98.1
6
11
21
0
100
—
—
22
19.5
98.1
—
12
23
38.3
92.4
—
—
24
55.6
83.2
7
13
25
70.7
70.7
—
—
26
83.2
55.6
—
14
27
92.4
38.3
—
—
28
98.1
19.5
8
15
29
100
0
—
—
30
98.1
–19.5
—
16
31
92.4
–38.3
—
—
32
83.2
–55.6
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Technical Data (continued)
4. Each phase current value (Timing chart)
1) 2-phase excitation drive (4-step sequence)
(ST1AB/ST1CD = Low, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low)
1
CLKAB/
CLKCD
2
3
4
1
2
3
4
1
1
CLKAB/
CLKCD
2
3
4
1
2
3
4
1
+100%
+100%
IAOUT1/
ICOUT1
0%
IBOUT1/
IDOUT1
IAOUT1/
ICOUT1
0%
–100%
–100%
+100%
+100%
0%
IBOUT1/
IDOUT1
0%
–100%
–100%
REV
(DIRAB/DIRCD = High)
FWD
(DIRAB/DIRCD = Low)
2) Half step drive (8-step sequence)
(ST1AB/ST1CD = Low, ST2AB/ST2CD = High, ST3AB/ST3CD = Low)
1
2
3
4
5
6
7
8
1
2
CLKAB/
CLKCD
CLKAB/
CLKCD
1
2
3
4
5
6
7
8
+100%
IAOUT1/
ICOUT1
0%
IBOUT1/
IDOUT1
2
+100%
IAOUT1/
ICOUT1
0%
–100%
–100%
+100%
+100%
0%
IBOUT1/
IDOUT1
0%
–100%
–100%
FWD
(DIRAB/DIRCD = Low)
1
REV
(DIRAB/DIRCD = High)
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Technical Data (continued)
4. Each phase current value (Timing chart) (continued)
3) 1-2-phase excitation (8-step sequence)
(ST1AB/ST1CD = High, ST2AB/ST2CD = Low, ST3AB/ST3CD = Low)
1
2
3
4
5
6
7
8
1
1
2
2
3
4
5
6
7
8
1
2
CLKAB/
CLKCD
CLKAB/
CLKCD
+100%
+70.7%
IAOUT1/
ICOUT1
0%
IBOUT1/
IDOUT1
+100%
+70.7%
IAOUT1/
ICOUT1
0%
–70.7%
–100%
–70.7%
–100%
+100%
+70.7%
+100%
+70.7%
0%
IBOUT1/
IDOUT1
0%
–70.7%
–100%
FWD
(DIRAB/DIRCD = Low)
–70.7%
–100%
REV
(DIRAB/DIRCD = High)
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Technical Data (continued)
4. Each phase current value (Timing chart) (continued)
4) W1-2-phase excitation (16-step sequence)
(ST1AB/ST1CD = High, ST2AB/ST2CD = High, ST3AB/ST3CD = Low)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
CLKAB/
CLKCD
+100%
+92.4%
+70.7%
+38.3%
IAOUT1/
ICOUT1
0%
–38.3%
–70.7%
–92.4%
–100%
+100%
+92.4%
+70.7%
+38.3%
IBOUT1/
IDOUT1
0%
–38.3%
–70.7%
–92.4%
–100%
FWD
(DIRAB/DIRCD = Low)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
CLKAB/
CLKCD
+100%
+92.4%
+70.7%
+38.3%
IAOUT1/
ICOUT1
0%
–38.3%
–70.7%
–92.4%
–100%
+100%
+92.4%
+70.7%
IBOUT1/
IDOUT1
+38.3%
0%
–38.3%
–70.7%
–92.4%
–100%
REV
(DIRAB/DIRCD = High)
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Technical Data (continued)
4. Each phase current value (Timing chart) (continued)
5) 2W1-2-phase excitation (32-step sequence)
(ST3AB/ST3CD = High)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2
CLKAB/
CLKCD
+100%
+98.1%
+92.4%
+83.2%
+70.7%
+55.6%
+38.3%
+19.5%
IAOUT1/
ICOUT1
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
+100%/–100%
+98.1%
+92.4%
+83.2%
+70.7%
+55.6%
+38.3%
IBOUT1/
IDOUT1
+19.5%
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
–100%
FWD
(DIRAB/DIRCD = Low)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2
CLKAB/
CLKCD
+100%
+98.1%
+92.4%
+83.2%
+70.7%
+55.6%
+38.3%
IAOUT1/
ICOUT1
+19.5%
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
+100%/–100%
+98.1%
+92.4%
+83.2%
+70.7%
IBOUT1/
IDOUT1
+55.6%
+38.3%
+19.5%
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
–100%
REV
(DIRAB/DIRCD = High)
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Technical Data (continued)
5. Timing chart when DIR switches
(Example 1) Timing chart at 1-2-phase excitation (DIRAB/DIRCD : Low → High)
CLKAB/
CLKCD
DIRAB/
DIRCD
IAOUT1/
ICOUT1
IBOUT1/
IDOUT1
State (DIRAB/DIRCD : Low) 5
6
7
6
5
4
3
When DIRAB(DIRCD) switches,
the state before switching is kept and operates continuously.
(Example 2) Timing chart at 1-2-phase excitation (DIRAB/DIRCD : High → Low)
CLKAB/
CLKCD
DIRAB/
DIRCD
IAOUT1/
ICOUT1
IBOUT1/
IDOUT1
State (DIRAB/DIRCD : High) 5
6
7
6
5
4
3
When DIRAB(DIRCD) switches,
the state before switching is kept and operates continuously.
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Technical Data (continued)
6. Home Position function (TEST = High)
This LSI has built-in Home Position function to reduce the displacement of motor current state at the change of excitation mode
during motor drive. Low-level voltage is output to STPHAB pin and STPHCD pin at the timing when the displacement of motor
current state doesn't occur at the change of excitation mode. The timing when Low-level voltage is output to STPHAB pin and
STPHCD pin is as follows. The Home Position function becomes valid by setting TEST pin to High.
Connect pull-up resistor to power supply (recommendation : S5VOUT), because STPHAB pin and STPHCD pin are composed
by open drain circuit. The recommended value of pull-up resistor is 10 kΩ.
y Home Position output timing chart (DIRAB / DIRCD = Low)
1) 2W1-2-phase excitation
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
CLKAB/
CLKCD
+100%
+98.1%
+92.4%
+83.2%
+70.7%
+55.6%
+38.3%
IAOUT1/
ICOUT1
+19.5%
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
–100%
+100%
+98.1%
+92.4%
+83.2%
+70.7%
+55.6%
IBOUT1/
IDOUT1
+38.3%
+19.5%
+0%
–19.5%
–38.3%
–55.6%
–70.7%
–83.2%
–92.4%
–98.1%
–100%
STPHAB/
STPHCD
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Technical Data (continued)
6. Home Position function (TEST = High) (continued)
y Home Position output timing chart (DIRAB / DIRCD = Low) (continued)
2) W1-2-phase excitation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLKAB/
CLKCD
+100%
+92.4%
+70.7%
+38.3%
IAOUT1/
ICOUT1
0%
–38.3%
–70.7%
–92.4%
–100%
+100%
+92.4%
+70.7%
+38.3%
IBOUT1/
IDOUT1
0%
–38.3%
–70.7%
–92.4%
–100%
STPHAB/
STPHCD
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Technical Data (continued)
6. Home Position function (TEST = High) (continued)
y Home Position output timing chart (DIRAB / DIRCD = Low) (continued)
3) 1-2-phase excitation
1
2
3
4
5
6
7
8
１
CLKAB/
CLKCD
+100%
+70.7%
IAOUT1/
ICOUT1
0%
–70.7%
–100%
+100%
+70.7%
IBOUT1/
IDOUT1
0%
–70.7%
–100%
STPHAB/
STPHCD
4) Half step
1
2
3
4
5
6
7
8
１
CLKAB/
CLKCD
+100%
IAOUT1/
ICOUT1
0%
–100%
+100%
IBOUT1/
IDOUT1
0%
–100%
STPHAB/
STPHCD
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Technical Data (continued)
6. Home Position function (TEST = High) (continued)
y Home Position output timing chart (DIRAB / DIRCD = Low) (continued)
5) 2-phase excitation
1
2
3
4
１
CLKAB/
CLKCD
+100%
IAOUT1/
ICOUT1
0%
–100%
+100%
IBOUT1/
IDOUT1
0%
–100%
STPHAB/
STPHCD
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Technical Data (continued)
7. STEP detection output function (TEST = Low)
Whenever edges signal is input into clock input pins, this IC outputs Low pulse signal from step detection output pins. The Low
pulse width depend on each excitation mode. Refer to the below table. The STEP detection function becomes valid by setting
TEST pin to Low. Connect pull-up resistor to supply voltage (Recommendation : S5VOUT), because STPHAB pin and
STPHCD pin are composed by open drain circuit. The recommended value of pull-up resistor is 10 kΩ.
CLK*
(Clock input pin)
Max. about 1 μs
STPH*
(Step detection output pin)
（* : AB or CD)
T1
Table
Pulse width (T1)
T1
T1
Step detection output pulse width
2-phase excitation
Half step
/ 1-2 phase excitation
W1-2-phase
excitation
2W1-2-phase
excitation
About 20 μs
About 20 μs
About 10 μs
About 5 μs
8. Over-current protection function
This IC has over-current protection (OCP) circuit to protect from the ground-fault etc. of the motor output. When motor current
more than setting value flows to power MOS for about 3.8 μs (Typ.) due to the ground-fault, all motor outputs are turned OFF
by latch operation. OCP is canceled by STBY = Low or UVLO (Under-voltage lockout) operation. However, the OCP circuit do
not guaranteed the protection circuit of set. Therefore, do not use the OCP function of this IC to protect a set. Note that this IC
might break before the protection function operates when it instantaneously exceeds the safe operation area and the maximum
rating. When the inductor element is large due to the length of wiring at ground-fault, note that this IC might break. Because the
motor output voltage falls on a negative voltage or excessively rises after motor current excessively flows to motor outputs. The
setup current of the OCP (reference) is as follows.
Table
Over-current protection setup current (Typ. value)
Setup current
A/Bch motor output
C/Dch motor output
2.2 A
3.3 A
9. About inputting the supply voltage to IF pins when VM power supply is not applied.
This IC does the measures of error for inputting voltage to IF pins when VM power supply is not applied.
IF pin : ENABLE*, DIR*, ST1*, ST2*, ST3*, CLK*, STBY, VREF* (* : AB or CD)
Therefore, this IC doesn't break and it doesn't cause error operation by the input voltage to the IF pins when VM supply voltage
is not supplied.
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Usage Notes
1. Special attention and precaution in using
1) This IC is intended to be used for general electronic equipment [Stepping motor drive].
Consult our sales staff in advance for information on the following applications:
x Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may
directly jeopardize life or harm the human body.
x Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the IC described in this book for any special application, unless our company agrees to your using the IC in this book
for any special application.
2) Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might
smoke or ignite.
3) Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In
addition, refer to the Pin Description for the pin configuration.
4) Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solderbridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because
the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during
transportation.
5) Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pinVM short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) .
Especially, for the pins below, take notice Power supply fault, Ground fault, short to motor current detection pin, load short and
short between the pin.
x Motor drive output pin (Pin 1, 5, 24, 28, 29, 33, 52, 56)
x Motor current detection pin (Pin 3, 26, 31, 54)
x Charge pump circuit pin (Pin 16, 17, 18)
x Power supply (Pin 41, 43)
And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and
smoke emission will depend on the current capability of the power supply.
6) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
7) When using the LSI for new models, verify the safety including the long-term reliability for each product.
8) When the application system is designed by using this LSI, be sure to confirm notes in this book.
Be sure to read the notes to descriptions and the usage notes in the book.
9) Connect the metallic plate (fin) on the back side of the IC with the GND potential. The thermal resistance and the electrical
characteristics are guaranteed only when the metallic plate (fin) is connected with the GND potential.
10) Confirm characteristics fully when using the LSI.
Secure adequate margin after considering variation of external part and this IC including not only static characteristics but
transient characteristics. Especially, Pay attention that abnormal current or voltage must not be applied to external parts because
the pins (Pin 1, 5, 16, 17, 18, 24, 28, 29, 33, 52, 56) output high current or voltage.
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Usage Notes (continued)
2. Notes of Power LSI.
1) Design the heat radiation with sufficient margin so that Power dissipation must not be exceeded base on the conditions of power
supply voltage, load and ambient temperature.
(It is recommended to design to set connective parts to 70% to 80% of maximum rating)
2) The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VM short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be
damaged before the thermal protection circuit could operate.
3) Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins
because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the
ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
4) The product which has specified ASO (Area of Safe Operation) should be operated in ASO.
5) Verify the risks which might be caused by malfunctions of external parts.
6) Set capacitance value between VPUMP and GND so that VPUMP (Pin 18) must not exceed 43 V transiently at the time of
motor standby to motor start.
7) This IC employs a PWM drive method that switches the high-current output of the output transistor. Therefore, the IC is apt
to generate noise that may cause the IC to malfunction or have fatal damage. To prevent these problems, the power supply must
be stable enough. Therefore, the capacitance between the S5VOUT and GND pins must be 0.1 μF and the one between the
VM and GND pins must be a minimum of 47 μF and as close as possible to the IC so that PWM noise will not cause the IC to
malfunction or have fatal damage.
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Usage Notes (continued)
3. Notes of this IC
1) Pulse blanking time
This IC has pulse blanking time (0.7 μs/Typ.value) to prevent erroneous current detection caused by noise. Therefore, the motor
current value will not be less than current determined by pulse blanking time. Pay attention at the time of low current control.
The relation between pulse blanking time and minimum current value is shown as Chart 1. In addition, increase-decrease of
motor current value is determined by L value, wire wound resistance, induced voltage and PWM on Duty inside a motor.
Setup current value
At normal operation
Minimum current value
Setup current value
In case of setting less
than minimum current
value
TB
TPWM
TPWM : PWM OFF period
TB
: Pulse blanking time
(Refer to ■ Electrical Characteristics B No.47)
Chart 1. RCS current waveform
2) VREF voltage
When VREF* voltage is set to Low-level, erroneous detection of current might be caused by noise because threshold of motor
current detection comparator becomes low (= VREF/10 × motor current ratio [%] (Refer to Page 33, 34). Use this IC after
confirming no misdetection with setup VREF* voltage.
If VREF* pin is open, input voltage might be irregular and rise, a large current might flow to the output. Therefore do not use on
condition that VREF* pin is open.
（* : AB or CD)
3) Notes on interface
Absolute maximum of Pin 6 to 8, Pin 12, Pin 21 to 23, Pin 34 to 40 and Pin 44 to 51 is –0.3 V to 6 V. When the setup current for
a motor is large and lead line of GND is long, GND pin potential might rise. Take notice that interface pin potential is negative
to difference in potential between GND pin reference and interface pin in spite of inputting 0 V to the interface pin. At that time,
pay attention allowable voltage range must not be exceeded.
4) Notes on test mode
When inputting voltage of above 0.6 V and below 4.0 V to TEST (Pin 12), this LSI might become test mode.
When disturbance noise etc. makes this LSI test mode, motor might not operate normally. Therefore, use this LSI on condition
that TEST pin is shorted to GND or S5VOUT at normal motor operation.
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Usage Notes (continued)
3. Notes of this IC (continued)
5) Notes on Standby mode release / Under-voltage lockout release
This LSI has all motor outputs OFF period of about 100 μs (typ) owing to release of Standby and UVLO (Refer to the below
figure).
This is why restart from Standby and UVLO after charge pump voltage rises sufficiently because charge pump operation stops at
Standby and UVLO.
When the charge pump voltage does not rise sufficiently during all motor outputs OFF period due to that capacitance between
VPUMP and GND becomes large etc., the IC might overheat and it might not operate normally. In this case, release Standby and
UVLO at ENABLE = Low-level, and restart at ENABLE = High-level after the charge pump voltage rises sufficiently.
Moreover, take notice that state of motor current becomes default position at Standby and UVLO operation following as 3.
Notes of this IC No.6.
After all motor outputs OFF period, the ground-fault detection period is set to about 6.4 μs in order to detect the ground-fault of
motor output before motor is turned on.
All the upper side power MOS are turned on during the above ground fault detection period, and then whether the ground-fault
occurs or not is checked. (Refer to the following contents.)
If the ground-fault is detected at that time, all motor outputs are turned off, and motor drive stops.
【At Standby release】
STBY
Standby
Motor output
Low
Standby
All motor outputs
OFF
High
Standby release
All motor outputs OFF
Ground fault Start (At ENABLE = High)
All motor outputs OFF
detection
(At ENABLE = Low)
About 100 μs(typ)
About 6.4 μs(typ)
【At under-voltage lockout release】
VM
Motor output
Low
High
All motor outputs
OFF (UVLO)
All motor outputs OFF
Start (At ENABLE = High)
About 100 μs(typ)
Ground fault
All motor outputs OFF
detection
(At ENABLE = Low)
About 6.4 μs(typ)
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Usage Notes (continued)
3. Notes of this IC (continued)
6) Default of motor current state
The defaults of motor current state after the releases of UVLO and standby in each excitation mode are as follows.
Table
Default position of each excitation mode
Excitation mode
Default electrical
angle*
2-phase excitation (4-step)
–45°
Half step (8-step)
–45°
1-2 phase excitation (8-step)
–45°
W1-2 phase excitation (16-step)
–45°
2W1-2 phase excitation (32-step)
–45°
*Definition of electric angle
Electric angle is defined as 0° on the conditions of AOUT1/COUT1
current = 100% and BOUT1/DOUT1 current = 0%.
It is defined at DIR = Low as "+" direction.
It is defined at DIR = High as "–" direction.
Electrical angle : 0°
Default electrical angle : –45°
Default position: 2-phase excitation / Half step
AOUT1/COUT1 current
DIR = "L"
Default position :
1-2 / W1-2 / 2W1-2 phase excitation
DIR = "H"
BOUT1/DOUT1 current
7) CLK* input signal and DIR* input signal
The set/hold time of CLK* and DIR* input signals, CLK* input minimum pulse width (High/Low) are as follows.
Input signals after securing set/hold time.
CLK*
C
D
A
B
DIR*/ST1*/
ST2*/ST3*
Period
Contents
Time
A
CLK* input minimum pulse width (High)
10 μs or more
B
CLK* input minimum pulse width (Low)
10 μs or more
C
DIR*/ST1*/ST2*/ST3* set time
2 μs or more
D
DIR*/ST1*/ST2*/ST3* hold time
2 μs or more
* : AB or CD
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Usage Notes (continued)
3. Notes of this IC (continued)
8) CLK input at ENABLE = Low
As the below figure (Ex. 1-2 phase excitation), when inputting CLKAB at the time of motor stop and ENABLEAB = Low (all
motor outputs OFF → Motor current = 0 A), the setup value of motor current will proceed at CLKAB input. Therefore, in case
of restart at ENABLEAB = High, take notice that the position of restart is where the current state just before motor stop gains
CLKAB input. For IBOUT, ICOUT and IDOUT, the operation is same as the below.
Example) 1-2 phase excitation
CLKAB
1 2 3 4 5
6
3 4 5 6 7 8
7 8
1 2
IAOUT
ENABLEAB
High
Low
High
Motor stop
In spite of stop at state[6] , because CLKAB is input at ENABLEAB = Low,
the motor will restart after ENABLEAB = High at state [3].
CLKAB
1 2
3 4 5
6
6 7 8 1 2
IAOUT
ENABLEAB
High
Low
High
Motor stop
In spite of stop at state [6] , because CLKAB is not input at ENABLEAB = Low,
the motor will restart after ENABLE AB= High at state [6] just before stop.
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Usage Notes (continued)
3. Notes of this IC (continued)
9) Notes on RCS line
Take consideration in the below figure and the points and design PCB pattern.
(1) Point 1
Design so that the wiring to the current detection pin (RCSA/RCSB/RCSC/RCSD pin) of this IC is thick and short to
lower impedance. This is why current can not be detected correctly owing to wiring impedance and current might not be
supplied to a motor sufficiently.
(2) Point 2
Design so that the wiring between current detection resister and connecter GND (the below figure Point 2) is thick and
short to lower impedance. As the same as Point 1, sufficient current might not be supplied due to wiring impedance. In
addition, if there is a common impedance on the side of GND of RCSA/RCSB/RCSC/RCSD, peak detection might be
erroneous detection. Therefore, install the wiring on the side of GND of RCSA/RCSB/RCSC/RCSD independently.
(3) Point 3
Connect GND pin of this IC to the connecter on PCB independently. Separate the wiring removed current detection
resister of large current line (Point 2) from GND wiring and make these wirings one-point shorted at the connecter as
the below figure. That can make fluctuation of GND minimum.
Motor current
detection resistor
Point 2
Point 1
(A)
Connecter GND
RCSA/RCSB/RCSC/RCSD
Motor
IC
GND
Point 3
10)
A high current flows into the IC. Therefore, the common impedance of PCB can not be ignored. Take the following points into
consideration and design the PCB pattern for a motor. Because the wiring connecting to VM1 (Pin 43) and VM2 (Pin 41)of this
IC is high-current, it is easy to generate noise at time of switching by wiring L. That might cause malfunction and
destruction (Figure 1). As Figure 2, the escape way of the noise is secured by connecting a capacitor to the connector
close to the VM pin of the IC. This makes it possible to suppress the fluctuation of direct VM pin voltage of the IC. Make the
setting as shown in Figure 2 as much as possible.
Low spike amplitude
due to capacitance
between VM pin
and GND
VM
VM
L
L
VM
VM
GND
GND
IC
IC
C
C
RCS
RCS
GND
GND
Figure 1. No recommended pattern
Figure 2. Recommended pattern
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
AN44071A
Product Standards
Total Pages
Page
52
52
Usage Notes (continued)
3. Notes of this IC (continued)
11)
IC junction temperature
In case of measuring chip temperature of this IC, measure the voltage of TjmonABCD pin (Pin 10) and estimate the chip
temperature from the data below. However, because this data is technical reference data, conduct a sufficient reliability test of
the IC and evaluate the product with the IC incorporated.
TjmonABCD pin temperature characteristics
VBE[V]
ΔVBE / Δtemp = –1.87 [mV / °C]
Temp[°C]
0
150
12) Power-on and Supply voltage change
When supplying to VM pin (Pin 41, 43) or raising supply voltage, set the rise speed of VM voltage to less than 0.1 V/μs . If the
rise speed of supply voltage is too rapid, it might cause error of operation and destruction of the IC. If the rise speed of VM
voltage is more rapid than 0.1V/us, conduct a sufficient reliability test and also check a sufficient evaluation for a product.
In addition, rise the VM supply voltage in an ENABLE = Low state when change VM supply voltage from low voltage to high
voltage within the operating supply voltage range.
Since there is not the all motor outputs OFF period shown in 3. Notes of this IC 5) (page 48) for the supply voltage change
within the operating supply voltage range, the VPUMP voltage is in a low voltage state due to not following to VM supply
voltage change enough, and this IC might not operate normally.
Therefore, restart this IC by setting ENABLE to High after the VPUMP voltage rises enough.
In addition, it is recommended to fall VM voltage in motor stop state (ENABLEAB/CD = Low or STBY = Low) for the stable
fall of supply voltage.
Supply voltage
VM
Rise at less than 0.1 V/μs
Time
13) Pins to set mode
x As for the High/Low setting of DECAY1AB, DECAY2AB, DECAY1CD, DECAY2CD, PWMSWAB and PWMSWCD, it is
recommended to short to GND or S5VOUT. If the above pins are high-impedance such as open, note that this IC might not
operate normally because it easily influences the noise
x PWMSWAB/CD can be set to Middle by setting PWMSWAB/CD to Open. However, it might occur the error of operation due
to the noise. In case, connect the capacity of 0.01 μF or more between PWMSWAB/CD and GND .
2010-08-20
Established
Revised
Semiconductor Company, Panasonic Corporation
Regulations
No.
Total pages
Page
6
1
SC3S1959
Package Standards
Package Code
HSOP056-P-0300B
Semiconductor Company
Panasonic Corporation
Established by
Applied by
Checked by
Prepared by
H.Shidooka
H.Yoshida
M.Okajima
M.Itoh
-
-
Established
Revised
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Package Standards
Total pages
Page
6
2
1. Outline Drawing
Unit:mm
Package Code : HSOP056-P-0300B
゜
゜
Body Material
: Epoxy Resin
Lead Material
: Cu Alloy
Lead Finish Method : Pd Plating
-
-
Established
Revised
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Package Standards
Total pages
Page
6
3
2. Package Structure (Technical Report : Reference Value)
Package Code : HSOP056-P-0300B
Chip Material
Si
1
Leadframe material
Cu alloy
2
Inner lead surface
Pd plating
3
Outer lead surface
Pd plating
4
Method
Resin adhesive method
Material
Adhesive material
Method
Thermo-compression bonding
Material
Au
Method
Transfer molding
Material
Epoxy resin
Chip mount
Wirebond
Molding
Mass
3
4
-
Revised
6
7
250 mg
2
Established
5
1
6
5
7
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Package Standards
Total pages
Page
6
4
3. Mark Layout
Package Code : HSOP056-P-0300B
Product Name
Date Code
1-pin direction
-
-
Established
Revised
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Package Standards
Total pages
Page
6
5
4. Power Dissipation (Technical Report)
Package Code : HSOP056-P-0300B
1.800
Mount On PWB［GlassEpoxy:50X50X0.8t(mm)］
Rth(j-a) = 79.5 ºC/W
1.572
1.600
1.400
Power Dissipation(Ｗ)
1.200
1.000
0.863
0.800
0.600
Without PWB
Rth(j-a) = 144.9 ºC/W
0.400
0.200
0.000
0
25
50
75
100
125
150
o
Ambient Temperature( C )
-
-
Established
Revised
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Package Standards
Total pages
Page
6
6
5. Power Dissipation (Supplementary Explanation)
[Experiment environment]
Power Dissipation（Technical Report）is a result in the experiment environment of SEMI standard
conformity.
（Ambient air temperature (Ta) is 25 degrees C）
[Supplementary information of PWB to be used for measurement]
The supplement of PWB information for Power Dissipation data (Technical Report）are shown
below.
Indication
Total Layer
Resin Material
Glass-Epoxy
1-layer
FR-4
4-layer
4-layer
FR-4
[Notes about Power Dissipation（Thermal Resistance）]
Power Dissipation values（Thermal Resistance）depend on the conditions of the surroundings, such as
specification of PWB and a mounting condition , and a ambient temperature. (Power Dissipation (Thermal
Resistance) is not a fixed value.)
The Power Dissipation value（Technical Report）is the experiment result in specific conditions (evaluation
environment of SEMI standard conformity) ,and keep in mind that Power Dissipation values (Thermal
resistance) depend on circumference conditions and also change.
[Definition of each temperature and thermal resistance]
Ta ：Ambient air temperature
※The temperature of the air is defined at the position where the convection,
radiation, etc. don’t affect the temperature value, and it’s separated from the heating
elements.
Tc ：It’s the temperature near the center of a package surface. The package surface is
defined at the opposite side if the PWB.
Tj ：Semiconductor element surface temperature (Junction temperature.)
Rth(j-c)：The thermal resistance (difference of temperature of per 1 Watts) between a
semiconductor element junction part and the package surface
Rth(c-a)：The thermal resistance (difference of temperature of per 1 Watts) between the
package surface and the ambient air
Rth(j-a)：The thermal resistance (difference of temperature of per 1 Watts) between a
semiconductor element junction part and the ambient air
Ta
[Definition formula]
Tj={Rth(j-c)+Rth(c-a)}×P+Ta
Rth(c-a)
=Rth(j-a)×P+Ta
Rth(j-a)
Tc
Tj
Package
Semiconductor element
Fig1. Definition image
-
Revised
Tj-Tc
P
(℃/W)
Rth(c-a) =
Tc-Ta
P
(℃/W)
Rth(j-a) =
Tj-Ta
P
(℃/W)
Rth(j-c)
PWB
Established
Rth(j-c) =
= Rth(j-c)＋Rth(c-a)
P:power(W)
Semiconductor Company, Panasonic Corporation
Established: 2009-06-05
Revised
: -
Recommended
Soldering Conditions
Total pages
page
2
1
Product name : AN44071A-VF
Package : HSOP056-P-0300B
１．Recommended Soldering Conditions
In case that the semiconductor packages are mounted on the PCB, the soldering should be
performed under the following conditions.
① Reflow soldering
Reflow peak temp. :
℃
260
240
220
200
180
160
140
max. 260 ℃
No． mark
tp
a
T1
t1
contents
value
Tp 260 ℃
255 ℃
1
T1 Pre-heating temp.
2
ｔ１
Pre-heating temp. hold time 60 s～120 s
220 ℃
3
a
Rising rate
b
tw
Time
150 ℃～180 ℃
2 ℃/s～5 ℃/s
4
Tp Peak temp.
255 ℃+5 ℃､-0 ℃
5
tp
Peak temp. hold time
10 s±3 s
6
tw
High temp. region hold time within 60 s (≧220 ℃)
7
b
Down rate
2 ℃/s～5 ℃/s
8
-
Number of reflow
within 2 times
＊Peak temperature : less than 260 ℃
＊Temperature is measured at package surface point
② Wave soldering (Flow soldering)
＊Temp. of solder : 260 ℃ or less
＊Soak time : within 5 s
＊Number of flow : only 1 time
③ Manual soldering
＊Iron Temperature : 350 ℃ or less (Device lead temperature : 270 ℃､10 s max.)
＊Soldering time : within 3 s
＊Number of manual soldering : only 1 time
No. 11-155
2012/3/6
Prepared
Revised
Industrial Devices Company, Panasonic Corporation
Recommended
Soldering Conditions
Total pages
page
2
2
2．Storage environment after dry pack opening
Open dry pack
Soldering
Storage environment kept up to soldering
(at 30 ℃/70 %RH max. , within 168h)
Bake at 125 ℃
with 15 h to 25 h
When the storage time exceeds
*Please refer to the following when
doing at the low temperature bake.
※ Because the taping and the magazine materials are not the heat-resistant materials,
the bake at 125℃ cannot be done.
Therefore, please solder everything or control everything in the rule time.
Please keep them in an equal environment with the moisture-proof packaging or dry box.
(Temperature: room temperature, relative humidity: 30% or less. )
To control storage time, when bake in the taping and the magazine is necessary, it is
necessary for each type to set a bake condition. Please inquire of our company.
☆ AN44071A-VF limitation, low temperature bake condition ： 40 ℃ / 25 %RH or less / 192 h
3．Note
① Storage environment conditions: keep the following conditions Ta=5 ℃～30 ℃､RH=30 %～70 %.
② Storage period before opening dry pack shall be 1year from a shipping day under Ta=5 ℃～30 ℃､
RH=30 %～70 %. When the storage exceeds, Bake at 125 ℃ with 15 h to 25 h.
③ Baking cycle should be only one time.
Please be cautious of solderability at baking.
④ In case that use reflow two times, 2nd reflow must be finished within 168 hours.
⑤ Remove flux sufficiently from product in the washing process.
( Flux : Chlorineless rosin flux is recommended.)
⑥ In case that use ultrasonic for product washing,
There is the possibility that the resonance may occur due to the frequency and shape of PCB.
It may be affected to the strength of lead. Please be cautious of this matter.
No. 11-155
2012/3/6
Prepared
Revised
Semiconductor Company, Panasonic Corporation
Recommended
Land Pattern
Total pages
page
1
1
2009.10.07
Prepared
Revised
Semiconductor Company, Panasonic Corporation
Packing Specification
Total pages
page
3
1
Specifications of packing by the embossment tape
( Specifications for dampproof packing of the reel without the inner carton)
Embossment carrier tape
Top cover tape
C3 Label (Sampl)
Reel
AN12345A-NB
(3N)AN12345A-NB
3000pcs.
1000
(3N)2 10N112200-NB
108010
1.23-45
AN12345A-NB
AN12345A-NB
410N112300 2058
USP4B42516
AN12345A-NB
12345678 3000 23456789 3000 34567890 3000
307 150000
45678901 3000
MADE IN JAPAN
Panasonic M
Desiccant
Laminated aluminum bag
Corrugated cardboard for partition
Inner frame
Outer box
C3 Label (Sampl)
AN12345A-NB
(3N)AN12345A-NB
90000pcs.
1000
(3N)2 10N112200-NB 108010
AN12345A-NB
410N112300 2058
1.23-45
AN12345A-NB
USP4B42516
AN12345A-NB
12345678 3000 23456789 3000 34567890 3000
307
150000
Panasonic M
45678901 3000
MADE IN JAPAN
2009.03.09
Prepared
Revised
Semiconductor Company，Panasonic Corporation
Packing Specification
Total pages
page
3
2
Package : HSOP056-P-0300B
1
Unit : mm
Packing
1) Tape
VF
2) Reel
Draw out direction
Emboss
carrier tape
25.5
330
220
3) Packing case
360
360
2
Packing quantity
Form
IC quantity
Contents
Reel
3000 Pcs
Packing case
15000 Pcs
Reel × 1Pcs
Reel
×
５Pcs
2009.03.09
Prepared
Revised
Semiconductor Company，Panasonic Corporation
Packing Specification
Package : HSOP056-P-0300B
Total pages
page
3
3
Unit : mm
2009.03.09
Prepared
Revised
Semiconductor Company，Panasonic Corporation
Industrial Devices Company, Panasonic Corporation
1 Kotari-yakemachi, Nagaokakyo City, Kyoto 617-8520, Japan
Tel:075-951-8151
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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AN44071A-VF