ONSEMI AMIS30522C5222G

AMIS-30522
Micro-Stepping Motor Driver
1.0 Introduction
The AMIS-30522 is a micro-stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a
SPI interface with an external microcontroller. It has an on-chip voltage regulator, reset-output and watchdog reset, able to supply
peripheral devices. AMIS-30522 contains a current-translation table and takes the next micro-step depending on the clock signal on
the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The chip provides a so-called “speed and load
angle” output. This allows the creation of stall detection algorithms and control loops based on load-angle to adjust torque and
speed. It is using a proprietary PWM algorithm for reliable current control.
The AMIS-30522 is implemented in I2T100 technology, enabling both high-voltage analog circuitry and digital functionality on the
same chip. The chip is fully compatible with the automotive voltage requirements.
The AMIS-30522 is ideally suited for general-purpose stepper motor applications in the automotive, industrial, medical, and marine
environment. With the on-chip voltage regulator it further reduces the BOM for mechatronic stepper applications.
2.0 Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual H-Bridge for 2-phase stepper motors
Programmable peak-current up to 1.6A using a 5-bit current DAC
On-chip current translator
SPI interface
Speed and load angle output
Seven step modes from full step up to 32 micro-steps
Fully integrated current-sense
PWM current control with automatic selection of fast and slow decay
Low EMC PWM with selectable voltage slopes
Active fly-back diodes
Full output protection and diagnosis
Thermal warning and shutdown
Compatible with 5V and 3.3V microcontrollers
Integrated 5V regulator to supply external microcontroller
Integrated reset function to reset external microcontroller
Integrated watchdog function
3.0 Ordering information
Table 1: Ordering Information
Part Number
Package
AMIS30522C5222G
AMIS30522C5222RG
NQFP-32 (7 x 7mm)
NQFP-32 (7 x 7mm)
©2008 SCILLC. All rights reserved.
June 2008 – Rev. 2
Shipping Configuration
Tube/Tray
Tape & Reel
Temperature Range
-40°C to125°C
-40°C to 125°C
Device/Family Specific #1
1600mA
1600mA
Publication Order Number:
AMIS30522/D
AMIS-30522
4.0 Block Diagram
CLK
Timebase
VDD
CPN CPP VCP
Vreg
Chargepump
POR
CS
DI
OTP
SPI
DO
NXT
Logic &
Registers
DIR
Load
Angle
SLA
Temp.
Sense
POR/WD
VBB
EMC
T
R
A
N
S
L
A
T
O
R
MOTXP
P
W
M
I-sense
EMC
MOTYP
P
W
M
MOTYN
I-sense
CLR
Bandgap
ERR
MOTXN
AMIS-30522
GND
PC20070322.2
Figure 1: Block Diagram AMIS-30522
5.0 Pin Description
Table 2: Pin List and Description
Name
Pin
Description
DO
31
SPI data output (open drain)
VDD
32
Logic supply output (needs external decoupling capacitor)
GND
1
Ground, heat sink
DI
2
SPI data in
CLK
3
SPI clock input
NXT
4
Next micro-step input
DIR
5
Direction input
ERRB
6
Error output (open drain)
SLA
7
Speed load angle output
CPN
9
Negative connection of charge pump capacitor
CPP
10
Positive connection of charge pump capacitor
VCP
11
Charge pump filter-capacitor
CLR
12
“Clear” = chip reset input
CSB
13
SPI chip select input
VBB
14
High voltage supply Input
MOTYP
15, 16
Negative end of phase Y coil output
GND
17, 18
Ground, heat sink
MOTYN
19, 20
Positive end of phase Y coil output
MOTXN
21, 22
Positive end of phase X coil output
GND
23, 24
Ground, heat sink
MOTXP
25, 26
Negative end of phase X coil output
VBB
27
High voltage supply input
/
8, 30
No function (to be left open in normal operation)
PORB/WD
28
Power-on-reset (POR)and watchdog reset output (open drain)
TSTO
29
Test pin input (to be tied to ground in normal operation)
Rev. 2 | Page 2 of 29 | www.onsemi.com
AMIS-30522
28
MOTXP
29
MOTXP
30
VBB
DO
31
POR/WD
TSTO
VDD
GND
32
27
26
25
1
24
GND
DI
CLK
NXT
2
23
GND
3
22
4
21
DIR
5
20
MOTYN
ERR
6
19
SLA
7
18
8
17
MOTYN
GND
GND
AMIS-30522
13
14
15
16
MOTYP
CS
12
MOTYP
VBB
CPP
CPN
11
VCP
10
CLR
9
MOTXN
MOTXN
PC20070309.2
Figure 2: Pin Out AMIS-30522
5.1 Package Thermal Characteristics
The NQFP is designed to provide superior thermal performance, and using an exposed die pad on the bottom surface of the
package partly contributes to this. In order to take full advantage of this thermal performance, the PCB must have features to
conduct heat away from the package. A thermal grounded pad with thermal via’s can achieve this. With a layout as shown in Figure
3, the thermal resistance junction – to – ambient can be brought down to a level of 30°C/W.
Figure 3: PCB Ground Plane Layout Condition
Rev. 2 | Page 3 of 29 | www.onsemi.com
AMIS-30522
6.0 Electrical Specification
6.1 Absolute Maximum Ratings
Stresses above those listed in Table 3 may cause immediate and permanent device failure. It is not implied that more that one of
these conditions can be applied simultaneously.
Table 3: Absolute Maximum Ratings
Symbol
Parameter
(1)
VBB
Analog DC supply voltage
Tstrg
Storage temperature
Tamb
Ambient temperature under bias
(2)
VESD
Electrostatic discharges on component level
Notes:
(1)
(2)
Min.
-0.3
-55
-50
-2
Max.
+40
+160
+150
+2
Units
V
°C
°C
kV
For limited time <0.5s.
Human body model (100pF via 1.5 kΩ, according to JEDEC EIA-JESD22-A114-B).
6.2 Recommend Operation Conditions
Operating ranges define the limits for functional operation and parametric characteristics of the device. Note that the functionality
of the chip outside these operating ranges is not guaranteed. Operating outside the recommended operating ranges for extended
periods of time may affect device reliability.
Table 4: Operating Ranges
Symbol
Parameter
VBB
Analog DC supply
(1)
VDD
Logic supply output voltage
(2)
Iddd
Dynamic current of VDD pin (internal and external loads)
Ta
Ambient temperature VBAT≤+18
Ta
Ambient temperature VBAT≤+29
Tj
Junction temperature
Notes:
(1)
(2)
Min.
+6
4.75
-40
-40
Voltage output.
Dynamic current is with oscillator running, all analog cells active. All outputs unloaded, no floating inputs.
Rev. 2 | Page 4 of 29 | www.onsemi.com
Max.
+30
5.25
18
+125
+85
+160
Units
V
V
mA
°C
°C
°C
AMIS-30522
6.3 DC Parameters
The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified. Convention: currents
flowing in the circuit are defined as positive.
Table 5: DC parameters
Symbol
Pin(s)
Parameter
Supply & Voltage Regulator
VBB
Nominal operating supply range
VBB
IBB
Total internal current consumption
VDD
Regulated Output Voltage
IINT
Internal load current
Max. Output Current (external and
ILOAD
VDD
internal loads)
IDDLIM
Current limitation
ILOAD_PD
Output current in Power Down
Power-on-Reset (POR)
VDDH
Internal POR comparator threshold
VDD
VDDL
Internal POR comparator threshold
Motor Driver
Max current through motor coil in
IMDmax,Peak
normal operation
MOTXP
MOTXN Max RMS current through coil in normal
IMDmax,RMS
operation
MOTYP
MOTYN
IMDabs
Absolute error on coil current
IMDrel
Error on current ratio Icoilx / Icoily
Temperature coefficient of coil current
ISET_TC1
set-level, CUR[4:0] = 0 ..27
Temperature coefficient of coil current
ISET_TC2
set-level, CUR[4:0] = 28 ..31
On-resistance high-side driver,
RHS
CUR[4:0] = 0...31
On-resistance low-side driver,
RLS3
CUR[4:0] = 23...31
On-resistance low-side driver,
RLS2
CUR[4:0] = 16...22
On-resistance low-side driver,
RLS1
CUR[4:0] = 9...15
On-resistance low-side driver,
RLS0
CUR[4:0] = 0...8
IMpd
Pull down current
Digital Inputs
Ileak
Input Leakage (3)
DI, CLK
NXT, DIR
VIL
Logic Low Threshold
CLR, CSB
VIH
Logic High Threshold
Rpd_CLR
CLR
Internal Pull Down Resistor
Rpd_TST
TST0
Internal Pull Down Resistor
Digital Outputs
VOL
Logic Low level open drain
DO, ERRB,
PORB/WD
Thermal Warning & Shutdown
Ttw
Thermal Warning
Ttsd(1) (2)
Thermal shutdown
Charge Pump
Vcp
Cbuffer
Cpump
Notes:
(1)
(2)
(3)
VCP
CPP CPN
Remark/Test Conditions
Typ
Max
Unit
5
30
8
5.25
V
mA
V
150
mA
4.4
V
V
6
Unloaded outputs
4.75
Unloaded outputs
6V < VBB < 8V
8V < VBB < 30V
Pin shorted to ground
20
50
1
VDD rising
VDD falling
4.0
4.25
3.68
1600
mA
800
mA
-10
-7
10
7
%
%
-40 °C ≤ Tj ≤ 160 °C
-240
ppm/K
-40 °C ≤ Tj ≤ 160 °C
-490
ppm/K
Vbb = 12V, Tj = 27 °C
Vbb = 12V, Tj = 160 °C
Vbb = 12V, Tj = 27 °C
Vbb = 12V, Tj = 160 °C
Vbb = 12V, Tj = 27 °C
Vbb = 12V, Tj = 160 °C
Vbb = 12V, Tj = 27 °C
Vbb = 12V, Tj = 160 °C
Vbb = 12V, Tj = 27 °C
Vbb = 12V, Tj = 160 °C
HiZ mode
0.45
0.94
0.45
0.94
0.90
1.9
1.8
3.8
3.6
7.5
0.5
Tj = 160 °C
0
2.20
120
3
IOL = 5 mA
138
6V< VBB < 15V
15V < VBB < 30V
Output voltage
Min
External buffer capacitor
External pump capacitor
No more than 100 cumulated hours in life time above Ttw.
Thermal shutdown and low temperature warning are derived from thermal warning.
Not valid for pins with internal pull-down resistor.
Rev. 2 | Page 5 of 29 | www.onsemi.com
VBB+12.5
180
180
145
Ttw + 20
2 * VBB – 2.5
VBB+14
220
220
0.56
1.25
0.56
1.25
1.2
2.5
2.3
5.0
4.5
10
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
mA
1
0.65
VDD
300
9
µA
V
V
kΩ
kΩ
0.5
V
152
°C
°C
VBB+15.5
470
470
V
V
nF
nF
AMIS-30522
6.4 AC Parameters
The AC parameters are given for VBB and temperature in their operating ranges.
Table 6: AC Parameters
Symbol
Pin(s)
Parameter
Internal Oscillator
fosc
Frequency of internal oscillator
Motor Driver
PWM frequency
fPWM
Double PWM frequency
MOTxx
fj
PWM jitter frequency
fd
PWM jitter Depth
Remark/Test Conditions
Frequency depends only on
internal oscillator
Tbrise
MOTxx
Turn-on voltage slope, 10% to 90%
Tbfall
MOTxx
Turn-off voltage slope, 90% to 10%
Digital Outputs
DO
TH2L
ERRB
Charge Pump
fCP
CPN CPP
TCPU
MOTxx
CLR Function
TCLR
CLR
Power-Up
Charge pump frequency
Start-up time of charge pump
tPU
Power-up time
PORB/
WD
tPD
tPOR
tRF
Watchdog
tWDTO
PORB/
tWDPR
WD
tWDRD
Min.
Typ.
Max.
Unit
3.6
4
4.4
MHz
20.8
41.6
22.8
45.6
tbd
tbd
150
100
50
25
150
100
50
25
24.8
49.6
kHz
kHz
Hz
% fPWM
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
50
ns
EMC[1:0] = 00
EMC[1:0] = 01
EMC[1:0] = 10
EMC[1:0] = 11
EMC[1:0] = 00
EMC[1:0] = 01
EMC[1:0] = 10
EMC[1:0] = 11
Capacitive load 400pF and pullup resistor of 1.5 kΩ
Output fall-time from VinH to VinL
250
kHz
Spec external components
Hard reset duration time
20
VBB=12V, ILOAD=50mA,
CLOAD=220nF
External conditions tbd
Power-down time
Reset duration
Reset filter time
90
µs
110
µs
ms
ms
µs
100
1
Watchdog time out interval
Prohibited watchdog acknowledge delay
Watchdog reset delay
32
512
2
tbd
ms
ms
µs
6.5 SPI Timing
Table 7: SPI Timing Parameters
Symbol
Parameter
tCLK
SPI clock period
tCLK_HIGH
SPI clock high time
tCLK_LOW
SPI clock low time
tSET_DI
DI set up time, valid data before rising edge of CLK
tHOLD_DI
DI hold time, hold data after rising edge of CLK
tCSB_HIGH
CSB high time
tSET_CSB
CSB set up time, CSB low before rising edge of CLK
tSET_CLK
CLK set up time, CLK low before rising edge of CSB
Rev. 2 | Page 6 of 29 | www.onsemi.com
Min.
1
100
100
50
50
2.5
100
100
Typ.
Max.
Unit
μs
ns
ns
ns
ns
μs
ns
ns
AMIS-30522
0,2 VCC
CS
0,2 VCC
tSET_CSB
tCLK
tSET_CLK
0,8 VCC
CLK
0,2 VCC
0,2 VCC
tCLK_HI
tSET_DI
DI
tCLK_LO
tHOLD_DI
0,8 VCC
VALID
PC20070608.1
Figure 4: SPI Timing
7.0 Typical Application Schematic
Figure 5: Typical Application Schematic AMIS-30522
Table 8: External Components List and Description
Component
Function
(1)
C1
VBB buffer capacitor
C2, C3
VBB decoupling block capacitor
C4
VDD buffer capacitor
C5
VDD buffer capacitor
C6
Charge-pump buffer capacitor
C7
Charge-pump pumping capacitor
C8
Low pass filter SLA
R1
Low pass filter SLA
R2, R3, R4
Pull up resistor open drain output
D1
Optional reverse protection diode
Typ. Value
100
100
220
100
220
220
1
5.6
4,7
e.g. 1N4003
Notes:
1.
Low ESR < 1Ohm.
Rev. 2 | Page 7 of 29 | www.onsemi.com
Tolerance
-20 +80%
-20 +80%
+/- 20 %
+/- 20%
+/- 20%
+/- 20%
+/- 20%
+/- 1%
+/- 1%
Unit
μF
nF
nF
nF
nF
nF
nF
kΩ
kΩ
AMIS-30522
8.0 Functional Description
8.1 H-Bridge Drivers
A full H-bridge is integrated for each of the two stator windings. Each H-bridge consists of two low-side and two high-side N-type
MOSFET switches. Writing logic ‘0’ in bit <MOTEN> disables all drivers (high-impedance). Writing logic ‘1’ in this bit enables both
bridges and current can flow in the motor stator windings.
In order to avoid large currents through the H-bridge switches, it is guaranteed that the top- and bottom-switches of the same halfbridge are never conductive simultaneously (interlock delay).
A two-stage protection against shorts on motor lines is implemented. In a first stage, the current in the driver is limited. Secondly,
when excessive voltage is sensed across the transistor, the transistor is switched off.
In order to reduce the radiated/conducted emission, voltage slope control is implemented in the output switches. The output slope
is defined by the gate-drain capacitance of output transistor and the (limited) current that drives the gate. There are two trimming
bits for slope control (see Table 27).
The power transistors are equipped with so-called “active diodes”: when a current is forced trough the transistor switch in the
reverse direction, i.e. from source to drain, then the transistor is switched on. This ensures that most of the current flows through
the channel of the transistor instead of through the inherent parasitic drain-bulk diode of the transistor.
Depending on the desired current range and the micro-step position at hand, the Rdson of the low-side transistors will be adapted
such that excellent current-sense accuracy is maintained. The Rdson of the high-side transistors remain unchanged, see Error!
Reference source not found. for more details.
8.2 PWM Current Control
A PWM comparator compares continuously the actual winding current with the requested current and feeds back the information to
a digital regulation loop. This loop then generates a PWM signal, which turns on/off the H-bridge switches. The switching points of
the PWM duty-cycle are synchronized to the on-chip PWM clock. The frequency of the PWM controller can be doubled and an
artificial jitter can be added (see Table 16). The PWM frequency will not vary with changes in the supply voltage. Also variations in
motor-speed or load-conditions of the motor have no effect. There are no external components required to adjust the PWM
frequency.
8.2.1. Automatic Forward and Slow-Fast Decay
The PWM generation is in steady-state using a combination of forward and slow-decay. The absence of fast-decay in this mode,
guarantees the lowest possible current-ripple “by design”. For transients to lower current levels, fast-decay is automatically
activated to allow high-speed response. The selection of fast or slow decay is completely transparent for the user and no additional
parameters are required for operation.
Icoil
Set value
Actual value
t
0
TPWM
Forward & Slow Decay
Forward & Slow Decay
Fast Decay & Forward
PC20070604.1
Figure 6: Forward and Slow/Fast Decay PWM
Rev. 2 | Page 8 of 29 | www.onsemi.com
AMIS-30522
8.2.2. Automatic Duty Cycle Adaptation
In case the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the
requested average current in the coils. This process is completely automatic and requires no additional parameters for operation.
The over-all current-ripple is divided by two if PWM frequency is doubled (see Table 16).
Icoil
Duty Cycle
< 50%
Duty Cycle >50%
Duty Cycle < 50%
Actual value
Set value
t
PC20070604.2
TPWM
Figure 7: Automatic Duty Cycle Adaptation
8.3 Step Translator
8.3.1. Step Mode
The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL, and
input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode.
One out of seven possible stepping modes can be selected through SPI-bits SM[2:0] (see Table 28) After power-on or hard reset,
the coil-current translator is set to the default 1/32 micro-stepping at position ‘0’. Upon changing the step mode, the translator
jumps to position 0* of the corresponding stepping mode. When remaining in the same step mode, subsequent translator positions
are all in the same column and increased or decreased with 1. Error! Reference source not found. lists the output current vs. the
translator position.
As shown in Figure 8 the output current-pairs can be projected approximately on a circle in the (Ix,Iy) plane. There is, however, one
exception: uncompensated half step. In this step mode the currents are not regulated to a fraction of Imax but are in all intermediate
steps regulated at 100 percent. In the (Ix,Iy) plane the current-pairs are projected on a square. Error! Reference source not found.
lists the output current vs. the translator position for this case.
Table 9: Square Translator Table for Full Step and Uncompensated Half Step
Stepmode ( SM[2:0] )
MSP[6:0]
110
101
Full Step
Uncompensated Half-Step
000 0000
0*
001 0000
1
1
010 0000
2
011 0000
2
3
100 0000
4
101 0000
3
5
110 0000
6
111 0000
0*
7
Rev. 2 | Page 9 of 29 | www.onsemi.com
% of Imax
Coil x
Coil y
0
100
100
100
0
-100
-100
-100
100
100
0
-100
-100
-100
0
100
AMIS-30522
Table 10: Circular Translator Table
Stepmode ( SM[2:0] )
MSP[6:0]
000
001
010
011
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
001 1000
001 1001
001 1010
001 1011
001 1100
001 1101
001 1110
001 1111
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000
010 1001
010 1010
010 1011
010 1100
010 1101
010 1110
010 1111
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
1/32
‘0’
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1/16
0*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
1/8
0*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
1/4
0*
1
2
3
4
5
6
7
-
% of Imax
100
1/2
0*
1
2
3
-
Coil x
Coil y
0
3.5
8.1
12.7
17.4
22.1
26.7
31.4
34.9
38.3
43
46.5
50
54.6
58.1
61.6
65.1
68.6
72.1
75.5
79
82.6
84.9
87.2
89.5
91.8
93
94.1
95.3
96.5
97.7
98.8
100
98.8
97.7
96.5
95.3
94.1
93
91.8
89.5
87.2
84.9
82.6
79
75.5
72.1
68.6
65.1
61.6
58.1
54.6
50
46.5
43
38.3
34.9
31.4
26.7
22.1
17.4
12.7
8.1
3.5
100
98.8
97.7
96.5
95.3
94.1
93
91.8
89.5
87.2
84.9
82.6
79
75.5
72.1
68.6
65.1
61.6
58.1
54.6
50
46.5
43
38.3
34.9
31.4
26.7
22.1
17.4
12.7
8.1
3.5
0
-3.5
-8.1
-12.7
-17.4
-22.1
-26.7
-31.4
-34.9
-38.3
-43
-46.5
-50
-54.6
-58.1
-61.6
-65.1
-68.6
-72.1
-75.5
-79
-82.6
-84.9
-87.2
-89.5
-91.8
-93
-94.1
-95.3
-96.5
-97.7
-98.8
Stepmode ( SM[2:0] )
% of Imax
MSP[6:0]
000
001
010
011
100
100 0000
100 0001
100 0010
100 0011
100 0100
100 0101
100 0110
100 0111
100 1000
100 1001
100 1010
100 1011
100 1100
100 1101
100 1110
100 1111
101 0000
101 0001
101 0010
101 0011
101 0100
101 0101
101 0110
101 0111
101 1000
101 1001
101 1010
101 1011
101 1100
101 1101
101 1110
101 1111
110 0000
110 0001
110 0010
110 0011
110 0100
110 0101
110 0110
110 0111
110 1000
110 1001
110 1010
110 1011
110 1100
110 1101
110 1110
110 1111
111 0000
111 0001
111 0010
111 0011
111 0100
111 0101
111 0110
111 0111
111 1000
111 1001
111 1010
111 1011
111 1100
111 1101
111 1110
111 1111
1/32
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1/16
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
-
1/8
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
1/4
8
9
10
11
12
13
14
15
-
1/2
4
5
6
7
-
Rev. 2 | Page 10 of 29 | www.onsemi.com
Coil x
Coil y
0
-3.5
-8.1
-12.7
-17.4
-22.1
-26.7
-31.4
-34.9
-38.3
-43
-46.5
-50
-54.6
-58.1
-61.6
-65.1
-68.6
-72.1
-75.5
-79
-82.6
-84.9
-87.2
-89.5
-91.8
-93
-94.1
-95.3
-96.5
-97.7
-98.8
-100
-98.8
-97.7
-96.5
-95.3
-94.1
-93
-91.8
-89.5
-87.2
-84.9
-82.6
-79
-75.5
-72.1
-68.6
-65.1
-61.6
-58.1
-54.6
-50
-46.5
-43
-38.3
-34.9
-31.4
-26.7
-22.1
-17.4
-12.7
-8.1
-3.5
-100
-98.8
-97.7
-96.5
-95.3
-94.1
-93
-91.8
-89.5
-87.2
-84.9
-82.6
-79
-75.5
-72.1
-68.6
-65.1
-61.6
-58.1
-54.6
-50
-46.5
-43
-38.3
-34.9
-31.4
-26.7
-22.1
-17.4
-12.7
-8.1
-3.5
0
3.5
8.1
12.7
17.4
22.1
26.7
31.4
34.9
38.3
43
46.5
50
54.6
58.1
61.6
65.1
68.6
72.1
75.5
79
82.6
84.9
87.2
89.5
91.8
93
94.1
95.3
96.5
97.7
98.8
AMIS-30522
Figure 8: Translator Table: Circular and Square
8.3.2. Direction
The direction of rotation is selected by means of following combination of the DIR input pin and the SPI-controlled direction bit
<DIRCTRL>. (Table 16)
8.3.3. NXT input
Changes on the NXT input will move the motor current one step up/down in the translator table. Depending on the NXT-polarity bit
<NXTP> (Table 16), the next step is initiated either on the rising edge or the falling edge of the NXT input.
tNXT_HI
0,5 VCC
NXT
tDIR_SET
DIR
tNXT_LO
tDIR_HOLD
VALID
PC20070609.1
Figure 9: NXT-input Timing Diagram
Table 11: Timing Table NXT Pin
Symbol
Parameter
tNXT_HI
NXT minimum, high pulse width
tNXT_LO
NXT minimum, low pulse width
tDIR_SET
NXT hold time, following change of DIR
tDIR_HOLD
NXT hold time, before change of DIR
Rev. 2 | Page 11 of 29 | www.onsemi.com
Min.
2
2
0.5
0.5
Typ.
Max.
Unit
µs
µs
µs
µs
AMIS-30522
8.3.4. Translator Position
th
The translator position can be read in Table 32. This is a 7-bit number equivalent to the 1/32 micro-step from Error! Reference
source not found.. The translator position is updated immediately following a NXT trigger.
NXT
Update
Translator Position
Update
Translator Position
PC20070604.4
Figure 10: Translator Position Timing Diagram
8.3.5. Synchronization of Step Mode and NXT Input
When step mode is re-programmed to another resolution (Table 15), then this is put in effect immediately upon the first arriving
“NXT” input. If the micro-stepping resolution is increased (Figure 11), then the coil currents will be regulated to the nearest microstep, according to the fixed grid of the increased resolution. If however the micro-stepping resolution is decreased, then it is
possible to introduce an offset (or phase shift) in the micro-step translator table.
If the step resolution is decreased at a translator table position that is shared both by the old and new resolution setting, then the
offset is zero and micro-stepping is proceeds according to the translator table.
If the translator position is not shared both by the old and new resolution setting, then the micro-stepping proceeds with an offset
relative to the translator table (See Figure 10 right hand side).
Change from lower to higher resolution
Iy
Iy
DIR
NXT3
endpos
NXT2
DIR
NXT1
NXT4
Iy
NXT1
endpos
DIR
startpos
NXT2
Ix
Ix
1/4th step
Iy
DIR
startpos
Ix
Halfstep
Change from higher to lower resolution
1/8th step
Ix
NXT3
Halfstep
PC20070604.6
Figure 11: NXT-Step Mode Synchronization
Left: Change from lower to higher resolution. The left-hand side depicts the ending half-step position during which a new step mode
resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the micro-step
position.
Right: Change from higher to lower resolution. The left-hand side depicts the ending micro-step position during which a new step
mode resolution was programmed. The right-hand side diagram shows the effect of subsequent NXT commands on the half-step
position.
Note:
It is advised to reduce the micro-stepping resolution only at micro-step positions that overlap with desired micro-step positions of the new resolution.
Rev. 2 | Page 12 of 29 | www.onsemi.com
AMIS-30522
8.4 Programmable Peak-Current
The amplitude of the current waveform in the motor coils (coil peak current = Imax) is adjusted by means of an SPI parameter
"CUR[4:0]" (Table 15). Whenever this parameter is changed, the coil-currents will be updated immediately at the next PWM period.
More information can be found in Table 26.
8.5 Speed and Load Angle Output
The SLA-pin provides an output voltage that indicates the level of the Back-e.m.f. voltage of the motor. This Back-e.m.f. voltage is
sampled during every so-called "coil current zero crossings". Per coil, two zero-current positions exist per electrical period, yielding
in total four zero-current observation points per electrical period.
VBEMF
ICOIL
t
ZOOM
Previous
Micro-step
ICOIL
Coil Current Zero Crossing
Next
Micro-step
Current Decay
Zero Current
t
VCOIL
VBB
Voltage Transient
VBEMF
t
PC20070604.7
Figure 12: Principle of Bemf Measurement
Because of the relatively high recirculation currents in the coil during current decay, the coil voltage VCOIL shows a transient
behavior. As this transient is not always desired in application software, two operating modes can be selected by means of the bit
<SLAT> (see "SLA-transparency" in Table 17). The SLA pin shows in "transparent mode" full visibility of the voltage transient
behavior. This allows a sanity-check of the speed-setting versus motor operation and characteristics and supply voltage levels. If
the bit “SLAT” is cleared, then only the voltage samples at the end of each coil current zero crossing are visible on the SLA-pin.
Because the transient behavior of the coil voltage is not visible anymore, this mode generates smoother Back e.m.f. input for postprocessing, e.g. by software.
In order to bring the sampled Back e.m.f. to a descent output level (0 to 5V), the sampled coil voltage VCOIL is divided by 2 or by 4.
This divider is set through an SPI bit <SLAG>. (Table 17)
Table 12: Parameter Table SLA Pin
Symbol
Pin(s)
Parameter
Vout
Output voltage range
Voff
Output offset the SLA pin
Rout
Output resistance SLA pin
SLA
Cload
Load capacitance SLA pin
Gsla
Gain of SLA pin = VBEMF / VCOIL
Remark/Test Conditions
0.2V < Vsla < Vdd – 0.2V
SLAG=0
SLAG=1
Rev. 2 | Page 13 of 29 | www.onsemi.com
Min
0.5
-25
Typ
0.5
0.25
Max
4.5
25
1
50
Unit
V
mV
kΩ
pF
AMIS-30522
The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals
that define together with SLAT the sampling and hold moments of the coil voltage.
Ssh
VCOIL
Sh
div2
div4
buf
SLA-pin
Ch
Csh
Icoil=0
PWMsh
SLAT
NOT(Icoil=0)
PWMsh
Icoil=0
SLAT
VCOIL
t
SLA-pin
last sample
is retained
VBEMF
retain last sample
previous output is kept at SLA pin
t
SLAT=1 => SLA-pin is "transparent" during
VBEMF sampling @ Coil Current Zero
Crossing. SLA-pin is updated "real-time".
SLAT=0 => SLA-pin is not "transparent" during
VBEMF sampling @ Coil Current Zero Crossing.
SLA-pin is updated when leaving current-less state.
PC20070604.8
Figure 13: Timing Diagram of SLA-pin
8.6 Warning, Error Detection and Diagnostics Feedback
8.6.1. Thermal Warning and Shutdown
When junction temperature rises above TTW, the thermal warning bit <TW> is set (Table 29). If junction temperature increases
above thermal shutdown level, then the circuit goes in “Thermal Shutdown” mode (<TSD>) and all driver transistors are disabled
(high impedance) (Table 31). The conditions to reset flag <TSD> is to be at a temperature lower than TTW and to clear the <TSD>
flag by reading it using any SPI read command.
8.6.2. Over-Current Detection
The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection
threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit.
Each driver transistor has an individual detection bit in
Table 30 and (Table 31(<OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clean the status
bits to reactivate the drivers.
8.6.3. Open Coil Detection
Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle
is detected for longer than 200ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI
status register is set (<OPENX> or <OPENY>). (Table 29)
Rev. 2 | Page 14 of 29 | www.onsemi.com
AMIS-30522
8.6.4. Charge Pump Failure
The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If supply
voltage is too low or external components are not properly connected to guarantee Rdson of the drivers, then the bit <CPFAIL> is
set in Table 29. Also after POR the charge pump voltage will need some time to exceed the required threshold. During that time
<CPFAIL> will be set to “1”.
8.6.5. Error Output
This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic
combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL>
8.7 Logic Supply Regulator
AMIS-30522 has an on-chip 5V low-drop regulator with external capacitor to supply the digital part of the chip, some low-voltage
analog blocks and external circuitry. The voltage is derived from an internal bandgap reference. To calculate the available drivecurrent for external circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and
the loads connected to logic outputs. See Error! Reference source not found..
8.8 Power-On Reset (POR) Function
The open drain output pin PORB/WD provides an “active low” reset for external purposes. At power-up of AMIS-30522, this pin will
be kept low for some time to reset for example an external microcontroller. A small analog filter avoids resetting due to spikes or
noise on the VDD supply.
VBB
t
VDD
tPD
tPU
VDDH
VDDL
t
< tRF
POR/WD pin
tPOR
tRF
PC20070604.8
Figure 14: Power-on-Reset Timing Diagram
8.9 Watchdog Function
The watchdog function is enabled/disabled through <WDEN> bit (Table 14). Once this bit has been set to “1” (watchdog enable), the
microcontroller needs to re-write this bit to clear an internal timer before the watchdog timeout interval expires. In case the timer is
activated and WDEN is acknowledged too early (before tWDPR) or not within the interval (after tWDTO), then a reset of the
microcontroller will occur through PORB/WD pin. In addition, a warm/cold boot bit <WD> is available in Table 29 for further
processing when the external microcontroller is alive again.
Rev. 2 | Page 15 of 29 | www.onsemi.com
AMIS-30522
VBB
t
VDD
tPU
VDDH
t
tPOR
POR/WD pin
tDSPI
tWDRD tPOR
Enable WD
> tWDPR and < tWDTO
= tWDPR or = tWDTO
Acknowledge WD
t
tWDTO
WD timer
t
PC20070604.9
Figure 15: Watchdog Timing Diagram
Note: tDSPI is the time needed by the external microcontroller to shift-in the <WDEN> bit after a power-up.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (Table 14). The timing is given in Table
13.
Table 13: Watchdog Timeout Interval as Function of WDT[3.0]
WDT[3:0]
Index
tWDTO (ms)
0
0
0
0
0
32
1
0
0
0
1
64
2
0
0
1
0
96
3
0
0
1
1
128
4
0
1
0
0
160
5
0
1
0
1
192
6
0
1
1
0
224
7
0
1
1
1
256
8
1
0
0
0
288
9
1
0
0
1
320
A
1
0
1
0
352
B
1
0
1
1
384
C
1
1
0
0
416
D
1
1
0
1
448
E
1
1
1
0
480
F
1
1
1
1
512
Rev. 2 | Page 16 of 29 | www.onsemi.com
AMIS-30522
8.10 CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30522, the input CLR needs to
be pulled to logic 1 during minimum time given by TCLR. (Table 6). This reset function clears all internal registers without the need of
a power-cycle. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. Logic
0 on CLR pin resumes normal operation again.
The voltage regulator remains functional during and after the reset and the PORB/WD pin is not activated. Watchdog function is
reset completely.
8.11 Sleep Mode
The bit <SLP> in Table 17 is provided to enter a so-called “sleep mode”. This mode allows reduction of current-consumption when
the motor is not in operation. The effect of sleep mode is as follows:
•
•
•
•
•
•
•
The drivers are put in HiZ
All analog circuits are disabled and in low-power mode
All internal registers are maintaining their logic content
NXT and DIR inputs are forbidden
SPI communication remains possible (slight current increase during SPI communication)
Reset of chip is possible through CLR pin
Oscillator and digital clocks are silent, except during SPI communication
The voltage regulator remains active but with reduced current-output capability (ILOADSLP). The watchdog timer stops running and it’s
value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start-up time is needed for the charge pump to stabilize. After this
time, NXT commands can be issued.
Rev. 2 | Page 17 of 29 | www.onsemi.com
AMIS-30522
9.0 SPI Interface
The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS-30521. The
implemented SPI block is designed to interface directly with numerous micro-controllers from several manufacturers. AMIS-30521
acts always as a Slave and can’t initiate any transmission. The operation of the device is configured and controlled by means of
SPI registers which are observable for read and/or write from the Master.
9.1 SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line
(CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO signal is the output from
the Slave (AMIS-30521), and DI signal is the output from the Master. A chip select line (CSB) allows individual selection of a Slave
SPI device in a multiple-slave system. The CSB line is active low. If AMIS-30521 is not selected, DO is pulled up with the external
pull up resistor. Since AMIS-30521 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling
edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation.
The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK,
DO and DI pins are directly connected between the Master and the Slave.
1
# CLK cycle
2
3
4
5
6
7
8
CS
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
PC20080630.5
Figure 16: Timing Diagram of a SPI transfer
Note: At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the addressed
internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS-30521 system clock when
CSB = High
9.2 Transfer packet:
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
Figure 17: SPI transfer packet
Rev. 2 | Page 18 of 29 | www.onsemi.com
AMIS-30522
Byte 1 contains the Command and the SPI Register Address and indicates to AMIS-30521 the chosen type of operation and
addressed register. Byte 2 contains data, or sent from the Master in a WRITE operation, or received from AMIS-30521 in a READ
operation.
2 command types can be distinguished in the communication between master and AMIS-30521:
•
READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
•
WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
9.2.1. READ operation
If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This
READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data-out
shift register is updated with the content of the corresponding internal SPI register. In the next 8-bit clock pulse train this data is
shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive
command or is dummy data.
Registers are updated with the internal status at the rising
edge of the internal AMIS-30521 clock when CS = 1
CS
COMMAND
DI
READ DATA from ADDR1
COMMAND or DUMMY
DATA from previous command or
NOT VALID after POR or RESET
DATA
DO
OLD DATA or NOT VALID
DATA
DATA from ADDR1
PC20080630.1
Figure 18: Single READ operation where DATA from SPI register with Address 1 is read by the Master
All 4 Status Registers (see SPI Registers) contain 7 data bits and a parity check bit The most significant bit (D7) represents a parity
of D[6:0]. If the number of logical ones in D[6:0] is odd, the parity bit D7 equals “1”. If the number of logical ones in D[6:0] is even
then the parity bit D7 equals “0”. This simple mechanism protects against noise and increases the consistency of the transmitted
data. If a parity check error occurs it is recommended to initiate an additional READ command to obtain the status again.
Also the Control Registers can be read out following the same routine. Control Registers don’t have a parity check. The CSB line is
active low and may remain low between successive READ commands as illustrated in Figure 19. There is however one exception.
In case an error condition is latched in one of Status Registers (see SPI Registers) the ERRB pin is activated. (See 8.6.5. Error
Output). This signal flags a problem to the external microcontroller. By reading the Status Registers information about the root
cause of the problem can be determined. After this READ operation the Status Registers are cleared. Because the Status
Registers and ERRB pin (see SPI Registers) are only updated by the internal system clock when the CSB line is high, the Master
should force CSB high immediately after the READ operation. For the same reason it is recommended to keep the CSB line high
always when the SPI bus is idle
9.2.2. WRITE operation
If the Master wants to write data to a Control Register it initiates the communication by sending a WRITE command. This contains
the address of the SPI register to write to. The command is followed with a data byte. This incoming data will be stored in the
corresponding Control Register after CSB goes from low to high! AMIS-30521 responds on every incoming byte by shifting out via
DO the data stored in the last received address.
It is important that the writing action (command - address and data) to the Control Register is exactly 16 bits long. If more or less
bits are transmitted the complete transfer packet is ignored.
A WRITE command executed for a read-only register (e.g. Status Registers) will not affect the addressed register and the device
operation.
Because after a power-on-reset the initial address is unknown the data shifted out via DO is not valid.
Rev. 2 | Page 19 of 29 | www.onsemi.com
AMIS-30522
Figure 19: Single WRITE operation where DATA from the Master is written in SPI register with Address 3
9.2.3. Examples of combined READ and WRITE operations
In the following examples successive READ and WRITE operations are combined. In Figure 18 the Master first reads the status
from Register at ADDR4 and at ADDR5 followed by writing a control byte in Control Register at ADDR2. Note that during the write
command (in Figure 4) the old data of the pointed register is returned at the moment the new data is shifted in
Figure 20: 2 successive READ commands followed by a WRITE command
After the write operation the Master could initiate a read back command in order to verify the data correctly written as illustrated in
Figure 19. During reception of the READ command the old data is returned for a second time. Only after receiving the READ
command the new data is transmitted. This rule also applies when the master device wants to initiate an SPI transfer to read the
Status Registers. Because the internal system clock updates the Status Registers only when CSB line is high, the first read out
byte might represent old status information.
Rev. 2 | Page 20 of 29 | www.onsemi.com
AMIS-30522
Registers are updated with the internal status at the rising
edge of the internal AMIS-30521 clock when CS = 1
Registers are updated with the internal
status at the rising edge of CS
CS
COMMAND
DI
DATA
COMMAND
WRITE DATA to ADDR2
NEW DATA for ADDR2
READ DATA from ADDR2
COMMAND or DUMMY
DATA
DATA
DATA
DATA
DATA from previous command or
NOT VALID after POR or RESET
DO
OLD DATA or NOT VALID
OLD DATA from ADDR2
OLD DATA from ADDR2
NEW DATA from ADDR2
PC20080630.4
Figure 21: A WRITE operation where DATA from the Master is written in SPI register with Address 2
followed by a READ back operation to confirm a correct WRITE operation
Note: The internal data-out shift buffer of AMIS-30521 is updated with the content of the selected SPI register only at the
last (every eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for
transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might
represent old data.
Rev. 2 | Page 21 of 29 | www.onsemi.com
AMIS-30522
9.3 SPI Control Registers
All SPI control registers have Read/Write Access and default to "0" after power-on or hard reset.
Table 14: SPI Control Register WR
Address
00h
Content
Access
Reset
Data
Where:
R/W
Reset:
WDEN:
WDT[3:0]:
Control Register (WR)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
Bit 7
R/W
0
WDEN
R/W
0
R/W
R/W
0
0
WDT[3:0]
R/W
0
Bit 2
Bit 1
Bit 0
R/W
0
-
R/W
0
-
R/W
0
-
Read and Write access
Status after power-On or hard reset
Watchdog enable. Writing “1” to this bit will activate the watchdog timer (if not enabled yet) or will clear this timer
(if already enabled). Writing “0” to this bit will clear WD bit (Table 29).
Watchdog timeout interval
Table 15: SPI Control Register 0
Address
01h
Content
Access
Reset
Data
Where:
R/W
Reset:
SM[2:0]:
CUR[4:0]:
Control Register 0 (CR0)
Structure
Bit 7
R/W
0
Bit 6
Bit 5
R/W
R/W
0
0
SM[2:0]
Bit 4
R/W
0
Bit 3
R/W
0
Bit 2
Bit 1
R/W
R/W
0
0
CUR[4:0]
Bit 0
R/W
0
Read and Write access
Status after power-On or hard reset
Step mode
Current amplitude
Table 16: SPI Control Register 1
Address
02h
Content
Access
Reset
Data
Where:
R/W
Reset::
DIRCTRL
NXTP
PWMF
PWMJ
EMC[1:0]
Bit 7
R/W
0
DIRCTRL
Control Register 1 (CR1)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
R/W
0
NXTP
R/W
0
PWMJ
R/W
R/W
0
0
EMC[1:0]
Control Register 2 (CR2)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
0
SLP
R/W
0
-
R/W
0
-
R/W
0
-
R/W
0
-
R/W
0
-
R/W
0
PWMF
Bit 0
Read and Write access
Status after power-On or hard reset
Direction control
NEXT polarity
PWM frequency
PWM jitter
EMC slope control
Table 17: SPI Control Register 2
Address
03h
Content
Access
Reset
Data
Bit 7
R/W
0
MOTEN
R/W
0
SLAG
Where:
R/W
Reset:
MOTEN
SLP
SLAG
Read and Write access
Status after power-On or hard reset
Motor enable
Sleep
Speed load angle gain
SLAT
Speed load angle transparency
R/W
0
SLAT
R/W
0
-
Rev. 2 | Page 22 of 29 | www.onsemi.com
AMIS-30522
Table 18: SPI Control Parameter Overview SLAT
Symbol
Description
SLAT
Status
Speed load angle transparency bit
Table 19: SPI Control Parameter Overview SLAG
Symbol
Description
SLAG
Status
Speed load angle gain setting
Status
Enables doubling of the PWM frequency
Status
Enables jittery PWM
Status
Enables sleep mode
Status
Activates the motor driver outputs
Status
<DIR> = 0
Controls the direction of rotation
(in combination with logic level on input DIR)
<DIR> = 1
Table 25: SPI Control Parameter Overview NXTP
Symbol
Description
NXTP
CUR[4:0]
<DIRCTRL> = 0
<DIRCTRL> = 1
<DIRCTRL> = 0
<DIRCTRL> = 1
Status
Value
CW motion
CCW motion
CCW motion
CW motion
Value
Trigger on rising edge
<NXTP> = 0
Selects if NXT triggers on rising or falling edge
Trigger on falling edge
<NXTP> = 1
Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.
Table 26: SPI Control Parameter Overview CUR[4:0]
CUR[4:0]
Index
Current (mA)
0
0
0
0
0
0
30
1
0
0
0
0
1
60
2
0
0
0
1
0
90
3
0
0
0
1
1
100
4
0
0
1
0
0
110
5
0
0
1
0
1
120
6
0
0
1
1
0
135
7
0
0
1
1
1
150
8
0
1
0
0
0
160
9
0
1
0
0
1
180
A
0
1
0
1
0
200
B
0
1
0
1
1
220
C
0
1
1
0
0
240
D
0
1
1
0
1
270
E
0
1
1
1
0
300
F
0
1
1
1
1
325
EMC[1:0]
Value
Drivers disabled
Drivers enabled
<MOTEN> = 0
<MOTEN> = 1
Table 24: SPI Control Parameter Overview DIRCTRL
Symbol
Description
DIRCTRL
Behavior
Active mode
Sleep mode
<SLP> = 0
<SLP> = 1
Table 23: SPI Control Parameter Overview MOTEN
Symbol
Description
MOTEN
Behavior
Jitter disabled
Jitter enabled
<PWMJ> = 0
<PWMJ> = 1
Table 22: SPI Control Overview SLP
Symbol
Description
SLP
Value
fPWM = 22.8kHz
fPWM = 45.6kHz
<PWMF> = 0
<PWMF> = 1
Table 21: SPI Control Parameter Overview PWMJ
Symbol
Description
PWMJ
Value
Gain = 0.5
Gain = 0.25
<SLAG> = 0
<SLAG> = 1
Table 20: SPI Parameter Overview PWMF
Symbol
Description
PWMF
Behavior
SLA is transparent
SLA is NOT transparent
<SLAT> = 0
<SLAT> = 1
Index
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Adjusts the dV/dt of the PWM voltage slopes on the motor pins.
Rev. 2 | Page 23 of 29 | www.onsemi.com
CUR[4:0]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Current (mA)
365
400
440
485
535
595
650
725
800
885
970
1070
1190
1300
1450
1600
AMIS-30522
Table 27: SPI Control Parameter Overview EMC[1:0]
EMC[1:0]
Index
Slope (V/μs)
0
0
0
150
1
0
1
100
2
1
0
50
3
1
1
25
Remark
Turn-on and turn-off voltage slope 10% to 90%
“
“
“
Selects the micro-stepping mode.
SM[2:0]
Table 28: SPI Control Parameter Overview SM[2:0]
SM[2:0]
Index
Step Mode
1
0
0
0
0
/32
1
1
0
0
1
/16
1
2
0
1
0
/8
3
0
1
1
¼
4
1
0
0
½
5
1
0
1
½
6
1
1
0
Full
7
1
1
1
N/A
Remark
Micro-step
Micro-step
Micro-step
Micro-step
Uncompensated half-step
Compensated half-step
Full step
For future use
9.4 SPI Status Register Description
All four SPI status registers have Read Access and are default to "0" after power-on or hard reset.
Table 29: SPI Status Register 0
Address
Content
Access
Reset
Data
04h
Where:
R
Reset
PAR
TW
Cpfail
WD
OPENX
OPENY
Bit 7
R
0
PAR
Status Register 0 (SR0)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
R
0
TW
R
0
CPfail
R
0
WD(1)
R
0
OPENX
Bit 2
Bit 1
Bit 0
R
0
OPENY
R
0
-
R
0
-
Read only mode access
Status after power-on or hard reset
Parity check
Thermal warning
Charge pump failure
Watchdog event
Open Coil X detected
Open Coil Y detected
Remark: WD(1) – This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1”
after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be
cleared only when the master writes “0” to WDEN bit. (Table 14).
Data is not latched
Rev. 2 | Page 24 of 29 | www.onsemi.com
AMIS-30522
Table 30: SPI Status Register 1
Address
05h
Content
Bit 7
Access
Reset
Data
Where:
R
Reset
PAR
OVXPT
OVXPB
OVXNT
OVXNB
R
0
PAR
Status Register 1 (SR1)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
R
0
OVCXPT
R
0
OVCXPB
R
0
OVCXNT
Bit 2
Bit 1
Bit 0
R
0
-
R
0
-
R
0
-
R
0
OVCXNB
Read only mode access
Status after power-on or hard reset
Parity check
Over-current detected on X H-bridge: MOTXP terminal, top transistor
Over-current detected on X H-bridge: MOTXP terminal, bottom transistor
Over-current detected on X H-bridge: MOTXN terminal, top transistor
Over-current detected on X H-bridge: MOTXN terminal, bottom transistor
Remark: Data is latched
Table 31: SPI Status Register 2
Address
06h
Content
Bit 7
Access
Reset
Data
Where:
R
Reset
PAR
OVCYPT
OVCYPB
OVCYNT
OVCYNB
TSD
R
0
PAR
Status Register 2 (SR2)
Structure
Bit 6
Bit 5
Bit 4
R
0
OVCYPT
R
0
OVCYPB
R
0
OVCYYNT
Bit 3
Bit 2
Bit 1
Bit 0
R
0
OVCYNB
R
0
TSD
R
0
-
R
0
-
Read only mode access
Status after power-on or hard reset
Parity check
Over-current detected on Y H-bridge: MOTYP terminal, top transistor
Over-current detected on Y H-bridge: MOTYP terminal, bottom transistor
Over-current detected on Y H-bridge: MOTYN terminal, top transistor
Over-current detected on Y H-bridge: MOTYN terminal, bottom transistor
Thermal shutdown
Remark: Data is latched
Table 32: SPI Status Register 3
Address
07h
Content
Access
Reset
Data
Where:
R
Reset
PAR
MSP[6:0]
Bit 7
R
0
PAR
Status Register 3 (SR3)
Structure
Bit 6
Bit 5
Bit 4
R
0
R
0
Bit 3
R
R
0
0
MSP[6:0]
Read only mode access
Status after power-on or hard reset
Parity check
Translator micro-step position
Remark: Data is not latched
Rev. 2 | Page 25 of 29 | www.onsemi.com
Bit 2
Bit 1
Bit 0
R
0
R
0
R
0
AMIS-30522
Table 33: SPI Status Flags Overview
Flag
Mnemonic
Length
(bit)
Related SPI Register
Charge pump failure
CPFail
1
Status Register 0
Micro-step position
OPEN Coil X
OPEN Coil Y
OVer Current on X
H-bridge; MOTXN
terminal; Bottom tran.
OVer Current on X
H-bridge; MOTXN
terminal; Top transist.
OVer Current on X
H-bridge; MOTXP
terminal; Bottom tran.
OVer Current on X
H-bridge; MOTXP
terminal; Top transist.
OVer Current on Y
H-bridge; MOTYN
terminal; Bottom tran.
OVer Current on Y
H-bridge; MOTYN
terminal; Top transist.
OVer Current on Y
H-bridge; MOTYP
terminal; Bottom tran.
OVer Current on Y
H-bridge; MOTYP
terminal; Top transist.
Thermal shutdown
Thermal warning
Watchdog event
MSP[6:0]
OPENX
OPENY
7
1
1
Status Register 3
Status Register 0
Status Register 0
OVCXNB
1
Status Register 1
OVCXNT
1
Status Register 1
OVCXPB
1
Status Register 1
OVCXPT
1
Status Register 1
OVCYNB
1
Status Register 2
OVCYNT
1
Status Register 2
OVCYPB
1
Status Register 2
OVCYPT
1
Status Register 2
TSD
TW
WD
1
1
1
Status Register 2
Status Register 0
Status Register 0
Comment
‘0’ = no failure
‘1’ = failure: indicates that the charge pump does
not reach the required voltage level. Note 1
Translator micro step position
‘1’ = Open coil detected
‘1’ = Open coil detected
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XN-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XN-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor XP-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor XP-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YN-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YN-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at bottom transistor YP-terminal
‘0’ = no failure
‘1’ = failure: indicates that over current is
detected at top transistor YP-terminal
‘1’ = watchdog reset after time-out
Rev. 2 | Page 26 of 29 | www.onsemi.com
Reset State
‘0’
‘0000000’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
AMIS-30522
10.0 Package Outline
Dimensions:
Dim
Min
A
0.8
A1
0
A2
0.576
A3
b
0.25
C
0.24
D
D1
E
E1
e
J
5.37
K
5.37
L
0.35
P
R
2.185
Notes :
Nom
0.02
0.615
0.203
0.3
0.42
7
6.75
7
6.75
0.65
5.47
5.47
0.4
45
Max
0.9
0.05
0.654
0.35
0.6
5.57
5.57
0.45
2.385
Unit
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Degree
mm
2 Dimensions apply to plated terminal and are measured between 0.2 and
0.25 mm from terminal tip.
3 The pin #1 indication must be placed on the top surface of the package
by using indentation mark or other feature of package body.
4 Exact shape and size of this feature is optional
5
Applied for exposed pad and terminals. Exclude embedding part of
exposed pad from measuring.
6 Applied only to terminals
7 Exact shape of each corner is optional
7x7 NQFP
Figure 22: NQFP-32: No Lead Quad Flat Pack; 32 Pins; Body Size 7x7mm (AMIS Reference: NQFP-32)
Rev. 2 | Page 27 of 29 | www.onsemi.com
AMIS-30522
11.0 Soldering
11.1 Introduction to Soldering Surface Mount Packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS
“Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that
is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards
(PCB) with high population densities. In these situations re-flow soldering is often used.
11.2 Re-flow Soldering
Re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the PCB by
screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for re-flowing; for
example, infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on the heating method.
Typical re-flow peak temperatures range from 215 to 260°C. The top-surface temperature of the packages should preferably be
kept below 230°C.
11.3 Wave Soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or PCBs with a high component
density, as solder bridging and non-wetting can present major problems. To overcome these problems, the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar
wave.
• For packages with leads on two sides and a pitch (e):
•Larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the
PCB;
•Smaller than 1.27mm, the footprint longitudinal axis must be parallel to the transport direction of the PCB. The footprint
must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45º angle to the transport direction of the PCB. The
footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by
screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is
four seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
11.4 Manual Soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to the
flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C.
When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C.
Table 34: Soldering Process
Soldering Method
Package
Wave
BGA, SQFP
HLQFP, HSQFP, HSOP, HTSSOP, SMS
(3)
PLCC , SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
Notes:
(1)
(2)
(3)
(4)
(5)
Not suitable
(2)
Not suitable
Suitable
(3) (4)
Not recommended
(5)
Not recommended
Re-flow
(1)
Suitable
Suitable
Suitable
Suitable
Suitable
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body
size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.”
These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved, and as solder
may stick to the heatsink (on top version).
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder
thieves downstream and at the side corners.
Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages
with a pitch (e) equal to or smaller than 0.65mm.
Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65mm; it is definitely not suitable for packages with
a pitch (e) equal to or smaller than 0.5mm.
Rev. 2 | Page 28 of 29 | www.onsemi.com
AMIS-30522
12.0 Document History
Table 35: Revision History
Revision
Date
0.1
18-Jan-06
0.2
24-Jan-06
0.3
9-Feb-06
0.4
9-Mar-06
0.5
0.6
1.0
22-Mar-06
24-May-06
6-June-07
2.0
3-July-08
Modification
Initial draft
Draft: changed PWM description, added SLA pin description, changed POR and WD paragraphs.
CEN->CENB, NXT pin timing, SPI I/F, 30522 section 8.5, 8.6,8.7, 30522 section 8.4,8.5
Updated pin-out & added drawing, CENB->CLR, ERR->ERRB, removed SWP bits, updated SPI bits, added
package details
Renamed CS -> CSB, Swapped pins CLR and CSB
Updated pins, AC&DC tables, SLA specs, SM[2:0] decoding
Final version derived from common 30521/30522 datasheet
Move content into ON Semiconductor template; update OPN table, AC&DC tables, Application Schematic,
SPI interface, SPI registers, Timing NXT
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
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use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
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