Ordering number : ENA2210A STK551U362A-E Thick-Film Hybrid IC Inverter Power H-IC for 3-phase Motor Drive http://onsemi.com Overview This “Inverter Power H-IC” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a single SIP module (Single-In line Package). Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. Function Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit All control input and status output are at low voltage levels directly compatible with microcontrollers Built-in dead time for shoot-thru protection Externally accessible embedded thermistor for substrate temperature measurement The level of the over-current protection current is adjustable with the external resistor, “RSD” Certification UL1557 (File Number : E339285). Specifications Absolute Maximum Ratings at Tc = 25C Parameter Symbol Conditions *1 Ratings Unit 450 V Supply voltage VCC V+ to V-, surge < 500V Collector-emitter voltage VCE V+ to U,V,W or U,V,W to V- 600 V V+, V-, U,V,W terminal current ±10 A A Output current Io V+, V-, U,V,W terminal current at Tc = 100C ±5 Output peak current Iop V+, V-, U,V,W terminal current for a Pulse width of 1ms. ±20 A Pre-driver voltage VD1,2,3,4 VB1 to U, VB2 to V, VB3 to W, VDD to VSS 20 V Input signal voltage VIN HIN1, 2, 3, LIN1, 2, 3 0.3 to VDD V FAULT terminal voltage VFAULT FAULT terminal 0.3 to VDD V *2 Maximum power dissipation Pd IGBT per channel 30 W Junction temperature Tj IGBT,FRD 150 C 40 to +125 C Storage temperature Tstg Operating case temperature Tc Tightening torque Withstand voltage Vis H-IC case temperature 40 to +100 C Case mounting screws *3 1.0 Nm 50Hz sine wave AC 1 minute *4 2000 VRMS Reference voltage is “VSS” terminal voltage unless otherwise specified. *1: Surge voltage developed by the switching operation due to the wiring inductance between + and U-(V-, W-) terminal. *2: Terminal voltage: VD1=VB1-U, VD2=VB2-V, VD3=VB3-W, VD4=VDD-VSS *3: Flatness of the heat-sink should be 0.15mm and below. *4: Test conditions : AC2500V, 1 second. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. Semiconductor Components Industries, LLC, 2013 December, 2013 Ver.131206YK D1813HK 018-13-0060/72913HK No.A2210-1/15 STK551U362A-E Electrical Characteristics at Tc 25C, VD1, VD2, VD3, VD4 = 15V Parameter Symbol Conditions Ratings Test circuit Unit min typ max - - 0.1 mA - - 0.1 mA Power output section Collector-emitter cut-off current ICE VCE = 600V Bootstrap diode reverse current IR(BD) VR(BD) Collector to emitter saturation voltage Diode forward voltage VCE(SAT) VF Fig.1 Io = 10A Upper side - 1.8 2.4 Tj = 25C Lower side *1 - 2.1 2.7 Io = 5A Upper side - 1.3 - Tj = 100C Lower side *1 - 1.6 - Io = 10A Upper side - 1.8 2.3 Tj = 25C Lower side *1 - 2.1 2.6 Io = 5A Upper side - 1.3 - Tj = 100C Lower side *1 Fig.2 Fig.3 V V - 1.6 - Junction to case θj-c(T) IGBT - - 4 thermal resistance θj-c(D) FRD - - 5 - 0.08 0.4 - 1.6 4 2.5 - - - - 0.8 V 0.5 0.8 - V A C/W Control (Pre-driver) section Pre-driver power dissipation ID VD1, 2, 3 = 15V VD4 = 15V Fig.4 mA High level Input voltage Vin H Low level Input voltage Vin L Input threshold voltage hysteresis*1 Vinth(hys) Logic 1 input leakage current IIN+ VIN = +3.3V - 100 143 Logic 0 input leakage current IIN- VIN = 0V - - 2 A FAULT terminal input electric current IoSD FAULT : ON/VFAULT = 0.1V - 2 - mA FAULT clear time FLTCLR Fault output latch time. 18 - 80 ms VCC and VS undervoltage positive VCCUV+ going threshold. VSUV+ 10.5 11.1 11.7 V VCC and VS undervoltage negative VCCUV- going threshold. VSUV- 10.3 10.9 11.5 V 0.14 0.2 - A VCC and VS undervoltage hysteresis HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 to VSS VCCUVH VSUVH- Over current protection level ISD PW = 100μs, RSD = 0Ω Output level for current monitor ISO Io = 10A Thermistor for substrate temperature Rt Fig.5 Thermistor Resistance at 25C (Vth) V 18.1 - 22.9 A 0.31 0.33 0.35 V 90 100 110 kΩ Reference voltage is “VSS” terminal voltage unless otherwise specified. *1: The lower side’s VCE(SAT) and VF include a loss by the shunt resistance No.A2210-2/15 STK551U362A-E Parameter Symbol Conditions Ratings Test circuit Unit min typ max 0.3 0.6 1.3 - 1.0 1.8 - 100 - J - 110 - J - 210 - J Switching Character Switching time Turn-on switching loss tON Io = 10A tOFF Inductive load Eon Ic = 5A,V = 300V, + s Turn-off switching loss Eoff VDD = 15V, L = 3.9mH Total switching loss Etot Tc = 25C Turn-on switching loss Eon Ic = 5A, V = 300 V, - 110 - J Turn-off switching loss Eoff VDD = 15V, L = 3.9mH - 230 - J Total switching loss Etot Tc = 100C - 340 - J Diode reverse recovery energy Erec + IF = 5A, V = 400V, VDD = 15V, - 10 - J Diode reverse recovery time Trr L = 3.9mH, Tc = 100C - 50 - ns Reverse bias safe operating area RBSOA Io = 20A, VCE = 450V Short circuit safe operating area SCSOA VCE = 400V, Tc = 100C Allowable offset voltage slew rate dv/dt Between U,V,W to U-,V-,W- + Fig.6 Full square 4 50 - - s 50 V/ns Reference voltage is “VSS” terminal voltage unless otherwise specified. Notes: 1. When the internal protection circuit operates, a Fault signal is turned ON (When the Fault terminal is low level, Fault signal is ON state : output form is open DRAIN) but the Fault signal does not latch.After protection operation ends,it returns automatically within about 18ms to 80ms and resumes operation beginning condition. So, after Fault signal detection, set all input signals to OFF (Low) at once.However, the operation of pre-drive power supply low voltage protection (UVLO:with hysteresis about 0.2V) is as follows. Upper side: The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘low’. Lower side: The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. When assembling the H-IC on the heat sink with M3 type screw, tightening torque range is 0.6 Nm to 0.9 Nm. 3. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating malfunction. No.A2210-3/15 STK551U362A-E Module Pin-Out Description Pin Name Description 1 VB3 High Side Floating Supply Voltage 3 2 W, VS3 Output 3 - High Side Floating Supply Offset Voltage 3 ― 4 ― 5 VB2 High Side Floating Supply voltage 2 6 V,VS2 Output 2 - High Side Floating Supply Offset Voltage Without Pin Without Pin 7 ― Without Pin 8 ― Without Pin 9 VB1 High Side Floating Supply voltage 1 10 U,VS1 Output 1 - High Side Floating Supply Offset Voltage 11 ― Without Pin 12 ― none 13 V+ Positive Bus Input Voltage 14 NA none 15 NA none 16 V- Negative Bus Input Voltage 17 HIN1 Logic Input High Side Gate Driver - Phase 1 18 HIN2 Logic Input High Side Gate Driver - Phase V 19 HIN3 Logic Input High Side Gate Driver - Phase W 20 LIN1 Logic Input Low Side Gate Driver - Phase U 21 LIN2 Logic Input Low Side Gate Driver - Phase V 22 LIN3 Logic Input Low Side Gate Driver - Phase W 23 FLTEN Enable input / Fault output 24 ISO Current monitor output 25 VDD +15V Main Supply 26 VSS Negative Main Supply 27 ISD Over current detection and setting 28 RCIN Fault clear time setting output 29 TH Thermistor output No.A2210-4/15 STK551U362A-E Equivalent Block Diagram VB3(1) W,VS3(2) VB2(5) V,VS2(6) VB1(9) U,VS1(10) +(13) DB DB DB U.V. U.V. U.V. Shunt-Resistor -(16) RCIN(28) Latch time TH(29) Level Shifter Level Shifter Level Shifter HIN1(17) HIN2(18) HIN3(19) Logic Logic Logic LIN1(20) LIN2(21) LIN3(22) FAULT(23) ISO(24) VDD(25) Thermistor Latch Over-Current VSS(26) VDD-UnderVoltage ISD(27) No.A2210-5/15 STK551U362A-E Test Circuit (The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.) ■ ICE / IR(BD) ICE U+ V+ W+ U- V- W- M 13 13 13 10 6 2 N 10 6 2 16 16 16 9 M A VD1=15V 10 5 VD2=15V 6 VCE 1 U(BD) V(BD) W(BD) M 9 5 1 N 26 26 26 VD3=15V 2 25 VD4=15V 26 N Fig. 1 9 5V VD1=15V ■ VCE(SAT) (Test by pulse) M 10 U+ V+ W+ U- V- W- M 13 13 13 10 6 2 N 10 6 2 16 16 16 m 17 18 19 20 21 22 5 VD2=15V 6 V Io 1 VD3=15V VCE(SAT) 2 25 VD4=15V m 26 27 N Fig. 2 ■ VF (Test by pulse) U+ V+ W+ U- V- W- M 13 13 13 10 6 2 N 10 6 2 16 16 16 M V VF Io N Fig. 3 ■ ID VD1 VD2 VD3 VD4 M 9 5 1 25 N 10 6 2 26 ID A M VD* N Fig. 4 No.A2210-6/15 STK551U362A-E ■ ISD 9 Input signal 10 VD1=15V 10 (0 to 5V) 5 VD2=15V 6 Io 1 VD3=15V 2 25 VD4=15V Io ISD Input signal 20 26 27 16 100μS Fig. 5 ■ Switching time (The circuit is a representative example of the lower side U phase.) 9 13 VD1=15V 10 Input signal (0 to 5V) 5 VD2=15V 6 10 1 Vcc CS VD3=15V 2 25 90% Io VD4=15V 10% tON Input signal Io 20 26 27 16 tOFF Fig. 6 No.A2210-7/15 STK551U362A-E Logic Timing Chart VBS undervoltage protection reset signal ON HIN1,2,3 OFF LIN1,2,3 *2 VDD VDD undervoltage protection reset voltage *3 VBS undervoltage protection reset voltage VB1,2,3 *4 -------------------------------------------------------ISD operation current level------------------------------------------------------- -terminal (BUS line) Current FAULT terminal Voltage (at pulled-up) ON *1 Upper U, V, W OFF *1 Lower U ,V, W Automatically reset after protection (18ms to 80ms) Fig. 7 Notes *1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be added externally. *2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. part. When VDD rises the operation will resume immediately. *3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gat voltage rises. *4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18 to 80ms after the over current condition is removed. No.A2210-8/15 STK551U362A-E Logic level table V+ Ho HIN1,2,3 (15,16,17) IC Driver LIN1,2,3 (18,19,20) U,V,W (8,5,2) Lo FLTEN Itrip HIN1,2,3 LIN1,2,3 U,V,W 1 0 1 0 Vbus 1 0 0 1 0 1 0 0 0 Off 1 0 1 1 Off 1 1 X X Off 0 X X X Off Fig. 8 Sample Application Circuit STK551U362A-E VB1: 9 + : 13 U,VS1:10 VCC CB VD1 CB VD2 CB VD3 CS1 CS2 VB2: 5 V,VS2: 6 - : 16 VB3: 1 W,VS3: 2 RCIN:28 U,VS1:10 HIN1:17 HIN2:18 V,VS2: 6 HIN3:19 Control LIN1:20 Circuit LIN2:21 (5V) LIN3:22 ISO:24 FAULT:23 TH:29 W,VS3: 2 VDD:25 Vss:26 RP CD4 RP VD=15V ISD:27 RSD Fig. 9 No.A2210-9/15 STK551U362A-E Recommended Operating Conditions at Tc = 25C Item Symbol Supply voltage VCC + to U-(V-,W-) Pre-driver VD1,2,3 VB1 to U, VB2 to V, VB3 to W supply voltage VD4 VDD to VSS ON-state input voltage VIN(ON) HIN1, HIN2, HIN3, OFF-state input voltage VIN(OFF) LIN1, LIN2, LIN3 PWM frequency fPWM Dead time DT Turn-off to turn-on Allowable input pulse width PWIN ON and OFF Tightening torque Ratings Conditions ‘M3’ type screw *1 min typ max Unit 0 280 450 12.5 15 17.5 V 13.5 15 16.5 3.0 - 5.0 0 - 0.3 1 - 20 kHz 1.5 - - s 1 - - s 0.6 - 0.9 Nm V V *1 Pre-drive power supply (VD4=15±1.5V) must be have the capacity of Io=20mA(DC), 0.5A(Peak). Usage Precautions 1. This H-IC includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF, however this value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about 20Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor. When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply. 2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF. 3. “ISO” (pin24) is terminal for current monitor. When the pull-down resistor is used, please select it more than 5.6kΩ 4. “FAULT” (pin23) is open DRAIN output terminal. (Active Low). Pull up resistor is recommended more than 5.6kΩ. 5. Inside the H-IC, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used. The temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below. 6. pull down resistor of 33kΩ is provided internally at the signal input terminals. An external resistor of 2.2k to 3.3kΩ should be added to reduce the influence of external wiring noise. 7. The over-current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for safety. 8. When “-” and “VSS” terminal are short-circuited on the outside, level that over-current protection (ISD) might be changed from designed value as H-IC. Please check it in your set (“N” terminal and “VSS” terminal are connected in H-IC). 9. The over-current protection function operates normally when an external resistor RSD is connected between ISD and VSS terminals. Be sure to connect this resistor. The level of the overcurrent protection can be changed according to the RSD value. 10. When input pulse width is less than 1.0μs, an output may not react to the pulse. (Both ON signal and OFF signal) This data shows the example of the application circuit, does not guarantee a design as the mass production set. No.A2210-10/15 STK551U362A-E The characteristic of thermistor Parameter Symbol Condition Min Typ. Max Unit Resistance R25 Tc = 25C 97 100 103 kΩ Resistance R100 Tc = 100C B-Constant (25 to 50 C) Temperature Range B 4.93 5.38 5.88 kΩ 4165 4250 4335 k 40 - +125 C Fig. 10 Condition Pull-up resistor = 39k Pull-up voltage of TH = 5V Fig. 11 No.A2210-11/15 STK551U362A-E The characteristic of PWM switching frequency Maximum sinusoidal phase current as function of switching frequency (VBUS=400V, Tc=100C) Fig.12 Switching waveform IGBT Turn-on. Typical turn-on waveform @Tc=100deg, VBUS=400V X (200ns/div) Turn on VCE (100V/div) Io (5A/div) Fig. 13 IGBT Turn-off. Typical turn-off waveform @Tc=100deg, VBUS=400V X (200ns/div) Turn off VCE (100V/div) Io (5A/div) Fig. 14 No.A2210-12/15 STK551U362A-E CB capacitor value calculation for bootstrap circuit Calculate condition Item Upper side power supply. Total gate charge of output power IGBT at 15V. Upper side power supply low voltage protection. Upper side power dissipation. ON time required for CB voltage to fall from 15V to UVLO Symbol VBS Qg UVLO IDmax Ton-max Value 15 89 12 400 - Unit V nC V μA s Capacitance calculation formula CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is calculated as follows: VBS * CB – Qg – IDmax * Ton-max = UVLO * CB CB = (Qg + IDmax * Ton-max) / (VBS – UVLO) The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to production. Tonmax-Cb characteristic Fig 15 No.A2210-13/15 STK551U362A-E Package Dimensions (unit : mm) SIP29 56x21.8 CASE 127BW ISSUE O missing pin : 3,4,7,8,11,12,14,15 13.9 (10.9) R1.7 1 21.8 3.4 56.0 +0 . 2 0.6 −0.05 1.27 1.27 × 28=35.56 0.5 +0 . 2 0.5−0.05 5.0 29 3.2 +0 . 1 6.7−0.5 2.0 5.7 46.2 50.0 62.0 No.A2210-14/15 STK551U362A-E ORDERING INFORMATION Device STK551U362A-E Package SIP29 56x21.8 (Pb-Free) Shipping (Qty / Packing) 8 / Tube ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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