Ordering number : ENA2217A STK554U362A-E Thick-Film Hybrid IC Inverter Power H-IC for 3-phase Motor Drive http://onsemi.com Overview This “Inverter Power H-IC” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a single small SIP module. Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. Function Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers. A single power supply drive is enabled through the use of bootstrap circuits for upper power supplies Built-in dead-time for shoot-thru protection Having open emitter output for low side IGBTs; individual shunt resistor per phase for OCP Externally accessible embedded thermistor for substrate temperature measurement Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output stage by external input Certification UL1557 (File number: E339285). Specifications Absolute Maximum Ratings at Tc = 25C Parameter Symbol Remarks Unit 450 V VCC V+ to U-, V-, W-, surge<500V Collector-emitter voltage VCE V+ to U, V, W or U, V, W, to U-, V-, W- 600 V V+,U-,V-,W-,U,V,W terminal current ±10 A V+,U-,V-,W-,U,V,W terminal current, Tc=100C ±7 A ±20 A 20 V HIN1, 2, 3, LIN1, 2, 3 0.3 to VDD V FLTEN terminal Output current Output peak current Pre-driver voltage Input signal voltage Io Iop VD1,2,3,4 VIN *1 Ratings Supply voltage V+,U-,V-,W-,U,V,W terminal current, P.W.=1ms VB1 to U, VB2 to V, VB3 to W, VDD to VSS *2 0.3 to VDD V Maximum power dissipation Pd IGBT per 1 channel 30 W Junction temperature Tj IGBT, FRD, Pre-Driver IC 150 C Storage temperature Tstg 40 to +125 C 40 to +100 C 0.9 Nm 2000 VRMS FLTEN terminal voltage Operating case temperature VFLTEN Tc Tightening torque Withstand voltage H-IC case A screw part Vis *3 50Hz sine wave AC 1 minute *4 Reference voltage is “VSS” terminal voltage unless otherwise specified. *1: Surge voltage developed by the switching operation due to the wiring inductance between + and U-(V-, W-) terminal. *2: VD1=VB1 to U, VD2=VB2 to V, VD3=VB3 to W, VD4=VDD to VSS terminal voltage. *3: Flatness of the heat-sink should be less than 50m to +100m. *4: Test conditions : AC2500V, 1 second Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. Semiconductor Components Industries, LLC, 2013 December, 2013 Ver. 131209DS D1913HK 018-13-0043/90413HK No.A2217-1/15 STK554U362A-E Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15V Parameter Symbol Conditions Test circuit MIN TYP MAX Unit Power output section Collector-emitter cut-off current ICE VCE = 600V Bootstrap diode reverse current IR(BD) VR(BD) = 600V Collector to emitter saturation voltage Diode forward voltage Junction to case thermal resistance VCE(SAT) VF Ic = 10A, Tj=25C Ic = 5A, Tj=100C IF = -10A, Tj=25C IF = -5A, Tj=100C θj-c(T) IGBT θj-c(D) FWD Fig.1 Fig.2 Fig.3 - - - 100 μA - - 100 μA - 1.6 2.2 - 1.35 - - 1.6 2.1 - 1.3 - - - 4 - - 5 - 0.08 0.4 - 1.6 4 V V C /W Control (Pre-driver) section Pre-driver power dissipation ID VD1,2,3 = 15V VD4 = 15V Fig.4 mA High level Input voltage Vin H HIN1,HIN2,HIN3, - 2.5 - - V Low level Input voltage Vin L LIN1,LIN2,LIN3 to VSS - - - 0.8 V Logic 1 input leakage current IIN+ VIN=+3.3V - - 100 143 μA Logic 0 input leakage current IIN- VIN=0V - - - 2 μA FLTEN terminal sink current IoSD FAULT:ON / VFLTEN=0.1V - - 2 - mA - 1.3 1.65 2 ms - - - 2.5 V FLTEN clearance delay time FLTEN Threshold FLTCLR VEN+ From time fault condition clear VEN rising VEN- VEN falling - 0.8 - - V ITRIP threshold voltage VITRIP ITRIP(16) to VSS(29) - 0.44 0.49 0.54 V ITRIP to shutdown propagation delay tITRIP - 340 550 800 ns ITRIP blanking time tITRIPBL - 250 350 - ns - 10.5 11.1 11.7 V - 10.3 10.9 11.5 V - 0.14 0.2 - V - 42.3 47 51.7 kΩ VCC and VBS supply undervoltage protection reset VCC and VBS supply undervoltage protection set VCC and VBS supply undervoltage hysteresis Thermistor for substrate temperature Monitor VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH Rt Resistance between TH(27) and VSS(29) Reference voltage is “VSS” terminal voltage unless otherwise specified. No.A2217-2/15 STK554U362A-E Parameter Symbol Conditions Test circuit MIN TYP MAX Unit - 0.4 - - 0.65 - - 130 - μJ Switching Character t ON Io = 10A t OFF Inductive load Eon Io=5A,V =300V, Turn-off switching loss Eoff VDD=15V,L=650uH Total switching loss Etot Tc=25C Turn-on switching loss Eon + Io=5A,V =300V, Turn-off switching loss Eoff VDD=15V,L=650uH Total switching loss Etot Tc=100C Switching time Turn-on switching loss Fig.5 + Fig.5 Fig.5 + μs - 122 - μJ - 252 - μJ - 156 - μJ - 154 - μJ - 310 - μJ Diode reverse recovery energy Erec I0=5A, V =400V, VDD=15V, - - 6.9 - μJ Diode reverse recovery time Trr L=650uH, Tc=100C - - 57 - ns Reverse bias safe operating area RBSOA Io = 20A, VCE = 450V - Short circuit safe operating area SCSOA VCE = 400V, Tc=100C - 4 - - μs Allowable offset voltage slew rate dv/dt - 50 - 50 V/ns Between U(V,W) to U-(V-,W-) Full square- - Reference voltage is “VSS” terminal voltage unless otherwise specified. Notes 1. The pre-drive power supply low voltage protection has approximately 200mV of hysteresis and operates as follows. Upper side ：The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘low’. Lower side ：The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 2. When assembling the H-IC on the heat sink the tightening torque range is 0.6Nm to 0.9Nm. 3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction. 4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). No.A2217-3/15 STK554U362A-E Module Pin-Out Description Pin Name Description 1 VB3 High Side Floating Supply Voltage 3 2 W, VS3 Output 3 - High Side Floating Supply Offset Voltage 3 - Without pin 4 - Without pin 5 VB2 High Side Floating Supply voltage 2 6 V,VS2 Output 2 - High Side Floating Supply Offset Voltage 7 - Without pin 8 - Without pin 9 VB1 High Side Floating Supply voltage 1 10 U,VS1 Output 1 - High Side Floating Supply Offset Voltage 11 - Without pin 12 - Without pin 13 V+ Positive Bus Input Voltage 14 - Without pin 15 - Without pin 16 ITRIP Current protection pin 17 U- Low Side Emitter Connection - Phase U 18 FLTEN Enable input / Fault output 19 V- Low Side Emitter Connection - Phase V 20 HIN1 Logic Input High Side Gate Driver - Phase U 21 W- Low Side Emitter Connection - Phase W 22 HIN2 Logic Input High Side Gate Driver - Phase V 23 HIN3 Logic Input High Side Gate Driver - Phase W 24 LIN1 Logic Input Low Side Gate Driver - Phase U 25 LIN2 Logic Input Low Side Gate Driver - Phase V 26 LIN3 Logic Input Low Side Gate Driver - Phase W 27 TH Thermistor output 28 VDD +15V Main Supply 29 VSS Negative Main Supply No.A2217-4/15 STK554U362A-E Equivalent Block Diagram VB3( 1) W,VS3( 2) VB2( 5) V,VS2( 6) VB1( 9) U,VS1(10) V+ (13) DB DB DB U.V. U.V. U.V. U- (17) V- (19) W- (21) Level Level Level Shifter Shifter Shifter HIN1(20) HIN2(22) HIN3(23) Logic Logic Logic LIN1(24) LIN2(25) LIN3(26) Thermistor TH(27) ITRIP(16) Shutdown VDD(28) VSS(29) Enable/Disable Under voltage + Detect - S Timer Q R Vref Latch time about 2ms FLTEN(18) No.A2217-5/15 STK554U362A-E Test Circuit (The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.) ICE / IR(BD) M N U+ 13 10 M N U(BD) 9 29 V+ 13 6 W+ 13 2 U10 17 V6 19 W2 21 ICE 9 M A VD1=15V 10 5 V(BD) 5 29 VD2=15V W(BD) 1 29 6 VCE 1 VD3=15V 2 28 VD4=15V 29 N Fig.1 VCE(SAT) (Test by pulse) M N m U+ 13 10 20 V+ 13 6 22 W+ 13 2 23 U10 17 24 V6 19 25 W2 21 26 9 M VD1=15V 10 5 VD2=15V 6 V Ic 1 VD3=15V VCE(SAT) 2 28 VD4=15V 5V m 29 16 N Fig.2 VF (Test by pulse) M N U+ 13 10 V+ 13 6 W+ 13 2 U10 17 V6 19 W2 21 M V VF IF N Fig.3 ID M N VD1 9 10 VD2 5 6 VD3 1 2 VD4 28 29 ID A M VD* N Fig.4 No.A2217-6/15 STK554U362A-E Switching time (The circuit is a representative example of the lower side U phase.) 9 Input signal (0 to 5V) 13 VD1=15V 10 5 VD2=15V 6 90% Io 10 1 Vcc CS VD3=15V 2 28 10% tON tOFF VD4=15V Input signal Io 24 29 16 17 Fig.5 RB-SOA (The circuit is a representative example of the lower side U phase.) Input signal (0 to 5V) 9 13 VD1=15V 10 5 VD2=15V 6 Io 10 1 Vcc CS VD3=15V 2 28 VD4=15V Input signal Io 24 29 16 17 Fig.6 No.A2217-7/15 STK554U362A-E Input / Output Timing Chart VBS undervoltage protection reset signal ON HIN1,2,3 OFF LIN1,2,3 *2 VDD VDD undervoltage protection reset voltage *3 VBS undervoltage protection reset voltage VB1,2,3 VIT≥0.54V *4 ITRIP terminal Voltage VIT<0.44V FLTEN ON Upper U, V, W *1 OFF Lower U ,V, W *1 Automatically reset after protection (typ.2ms) Fig. 7 Notes: 1. *1 shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay externally. 2. *2 when VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume immediately. 3. *3 when the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gate voltage rises. 4. *4 when VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2ms (typ) after over current condition is removed. No.A2217-8/15 STK554U362A-E Logic level table V+ Ho HIN1,2,3 (15,16,17) LIN1,2,3 (18,19,20) IC Driver U,V,W (8,5,2) Lo FLTEN Itrip HIN1,2,3 LIN1,2,3 U,V,W 1 0 1 0 Vbus 1 0 0 1 0 1 0 0 0 Off 1 0 1 1 Off 1 1 X X Off 0 X X X Off Fig. 8 Sample Application Circuit STK554U362A-E VB1: 9 V+:3 Vcc CI CB1 U,VS1:10 CS VB2: 5 CB2 V,VS2: 6 U-:7 RSU RSV RSW VB3: 1 V-:19 W-:21 CB3 W,VS3: 2 Op-Amp, Controller U,VS1:10 HIN1:20 HIN2:22 V,VS2: 6 HIN3:23 Control LIN1:24 Circuit LIN2:25 (5V) LIN3:26 TH:27 FLTEN:18 RS, Controller ITRIP:16 VDD:28 VSS:29 W,VS3: 2 RP RTH CD4 VD4=15V Fig.9 No.A2217-9/15 STK554U362A-E Recommended Operating Condition at Tc = 25C Item Symbol Conditions Min. Typ. Max. Unit V Supply voltage VCC V+ to U-(V-,W-) 0 280 450 Pre-driver VD1,2,3 VB1 to U,VB2 to V,VB3 to W 12.5 15 17.5 supply voltage VD4 VDD to VSS 13.5 15 16.5 ON-state input voltage VIN(ON) HIN1,HIN2,HIN3, 3.0 - 5.0 OFF-state input voltage VIN(OFF) LIN1,LIN2,LIN3 0 - 0.3 PWM frequency fPWM 1 - 20 kHz 0.5 - - μs 1 - - μs 0.6 - 0.9 Nm *1 Dead time DT Turn-off to turn-on (external) Allowable input pulse width PWIN ON and OFF Tightening torque ‘M3’ type screw V V *1 Pre-drive power supply (VD4=15±1.5V) must have the capacity of Io=20mA (DC), 0.5A (Peak). Usage Precaution 1. This H-IC includes internal bootstrap diode and resistor. By adding a bootstrap capacitor “CB”, a high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF, however, this value needs to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about 20Ω) in series between each 3-phase upper side power supply terminals (VB1,2,3) and each bootstrap capacitor. When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply. 2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10μF. 3. The “FLTEN” terminal (Pin 18) is I/O terminal; Fault output / Enable input. It is used to indicate an internal fault condition of the module and also can be used to disable the module operation. 4. Inside the H-IC, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used. The temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below. 5. The pull-down resistor (:33kΩ(typ)) is connected with the inside of the signal input terminal, but please connect the pull-down resistor(about 2.2 to 3.3kΩ) outside to decrease the influence of the noise by wiring etc. 6. As protection of H-IC to the unusual current by a short circuit etc,, it recommends installing shunt resistors and an over-current protection circuit outside. Moreover, for safety, a fuse on Vcc line is recommended. 7. Disconnection of terminals U, V, or W during normal motor operation will cause damage to H-IC, use caution with this connection. . 8. The “ITRIP” terminal (Pin 16) is the input terminal to shut down. When VITRIP exceeds threshold (0.44V to 0.54V) all IGBT’s are turned off. And normal operation resumes 2ms (typ) after over current condition is removed. Therefore, please turn all the input signals off (Low) in case of detecting error at the “FLTEN” terminal. 9. When input pulse width is less than 1μs, an output may not react to the pulse. (Both ON signal and OFF signal) This data shows the example of the application circuit, and does not guarantee a design as the mass production set. No.A2217-10/15 STK554U362A-E The characteristic of thermistor Symbol Condition Min Typ. Max Unit Resistance Parameter R25 T = 25C 44.6 47.0 49.4 kΩ Resistance R125 T = 125C 1.28 1.41 1.53 kΩ 4010 4050 4091 K +125 C B-Constant(25-50C) B 40 Temperature Range Fig.10 Variation of thermistor resistance with temperature Condition Pull-up resistor = 4.7kphm Pull-up voltage of TH = 5V Fig.11 Variation of temperature sense voltage with thermistor temperature No.A2217-11/15 STK554U362A-E Maximum Phase current Fig.12 Maximum sinusoidal phase current as function of switching frequency at Tc=100C, Vcc=300V Switching waveform X:100nS/div Ic: 5A/div Vce: 100V/div Fig. 13 IGBT Turn-on. Typical turn-on waveform at Tc=100C, Vcc=300V, Ic=10A X:100nS/div Vce: 100V/div Ic: 5A/div Fig. 14 IGBT Turn-off. Typical turn-off waveform Tc=100C, Vcc=300V, Ic=10A No.A2217-12/15 STK554U362A-E CB capacitor value calculation for bootstrap circuit Calculate condition Item Upper side power supply. Total gate charge of output power IGBT at 15V. Upper side power supply low voltage protection. Upper side power dissipation. ON time required for CB voltage to fall from 15V to UVLO Symbol VBS Qg UVLO IDmax Ton-max Value 15 89 12 400 - Unit V nC V μA s Capacitance calculation formula CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is calculated as follows: VBS * CB – Qg – IDmax * Ton-max = UVLO * CB CB = (Qg + IDmax * Ton-max) / (VBS – UVLO) The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47μF, however, the value needs to be verified prior to production. Bootstrap Capacitance CB [uF] CB vs Ton-max Ton-max[ms] Fig.15 Ton-max vs CB characteristic No.A2217-13/15 STK554U362A-E Package Dimensions (unit : mm) SIP29 56x21.8 CASE 127BW ISSUE O missing pin : 3,4,7,8,11,12,14,15 13.9 (10.9) R1.7 1 21.8 3.4 56.0 +0 . 2 0.6 −0.05 1.27 1.27 × 28=35.56 0.5 +0 . 2 0.5−0.05 5.0 29 3.2 +0 . 1 6.7−0.5 2.0 5.7 46.2 50.0 62.0 No.A2217-14/15 STK554U362A-E ORDERING INFORMATION Device STK554U362A-E Package SIP29 56x21.8 (Pb-Free) Shipping (Qty / Packing) 8 / Tube ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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