STK531U369A E D

STK531U369A-E
Inverter IPM
for 3-phase Motor Drive
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Overview
This “Inverter IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase
outputs in a single SIP module (Single-In line Package). Output stage uses IGBT/FRD technology and implements
Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal
Boost diodes are provided for high side gate boost drive.
Function
 Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit
 All control input and status output are at low voltage levels directly compatible with microcontrollers
 Built-in cross conduction prevention
 Externally accessible embedded thermistor for substrate temperature measurement
 The level of the over current protection is adjustable with the external resistor, “RSD”
Certification
 UL Recognized (File number : E339285)
Specifications
Absolute Maximum Ratings at Tc = 25C
Parameter
Symbol
Remarks
Supply voltage
VCC
P to N, surge < 500V
Collector-emitter voltage
VCE
Output current
Io
Output peak current
Ratings
Unit
450
V
P to U, V, W or U, V, W, to N
600
V
P, N, U, V, W terminal current
±10
A
P, N, U, V, W terminal current at Tc = 100C
±5
A
Iop
P, N, U, V, W terminal current, PW = 1ms
±20
A
Pre-driver voltage
VD1,2,3,4
VB1 to U, VB2 to V, VB3 to W, VDD to VSS
20
V
Input signal voltage
VIN
HIN1, 2, 3, LIN1, 2, 3
0.3 to VDD
V
FAULT terminal voltage
VFAULT
FAULT terminal
0.3 to VDD
V
Maximum power dissipation
Pd
IGBT per 1 channel
31.2
W
Junction temperature
Tj
IGBT, FRD
Storage temperature
Tstg
Operating case temperature
Tc
Tightening torque
Isolation voltage
Vis
*1
*2
IPM case temperature
150
C
40 to +125
C
20 to +100
C
A screw part
*3
0.9
Nm
50Hz sine wave AC 1 minute
*4
2000
VRMS
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : Surge voltage developed by the switching operation due to the wiring inductance between P and N terminal.
*2 : VD1=VB1 to U, VD2=VB2 to V, VD3=VB3 to W, VD4=VDD to VSS terminal voltage.
*3 : Flatness of the heat-sink should be lower than 0.15mm.
*4 : Test conditions : AC2500V, 1 second.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
February 2015 - Rev. 1
1
Publication Order Number :
STK531U369A-E/D
STK531U369A-E
Electrical Characteristics at Tc = 25C, VD1, VD2, VD3, VD4 = 15V
Parameter
Symbol
Conditions
Test
circuit
MIN
TYP
MAX
Unit
-
-
0.1
mA
-
-
0.1
mA
-
1.9
2.4
-
2.2
2.7
-
1.5
-
Power output section
Collector-emitter cut-off current
ICE
VCE = 600V
Bootstrap diode reverse current
IR(BD)
VR(BD) = 600V
Collector to emitter saturation voltage
VCE(SAT)
Fig.1
Upper side
Ic = 10A
Tj = 25C
Lower side *1
Upper side
Ic = 5A
Tj = 100C
Fig.2
Lower side *1
-
1.7
-
IF = 10A
Tj = 25C
Upper side
-
1.8
2.1
IF = 5A
Tj = 100C
Upper side
Diode forward voltage
VF
Junction to case
thermal resistance
θj-c(T)
IGBT
θj-c(D)
FWD
Lower side *1
Fig.3
Lower side *1
-
-
2.1
2.4
-
1.4
-
V
V
-
1.6
-
-
-
4.0
-
-
6.0
-
0.08
0.4
-
1.6
4.0
2.5
-
-
-
-
0.8
V
0.5
0.8
-
V
µA
C/W
Control (Pre-driver) section
Pre-driver current consumption
ID
High level Input voltage
Vin H
Low level Input voltage
Vin L
Input threshold voltage hysteresis
*2
VD1, 2, 3 = 15V
Fig.4
VD4 = 15V
HIN1, HIN2, HIN3,
LIN1, LIN2, LIN3 to VSS
Vinth(hys)
mA
V
Logic 1 input leakage current
IIN+
VIN = +3.3V
-
100
143
Logic 0 input leakage current
IIN
VIN = 0V
-
-
2
µA
FAULT terminal sink current
IoSD
FAULT : ON / VFAULT = 0.1V
-
2
-
mA
FAULT clear time
FLTCLR
Fault output latch time
18
-
80
ms
VCC and VS undervoltage positive
going threshold
VCCUV+
VSUV+
10.5
11.1
11.7
V
VCC and VS undervoltage negative
going threshold
VSUV
10.3
10.9
11.5
V
0.14
0.2
-
V
VCC and VS undervoltage hysteresis
VCCUV
VCCUVH
VSUVH
Over current protection level
ISD
PW = 100μs, RSD = 0Ω
Electric current output signal level
ISO
Io = 10A
Fig.5
18.1
-
22.9
A
-
0.31
0.33
0.35
V
Reference voltage is “VSS” terminal voltage unless otherwise specified.
*1 : The lower side’s VCE(SAT) and VF include a loss by the shunt resistance
*2 : Input threshold voltage hysteresis indicates a reference value based on the design value of built-in pre-driver IC
Electrical Characteristics at Tc  25C, VD1, VD2, VD3, VD4 = 15V, VCC = 300V, L = 3.9mH
Parameter
Switching time
Symbol
tON
tOFF
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Etot
Conditions
Test
circuit
Io = 10A
Io = 5A
Fig.6
MIN
TYP
MAX
0.3
0.5
1.2
-
0.8
1.5
Unit
µs
-
200
-
-
130
-
µJ
µJ
-
330
-
µJ
-
240
-
µJ
-
130
-
µJ
Etot
-
370
-
µJ
Erec
-
17
-
µJ
-
62
-
ns
-
µs
Turn-on switching loss
Eon
Turn-off switching loss
Eoff
Total switching loss
Diode reverse recovery energy
Diode reverse recovery time
trr
Reverse bias safe operating area
RBSOA
Io = 20A, VCE = 450V
Short circuit safe operating area
SCSOA
VCE = 400V, Tc = 100C
Io = 5A, Tc = 100C
IF = 5A, P = 400V, Tc = 100C
Full square
4
-
Reference voltage is “VSS” terminal voltage unless otherwise specified.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Notes:
1. The pre-drive power supply low voltage protection has approximately 0.2V of hysteresis and operates as follows.
Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the
input signal will turn ‘high’.
Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.
2. The pre-drive low voltage protection is the feature to protect devices when the pre-driver supply voltage falls due to an operating malfunction.
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2
STK531U369A-E
Equivalent Block Diagram
VB3(1)
W,VS3(2)
VB2(5)
V,VS2(6)
VB1(9)
U,VS1(10)
P (13)
BD
BD
BD
U.V.
U.V.
U.V.
Shunt-Resistor
N (16)
RCIN(28)
Latch time
TH(29)
Level
Shifter
Level
Shifter
Level
Shifter
HIN1(17)
HIN2(18)
HIN3(19)
Logic
Logic
Logic
LIN1(20)
LIN2(21)
LIN3(22)
FAULT(23)
ISO(24)
VDD(25)
Thermistor
Latch
Latch time is 18ms to 80ms
Over-Current
VDD-UnderVoltage
VSS(26)
ISD(27)
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3
(Automatic reset)
STK531U369A-E
Module Pin-Out Description
Pin
Name
Description
1
VB3
High Side Floating Supply Voltage 3
2
W, VS3
Output 3 - High Side Floating Supply Offset Voltage
3

Without Pin
4

Without Pin
5
VB2
High Side Floating Supply voltage 2
6
V,VS2
Output 2 - High Side Floating Supply Offset Voltage
7

Without Pin
8

Without Pin
9
VB1
High Side Floating Supply voltage 1
10
U,VS1
Output 1 - High Side Floating Supply Offset Voltage
11

Without Pin
12

Without Pin
13
P
Positive Bus Input Voltage
14

Without Pin
15

Without Pin
16
N
Negative Bus Input Voltage
17
HIN1
Logic Input High Side Gate Driver - Phase U
18
HIN2
Logic Input High Side Gate Driver - Phase V
19
HIN3
Logic Input High Side Gate Driver - Phase W
20
LIN1
Logic Input Low Side Gate Driver - Phase U
21
LIN2
Logic Input Low Side Gate Driver - Phase V
22
LIN3
Logic Input Low Side Gate Driver - Phase W
23
FAULT
Fault output
24
ISO
Current monitor output
25
VDD
+15V Main Supply
26
VSS
Negative Main Supply
27
ISD
Over current detection and setting
28
RCIN
Fault clear time setting output
29
TH
Thermistor output
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STK531U369A-E
Test Circuit
(The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase.)
 ICE / IR(BD)
M
N
U+
13
10
M
N
U(BD)
9
26
V+
13
6
W+
13
2
V(BD)
5
26
U10
16
V6
16
W2
16
9
M
A
ICE
VD1=15V
10
5
W(BD)
1
26
VD2=15V
6
VCE
1
VD3=15V
2
25
VD4=15V
26
N
Fig.1
 VCE(SAT) (Test by pulse)
M
N
m
U+
13
10
17
V+
13
6
18
W+
13
2
19
U10
16
20
V6
16
21
9
W2
16
22
M
VD1=15V
10
5
VD2=15V
6
V
Ic
1
VD3=15V
VCE(SAT)
2
25
VD4=15V
5V
m
26
27
N
Fig.2
 VF (Test by pulse)
M
M
N
U+
13
10
V+
13
6
W+
13
2
U10
16
V6
16
W2
16
V
N
Fig.3
 ID
M
N
VD1
9
10
VD2
5
6
VD3
1
2
VD4
25
26
Fig.4
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5
VF
IF
STK531U369A-E
■ ISD
9
Input signal
(0 to 5V)
10
VD1=15V
10
5
VD2=15V
6
Io
1
VD3=15V
2
25
Io
VD4=15V
ISD
Input signal
20
26
27
100μs
16
Fig.5
 Switching time (The circuit is a representative example of the lower side U phase.)
9
Input signal
(0 to 5V)
13
VD1=15V
10
5
VD2=15V
6
90%
Io
10
1
VCC
CS
VD3=15V
2
25
10%
tON
VD4=15V
tOFF
Input signal
Io
20
26
27
16
Fig.6
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STK531U369A-E
Input / Output Timing Chart
VBS under voltage protection reset signal
ON
HIN1,2,3
OFF
LIN1,2,3
*2
VDD
VDD under voltage protection reset signal
*3
VB1,2,3
VBS under voltage protection reset signal
*4
-------------------------------------------------------ISD operation current level-------------------------------------------------------
N terminal
(BUS line)
current
FAULT terminal
voltage
(at pulled-up)
ON
*1
Upper
U, V, W
OFF
*1
Lower
U ,V, W
Utmatically reset after protection
(18ms to 80ms)
Fig. 7
Notes
*1 : Diagram shows the prevention of shoot-through via control logic. More dead time to account for switching delay needs to be
added externally.
*2 : When VDD decreases all gate output signals will go low and cut off all of 6 IGBT outputs. When VDD rises the operation will
resume immediately.
*3 : When the upper side gate voltage at VB1, VB2 and VB3 drops only, the corresponding upper side output is turned off. The
outputs return to normal operation immediately after the upper side gate voltage rises.
*4 : In case of over current detection, all IGBT’s are turned off and the FAULT output is asserted. Normal operation resumes in 18
to 80ms after the over current condition is removed.
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STK531U369A-E
Logic level table
P(13)
INPUT
Upper
IGBT
HIN1,2,3
(17,18,19)
IC
Driver
LIN1,2,3
(20,21,22)
U,V,W
(10,6,2)
Lower
IGBT
OUTPUT
HIN
LIN
OCP
Upper
IGBT
Lower
IGBT
U,V,W
FAULT
H
L
OFF
ON
OFF
P
OFF
L
H
OFF
OFF
ON
N
OFF
L
L
OFF
OFF
OFF
High
Impedance
OFF
H
H
OFF
OFF
OFF
High
Impedance
OFF
X
X
ON
OFF
OFF
High
Impedance
ON
N(16)
Fig. 8
Sample Application Circuit
STK531U369A-E
VB1 : 9
P : 13
U,VS1 : 10
VCC
CB
VD1
CB
VD2
CB
VD3
CS1
CS2
VB2 : 5
V,VS2 : 6
N : 16
VB3 : 1
W,VS3 : 2
RCIN : 28
U,VS1 : 10
HIN1 : 17
HIN2 : 18
HIN3 : 19
Control
Circuit
(5V)
LIN1 : 20
LIN2 : 21
LIN3 : 22
V,VS2 : 6
ISO : 24
FAULT : 23
TH : 29
VDD : 25
CD
VSS : 26
W,VS3 : 2
RP
RP
VD=15V
ISD : 27
RSD
Fig.9
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STK531U369A-E
Recommended Operating Condition
Item
Supply voltage
Pre-driver supply voltage
PWM frequency
Symbol
VCC
Conditions
MIN
TYP
MAX
Unit
0
280
450
V
P to N
VD1,2,3
VB1 to U, VB2 to V, VB3 to W
VD4
VDD to VSS
*1
12.5
15
17.5
13.5
15
16.5
1
-
20
kHz
fPWM
V
Dead time
DT
Turn-off to Turn-on
2
-
-
μs
Allowable input pulse width
PWIN
ON and OFF
1
-
-
μs
0.6
-
0.9
Nm
Tightening torque
‘M3’ type screw
*1 : Pre-drive power supply (VD4=15±1.5V) must have the capacity of Io=20mA (DC), 0.5A (Peak).
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Usage Precaution
1. This IPM includes bootstrap diode and resistors. Therefore, by adding a capacitor “CB”, a high side drive voltage is generated; each
phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47μF, however this value needs
to be verified prior to production. If selecting the capacitance more than 47μF (±20%), connect a resistor (about 20Ω) in series between
each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap capacitor. When not using the bootstrap circuit, each
upper side pre-drive power supply requires an external independent power supply.
2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge
voltages. Recommended value of “CS” is in the range of 0.1 to 10μF.
3. “ISO” (pin24) is terminal for current monitor. High current may flow into that course when short-circuiting the “ISO” terminal and “VSS”
terminal. Please do not connect them.
4. “FAULT” (pin23) is open DRAIN output terminal (Active Low). Pull up resistor is recommended more than 6.8kΩ.
5. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate is connected between VSS terminal and TH terminal
therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used. The
temperature monitor example application is as follows, please refer the Fig.10, and Fig.11 below.
6. Pull down resistor of 33kΩ is provided internally at the signal input terminals. An external resistor of 2.2k to 3.3kΩ should be added to
reduce the influence of external wiring noise.
7. The over current protection feature is not intended to protect in exceptional fault condition. An external fuse is recommended for safety.
8. The level of the over current protection might be changed from IPM design value when “ISD” terminal and “VSS” terminal are shorted at
external. Be confirm with actual application(“N” terminal and “VSS” terminal are shorted at internal).
9. The level of the over current protection is adjustable with the external resistor “RSD” between “ISD” terminal and “VSS” terminal.
10. When input pulse width is less than 1.0μs, an output may not react to the pulse. (Both ON signal and OFF signal)
This data shows the example of the application circuit, does not guarantee a design as the mass production set.
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STK531U369A-E
The characteristic of thermistor
Parameter
Resistance
B-Constant (25 to 50 C)
Temperature Range
Symbol
R25
R100
B
Condition
MIN
99
5.18
4208
Tc = 25C
Tc = 100C
TYP
100
5.38
4250
-
40
MAX
101
5.60
4293
+125
Unit
kΩ
kΩ
K
C
Case Temperature(Tc) - Thermal resistance(RTH)
10000
Thermistor Resistanse, RTH-Kohm
min
typ
1000
max
100
10
1
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
100 110 120 130
Case temperature, Tc-degC
Fig.10 Variation of thermistor resistance with temperature
Case Temperature(Tc) - TH to Vss voltage characteristic
6.00
min
TH - Vss terminal voltage, VTH-V
5.00
typ
max
4.00
3.00
2.00
1.00
0.00
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
100 110 120 130
Case temperature, Tc-degC
Fig.11 Variation of thermistor terminal voltage with temperature
(39k pull-up resistor, 5V)
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STK531U369A-E
CB capacitor value calculation for bootstrap circuit
Calculate conditions
Parameter
Symbol
Value
Upper side power supply.
VBS
15
V
Total gate charge of output power IGBT at 15V.
QG
89
nC
Upper limit power supply low voltage protection.
UVLO
12
V
IDmax
400
μA
TONmax
-
s
Upper side power dissipation.
ON time required for CB voltage to fall from 15V to UVLO
Unit
Capacitance calculation formula
Thus, the following formula are true
VBS  CB  QG  IDMAX  TONMAX = UVLO  CB
therefore,
CB = (QG + IDMAX  TONMAX) / (VBS  UVLO)
The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated
above. The recommended value of CB is in the range of 1 to 47μF, however, this value needs to be verified prior to production.
CB vs Tonmax
Bootstrap Capacitance CB [uF]
100
10
1
0.1
0.01
0.1
1
10
Tonmax [ms]
Fig. 12 Tonmax - CB characteristic
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11
100
1000
STK531U369A-E
Package Dimensions
unit : mm
The tolerances of length are +/ 0.5mm unless otherwise specified.
SIP29 44x26.5
CASE 127CH
ISSUE O
44.0
41.0
2 R 1.8
29.0
( 15.75)
S IP 05 Full
( 24.0)
26.5
3.6
missing pin : 3, 4, 7, 8, 11, 12, 14, 15
0.6
1.27
3.2
0.50
1.27=35.56
5.5
28
5.0
29
1
( 35.0)
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6.20
STK531U369A-E
ORDERING INFORMATION
Device
STK531U369A-E
Package
Shipping (Qty / Packing)
SIP29 44x26.5
(Pb-Free)
11 / Tube
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