P4C168/P4C168L , P4C169, P4C170 ULTRA HIGH SPEED 4K x 4

P4C168/P4C168L , P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
Static CMOS RAMs
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– 20/25/35/45/55/70ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Single 5V±10% Power Supply
Fully TTL Compatible, Common I/O Ports
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ, LCC, SOIC, CERPACK, and Flat Pack
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of
16,384-bit ultra high-speed static RAMs organized as
4K x 4. All three devices have common input/output
ports.The P4C168 enters the standby mode when the
chip enable (CE) control goes HIGH; with CMOS input
levels, power consumption is only 83mW in this mode.
Both the P4C169 and the P4C170 offer a fast chip select
access time that is only 67% of the address access time.
In addition, the P4C170 includes an output enable (OE)
control to eliminate data bus contention. The RAMs operate from a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low
715 mW active, 193 mW standby.
Functional Block Diagram
Pin ConfigurationS
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent
board level densities. The P4C168 is also available in
20-pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
P4C168
P4C169
DIP (P2, C6, d2)
DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
P4C170
DIP (P3)
Document # SRAM107 REV E
1
Revised March 2010
P4C168/P4C168L, P4C169, P4C170
Maximum Ratings(1)
Symbol Parameter
Value
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
-0.5 to +7
V
TBIAS
Temperature Under
Bias
-55 to +125
°C
VTERM
Terminal Voltage with
respect to GND (up to
7.0V)
-0.5 to V CC
+ 0.5
V
TSTG
Storage Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
W
Operating Temperature
-55 to +125
°C
IOUT
DC Output Current
50
mA
TA
Unit
RECOMMENDED OPERATING CONDITIONS
Grade(2)
Ambient Temp
Gnd
Commercial 0°C to 70°C
0V
Military
0V
-55°C to +125°C
VCC
5.0V ± 10%
5.0V ± 10%
CAPACITANCES(2)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Sym
Parameter
Conditions Typ. Unit
CIN
Input Capacitance
VIN=0V
COUT
Output Capacitance VOUT=0V
5
pF
7
pF
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
Test Conditions
P4C168/169/170
P4C168L
Min
Max
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC+0.5
2.2
VCC+0.5
V
VIL
Input Low Voltage
-0.5(3)
0.8
-0.5(3)
0.8
V
VOL
Output Low Voltage (TTL Load)
IOL=+8 mA, VCC=Min
0.4
V
VOH
Output High Voltage (TTL Load)
IOH=-4 mA, VCC=Min
ILI
Input Leakage Current (Military)
Input Leakage Current (Commercial)
ILO
Output Leakage Current (Military)
Output Leakage Current (Commercial)
ICC
Standby Power Supply Current (TTL
Input Levels) (Military)
Standby Power Supply Current (TTL
Input Levels) (Commercial)
ISB1
VCC=Max, CS=VIH, VOUT=GND to
VCC
Dynamic Operating Current (Military)
Dynamic Operating Current (Commercial)
ISB
VCC=Max, VIN=GND to VCC
Standby Power Supply Current
(CMOS Input Levels) (Military)
Standby Power Supply Current
(CMOS Input Levels) (Commercial)
VCC=Max,f=Max, Outputs Open
CE1≥VIH,VCC=Max,f=Max,Outputs
Open
CE 1≥V HC,V CC=Max,f=0,Outputs
Open,VIN≤VLC or VIN≥VHC
0.4
2.4
2.4
V
-10
+10
-5
+5
-5
+5
-2
+2
-10
+10
-5
+5
-5
+5
-2
+2
—
120
—
120
—
100
—
100
—
40
—
40
—
35
—
35
—
20
—
1
—
15
—
0.2
µA
µA
mA
mA
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
periods may affect reliability..
cause permanent damage to the device. This is a stress rating only 2. This parameter is sampled and not 100% tested.
and functional operation of the device at these or any other conditions 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA,
above those indicated in the operational sections of this specification
respectively, are permissible for pulse widths up to 20 ns.
is not implied. Exposure to MAXIMUM rating conditions for extended
Document # SRAM107 REV E
Page 2 of 14
P4C168/P4C168L, P4C169, P4C170
DATA RETENTION CHARACTERISTICS (P4C168L only)
Sym
Parameter
Test Condition
Min
Typ. *
VCC=
2.0V
VDR
VCC for Data Retention
ICCDR
CE ≥ VCC - 0.2V,
VIN ≥ VCC - 0.2V,
or VIN ≤ 0.2V
Data Retention Current (Commercial)
Chip Deselect to Data Retention Time
tR†
Operation Recovery Time
2.0V
3.0V
2.0
Data Retention Current (Military)
tCDR
3.0V
Max
VCC=
Unit
V
2
3
200
300
µA
0.5
1.0
20
30
µA
0
ns
tRC§
ns
DATA RETENTION WAVEFORM
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(4)
Sym Parameter
-12
Min
-15
Max
Min
-20
Max
Min
-25
Max
Min
-35
Max
Min
Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
12
15
20
25
35
ns
tAC§
Chip Enable Access Time
12
15
20
25
35
ns
tAC
Chip Select Access Time
8
9
12
15
20
ns
‡
12
15
20
25
35
ns
tOH
Output Hold from Address Change
2
2
2
2
2
ns
t
Chip Enable to Output in Low Z
2
2
2
2
2
ns
tHZ†
Chip Disable to Output in High Z
7
8
9
10
15
ns
tOE†
Output Enable to Data Valid
8
10
12
15
15
ns
‡
LZ
tOLZ† Output Enable to Output in Low Z
0
tOHZ† Output Disable to Output in High Z
0
6
0
7
0
9
0
11
ns
15
ns
tRCS
Read Command Setup Time
0
0
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
0
0
ns
tPU
Chip Enable to Power Up Time
0
0
0
0
0
ns
§
tPD§
Chip Disable to Power Down Time
12
15
20
25
35
ns
Notes:
4. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
Document # SRAM107 REV E
Page 3 of 14
P4C168/P4C168L, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-45
Min
-55
Max
Min
-70
Max
Min
Max
Unit
tRC
Read Cycle Time
tAA
Address Access Time
45
55
70
ns
tAC§
Chip Enable Access Time
45
55
70
ns
tAC‡
Chip Select Access Time
25
30
35
ns
tOH
Output Hold from Address Change
2
2
2
ns
t
Chip Enable to Output in Low Z
2
2
2
ns
‡
LZ
tHZ
†
tOE†
45
55
70
ns
Chip Disable to Output in High Z
25
25
30
ns
Output Enable to Data Valid
20
25
30
ns
tOLZ† Output Enable to Output in Low Z
0
tOHZ† Output Disable to Output in High Z
0
20
0
25
ns
30
ns
tRCS
Read Command Setup Time
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
ns
tPU
§
Chip Enable to Power Up Time
0
0
0
ns
tPD
§
Chip Disable to Power Down Time
45
55
70
ns
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
Timing Waveform of Read Cycle No. 1 (ADDRESS controlled)(5,6)
Notes:
5.WE is HIGH for READ cycle.
6.CE/CS and OE are LOW for READ cycle.
Document # SRAM107 REV E
Page 4 of 14
P4C168/P4C168L, P4C169, P4C170
Timing Waveform of Read Cycle No. 2 (CE/CS controlled)(5,7)
Timing Waveform of Read Cycle No. 3—P4C170 Only (OE controlled)(5)
Notes:
7.ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, tAA must still be met.
8.Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
Document # SRAM107 REV E
9.Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 14
P4C168/P4C168L, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
Sym
Parameter
tWC
Write Cycle Time
12
15
18
20
30
ns
tCW
Chip Enable Time to End of Write
12
15
18
20
30
ns
tAW
Address Valid to End of Write
12
15
18
20
30
ns
tAS
Address Setup Time
0
0
0
0
0
ns
tWP
Write Pulse Width
12
15
18
20
30
ns
tAH
Address Hold Time
0
0
0
0
0
ns
tDW
Data Valid to End of Write
7
8
10
10
15
ns
tDH
Data Hold Time
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Min
Max
Min
Max
4
0
Min
Max
5
0
Min
6
0
Max
Min
7
0
Max
13
0
Unit
ns
ns
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-45
-55
-70
Sym
Parameter
tWC
Write Cycle Time
45
55
70
ns
tCW
Chip Enable Time to End of Write
40
50
60
ns
tAW
Address Valid to End of Write
40
50
60
ns
tAS
Address Setup Time
0
0
0
ns
tWP
Write Pulse Width
40
50
60
ns
tAH
Address Hold Time
0
0
0
ns
tDW
Data Valid to End of Write
20
20
25
ns
tDH
Data Hold Time
3
3
3
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Document # SRAM107 REV E
Min
Max
Min
20
0
Max
Min
25
0
Max
30
0
Unit
ns
ns
Page 6 of 14
P4C168/P4C168L, P4C169, P4C170
Timing Waveform of WRITE Cycle No. 1 (WE Controlled)(10)
Timing Waveform of Write Cycle No. 2 (CE/CS Controlled)(10)
Truth Tables
P4C168 (P4C169)
Mode
P4C170
CE (CS)
WE
Output
Mode
CE
WE
OE
Output
Standby (Deselect)
H
X
High Z
Deselect
H
X
X
High Z
Read
L
H
DOUT
Read
L
H
L
DOUT
Write
L
L
High Z
Output Inhibit
L
H
H
High Z
Write
L
L
X
High Z
Notes:
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
Document # SRAM107 REV E
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 7 of 14
P4C168/P4C168L, P4C169, P4C170
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long
high-inductance leads that cause supply bounce must be avoided by
bringing the VCC and ground planes directly up to the contactor fingers.
A high frequency capacitor of 0.01 µF is also required between VCC
and ground. To avoid signal reflections, proper termination must be
used; for example, a 50Ω test environment should be terminated into
a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
LCC PIN CONFIGURATION
LCC (L9)
Document # SRAM107 REV E
Page 8 of 14
P4C168/P4C168L, P4C169, P4C170
Ordering Information
SELECTION GUIDE
The P4C168/P4C168L, P4C169 and P4C170 are available in the following temperature, speed and package options.
Temperature
Range
Package
12
15
20
25
35
45
55
70
Commercial
Temperature
Plastic DIP
-12PC
-15PC
-20PC
-25PC
N/A
N/A
N/A
N/A
Plastic SOIC†
-12SC
-15SC
-20SC
-25SC
N/A
N/A
N/A
N/A
Plastic SOJ††
-12JC
-15JC
-20JC
-25JC
N/A
N/A
N/A
N/A
Military Temperature
(P4C168
Only)
Military Processed*
(P4C168
Only)
Speed
LCC
N/A
-15LM
-20LM
-25LM
-35LM
-45LM
-55LM
-70LM
CERDIP
N/A
-15DM
-20DM
-25DM
-35DM
-45DM
-55DM
-70DM
Side Brazed DIP
N/A
-15CM
-20CM
-25CM
-35CM
-45CM
-55CM
-70CM
CERPACK
N/A
-15FM
-20FM
-25FM
-35FM
-45FM
-55FM
-70FM
Solder Seal Flat Pack
N/A
-15FSM
-20FSM
-25FSM
-35FSM
-45FM
-55FM
-70FM
LCC
N/A
-15LMB
-20LMB
-25LMB
-35LMB
-45LMB
-55LMB
-70LMB
CERDIP
N/A
-15DMB
-20DMB
-25DMB
-35DMB
-45DMB
-55DMB
-70DMB
Side Brazed DIP
N/A
-15CMB
-20CMB
-25CMB
-35CMB
-45CMB
-55CMB
-70CMB
CERPACK
N/A
-15FMB
-20FMB
-25FMB
-35FMB
-45FMB
-55FMB
-70FMB
Solder Seal Flat Pack
N/A
-15FSMB
-20FSMB
-25FSMB
-35FSMB
-45FSMB
-55FSMB
-70FSMB
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM107 REV E
Page 9 of 14
P4C168/P4C168L, P4C169, P4C170
Pkg #
FS-2
# Pins
20
SOLDER SEAL FLAT PACKAGE
Symbol
Min
Max
A
0.045
0.115
b
0.015
0.022
b1
0.015
0.019
c
0.004
0.009
c1
0.004
0.006
D
-
0.540
E
0.245
0.300
E1
-
0.330
E2
0.130
-
E3
0.030
-
e
0.050 BSC
k
0.008
0.015
L
0.250
0.370
Q
0.026
0.045
S1
0.000
-
M
-
0.002
N
20
Pkg #
J2
# Pins
20 (300 mil)
Symbol
Min
Max
A
0.120
0.140
A1
0.080
-
b
0.014
0.020
C
0.008
0.013
D
0.496
0.512
e
SOJ SMALL OUTLINE IC PACKAGE
0.050 BSC
E
0.335
0.347
E1
0.292
0.300
E2
Q
0.267 BSC
0.025
-
Document # SRAM107 REV E
Page 10 of 14
P4C168/P4C168L, P4C169, P4C170
Pkg #
L9
# Pins
20
RECTANGULAR LEADLESS CHIP CARRIER
Symbol
Min
Max
A
0.060
0.075
A1
0.050
0.066
B1
0.022
0.028
D
0.280
0.305
D1
0.150 BSC
D2
0.075 BSC
D3
-
0.305
E
0.420
0.440
E1
0.250 BSC
E2
0.125 BSC
E3
-
0.440
e
0.050 BSC
h
0.020 REF
j
0.010 REF
L
0.045
0.055
L1
0.045
0.055
L2
0.075
0.098
ND
4
NE
6
Pkg #
P2
# Pins
20 (300 mil)
Symbol
Min
Max
A
-
0.210
A1
0.015
-
b
0.014
0.022
b2
0.045
0.070
C
0.008
0.014
D
0.980
1.060
E1
0.240
0.280
E
0.300
0.325
e
PLASTIC DUAL IN-LINE PACKAGE (P4C168, P4C169)
0.100 BSC
eB
-
0.430
L
0.115
0.150
0°
15°
α
Document # SRAM107 REV E
Page 11 of 14
P4C168/P4C168L, P4C169, P4C170
PLASTIC DUAL IN-LINE PACKAGE (P4C170)
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
Max
A
-
0.210
A1
0.015
-
b
0.014
0.022
b2
0.045
0.070
C
0.008
0.014
D
1.145
1.165
E1
0.240
0.280
E
0.300
0.325
e
0.100 BSC
eB
-
0.430
L
0.115
0.150
0°
15°
α
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S2
# Pins
20 (300 mil)
Symbol
Min
Max
A
0.093
0.104
A1
0.004
0.012
b2
0.013
0.020
C
0.009
0.012
D
0.496
0.511
e
0.050 BSC
E
0.291
0.299
H
0.394
0.419
h
0.010
0.029
L
0.016
0.050
0°
8°
α
Document # SRAM107 REV E
Page 12 of 14
P4C168/P4C168L, P4C169, P4C170
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D2
# Pins
20 (300 mil)
Symbol
Min
Max
A
-
0.200
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.060
E
0.220
0.310
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.070
S1
0.005
-
0°
15°
α
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg #
C6
# Pins
20 (300 mil)
Symbol
Min
Max
A
-
0.200
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.060
E
0.220
0.310
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.070
S1
0.005
-
S2
0.005
-
Document # SRAM107 REV E
Page 13 of 14
P4C168/P4C168L, P4C169, P4C170
REVISIONS
DOCUMENT NUMBER
SRAM 107
DOCUMENT TITLE
P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
REV
ISSUE DATE
ORIGINATOR
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
May-08
JDB
Added P4C168L, updated document formatting
C
Jun-08
JDB
Corrected Order Info drawing
D
Mar-09
JDB
Added C6 package drawing
E
Mar-10
JDB
Updated DC Electrical Characteristics table
Document # SRAM107 REV E
DESCRIPTION OF CHANGE
Page 14 of 14