P4C164

P4C164
ULTRA HIGH SPEED 8K X 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Common Data I/O
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Fully TTL Compatible Inputs and Outputs
Low Power Operation
Output Enable and Dual Chip Enable Control Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical Current (P4C164L Only)
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin Glass-sealed CERPACK
– 28-Pin Solder-sealed CERPACK
DESCRIPTION
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply. With battery
backup (P4C164L Only), data integrity is maintained with
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Functional Block Diagram
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C164 is available in 28-pin 300 mil DIP and SOJ,
28-pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin glass-sealed
CERPACK and solder-sealed flatpack.
Pin ConfigurationS
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOLDER-SEAL FLATPACK (FS-5), SOP (S6)
SEE PAGE 8 FOR LCC PIN CONFIGURATIONS
Document # SRAM115 REV H
Revised April 2011
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
Maximum Ratings(1)
Sym
Parameter
RECOMMENDED OPERATING CONDITIONS
Value
Unit
V
Grade(2)
Ambient Temp
GND
VCC
0°C to 70°C
0V
5.0V ± 10%
Industrial
-40°C to +85°C
0V
5.0V ± 10%
Military
-55°C to +125°C
0V
5.0V ± 10%
VCC
Power Supply Pin with
Respect to GND
-0.5 to +7
VTERM
Terminal Voltage with
Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5
V
TA
Operating Temperature
-55 to +125
°C
TBIAS
Temperature Under Bias
-55 to +125
°C
TSTG
Storage Temperature
-65 to +150
°C
Sym
Parameter
Commercial
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
PT
Power Dissipation
1.0
W
CIN
Input Capacitance
IOUT
DC Output Current
50
mA
COUT
Output Capacitance
Conditions
Typ
Unit
VIN=0V
5
pF
VOUT=0V
7
pF
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Sym Parameter
P4C164
Test Conditions
P4C164L
Unit
Min
Max
Min
Max
VCC + 0.5
2.2
VCC + 0.5
V
0.8
V
VCC + 0.5
V
0.2
V
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VCD
Input Clamp Diode Voltage
VCC = Min, IIN = -18 mA
-1.2
-1.2
V
VOL
Output Low Voltage (TTL Load)
IOL = +8 mA, VCC = Min
0.4
0.4
V
VOH
Output High Voltage (TTL Load)
IOH = -4 mA, VCC = Min
ILI
Input Leakage Current
VCC = Max,
VIN = GND to VCC
ILO
Output Leakage Current
VCC = Max, CE1 = VIH,
VOUT = GND to VCC
ISB
Standby Power Supply Current
(TTL Input Levels)
CE1 ≥ VIH or CE2 ≤ VIL,
ISB1
Standby Power Supply Current
(CMOS Input Levels)
(3)
VCC - 0.2
-0.5
VCC=Max, f=Max, Outputs Open
CE1 ≥ VHC or CE2 ≤ VLC,
(3)
0.8
VCC + 0.5
0.2
2.4
-0.5
(3)
VCC - 0.2
-0.5
(3)
2.4
V
MIL
-10
+10
-5
+5
IND/COM
-5
+5
N/A
N/A
MIL
-10
+10
-5
+5
IND/COM
-5
+5
N/A
N/A
MIL
—
40
—
40
IND/COM
—
30
—
N/A
MIL
—
25
—
1
VCC = Max, f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
µA
µA
mA
mA
IND/COM
—
15
—
N/A
N/A = Not applicable
Notes:
1.Stresses greater than those listed under Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to Maximum rating conditions for extended
periods may affect reliability.
Document # SRAM115 REV H
2.Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3.Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4.This parameter is sampled and not 100% tested.
Page 2
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym
Parameter
Temperature Range
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Unit
ICC
Dynamic
Operating
Current*
Commercial
200
180
170
160
155
150
145
N/A
130
125
mA
Industrial
N/A
190
180
170
160
155
150
N/A
145
140
mA
Military
N/A
N/A
180
170
160
155
150
145
145
145
mA
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH.
DATA RETENTION CHARACTERISTICS (P4C164L Only)
Sym
Parameter
Test Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
CE1 ≥ VCC -0.2V or
tCDR
Chip Deselect to Data Retention Time
CE2 ≤ 0.2V, VIN ≥ VCC -0.2V
tR†
Operation Recovery Time
or VIN ≤ 0.2V
Min
Typ* VCC=
2.0V
3.0V
Max VCC=
2.0V
3.0V
2.0
Unit
V
10
15
200
300
µA
0
ns
tRC§
ns
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETENTION WAVEFORM
Document # SRAM115 REV H
Page 3
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-8
Min
-10
Max
Max
10
Min
-15
Max
Max
Max
Address Access Time
8
10
12
15
20
ns
tAC
Chip Enable Access Time
8
10
12
15
20
ns
tOH
Output Hold from Address Change
3
3
3
3
3
ns
tLZ
Chip Enable to Output in Low Z
2
2
2
2
2
ns
tHZ
Chip Disable to Output in High Z
5
6
7
8
8
ns
tOE
Output Enable Low to Data Valid
5
6
7
9
10
ns
tOLZ
Output Enable Low to Low Z
tOHZ
Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
2
5
0
-25
Max
Max
35
Min
20
-70
Max
Min
-100
Max
Max
Address Access Time
25
35
45
70
100
ns
tAC
Chip Enable Access Time
25
35
45
70
100
ns
tOH
Output Hold from Address Change
3
3
3
3
3
ns
tLZ
Chip Enable to Output in Low Z
2
2
2
2
2
ns
tHZ
Chip Disable to Output in High Z
10
15
20
35
45
ns
tOE
Output Enable Low to Data Valid
13
18
20
35
45
ns
tOLZ
Output Enable Low to Low Z
tOHZ
Output Enable High to High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
12
0
2
15
0
20
2
20
0
20
100
Unit
tAA
2
70
Min
ns
Read Cycle Time
2
45
ns
15
-45
ns
tRC
Document # SRAM115 REV H
25
Min
9
0
12
-35
ns
9
0
10
ns
2
7
0
8
Min
2
6
0
20
Unit
tAA
2
15
Min
Read Cycle Time
2
12
Min
-20
tRC
Sym Parameter
8
Min
-12
2
35
0
25
ns
ns
45
0
35
ns
ns
45
ns
Page 4
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
5.WE is HIGH for READ cycle.
6.CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7.ADDRESS must be valid prior to, or coincident with CE1 transition LOW
and CE2 transition HIGH.
8.Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
Document # SRAM115 REV H
9.Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them.
Page 5
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym
Parameter
-8
Min
-10
Max
Min
-12
Max
Min
-15
Max
Min
-20
Max
Min
Max
Unit
tWC
Write Cycle Time
8
10
12
15
20
ns
tCW
Chip Enable Time to End of Write
6
7
8
12
15
ns
tAW
Address Valid to End of Write
7
8
10
12
15
ns
tAS
Address Setup Time
0
0
0
0
0
ns
tWP
Write Pulse Width
7
8
9
12
15
ns
tAH
Address Hold Time
0
0
0
0
0
ns
tDW
Data Valid to End of Write
6
7
8
9
11
ns
tDH
Data Hold Time
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Sym
Parameter
6
3
7
3
-25
Min
7
3
-35
Max
Min
7
3
-45
Max
Min
8
3
-70
Max
Min
ns
-100
Max
ns
Min
Max
Unit
tWC
Write Cycle Time
25
35
45
70
100
ns
tCW
Chip Enable Time to End of Write
18
25
33
50
70
ns
tAW
Address Valid to End of Write
18
25
33
50
70
ns
tAS
Address Setup Time
0
0
0
0
0
ns
tWP
Write Pulse Width
18
20
25
40
50
ns
tAH
Address Hold Time
0
0
0
0
0
ns
tDW
Data Valid to End of Write
13
15
20
30
40
ns
tDH
Data Hold Time
0
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tOW
Output Active from End of Write
Document # SRAM115 REV H
10
3
14
3
18
3
30
3
40
3
ns
ns
Page 6
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(11)
Timing Waveform of Write Cycle No. 2 (CE Controlled)(11)
Notes:
11. CE and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state
Document # SRAM115 REV H
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 7
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
Mode
CE1
CE2
OE
WE
Standby
H
X
X
X
High Z
Standby
Standby
X
L
X
X
High Z
Standby
DOUT Disabled
L
H
H
H
High Z
Active
Read
L
H
L
H
DOUT
Active
Write
L
H
X
L
High Z
Active
Figure 1. Output Load
I/O
Power
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C164/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
LCC PIN CONFIGURATIONS
LCC (L5)
"L" - STANDARD PIN-OUT
Document # SRAM115 REV H
LCC (L5)
"LS" - SPECIAL PIN-OUT
LCC (L6)
Page 8
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
ORDERING INFORMATION
Document # SRAM115 REV H
Page 9
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
SIDEBRAZED DUAL IN-LINE PACKAGE (300 mils)
C5
Pkg #
# Pins
28 (300 mil)
Symbol
Min
Max
A
-
0.225
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.485
E
0.240
0.310
eA
0.300 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.070
S1
0.005
-
S2
0.005
-
SIDEBRAZED DUAL IN-LINE PACKAGE (600 mils)
Pkg #
C5-1
# Pins
28 (600 mil)
Symbol
Min
Max
A
-
0.232
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.490
E
0.500
0.610
eA
0.600 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.060
S1
0.005
-
S2
0.005
-
Document # SRAM115 REV H
Page 10
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
CERDIP DUAL IN-LINE PACKAGE
D5-1
Pkg #
# Pins
28 (600 mil)
Symbol
Min
Max
A
-
0.232
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.490
E
0.500
0.610
eA
0.600 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.060
S1
0.005
-
α
0°
15°
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
Max
A
-
0.225
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D
-
1.485
E
0.240
0.310
eA
0.300 BSC
e
0.100 BSC
L
0.125
0.200
Q
0.015
0.060
S1
0.005
-
α
0°
15°
Document # SRAM115 REV H
Page 11
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
GLASS-SEALED CERAMIC FLATPACK
F4
Pkg #
# Pins
28
Symbol
Min
Max
A
0.060
0.090
b
0.015
0.022
c
0.004
0.009
D
-
0.730
E
0.330
0.380
e
0.050 BSC
k
0.005
0.018
L
0.250
0.370
Q
0.026
0.045
S
-
0.085
S1
0.005
-
Pkg #
FS-5
# Pins
28
SOLDER-SEAL CERAMIC FLATPACK
Symbol
Min
Max
A
0.090
0.130
b
0.015
0.022
c
0.004
0.009
D
0.740
E
0.380
0.420
E1
-
0.440
E2
0.180
-
E3
0.030
-
e
0.050 BSC
L
0.250
0.370
Q
0.026
0.045
S1
0.000
-
Document # SRAM115 REV H
Page 12
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
SOJ SMALL OUTLINE IC PACKAGE
J5
Pkg #
# Pins
28 (300 mil)
Symbol
Min
Max
A
0.120
0.148
A1
0.078
-
b
0.014
0.020
C
0.007
0.011
D
0.700
0.730
e
0.050 BSC
E
0.292
0.300
E1
0.335
0.347
E2
0.262
0.272
Q
0.025
-
Pkg #
L5
# Pins
28
RECTANGULAR LEADLESS CHIP CARRIER
Symbol
Min
Max
A
0.060
0.075
A1
0.050
0.065
B1
0.022
0.028
D
0.342
0.358
D1
0.200 BSC
D2
0.100 BSC
D3
-
0.358
E
0.540
0.560
E1
0.400 BSC
E2
0.200 BSC
E3
-
0.558
e
0.050 BSC
h
0.040 REF
j
0.020 REF
L
0.045
0.055
L1
0.045
0.055
L2
0.075
0.095
ND
5
NE
9
Document # SRAM115 REV H
Page 13
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
Pkg #
L6
# Pins
32
RECTANGULAR LEADLESS CHIP CARRIER
Symbol
Min
Max
A
0.060
0.075
A1
0.050
0.065
B1
0.022
0.028
D
0.442
0.458
D1
0.300 BSC
D2
0.150 BSC
D3
-
0.458
E
0.540
0.560
E1
0.400 BSC
E2
0.200 BSC
E3
-
0.558
e
0.050 BSC
h
0.040 REF
j
0.020 REF
L
0.045
0.055
L1
0.045
0.055
L2
0.075
0.095
ND
7
NE
9
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
Max
A
-
0.210
b
0.014
0.023
b2
0.045
0.070
C
0.008
0.014
D
1.345
1.400
E1
0.270
0.300
E
0.300
0.380
A1
e
PLASTIC DUAL IN-LINE PACKAGE (300 mils)
-
0.100 BSC
eB
-
0.430
L
0.115
0.150
α
0°
15°
Document # SRAM115 REV H
Page 14
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
PLASTIC DUAL IN-LINE PACKAGE (600 mils)
P6
Pkg #
# Pins
28 (600 mil)
Symbol
Min
Max
A
0.090
0.200
A1
0.000
0.070
b
0.014
0.020
b2
0.015
0.065
C
0.008
0.012
D
1.380
1.480
E1
0.485
0.550
E
0.600
0.625
e
eB
0.100 BSC
0.600 TYP
L
0.100
0.200
α
0°
15°
SOIC/SOP SMALL OUTLINE IC PACKAGE (SN)
Pkg #
S6
# Pins
28 (300 mil)
Symbol
Min
Max
A
0.090
0.110
A1
0.003
0.010
B
0.012
0.020
C
0.004
0.012
D
0.700
0.716
e
0.050 BSC
E
0.290
0.300
H
0.465
0.485
L
0.016
0.050
α
0°
9°
Document # SRAM115 REV H
Page 15
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER
SRAM115
DOCUMENT TITLE
P4C164 ULTRA HIGH SPEED 8Kx8 STATIC CMOS RAM
REV
ISSUE DATE
ORIGINATOR
OR
1997
DAB
New Data Sheet
A
Oct-2005
JDB
Changed logo to Pyramid
B
Jun-2006
JDB
Added 28-pin ceramic DIP
C
Aug-2006
JDB
Added Lead-Free designation
D
Aug-2006
JDB
Added "LS" - Special Pin-Out
E
Aug-2006
JDB
Updated SOJ package information
F
Jun-2007
JDB
Corrected SOP package details
G
Sep-2010
JDB
Added P4C164L for non-military temp. Format update.
H
Apr-2011
JDB
Added 28-pin solder-seal flatpack
Document # SRAM115 REV H
DESCRIPTION OF CHANGE
Page 16