PI3EQX4951B 3.3V, 1-port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Features Description ÎÎSATA2 i, m; external SATA2 Pericom Semiconductor’s PI3EQX4951B is a low power, signal ReDriver™. The device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI3EQX4951B supports two 100Ω Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user’s platform. ÎÎTwo 3.0Gbps differential signal pairs ÎÎIndependent Digital Output Emphasis Control ÎÎ100Ω Differential CML I/O’s ÎÎInput signal level detect and squelch for each channel ÎÎOOB Support ÎÎEnhanced Mode Features: The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver. àà Adjustable Receiver Equalization àà Independent Analog Output Swing Adjustment àà Independent Analog Output Emphasis Control àà Independent Channel Power Down Control A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independently. When the channels are enabled (x_EN=1) and operating, that channels input signal level (on xI+/-) determines whether the output is active. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. ÎÎLow Power (220mW per Channel) ÎÎStand-by Mode – Power Down State ÎÎSupply Voltage: 3.3V ÎÎPackaging (Pb-free & Green): In addition to signal conditioning, when EN = 0, the device enters a low power standby mode. àà 20-TQFN (4x4mm) Block Diagram 1 15 AI- 2 3 14 13 GND VDD 6 7 CML xO+ 8 9 10 VDD A_EM A_EQ MODE VDD xO- - Repeated 2 times EMx AI+ 1 AI- 2 3 A_EN# x_EQ x_EM BOBO+ 4 5 20 19 18 17 16 GND 6 7 8 9 10 15 14 13 12 AO+ AOB_EN# BI- 11 BI+ VDD EN B_EQ B_EM VDD Control Circuit GND BIBI+ Enhanced Mode (MODE = 1) Limiting Amp xl- 12 11 AO+ AO- VDD 5 A_EM 4 EN B_EM GND BOBO+ xl+ Power Management VDD AI+ CML X_EN# EN GND 20 19 18 17 16 Signal Detection Equalizer GND VDD Standard Mode (MODE = 0) MODE Pin Diagram (Top Side View) 10-0248 1 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Pin Description Standard Enhanced Mode Pin Mode Pin # # Pin Name Type Description Output emphasis adjustment for channel A. 9 19 A_EM Input àà When in Standard Mode (MODE= 0) digital control is enabled, and a 100KΩ pull-up resistor is enabled on A_EM. àà When in Enhanced Mode (MODE= 1) analog resistive adjustment of emphasis is enabled. Refer to Configuration Tables and System Implementation diagrams for design guidelines. — 3 A_EN# Input Channel A Enable, is active only when in Enhanced Mode (MODE=1). Low is normal operation. High is power down mode. Has internal 100KΩ pull-down resistor. — 18 A_EQ Input Channel A Equalization adjustment is active only in Enhanced Mode (MODE = 1). With internal 100KΩ pull-up to VDD. Refer to Enhanced Mode Configuration Table and System Implementation diagram for design guidelines. 1 2 1 2 AI+ AI- Input CML input forward channel A with internal 50Ω pull-up resistors connected to VBIAS (100Ω differential). 14 15 14 15 AOAO+ Output CML output channel A with internal 50Ω pull-up resistors connected to VBIAS (100Ω differential). Output emphasis adjustment for channel B. àà When in Standard Mode (MODE= 0) digital control is enabled, and a 100KΩ pull-up resistor is enabled on A_EM. àà When in Enhanced Mode (MODE= 1) analog resistive adjustment of emphasis is enabled. Refer to Configuration Tables and System Implementation diagrams for design guidelines. 8 9 B_EM Input — 13 B_EN# Input Channel B Enable, is active only when in Enhanced Mode (MODE=1). Low is normal operation. High is power down mode. Has internal 100KΩ pull-down resistor. — 8 B_EQ Input Channel A Equalization adjustment, is active only in Enhanced Mode (MODE = 1). With internal 100KΩ pull-up to VDD. Refer to Enhanced Mode Configuration Table and System Implementation diagram for design guidelines. 11 12 11 12 BI+ BI- Input CML input return channel B with internal 50Ω pull-up, resistor connected to VBIAS (100Ω differential). 4 5 4 5 BOBO+ Output Positive CML output channel B with internal 50Ω pull-up resistor connected to VBIAS (100Ω differential). 7 7 EN Input Chip Enable "High" provides normal operation. "Low" for power down mode. With internal 100KΩ pull-up resistor. 3, 13, 18, 19, Center Pad Center Pad GND GND Supply ground. 6,10, 16, 20 6, 10, 16, 20 VDD Power 3.3V supply voltage ± 10% Input MODE selects Enhanced Mode operation and pin function when high. When MODE is low, Standard Mode operation is selected. With internal 100KΩ pullup resistor to VDD. See Configuration tables for use information. 17 17 10-0248 MODE 2 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Configuration Table (Standard Mode) Input B Equalization @ f=1.5GHz Input A Equalization @ f=1.5GHz EN MODE B_EM(1) Output B A_EM (1) Emphasis Output A Emphasis 0 X X X Disable Disable Disable Disable 1 0 0 0 0dB 0dB 2.5dB 2.5dB 1 0 0 1 0dB 3.0dB 2.5dB 2.5dB 1 0 1 0 3.0dB 0dB 2.5dB 2.5dB 1 0 1 1 3.0dB 3.0dB 2.5dB 2.5dB Note: 1. Refer to Standard Mode Implementation Diagram Configuration Table (Enhanced Mode) EN MODE x_EN# x_EQ Input X Equalization 0 X X X n/a X n/a Chip Power Down 1 1 1 X n/a X n/a Chip enabled, Channel x disabled 1 1 0 0 2.5dB 1.1K to 15K resistor Resistor Controlled, 6dB to 0dB (1) Chip and channel enabled, low input equalization 1 1 0 1 6.5dB 1.1K to 15K resistor Resistor Controlled, 6dB to 0dB (1) Chip and channel enabled, high input equalization x_EM Output X Emphasis Function Note: 1. Refer to Enhanced Mode Implementation Diagram 10-0248 3 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature.................................................................–65°C to +150°C Supply Voltage to Ground Potential.........................................–0.5V to +4.6V DC SIG Voltage..................................................................–0.5V to VDD +0.5V Current Output ..................................................................... –25mA to +25mA Power Dissipation Continuous.............................................................. 500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Temperature......................................................................0 to +70°C ESD, Human Body Model.....................................................–6kV to +6kV AC/DC Electrical Characteristics Symbol Parameter VDD Power Supply Voltage PSTANDBY Supply Power, Standby PIDLE Supply Power, Idle PACTIVE Supply Power, Active IDD-STANDBY Supply Current Standby IDD-IDLE Supply Current Idle IDD-ACTIVE Supply Current Active tPD Latency Conditions Min. Typ. 3.0 EN = 0 EN = 1, x_EN# = 0 Max. Units 3.6 V 1.5 mW 235 DIFFP-P < V TH-SD EN = 1, x_EN# = 0 mW 440 DIFFP-P ≥ V TH-SD EN = 0 mW 0.4 EN = 1, x_EN# = 0, VRX-DIF- 70 FP-P < V TH-SD EN = 1, x_EN# = 0, VRX-DIF- mA 120 FP-P ≥ V TH-SD From input to output 2.0 ns CML Receiver Input ZRX-DC DC Input Impedance 40 50 60 ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 VRX-DIFFP-P Differential Input Peak-topeak Voltage 0.2 VRX-CM-ACP AC Peak Common Mode Input Voltage VTH-SD Signal detect Threshold EN = 1, x_EN# = 0 50 Ω 1.6 V 150 mV 200 (1) mVppd (continued) Note: Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011 10-0248 4 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration AC/DC Electrical Characteristics (CML Receiver Input continued) Symbol RLdd11_RX RLcc11_RX RLdc11_RX Parameter RX differential mode return loss RX common mode return loss RX impedance balance Conditions Min. 75MHz-300MHz 18 300MHz-600MHz 14 600MHz-1.2GHz 10 1.2GHz-2.4GHz 8 2.4GHz-3.0GHz 3 3.0 GHz-5.0GHz 1 150MHz – 300MHz 5 300MHZ – 600MHz 5 600MHz – 1.2GHz 2 1.2GHz – 2.4GHz 2 2.4GHz – 3.0GHz 1 3.0GHz – 5.0GHz 1 150MHz – 300MHz 30 300MHz – 600MHz 30 600MHz – 1.2GHz 20 1.2GHz – 2.4GHz 10 2.4GHz – 3.0GHz 4 3.0GHz – 5.0GHz 4 Typ. Max. Units dB dB dB Equalization TJ Total Jitter Measured at 3Gbps/500 0.37 UI DJ Deterministic Jitter Measured at 3Gbps/500 0.19 UI 120 Ω CML Transmitter Output (100Ω differential)1 ZTX-DIFF-DC DC Differential TX Impedance VTX-DIFFP-P Differential Peak-to-peak Output Voltage VTX-DIFFP-P = 2 * | VTX-D+ VTX-D- | 500 600 mV VTX-C Common-Mode Voltage | VTX-D+ + VTX-D-|/2 1 1.8 V tF, tR Transition Time 20% to 80%(1) 50 150 ps tF-tR Mis-match Transition Time 3G only; HFTP, MFTP 20 % Vamp_bal TX amplitude imbalance 3G only; HFTP, MFTP 10 % Tskew TX differential skew 1.5G and 3G; HFTP, MFTP 20 ps Vcm_ac TX AC common mode voltage 3G only; MFTP 50 mVpp VcmOOB OOB common mode delta voltage 50 mV VdiffOOB OOB differential delta voltage 25 mV 6 dB 80 100 VTX-Pre-Ratio-max Max TX Pre-emphasis Level Note: (continued) 1. Recommended output coupling capacitor is 4.7nF to 12nF (on each output) 10-0248 5 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration AC/DC Electrical Characteristics (CML Transmitter Output continued) Symbol RLdd11_TX RLcc11_TX RLdc11_TX Parameter TX differential mode return loss TX common mode return loss TX impedance balance Conditions Min. 150MHz – 300MHz 14 300MHz – 600MHz 8 600MHz – 1.2GHz 6 1.2GHz – 2.4GHz 6 2.4GHz – 3.0GHz 3 3.0 GHz – 5.0GHz 1 150MHz – 300MHz 5 300MHz – 600MHz 5 600MHz – 1.2GHz 2 1.2GHz – 2.4GHz 2 2.4GHz – 3.0GHz 1 3.0 GHz – 5.0GHz 1 150MHz – 300MHz 30 300MHz – 600MHz 20 600MHz – 1.2GHz 10 1.2GHz – 2.4GHz 10 2.4GHz – 3.0GHz 4 3.0 GHz – 5.0GHz 4 Typ. Max. Units dB dB dB LVCMOS Control Pins 0.65 × VDD VIH Input High Voltage VIL Input Low Voltage 0.35 × VDD IIH Input High Current 100 IIL Input Low Current 100 10-0248 6 www.pericom.com PS9016B V µA 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration FR4 Signal Source A B C D.U.T. SmA Connector SmA Connector In Out 30IN Test Condition Referenced in the Electrical Characteristic Table Pre-emphasis = 20 .Log(VDIFF-PRE/VDIFF) VD+ Common Mode Voltage VCM VDIFF VD+ VD- VDIFFp-p VCM V_D+ - V_D- 0V VDIFF-PRE VDIFF VD- VDIFFp-p 1stTBIT Definition of Differential Voltage and Differential Voltage Peak-to-Peak 2nd +TBIT(s) Definition of Pre-emphasis xO+ xI+ EQ xO- xIx_EM Recommended coupling capacitors are 4.7nF MODE Emphasis Setting for PCB Trace or Cable Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable R3 < 6 inch < 36 inch 0 > 6 inch > 36 inch open R3 Standard Mode Implementation Diagram 10-0248 7 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration VDD Equalization Setting for PCB Trace or Cable J1 MODE x_EQ Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable J1 < 6 inch < 36 inch 0 > 6 inch > 36 inch open xO+ xI+ EQ xIx_EM xORecommended coupling capacitors are 4.7nF REM 1.0K<REM<15K REM sets output emphasis level (See table) REM Suggested Inital Values for PCB Trace or Cable Output T/S/T 4/8/4 mil FR4 PCB trace Output AWG 28 SATA Cable Pre-emphasis dB REM < 3 inch < 18 inch 0 15k 4 inch 30 inch 1.5dB 7.5k 6 inch 30 inch 2.0dB 6.2k 8 inch 40 inch 2.5dB 5.1k 12 inch 60 inch 3.5dB 3.3k 16 inch 48 inch 4.5dB 2.2k 24 inch 48 inch 6.0dB 1.1k Enhanced Mode Implementation Diagram Notes: 1. Pericom PI3EQX4951 control pins are with internal 100k pull up R. 2. The R6, R10, R11 are use in standard mode. Application Schematic 10-0248 8 www.pericom.com PS9016B 12/09/10 PI3EQX4951B 3.3V, 1-Port, SATA2 i/m ReDriver™ with Analog/Digital Configuration Packaging Mechanical: 20-contact TQFN (ZD) 1 DATE: 09/11/08 DESCRIPTION: 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD20 REVISION: -- DOCUMENT CONTROL #: PD-2084 08-0456 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Number Package Code Package Description PI3EQX4951BZDE ZD Pb-Free and Green 20-contact TQFN (4x4mm) Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • All trademarks are property of their respective owners. 10-0248 9 www.pericom.com PS9016B 12/09/10