PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differential 3.3V, 2.5V LVPECL Fanout Buffer Features Description ÎÎ6 LVPECL outputs The PI6C4911506-06 is a high performance LVPECL fanout buffer device that accepts crystal, single ended and differential inputs. The part supports up to 1.5GHz frequency. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. ÎÎUp to 1.5GHz output frequency ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) ÎÎSelectable reference inputs support either single-ended or differential or Xtal ÎÎLow skew between outputs within banks (<40ps) ÎÎLow delay from input to output (Tpd typ. 1.5ns) ÎÎSeparate Input output supply voltage for level shifting ÎÎ2.5V / 3.3V power supply ÎÎIndustrial temperature support ÎÎTSSOP-24 package Block Diagram Pin Configuration (24-Pin TSSOP) Pullup CLK_EN nQ2 1 24 Q3 Q2 2 23 nQ3 VDD 3 22 VDD nQ1 4 21 Q4 Q1 5 20 nQ4 Q0 VEE 6 19 VDD nQ0 nQ0 7 18 Q5 Q0 8 17 nQ5 CLK_SEL0 9 16 CLK_SEL1 XTAL_IN 10 15 nCLK1 XTAL_OUT 11 14 CLK1 CLK_EN 12 13 CLK0 D Q CLK_SEL0 Pulldown CLK_SEL1 Pulldown LE XTAL_IN OSC 00 XTAL_OUT CLK0 Pulldown 01 Q5 CLK1 Pulldown nCLK1 Pullup 12-0290 6 LVPECL Outputs 1X nQ5 1 www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer Pinout Table Pin # Pin Name 1, 2 nQ2, Q2 Output Differential output pair. LVPECL interface levels 3, 19, 22 VDD Power Power supply pins 4, 5 nQ1, Q1 Output Differential output pair. LVPECL interface levels 6 VEE Power Negative supply pin 7, 8 nQ0, Q0 Output Differential output pair. LVPECL interface levels 9, 16 CLK_SEL0, CLK_SEL1 10 XTAL_IN 11 XTAL_OUT Type Input Description Pulldown Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B Input Parallel resonant crystal interface. XTAL_IN is the input Output Parallel resonant crystal interface. XTAL_OUT is the output Synchronizing clock enable. When HIGH, clock outputs follow clock input 12 CLK_EN Input Pullup When LOW, the outputs are disabled LVCMOS / LVTTL interface levels. See Table 3A 13 CLK0 Input Pulldown LVCMOS/LVTTL clock input 14 CLK1 Input Pulldown Non-inverting differential clock input 15 nCLK1 Input 17, 18 nQ5, Q5 Output Differential output pair. LVPECL interface levels 20, 21 nQ4, Q4 Output Differential output pair. LVPECL interface levels 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels Pullup Inverting differential clock input Note: 1. Pullup and Pulldown refer to internal input resistors. See Table "Pin Characteristics" on page 6, for typical values. 12-0290 2 www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Storage temperature....................................................-55 to +150ºC Supply Voltage to Ground Potential (VDD)........... -0.5 to +4.6V Inputs (Referenced to GND)............................-0.5 to VDD+0.5V Clock Output (Referenced to GND)...............-0.5 to VDD+0.5V Soldering Temperature (Max of 10 seconds).....................+260ºC Latch up...................................................................................200mA ESD Protection (Input)................................... 2000 V min (HBM) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Supply Characteristics and Operating Conditions Symbol Parameter Test Condition VDD Core Supply Voltage IDD Core Power Supply Current TA Ambient Operating Temperature Min. Typ. Max. Units 3.135 3.465 V 2.375 2.625 V 150 mA 85 °C Outputs unloaded -40 LVCMOS / LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage Test Condition VIL Input Low Voltage IIH CLK0, Input High Current CLK_SEL0:1 CLK_EN IIL Input Low Current 12-0290 Min. Typ. Max. VDD = 3.3V 2 VDD+0.3 VDD = 2.5V 1.7 VDD+0.3 VDD = 3.3V -0.3 0.8 VDD = 2.5V -0.3 0.7 VDD = VIN = 3.465V or 2.625V 150 VDD = VIN = 3.465V or 2.625V 20 CLK0, CLK_SEL0:1 VDD = 3.465V or 2.625V, VIN = 0V -15 CLK_EN VDD = 3.465V or 2.625V, VIN = 0V -150 3 Units V μA www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer Differential DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCMR Common Mode Input Voltage 1,2 VPP Peak-to-Peak Input Voltage IIL Input Low Current Input High Current IIH Test Condition Min. Typ. Max. VEE+0.5 VDD-0.85 0.15 1.3 1 nCLK1 VDD = 3.465V or 2.625V, VIN = 0V -150 CLK1 VDD = 3.465V or 2.625V, VIN = 0V -5 nCLK1 VDD = VIN = 3.465V or 2.625V 5 CLK1 VDD = VIN = 3.465V 150 Units V μA Note: 1. VIL should not be less than -0.3V. 2. Common mode voltage is defined as VCMR . DC Electrical Specifications- LVPECL Outputs Parameter Description VOH Output High voltage VOL Output Low voltage Conditions Min. Typ. Max. VDD =3.3V 2.1 2.6 VDD =2.5V 1.3 1.6 VDD =3.3V 1.3 1.8 VDD =2.5V 0.5 0.8 Units V V Crystal Characteristics Parameter Test Condition Min. Max. Units 40 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation Typ. Fundamental Frequency 12 Note: 1. Characterized using an 18pF parallel resonant crystal. 12-0290 4 www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer AC Characteristics, VDD = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay 1A, 1B Test Condition Min. Typ. Max. CLK1/nCLK1 1500 CLK0 300 Units MHz 1.5 ns 0.03 ps CLK1/nCLK1, 156.25MHz, tjit Buffer Additive Jitter, RMS tsk(o) Output Skew tsk(pp) Part-to-Part Skew 3 tR / tP Output Rise/Fall Time odc Output Duty Cycle Integration Range: 12kHz - 20MHz 55 ps 450 ps 120 350 ps 48 52 % 2 20% to 80% AC Characteristics, VDD = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay 1A, 1B Test Condition Min. Typ. Max. CLK1/nCLK1 1500 CLK0 300 Units MHz 1.5 ns 0.03 ps CLK1/nCLK1, 156.25MHz, tjit Buffer Additive Jitter, RMS Integration Range: 12kHz - 20MHz tsk(o) Output Skew 2 tsk(pp) Part-to-Part Skew tR / tP Output Rise/Fall Time odc Output Duty Cycle 55 ps 450 ps 120 350 ps 48 52 % 3 20% to 80% Note: 1A. Measured from the differential input crossing point to the differential output crossing point. 1B. Measured from VDD /2 input crossing point to the differential output crossing point. 2. Defined as skew between outputs at the same supply voltage and with equal load conditions. 3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. 12-0290 5 www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer Pin Characteristics Symbol Parameter Conditions CIN Input Capacitance RPULLDOWN Input Pulldown Resistor RPULLUP Input Pulup Resistor Min Typ Max Units 4 pF CLK0, CLK1 51 kΩ nCLK1 51 kΩ Control Input Function Table Inputs Outputs CLK_EN CLK_SEL1 CLK_SEL0 Selected Source Q0:Q5 nQ0:nQ5 0 0 0 XTAL Low High 0 0 1 CLK0 Low High 0 1 X CLK1/ nCLK1 Low High 1 0 0 XTAL Enabled Enabled 1 0 1 CLK0 Enabled Enabled 1 1 X CLK1/ nCLK1 Enabled Enabled Configuration Test Load Board Termination for LVPECL VDD ZO = 50Ω TLA L = 0 ~ 10in Device 100Ω TLA ZO = 50Ω 150Ω 12-0290 150Ω 6 www.pericom.com PI6C4911506-06 RevA 11/02/2012 PI6C4911506-06 Low Skew, 1-To-6, Crystal/LVCMOS/Differantial 3.3V, 2.5V LVPECL Fanout Buffer Packaging Mechanical: 24-Contact TSSOP (L) DATE: 05/03/12 DESCRIPTION: 24-pin, 173mil Wide TSSOP Notes: 1. Refer JEDEC: MO-153F/AD 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr 12-0374 PACKAGE CODE: L DOCUMENT CONTROL #: PD-1312 REVISION: F Ordering Code Package Code Package Type Operating Temperature PI6C4911506-06LIE L Pb-free & Green, 24-pin TSSOP -40°C to 85°C Note: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. “E” denotes Pb-free and Green 3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging 12-0290 7 www.pericom.com PI6C4911506-06 RevA 11/02/2012