PI6C49X0210

PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Features
•
•
•
•
•
•
•
•
•
•
Applications
10 single-ended outputs Fanout Buffer
Up to 200MHz output frequency
Ultra low output additive jitter = 0.05ps (typ.)
Selectable reference inputs support Xtal (10~50MHz), singleended and differential
Low output skew ~ 50ps (typ.)
Propagation delay ~2ns ([email protected])
2.5V / 3.3V operation
User configurable output VDD in different banks:
– Mixed 3.3V core/2.5V output operating supply
– Mixed 3.3V core/1.8V output operating supply
– Mixed 3.3V core/1.5V output operating supply
– Mixed 2.5V core/1.8V output operating supply
– Mixed 2.5V core/1.5V output operating supply
Industrial temperature range: –40°C to +85°C
Packaging (Pb-free & Green available):
– 32-pin TQFN (ZH)
• Networking systems including switches and Routers
• High frequency backplane based computing and telecom platforms
Description
The PI6C49X0210 is a high performance multi-voltage 10-outputs
CMOS Fanout Buffer with internal Crystal Oscillator. The XTAL
range is from 10MHz to 50MHz. The device has a wide range of
operating voltages of 2.5V and 3.3V. The device also provides user
selectable output VDD option, which provides excellent flexibilities
to users. This device is ideal for systems that need to distribute low
jitter clock signals to multiple destinations.
GNDO
ENABLE
IN_SEL0
IN_SEL1
IN1
IN1#
GND
GNDO
31
30
29
28
27
26
25
15
16
IN0#
GNDO
CLK5
GND
CLK6
17
14
18
8
13
19
7
IN0
20
6
12
5
CLK8
GNDO
CLK7
V DDO
XIN
21
XOUT
22
4
11
3
10
23
9
24
2
GNDO
13-0169
CLK9
V DDO
1
VDD
CLK0
V DDO
CLK1
GNDO
CLK2
V DDO
CLK3
CLK4
Block Diagram
32
Pin Configuration
1
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Pin Description
Pin#
Pin Name
Type
Description
1, 3, 5, 7, 8, 17,
18, 20, 22, 24
CLK0~9
Output
Clock Outputs
2, 6, 19, 23
VDDO
Output Power Supplier
15, 26
GND
Power
Power
4, 9, 16, 21, 25,
32
GNDO
Power
Core Ground
10
VDD
Core Power Supplier
11
XIN
12
XOUT
13
IN0
Power
Input
Output
Input
Pull-down
REF0 Diff or Single End
14
IN0#
Input
Pull-up/ Pulldown
REF0 Diff, When IN0 is single end ref
clock0 and IN0# internal bias as Vdd/2
27
IN1#
Input
Pull-up/ Pulldown
REF1 Diff, When IN1 is single end ref
clock1 and IN1# internal bias as Vdd/2
28
IN1
Input
Pull-down
REF1 Diff or Single End
30, 29
IN_SEL[0:1]
Input
Pull-down
IN-SEL[0:1] select XTAL, REF1 and REF0
input
31
ENABLE
Input
Output Ground
Crystal interface
Crystal interface
Active High Output Enable
Input Mode Selection Logic
IN_SEL0
IN_SEL1
Selected Input
1
1
XTAL
0
1
XTAL
1
0
REF1 Diff or Single End
0
0
REF0 Diff or Single End
Input/Output Operation State
Input State
Output State
IN[0:1], IN[0:1]# open
Logic Low
IN[0:1], IN[0:1]# both to ground
Logic Low
IN[0:1]=High, IN[0:1]# =Low
Logic High
IN[0:1]=Low, IN[0:1]# =High
Logic Low
Output Mode Selection
13-0169
ENABLE
Output CLK0~9
GND
High-impedance
VDD
Enabled
2
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Power Supply DC Characteristics (VDD/VDDO = 3.3V ± 5%, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
ENABLE = '0'
32
mA
IDDO
Output Supply Current
ENABLE = '0'
1
mA
Power Supply DC Characteristics (VDD/VDDO = 2.5V ± 5%, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
ENABLE = '0'
15
mA
IDDO
Output Supply Current
ENABLE = '0'
0.7
mA
Power Supply DC Characteristics (VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
ENABLE = '0'
29
mA
IDDO
Output Supply Current
ENABLE = '0'
0.6
mA
Power Supply DC Characteristics (VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
3.135
3.3
3.465
V
1.6
1.8
2.0
V
VDD
Core Supply Voltage
VDDO
Output Supply Voltage
IDD
Power Supply Current
ENABLE = '0'
29
mA
IDDO
Output Supply Current
ENABLE = '0'
0.4
mA
Power Supply DC Characteristics (VDD = 3.3V ± 5%, VDDO = 1.5V ± 0.15V, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
1.35
1.5
1.65
V
IDD
Power Supply Current
ENABLE = '0'
29
mA
IDDO
Output Supply Current
ENABLE = '0'
0.3
mA
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Power Supply DC Characteristics (VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
2.375
2.5
2.625
V
1.6
1.8
2.0
V
VDD
Core Supply Voltage
VDDO
Output Supply Voltage
IDD
Power Supply Current
ENABLE = '0'
13
mA
IDDO
Output Supply Current
ENABLE = '0'
0.4
mA
Power Supply DC Characteristics (VDD = 2.5V ± 5%, VDDO = 1.5V ± 0.15V, TA = -40°C to 85°C)
Symbols
Parameters
Test Conditions
Min.
Typ
Max.
Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
1.35
1.5
1.65
V
IDD
Power Supply Current
ENABLE = '0'
13
mA
IDDO
Output Supply Current
ENABLE = '0'
0.3
mA
13-0169
4
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Single-Ended DC Characteristics (TA = -40°C to 85°C)
Symbols
Parameters
VIH
Input High Voltage
VIL
Input Low Voltage
Test Conditions
Output High Voltage
(IOH = -12mA)
Output Low Voltage
(IOH = 8mA)
VOL
Output Low Voltage
(IOL = 12mA)
ROUT
Output Impedence
Max.
Units
2
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0.8
V
-0.3
0.7
V
VDD = 2.5V ± 5%
(1)
2.6
V
2
V
1.8
V
VDDO = 1.8V ±
0.2V(1)
1.5
V
VDDO = 1.5V ±
0.15V(1)
1.0
V
VDDO = 3.3V ± 5% (1)
3.0
V
VDDO = 2.5V ± 5%
2.0
V
VDDO = 1.8V ±
0.2V(1)
1.5
V
VDDO = 1.5V ±
0.15V(1)
1.0
V
VDDO = 2.5V ± 5%
VOH
Typ
VDD = 3.3V ± 5%
VDDO = 3.3V ± 5%
Output High Voltage
(IOH = -8mA)
Min.
VDDO = 2.5V ± 5%
(1)
VDD = 3.3V ± 5% (1)
0.5
V
VDDO = 2.5V ± 5%
0.5
V
VDDO
(1)
= 1.8V ± 0.2V
0.4
V
VDDO
(1)
= 1.5V ± 0.15V
0.35
V
VDDO = 3.3V ± 5% (1)
0.25
V
VDDO = 2.5V ± 5%
0.25
V
VDDO
(1)
= 1.8V ± 0.2V
0.3
V
VDDO
(1)
= 1.5V ± 0.15V
0.35
V
10
Ω
20
Ω
VDDO = 3.3V ± 5%
7
VDDO = 1.8V ± 5%
12
17
Notes:
1. Outputs terminated with 50Ω to VDDO /2. See Parameter Measurement section, "Load Test Circuit" diagrams.
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Differential input DC Characteristics (TA = -40°C to 85°C)
Symbols
IIH
Parameters
Input High
Current
Typ
Max.
Units
100
uA
VDD = VIN =3.465V
or 2.625V
IN[0:1]
VDD = 3.465V or
2.625V VIN = 0V
-1
uA
IN[0:1]#
VDD = 3.465V or
2.625V VIN = 0V
-50
uA
VDD = 3.3V
0.25
1.3
VDD = 2.5V
0.25
1.3
VDD = 3.3V
0.5
VDD -1.35V
VDD = 2.5V
0.5
VDD -0.85V
Input Low
Current
VPP
Peak-to-Peak Input Voltage (1)
Common Mode Input Voltage
(1,2)
Notes:
1. VIL should not be less than -0.3V.
2. Common mode voltage is defined as VIH.
13-0169
Min.
IN[0:1],
IN[0:1]#
IIL
VCMR
Test Conditions
6
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PI6C49X0210 Rev F
V
V
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
3.3V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.)
Storage Temperature............................................................–65°C to +150°C
VDD, VDDO Voltage................................................................–0.5V to +3.6V
Output Voltage (max. 4.6V)........................................... –0.5V to VDD+0.5V
Input Voltage (max 4.6V)............................................... –0.5V to VDD+0.5V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Characteristics (Over Operating Range: VDD/VDDO = 3.3V ± 5%, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz crystal @
(Integration Range:
100Hz-1MHz)
0.05
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz reference
input @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
800
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
64
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.)
Storage Temperature............................................................–65°C to +150°C
VDD, VDDO Voltage................................................................–0.5V to +3.6V
Output Voltage (max. 4.6V)........................................... –0.5V to VDD+0.5V
Input Voltage (max 4.6V)............................................... –0.5V to VDD+0.5V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Characteristics (Over Operating Range: VDD/VDDO = 2.5V ± 5%, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
fMAX
Using External Crystal
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.06
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
800
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
63
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
AC Characteristics (Over Operating Range: VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.05
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
800
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
62
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
9
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
AC Characteristics (Over Operating Range: VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.06
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
900
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
58
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
AC Characteristics (Over Operating Range: VDD = 3.3V ± 5%, VDDO = 1.5V ± 0.15V, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.07
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
900
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
53
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
AC Characteristics (Over Operating Range: VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.06
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
900
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
59
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
12
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
AC Characteristics (Over Operating Range: VDD = 2.5V ± 5%, VDDO = 1.5V ± 0.15V, TA = -40° to 85°C)
Parameters
Test Conditions(1)
Description
Using External Crystal
fMAX
Output Frequency Using External Clock
Source (2)
odc
Output Duty Cycle
125MHz
Min.
Typ
Max.
Units
10
50
DC
200
45
55
%
80
ps
(3)
MHz
tsk(o)
Output Skew
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integration Range: 100Hz1MHz)
0.08
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integration Range: 12kHz20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
tEN
tDIS
MUXisolation
20% to 80%
200
900
ps
Output Enable Time
ENABLE
5
cycles
Output Disable Time
ENABLE
5
cycles
(4)
(4)
MUX Isolation
155.52MHz
55
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
13-0169
13
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Waveforms
Output to Output Skew – tsk(O)
Duty Cycle – tDC
VOH
BCLKx
50%
VOL
tSK(O)
VOH
tSK(O)
BCLKy
tPW
VOH
VDDO/2
VOL
tPERIOD
VDDO/2
tDC = (tPW / tPERIOD ) x 100%
VOL
ENABLE Timing Diagram
BCLK[0:7]
ENABLE
AC Test Circuit Load
[VDD - VDDO/2]
Note:
VDD/VDDO = 1.8V ± 0.2V,
2.5V ± 5%,
3.3V ± 5%
[+VDDO/2]
VDD
VDDO
Z = 50-Ohm
GND
Scope
50Ohm
[-VDDO/2]
Crystal Characteristic (link to "http://www.pericom.com/products/timing/crystals/index.php" for more detailed and different size crystal specifications)
Parameters
Description
Min
OSCmode
Mode of Oscillation
FREQ
Frequency
10
ESR(1)
Equivalent Series Resistance
30
Cload
Load Capacitance
Cshunt
Shunt Capacitance
Typ
Max.
Units
50
MHz
50
Ohm
Fundamental
25
18
DRIVE level
pF
7
pF
1
mW
Note: 1. ESR value is dependent upon frequency of oscillation
13-0169
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Phase Noise and Additive Jitter
Output phase noise (Dark Blue) vs Input Phase noise (light blue)
Additive jitter is calculated at ~47fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2)
Oscillator Phase Jitter
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Application Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VDD
R1
1K
Single Ended
Clock Input
CLK
/CLK
C1
0.1µ
R2
1K
Figure 1. Single-ended input to Differential input device
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias,
0.1μF and 1μF bypass capacitors should be used for each pin.
VDD
VDD
0.1µF
1µF
VDDO
VDDO
0.1µF
13-0169
1µF
16
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
Application Notes
Clock IC Crystal loading cap. design guide
Clock IC
Rf
CL =crystal spec. loading cap.
C_in/out = (3~5pF) of IC pin cap.
C_in
Cb = PCB trace (2~4pF)
C_out
XTL_IN
XTL_OUT
Rd
Cb
Crystal (CL)
C1
C1,C2 = load cap. of design
Rd = 50 to 100ohm drive level limit
Cb
(Optimized for 25MHz 18pf XTAL
without Rd)
C2
Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm
Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too
Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate
ppm if necessary
Thermal Information
Symbol
Description
ΘJA
Junction-to-ambient thermal resistance
ΘJC
Junction-to-case thermal resistance
13-0169
Condition
44.7 °C/W
Still air
21.7 °C/W
17
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PI6C49X0210 Rev F
12/13/13
PI6C49X0210
High Performance 1:10 Multi-Voltage CMOS Buffer
DATE: 05/15/13
Notes:
DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH32
DOCUMENT CONTROL #: PD-2070HW
REVISION: B
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1,2,3)
Ordering Code
PI6C49X0210ZHIE
Package Code
Package Description
ZH
Pb-Free and Green 32-pin TQFN
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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PI6C49X0210 Rev F
12/13/13