PI6LC4830 HiFlexTM Network Clock Generator Features Description ÎÎ3.3V supply voltage The PI6LC4830 is an LC VCO based low phase noise design intended for the most demanding PCIe® 2.0 applications. Use of the ultra-low noise LC VCO allows for much greater noise margins than traditional solutions. This is ideal for noisy environments. ÎÎ3 HCSL and 1 LVCMOS 100MHz outputs with OE/ function ÎÎ1 LVCMOS 100/50MHz selectable ÎÎ25MHz crystal or differential input ÎÎLow 1ps RMS max integrated phase noise design ÎÎPLL Bypass mode for test VDD_Out IREF QA0+ QA0- 31 30 29 28 27 26 GND VDD 32 QA_OE VDDA_PLL Pin Configuration 25 PLL_Byps 1 REF_OUT_OE 2 23 QB_OE 3 22 QB_DIV2 4 VDD_PLL 5 IN+ 6 19 IN- 7 18 VDD_REF_Out 8 24 GND 21 20 13 14 15 VDD_OSC VDD_OutB_SE QA1+ QA1VDD_Out QA2+ QA2GND QA_CMOS VDD_OutA_SE 16 QB_CMOS 12 X2 11 X1 10 IN_SEL 17 9 REF_OUT- 5x5mm TQFN package REF_OUT+ ÎÎ32 lead Block Diagram PLL_Byps REF_OUT_OE REF_OUT QA0:QA2 100MHz HCSL Outputs IN_SEL OSC PLL IN+ IN- QA_CMOS /R QA_OE QB_CMOS /2 QB_DIV2 QB_OE 12-0238 1 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Pin Description Pin Number Pin Name Type Description 20, 21, 23, 24, 26, 27 QA0+, QA0-, QA1+, QA1-, QA2+, QA2- Output (HCSL) 100MHz HCSL Outputs 9, 10 REF_Out+, REF_Out- Output (LVPECL) 25MHz LVPECL output from fundamental oscillator core 12 X1 Input Crystal input pin 13 X2 Output Oscillator output pin 6, 7 IN+, IN- Input (Differential) HCSL/LVPECL/LVDS inputs 11 IN_SEL Input (LVCMOS) Low selects X1 and X2, High selects In+, In-. Internal pull up is 100k Ohms 1 PLL_Byps Input (LVCMOS) If Low, output buffers are switched to the PLL. If High, output buffers are switched to the input mux. Internal 100K-Ohm pulldown. 30, 3 QA_OE, QB_OE Input (LVCMOS) Low enables outputs, High selects high impedance mode. Internal 100K-Ohm pulldown 14 VDD_OSC Power Power for xtal Osc core 5 VDD_PLL Power Power for digital portion of PLL circuitry 22, 29 VDD_Out Power Power for output buffers 32 VDDA_PLL Power Power for analog core of PLL 19, 25 GND Power Ground 18 QA_CMOS Output (LVCMOS) 100MHz LVCMOS Output 16 QB_CMOS Output (LVCMOS) 100/50MHz Selectable LVCMOS Output 17 VDD_OutA_SE Power Bank A LVCMOS Power 15 VDD_OutB_SE Power Bank B LVCMOS Power 4 QB_DIV2 Input (LVCMOS) High selects 50MHz, Low selects 100MHz. Internal 100K-Ohm pull-up 28 IREF Output External resistor connection for internal current reference 8 VDD_REF_OUT Power Power for reference output 2 REF_OUT_OE Input (LVCMOS) Low enables outputs, High selects high impedance mode. Internal 100K-Ohm pull-down. 31 VDD Power Power for Core 12-0238 2 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage temperature............................................... -65ºC to +155ºC 3.3V Analog Supply Voltage...................................... -0.5 to +4.6V ESD Protection (HBM).......................................................... 2000V Operating Conditions (Over Operating Conditions) Symbol Parameters VDD_PLL Min. Max. PLL Power Supply Voltage 2.8 3.6 VDD_REF_Out Power Supply for Reference Out 2.9 3.6 VDD_OSC Power Supply Voltage for oscillator core 2.8 3.6 VDD_OutA, OutB Power Supply Voltage for Bank A and Bank B 2.9 3.6 VDD_Out Power Supply Voltage for Output Buffer 2.9 3.6 VDD 3.3V General Power Supply Voltage 2.9 3.6 VDDA_PLL Analog PLL Power Supply Voltage 2.8 3.6 TA Ambient Temperature -40 85 IDD_PLL PLL Power Supply Current At 3.6V, loaded 10 IDD_REF_OUT Current for Reference Out At 3.6V, loaded 36 IDD_OSC Current for Oscillator At 3.6V, loaded 12 At 3.6V, loaded 11 IDD_OUTA, OUTB Current for Bank A and Bank B Conditions IDD_OUT Current for Output Buffer At 3.6V, loaded 76 IDDA _PLL Analog PLL Current, VDDA_PLL At 3.6V, loaded 35 No load (Analog PLL Current Included) 85 IDD Total Power Supply Current All outputs loaded (Analog PLL Current Included) 180 PDiss Power Dissipation All outputs loaded 0.65 12-0238 3 PI6LC4830 Rev B Units V °C mA W 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator LVCMOS DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Conditions Min. Typ. VIH Input High Voltage 2 VDD + 0.3 VIL Input Low Voltage -0.3 0.8 VOH Output High Voltage IOH = -8mA VOL Output Low Voltage IOL = 8mA QA_OE, QB_OE, REF_OUT_OE, PLL_Byps V 0.4 45 VIN = VDD IN_SEL, QB_DIV2 5 Input Low Current for QA_OE, QB_OE, REF_OUT_OE, PLL_Byps IIL Units VDD - 0.4 Input High Current for IIH Max. VIN = 0V IN_SEL, QB_DIV2 μA -5 -45 Rpu Internal pull up resistance 105 kOhm Rdn Internal pull down resistance 105 kOhm ZO Output Impedance 30 Ohm CIN Input Capacitance for X1, X2 inputs 4 pF LVCMOS AC Characteristics (Over Operating Conditions) Symbol Parameter Conditions Min. ferror Frequency Synthesis Error Tr/Tf Output Rise/Fall time TDC Output Duty Cycle JCC Jitter, Cycle-to-Cycle Jphase Rms Phase jitter from 12kHz 20MHz TEN/DIS Output enable/disable time 80 ns TLOCK PLL Lock Time 5 ms 20% to 80%, CL = 10pF tDC = tH/tCY, tH = High Pulse Width, tCY = Output Cycle Time, @ VDD/2 45 Typ. Max. Units 0 ppm 1.2 2 ns 50 55 % 175 ps 0.4 1 12-0238 4 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Differential DC Input Characteristics (Over Operating Conditions) Symbol Parameters IIH Input High Current IN- VIN = VDD = 3.465V 5 IN+ VIN = VDD = 3.465V 45 IIL Input Low Current IN- VIN = 0V -45 IN+ VIN = 0V -5 VCMR Common Mode Voltage Range VPP Conditions Min. Typ. Units uA VDD0.85V 0.5 Peak-to-Peak Input Voltage Swing Max. 0.15 V 1.3 HCSL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Condition Min. VOH Output High Voltage VDD_OUT = VDD -0.15V (1) 660 VOL Output Low Voltage VCROSS Absolute Crossing Point Voltages D VCROSS Total variation of VCROSS overall edges IOH Output High Current w/ 475-Ohm resistor. Connected between IREF pin and GND Typ. Max. Units 900 150 250 mV 550 140 14 mA Note: 1. This voltage drop is to account for the voltage across the series resistor in the layout guidelines. HCSL AC Output Switching Characteristics(1,2,3) (Over Operating Conditions) Symbol Parameters Min ferror Frequency Synthesis Error Trise / Tfall Rise and Fall Time (measured between 0.175V to 0.525V) ΔTrise / ΔTfall 175 Typ Max. Units 0 ppm 250 700 Rise and Fall Time Variation 7 125 Tskew Output-to-Output Skew 20 100 TDC Duty Cycle (Measured at 100 MHz) 50 53 Jphase RMS phase jitter from 12kHz - 20MHz 0.4 1 THF-RMS >1.5MHz - 50MHz RMS jitter applying PCIE G2 jitter mask 2.2 3.1 PSR Power Supply Rejection with -30dBm input sine wave 100kHz to 600kHz -46 TEN/DIS Output enable/disable time 80 ns TLOCK PLL Lock Time 5 ms 47 Notes 2 ps 2 3 % ps dBc 3 2 3 2 Notes: 1. Test configuration is RS = 33Ω, Rp = 49.9Ω with 2pF load. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform. 12-0238 5 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator LVPECL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameters Condition Min. Typ. Max. VPP Output peak-peak Voltage VDD_REF_Out = 3.3± 5% 0.4 0.7 1 VOH Output High Voltage VDD_REF_Out = 3.3± 5% VDD-1.4 VDD-0.9 VOL Output Low Voltage VDD_REF_Out = 3.3± 5% VDD-2.0 VDD-1.7 Units V AC LVPECL Switching Characteristics Symbol Parameters Condition Min. Typ. Max. Units Trise / Tfall Rise and Fall Time 20% to 80%, singleended 200 320 450 ps TDC Duty Cycle Differential 47 50 53 % TEN/DIS Output enable/disable time 100 ns Crystal Characteristic (link to "http://www.pericom.com/saronix" for more detailed crystal specifications) Parameters Description Min OSCmode Mode of Oscillation Fundamental FREQ Frequency (1) Typ Max. 25 ESR Equivalent Series Resistance Cload Load Capacitance Cshunt Shunt Capacitance Units MHz 50 18 7 DRIVE level 1 Ohm pF mW Note: 1. ESR value is dependent upon frequency of oscillation Application Notes Crystal circuit connection The following diagram shows PI6LC4830 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 27pF Crystal�(CL�=�18pF) XTAL_OUT C2 33pF 12-0238 6 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf HCSL output buffer characteristics VDD Slope ~ 1/Rs RO IOUT ROS Iout 0V VOUT = 0.90V max 0.90V Figure 9. Simplified diagram of current-mode output buffer HCSL Buffer characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified VOUT N/A 900mV Current Accuracy (IREF pin) Symbol Conditions IOUT VDD = 3.30 ±5% Configuration Load Min. Max. R REF = 475Ω 1% Nominal test load for given configuration -12% INOMINAL +12% INOMINAL IREF = 2.32mA Note: 1. INOMINAL refers to the expected current based on the configuration of the device. Differential Clock Output Current Board Target Trace/Term Z Reference R, Iref = VDD/(3xRr) Output Current 100Ω R REF = 475Ω 1%, (100Ω differential ≈ 15% coupling ratio) IREF = 2.32mA 12-0238 7 IOH = 6 x IREF VOH @ Z 0.7V @ 50 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Typical HCSL Output Phase Noise (3.3V, 25°C) Typical LVCMOS Output Phase Noise (3.3V, 25°C) 12-0238 8 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Configuration Test Load Board Termination for HCSL outputs Rs 33Ω 5% PI6LC4830 Clock TLA Rs 33Ω 5% Clock# TLB Rp 49.9Ω 1% 475Ω 1% 2pF 5% Rp 49.9Ω 1% 2pF 5% Configuration Test Load Board Termination for LVPECL outputs VDD Z O = 50-Ohm TLA L = 0 ~ 10 in. 100-Ohm TLB Z O = 50-Ohm 150-Ohm 12-0238 150-Ohm 9 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Configuration CMOS Output VDD =+3.3V C L (10pF) Power Supply Filter 3.3V ± 5% VDDQx 0.1µF 4.7Ω VDDA_PLL 0.1µF 10µF m 12-0238 10 PI6LC4830 Rev B 08/17/12 PI6LC4830 HiFlexTM Network Clock Generator Packaging Mechanical: 32-Pin TQFN (ZH) Notes: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area (mesh stencile design is recommended) DATE: 06/30/11 DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH32 DOCUMENT CONTROL #: PD-2070 REVISION: B 11-0147 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1-3) Ordering Code Package Code Package Description PI6LC4830ZHE ZH 32-Pin, Pb-free & Green (TQFN) Notes: 1.Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 12-0238 All trademarks are property of their respective owners. 11 PI6LC4830 Rev B 08/17/12