PI6C48535-01B

PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Features
Description
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Maximum operation frequency: 500 MHz
4 pair of differential LVPECL outputs
Selectable CLK0 and CLK1 inputs
CLK0, CLK1 accept LVCMOS, LVTTL input level
Output Skew: 40ps (typical)
Propagation delay: 1.5ns (typical)
3.3V power supply
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Additive jitter of 0.03ps (typical)
Operating Temperature: -40oC to 85oC
Packaging (Pb-free & Green available): — 20-pin TSSOP (L)
The PI6C48535-01B is a high-performance low-skew LVPECL
fanout buffer. PI6C48535-01B features two selectable single-ended
clock inputs and translates to four LVPECL outputs. The CLK0
and CLK1 inputs accept LVCMOS or LVTTL signals. The outputs
are synchronized with input clock during asynchronous assertion/
deassertion of CLK_EN pin. PI6C48535-01B is ideal for singleended LVTTL/LVCMOS to LVPECL translations. Typical clock
translation and distribution applications are data-communications
and telecommunications.
Block Diagram
Pin Configuration
D
CLK_EN
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
12-0258
1
VEE
1
20
Q0
CLK_EN
2
19
NQ0
CLK_SEL
3
18
VCC
CLK0
4
17
Q1
NC
5
16
NQ1
CLK1
6
15
Q2
NC
7
14
NQ2
NC
8
13
VCC
NC
9
12
Q3
VCC
10
11
NQ3
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Pin Description
Name
Pin #
Type
Description
VEE
1
P
CLK_EN
2
I_PU
Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ
pull up.
CLK_SEL
3
I_PD
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/LVTTL level with 50KΩ pull down.
CLK0
4
I_PD
LVCMOS / LVTTL clock input
CLK1
6
I_PD
LVCMOS / LVTTL clock input
Connect to Negative power supply
NC
5, 7, 8, 9
VCC
10, 13,
18
No internal connection.
P
Connect to 3.3V.
Q3, nQ3
11, 12
O
Differential output pair, LVPECL interface level.
Q2, nQ2
14, 15
O
Differential output pair, LVPECL interface level.
Q1, nQ1
16, 17
O
Differential output pair, LVPECL interface level.
Q0, nQ0
19, 20
O
Differential output pair, LVPECL interface level.
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up.
Pin Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
CIN
Input Capacitance
R_pullup
Input Pullup Resistance
50
R_pulldown
Input Pulldown Resistance
50
Max.
Units
4
pF
KΩ
Control Input Function Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
nQ0:nQ3
0
0
CLK0
Diasbled: Low
Diasbled: High
0
1
CLK1
Disabled: Low
Disabled: High
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
12-0258
2
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
Enabled
CLK0
CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
Clock Input Function Table
Inputs
Outputs
CLK0 or CLK1
Q0:Q3
nQ0:nQ3
0
LOW
HIGH
1
HIGH
LOW
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VCC
Supply voltage
Referenced to GND
VIN
Input voltage
Referenced to GND
-0.5
VCC+0.5V
VOUT
Output voltage
Referenced to GND
-0.5
VCC+0.5V
TSTG
Storage temperature
-65
150
4.6
V
oC
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
Parameter
VCC
Power Supply Voltage
TA
Ambient Temperature
IDD
Power Supply Current
12-0258
Conditions
Min.
Typ.
Max.
3.0
3.3
3.6
V
85
oC
130
mA
-40
All outputs unloaded
3
PI6C48535-01B
Units
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
LVCMOS/LVTTL DC Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIH
Input High
Voltage
CLK0, CLK1, CLK_EN,
CLK_SEL
2
VCC+0.3
V
VIL
Input Low
Voltage
CLK0, CLK1
-0.3
0.8
V
CLK_EN, CLK_SEL
-0.3
0.8
V
IIH
Input High
Current
CLK0, CLK1, CLK_SEL
VIN = VCC = 3.6V
150
uA
CLK_EN
VIN = VCC = 3.6V
15
uA
IIL
Input Low
Current
CLK0, CLK1, CLK_SEL
VIN = 0V, VCC = 3.6V
-10
uA
CLK_EN
VIN = 0V, VCC = 3.6V
-150
uA
LVPECL DC Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VOH
Output High Voltage
VCC = 3.3V
2.1
2.6
VOL
Output Low Voltage
VCC = 3.3V
1.3
1.8
Units
V
AC Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V)
Symbol
Parameter
Conditions
Min.
fmax
Output Frequency
tPd
Propagation Delay
1.5
Tsk(o)
Output-to-output Skew
40
tr/tf
Output Rise/Fall time
odc
Output Duty Cycle
Jadd
Additive Jitter
20% - 80%
Typ.
Max.
Units
500
MHz
ns
ps
150
48
52
%
30
fs
Notes:
1. All parameters are measured with CMOS input of 266MHz unless stated otherwise
12-0258
4
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Configuration Test Load Board Termination for LVPECL
VCC
ZO = 50Ω
TLA
L = 0 ~ 10in
Device
100Ω
TLA
ZO = 50Ω
150Ω
12-0258
150Ω
5
PI6C48535-01B
Rev A
09/25/2012
PI6C48535-01B
3.3V Low Skew 1-to-4
LVTTL/LVCMOS to LVPECL Fanout Buffer
Packaging Mechanical: 20-Pin TSSOP (L)
20
.169
.177
1
.252
.260
6.4
6.6
.004 0.09
.008 0.20
.047
1.20
Max
.007
.012
0.19
0.30
.0256
BSC
0.65
4.3
4.5
0.45
0.75
SEATING
PLANE
.018
.030
.238
.269
6.1
6.7
.002 0.05
.006 0.15
Ordering Information
Ordering Code
Package Code
Package Description
PI6C48535-01BLIE
L
Pb-free & Green 20-pin 173-mil wide TSSOP
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free & Green
• X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
12-0258
6
PI6C48535-01B
Rev A
09/25/2012