PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Features Description • • • • • The PI6C48535-11B is a high-performance low jitter and low-skew LVPECL fanout buffer. PI6C48535-11B features selectable of single-ended clock or crystal inputs and translates to four LVPECL outputs. The CLK input accepts LVCMOS or LVTTL signals. The outputs are synchronized with input clock during asynchronous assertion /deassertion of CLK_EN pin. PI6C48535-11B is ideal for crystal or LVCMOS/LVTTL to LVPECL translation. Typical clock translation and distribution applications are data-communications and telecommunications. • • • • • • • Maximum output frequency: 500MHz 4 pair of differential LVPECL outputs Selectable CLK and crystal inputs CLK accepts LVCMOS, LVTTL input level Ultra low additive phase jitter: < 0.05 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range) Output Skew: 30ps (maximum) Part-to-part skew: 200ps (maximum) Propagation delay: 1.5ns (maximum) 3.3V power supply Pin-to-pin compatible to ICS8535-11, ICS8535-31 Operating Temperature: -40oC to 85oC Packaging (Pb-free & Green available): - 20-pin TSSOP (L) Block Diagram Pin Diagram CLK_EN D Q LE CLK 0 Xtal1 Xtal2 1 CLK_SEL Q0 nQ0 Q1 nQ1 VEE 1 20 CLK_EN 2 19 NQ0 CLK_SEL 3 18 VDD CLK 4 17 Q1 NC 5 16 NQ1 Xtal1 6 15 Q2 Xtal2 7 14 NQ2 NC 8 13 VDD NC 9 12 Q3 VDD 10 11 NQ3 Q0 Q2 nQ2 Q3 nQ3 12-0203 1 www.pericom.com PI6C48535-11B Rev A 06/01/12 PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Pin Description Name Pin # Type Description VEE 1 P CLK_EN 2 I_PU Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50KΩ pull up. CLK_SEL 3 I_PD Clock select input. When high, selects Xtal (Xtal1, Xtal2) inputs. When low, selects CLK input. LVCMOS/LVTTL level with 50KΩ pull down. CLK 4 I_PD LVCMOS / LVTTL clock input Xtal1, Xtal2 6, 7 Crystal input and output NC 5, 8, 9 No internal connection. VDD 10, 13, 18 P Connect to 3.3V Q3, nQ3 11, 12 O Differential output pair, LVPECL interface level. Q2, nQ2 14, 15 O Differential output pair, LVPECL interface level. Q1, nQ1 16, 17 O Differential output pair, LVPECL interface level. Q0, nQ0 19, 20 O Differential output pair, LVPECL interface level. Connect to Negative power supply Notes: 1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units CIN Input Capacitance 4 pF R_pullup Input Pullup Resistance 50 KΩ R_pulldown Input Pulldown Resistance 50 KΩ Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK Diasbled: Low Diasbled: High 0 1 Xtal1, Xtal2 Disabled: Low Disabled: High 1 0 CLK Enabled Enabled 1 1 Xtal1, Xtal2 Enabled Enabled Notes: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. 12-0203 2 www.pericom.com PI6C48535-11B Rev A 06/01/12 PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Figure 1. CLK_EN Timing Diagram Disabled Enabled CLK CLK_EN nQ0:nQ3 Q0:Q3 Clock Input Function Table Inputs Outputs CLK Q0:Q3 nQ0:nQ3 0 LOW HIGH 1 HIGH LOW Absolute Maximum Ratings Symbol Parameter Conditions Min. Typ. Max. VDD Supply voltage Referenced to GND VIN Input voltage Referenced to GND -0.5 VDD +0.5V VOUT Output voltage Referenced to GND -0.5 VDD +0.5V TSTG Storage temperature -65 150 Units 4.6 V oC Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci- fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Conditions Symbol Parameter VDD Power Supply Voltage TA Ambient Temperature IDD Power Supply Current 12-0203 Conditions Min. Typ. Max. 3.135 3.3 3.465 V 85 oC 130 mA -40 All outputs unloaded 3 www.pericom.com PI6C48535-11B Rev A Units 06/01/12 PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer LVCMOS/LVTTL DC Characteristics (TA = -40oC to 85oC, VDD = 3.3V ± 5% unless otherwise stated below.) Symbol Parameter Conditions Min Typ Max Units VIH Input High Voltage 2 VDD+0.3 VIL Input Low Voltage -0.3 0.8 IIH Input High Current IIL Input Low Current CLK, CLK_SEL VIN = VDD = 3.3V 150 CLK_EN VIN = VDD = 3.3V 10 CLK, CLK_SEL VIN = 0V, VDD = 3.3V -10 CLK_EN VIN = 0V, VDD = 3.3V -150 V µA LVPECL DC Characteristics (TA = -40oC to 85oC, VDD = 3.3V unless otherwise stated below.) Symbol Parameter Conditions Min. Typ. Max. VOH Output High Voltage 2.1 2.6 VOL Output Low Voltage 1.3 1.8 Units V Crystal Characteristics Parameter Min. Max. Units 40 MHz Equivalent Series Resistance (ESR) 70 Ω Shunt Capacitance 7 pF Mode of Oscillation Typ. Fundamental Frequency Range 12 AC Characteristics (TA = -40oC to 85oC, VDD = 3.3V ± 5%) Symbol Parameter Conditions fmax Output Frequency tjit Buffer Additive Jitter RMS 156.25MHz VSWING Peak-to-peak Output Voltage Swing 156.25MHz tPd Propagation Delay(1) (4) Tsk(o) Output-to-output Tsk(pp) Part-to-part Min. 0.6 Output Rise/Fall time odc Output duty cycle Osc Crystal Tolerance Units 500 MHz ps 1.1 V 1.5 ns 30 Skew(3) (4) tr/tf Max. 0.05 Skew(2) (4) (4) Typ. 200 20% - 80% (4) ps 100 400 48 52 % 1000 ppm Notes: 1. Measured from the VDD/2 of the input to the differential output crossing point 2. Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 4. All parameters are measured with CMOS input of 266MHz unless stated otherwise 12-0203 4 www.pericom.com PI6C48535-11B Rev A 06/01/12 PI6C48535-11B 3.3V Low Jitter 1-to-4 Crystal/LVCMOS to LVPECL Fanout Buffer Packaging Mechanical: 20-Pin TSSOP (L) DATE: 05/03/12 DESCRIPTION: 20-pin, 173mil Wide TSSOP Notes: 1. Refer JEDEC MO-153F/AC 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr PACKAGE CODE: L DOCUMENT CONTROL #: PD-1311 REVISION: F 12-0373 Ordering Information Ordering Code Package Code Package Description PI6C48535-11BLIE L Pb-free & Green 20-pin 173-mil wide TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 12-0203 5 www.pericom.com PI6C48535-11B Rev A 06/01/12