Pericom Product Datasheet - PLL Clock Driver for 1.35V/1.5V SSTE

PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
Features
Description
ÎÎ5 LVPECL outputs
The PI6C4911505-04 is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. The device has 2 selectable clock inputs that can accept most differential and single
ended clock sources. This device is ideal for systems that need to
distribute low jitter clock signals to multiple destinations.
ÎÎUp to 1.5GHz output frequency
ÎÎUltra low additive phase jitter: < 0.03 ps
(typ) (differential
156.25MHz, 12KHz to 20MHz integration range)
ÎÎTwo selectable inputs
ÎÎLow delay from input to output (Tpd typ. 1.5ns)
Applications
ÎÎ2.5V/3.3V power supply
ÎÎNetworking systems including switches and Routers
ÎÎIndustrial temperature support
ÎÎHigh frequency backplane based computing and telecom
ÎÎTSSOP-20 package
platforms
Pin Configuration (20-Pin TSSOP)
Block Diagram
nEN
Pulldown
D
Q
LE
CLK0
nCLK0
CLK1
CLK_SEL
Pulldown
Pullup
0
Pulldown
1
Q0
nQ0
Q1
nQ1
Pulldown
Q2
nQ2
Q3
nQ3
Q4
nQ4
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1
Q0
1
20
VDD
nQ0
2
19
nEN
Q1
3
18
VDD
nQ1
4
17
NC
Q2
5
16
CLK1
nQ2
6
15
CLK0
Q3
7
14
nCLK0
nQ3
8
13
NC
Q4
9
12
CLK_SEL
nQ4
10
11
VEE
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PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
Pinout Table
Pin #
Pin Name
Q0
1, 2
nQ0
Q1
3, 4
nQ1
Q2
5, 6
nQ2
Q3
7, 8
nQ3
Q4
9, 10
nQ4
Type
Description
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
11
VEE
Power
Negative power supply
12
CLK_SEL
Input
Clock input source selection pin
13, 17
NC
-
No connect
Input
Differential clock input
CLK0
14, 15
nCLK0
16
CLK1
Input
CMOS clock input
18, 20
VDD
Power
Power supply
19
nEN
Input
Synchronizing clock enable. When LOW, clock
outputs enabled. When HIGH, Q outputs are forced
low, nQ outputs forced high.
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PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
Function Table
Table 1: Input select function
CLK_SEL
Function
0
CLK0, nCLK0
1
CLK1
Table 2: Enable function
Outputs
nEN
Q0:Q4
nQ0:nQ4
1
Disabled; LOW
Disabled; HIGH
0
Enabled
Enabled
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PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Storage temperature....................................................-55 to +150ºC
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Supply Voltage to Ground Potential (VDD).............. -0.5 to +4.6V
Inputs (Referenced to GND).............................. -0.5 to VDD+0.5V
Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V
Soldering Temperature (Max of 10 seconds).....................+260ºC
Latch up...................................................................................200mA
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
VDD
Core Supply Voltage
IDD
Power Supply Current
TA
Ambient Operating Temperature
Test Condition
Min.
Typ.
Max.
3.0
3.3
3.6
2.375
2.5
2.625
All outputs unloaded
-40
Units
V
150
mA
85
°C
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
IIH
Input High current: CLK0, CLK1
IIL
Min.
Max.
Units
Input = VDD
150
uA
Input High current: nCLK0
Input = VDD
5
uA
Input Low current: CLK0, CLK1
Input = GND
-5
uA
Input Low current: nCLK0
Input = GND
-150
uA
CIN
Input capacitance
VIH
Input high voltage
VIL
Input low voltage
-0.3
VID
Input Differential Amplitude PK-PK
0.15
VCM
Common model input voltage
12-0269
Typ.
4
PF
VDD+0.3
VEE+0.5
4
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V
V
1.3
V
VDD -0.85
V
PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
DC Electrical Specifications - LVCMOS Inputs
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
Input High current
Input = VDD
150
uA
IIL
Input Low current
Input = GND
-150
VIH
Input high voltage
VDD =3.3V
2.0
VDD+0.3
V
VIL
Input low voltage
VDD =3.3V
-0.3
0.8
V
VIH
Input high voltage
VDD =2.5V
1.7
VDD+0.3
V
VIL
Input low voltage
VDD =2.5V
-0.3
0.7
V
uA
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
Output High voltage
VOH
Conditions
Min.
Typ.
Max.
VDD =3.3V
2.1
2.6
VDD =2.5V
1.3
1.6
VDD =3.3V
1.3
1.8
VDD =2.5V
VSWING
V
V
Output Low voltage
VOL
Units
Peak to Peak Output Voltage
Swing
0.5
0.8
0.6
1.1
V
`
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PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
FOUT
Clock output frequency
Tr
Output rise time
From 20% to 80%
150
ps
Tf
Output fall time
From 80% to 20%
150
ps
TODC
Output duty cycle
Frequency<650MHz, LVPECL input
48
VPP
Output swing Single-ended
LVPECL outputs
400
Tj
Buffer additive jitter RMS
TSK
Output Skew
TPD
Propagation Delay
TP2P Skew
Part to Part Skew1
CLK0/ nCLK0 input, LVPECL
1500
CLK1 input
300
Units
MHz
52
%
mV
0.03
1500
ps
35
ps
2100
ps
150
ps
1. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Configuration Test Load Board Termination for LVPECL
VDD
ZO = 50Ω
TLA
L = 0 ~ 10in
Device
100Ω
TLA
ZO = 50Ω
150Ω
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150Ω
6
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PI6C4911505-04 Rev A
10/31/12
PI6C4911505-04
High Performance 1:5 LVPECL Fanout Buffer
Packaging Mechanical: 20-Pin TSSOP (L)
DATE: 05/03/12
DESCRIPTION: 20-pin, 173mil Wide TSSOP
Notes:
1. Refer JEDEC MO-153F/AC
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1311
REVISION: F
12-0373
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6C4911505-04LIE
L
20-pin, TSSOP, Pb-Free and Green
Notes:
1. 1Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
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PI6C4911505-04 Rev A
10/31/12