PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Description Features ÎÎ2 Fully compatible HDMI™ signal support with backward compatibility to the DVI 1.0 standard, Pericom’s new “ActiveEye™” switch technology is all you need to connect multiple, unknown sources, to a single display. Without any affect on HDCP, these switches can be used almost anywhere. In addition to supporting DC coupled HDMI and DVI inputs, Pericom's PI3HDMI221-A can also level shift an AC coupled HDMI to a DC coupled HDMI output. Pericom’s HDMI product family has been designed specifically to support color depths of up to 12bits per channel, as specified in the HDMI revision 1.3 standard. We have integrated the entire interface solution so the TV designer doesn’t have to think about it. This includes, integrated DDC switching. digital video inputs can be switched to a single output ÎÎEach input can be AC coupled video or DC coupled, while the output will maintain its DC coupled, current-steering, TMDS compliance ÎÎTMDS pixel clock support up to 250MHz max (up to 2.5Gbps per lane) ÎÎDeep Color™ support up to 36bits max per link ÎÎIntegrated DDC switch to connect DDC path from HDMI input connectors to HDCP block in the HDMI Receiver. ÎÎHDCP reset circuitry for quick communication when switching from one port to another àà Automatic Termination turn-off circuitry when port is deselected ÎÎClock Detection: Will disable output TMDS channels when no TMDS pixel clock is present ÎÎFlexible termination; àà When TMDS channel is off, 50-Ohm termination pull to VDD is off ÎÎIntegrated ESD on all TMDS output pins àà 5kV Human Body Model per JESD22 àà ±8kV contact per IEC61000-4-2 ÎÎPackaging (Pb-free and Green) àà 56 contact TQFN (ZFE) 10-0228 1 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications NC NC VDD NC NC VDD5 S_DDC2 S_DDC1 56 55 54 53 52 51 50 49 Pin Configuration NC 1 48 NC NC 2 47 HPD2 VDD 3 46 HPD1 NC 4 45 HPD_sink NC 5 44 EQ_S0 D1-2 6 43 D1- D1+2 7 42 D1+ VDD 8 41 VDD D2-2 9 40 D2- D2+2 10 39 D2+ GND VDD 31 SDA_Sink D2-1 19 30 SCL_Sink D2+1 20 29 SDA2 10-0228 28 S_HS1 18 SCL2 D1+1 32 27 S_HS2 17 SDA1 D1-1 33 26 CLK+ 16 SCL1 CLK+2 34 25 CLK- 15 CLK+1 CLK-2 35 24 VDD 14 CLK-1 VDD 36 23 D3+ 13 VDD D3+2 22 D3- 37 D3+1 38 21 11 12 D3-1 D3-2 2 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Pin Description Pin # Pin Name I/O 17 20 22 25 D1+1 D2+1 D3+1 CLK+1 I Port 1 TMDS Positive inputs 7 10 12 15 D1+2 D2+2 D3+2 CLK+2 I Port 2 TMDS Positive inputs 16 19 21 24 D1-1 D2-1 D3-1 CLK-1 I Port 1 TMDS Negative inputs 6 9 11 14 D1-2 D2-2 D3-2 CLK-2 I Port 2 TMDS Negative inputs 1, 2, 4, 5, 48, 52, 53, 55, 56 NC 46 HPD1 O Port 1 HPD output 47 HPD2 O Port 2 HPD output 45 HPD_Sink I Sink side hot plug detector input. 26 SCL1 I/O Port A DDC Clock 28 SCL2 I/O Port B DDC Clock 30 SCL_Sink I/O Sink Side DDC Clock 27 SDA1 I/O Port A DDC Data 29 SDA2 I/O Port B DDC Data 31 SDA_Sink I/O Sink Side DDC Data 32, 33 S_HS1, S_HS2 I TMDS channel selection pins 49, 50 S_DDC1, S_DDC2 I DDC channel selection pins 3, 8, 13, 18, 23, 36, 41, 54 VDD 3.3V Power Supply 51 VDD5 5.0V Power Supply 42 39 37 34 D1+ D2+ D3+ CLK+ O TMDS positive outputs 43 40 38 35 D1D2D3CLK- O TMDS negative outputs 44 EQ_S0 I Equalizer control, Internal pull-up is added. 10-0228 Description No Connect 3 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Block Diagram D1+1 D1-1 D2+1 VDD VDD VDD VDD R R R R R R R R Receiver with EQ Receiver with EQ Receiver with EQ Receiver with EQ ... VDD D2-1 D3+1 D3-1 CLK+1 CLK-1 EQ_S0 R D1+2 R Receiver with EQ R Receiver with EQ D1-2 VDD R D2+2 2-to-1 MUX D2-2 R D3+2 R Receiver with EQ TDMS Drive ... VDD TDMS Drive D3-2 VDD TDMS Drive R CLK+2 R Receiver with EQ CLK-2 TDMS Drive D1+ D1D2+ D2- D3+ D3CLK+ CLK- HPD1 S_DDC1, S_HS1 HPD2 S_DDC2, S_HS2 Control Logic SCL1 HPD_SINK SCL_SINK SDA_SINK SDA1 SCL2 SDA2 10-0228 4 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Receiver Block The HDMI/DVI receive ports are terminated separately as follows: Truth Table EQ_S0(1) EQ value on TMDS data channels 0 6dB 1 12dB V DD Notes: 1) Internal 100K--Ohm pull down resistor R1 Control CLK±,�Dx± S_HS2/S_HS1 Each input has integrated equalization that can eliminate deterministic jitter caused by 20meter 24AWG cables. The Rx block is designed to receive all relevant signals directly from the HDMI connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, and DDC signals. Transmitter Block The transmitter block transmits the HDMI/DVI data according to HDMI revision 1.3 transmitter spec. Source Selection Look-up Table Control Bits(1,2) S_xxx2 S_xxx1 H H H L L L L H I/O Selected TMDS output SCL_SINK/SDA_SINK TMDS Port 1 is active and port 2 has SCL1/SDA1 50-Ohm termination disconnected TMDS Port 2 is active and port 1 has SCL2/SDA2 50-Ohm termination disconnected Hi-Z, all terminations are disconHigh-Z nected NONE(Z) NONE(Z) Are pulled HIGH by All terminations are disconnected external pull-up termination Hot Plug Detect Status HPD1 HPD2 HPD_SINK L L HPD_SINK L L HPD_SINK HPD_SINK Notes: 1) xxx equals DDC (pins 49&50) for SCL_Sink/SDA_sink, HPD1, and HPD2 configuration 2) xxx equals HS (pins 32&33) for TMDS output configuration 10-0228 5 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Electrical Specifications Absolute Maximum Conditions Symbol Parameter Min Typ Max Units Note VDD TMDS Supply Voltage -0.3 4.0 1, 2 VI Input Voltage -0.3 VDD+0.3 1, 2 VO Output Voltage -0.3 VDD+0.3 V 1, 2 +5V power supply used during power VDD5 -0.3 6.0 down situation Notes: 1. Permanent device damage can occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Electrical Specifications Normal Operating Conditions Symbol Parameter VDD TMDS Analog Supply Voltage +5V power supply used during power down (from VDD5 HDMI connector) to make sure DDC and HPD are still available when TV is off TA Ambient Temperature (with power applied) 10-0228 6 Min 3 Typ 3.3 4.5 0 Max 3.6 5.5 25 70 Units V °C PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) Symbol Description S_HS2/S_HS1 = HIGH/LOW HIGH/HIGH S_HS2/S_HS1 = LOW/HIGH Supply current ICC Test Conditions Min Typ Max Units 120 VIH = VDD, VIL = VDD-0.6V RT=50-Ohm, VDD=3.3V TMDS data inputs = 2.5Gbps HDMI data pattern TMDS clock input = 250MHz 35 IDD 5V power supply current consumption 5V is present, S_DDC2/S_DDC1 = X ICCQ 3.3V supply current when 5V is not present 5V is not present, S_xxx2/S_xxx1 = X 5 ICC_squelch Supply current when no TMDS CLK is present 3.3V and 5V supply is present S_HS2/S_HS1 = L/L or H/L or H/H No TMDS CLK input is present 5 5 mA Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) Symbol Parameter Test Conditions Min. Typ.(1) Max. Units TMDS Differential pins Single-ended high level output voltage VOH VOL Vswing VOD(O) VOD(U) DVOC(SS) IOS VI(open) RINT Single-ended low level output voltage Single-ended output swing voltage Overshoot of output differential voltage Undershoot of output differential voltage Change in steady-state common-mode output voltage between logic states Short Circuit output current Single-ended input voltage under high impedance input or open input Input termination resistance 10-0228 VDD-10 VDD+10 VDD-600 VDD–400 400 600 mV 15% 2 x Vswing VDD = 3.3V, RT = 50-Ohm II = 10uA VIN = 2.9V 25% 5 mV -12 12 mA VDD-10 VDD+10 mV 55 Ohm 45 7 50 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Symbol Parameter Test Conditions Min. Typ.(1) CLK_Detect TMDS clock detection for normal operation. Outputs are Hi-Z if CLK signal detected is outside of this Normal operating range Frequency Differential Voltage Swing is 140mV or higher IOZ Leakage current with Hi-Z I/O VDD = 3.6V, VDD5 = 5.5V 5 IOFF Leakage current when VDD is not present VDD = 0V or open, VDD5 = 5.5V 10 15 Max. Units 340 MHz µA Switching Characteristics (over recommended operating conditions unless otherwise noted) TMDS Differential Pins Symbol Parameter Test Conditions Min. Typ.(1) Max. Units 2000 tpd Propagation delay tr Differential output signal rise time (20% - 80%) tf Differential output signal fall time (20% - 80%) tsk(p) Pulse skew tsk(D) Intra-pair differential skew tsk(o) Inter-pair differential skew tjit(pp) Peak-to-peak output jitter CLK residual jitter tjit(pp) Peak-to-peak output jitter DATA residual jitter tSX Select to switch output 10 ten Enable time 600 tdis Disable time 10 140 140 VDD = 3.3V, RT = 50--Ohm 10 50 23 50 100 Data Input = 1.65 Gbps HDMITM data pattern CLK Input = 165 MHz clock 15 30 18 50 ps ns DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) Symbol tpd(DDC) Parameter Test Conditions Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn Min. Typ.(1) CL = 10pF Max. Units 2.5 ns 0.4 Control and Status Pins (OC_SX, EQ_SX, S, HPD_SINK, HPD) Symbol Parameter tpd(HPD) Propagation delay (from HPD_SINK to the active port of HPD) tsx(HPD) Switch time (from port select to the latest valid status of HPD) 10-0228 Test Conditions CL = 10pF Min. Typ.(1) Max. 2 6.0 Units ns 3 8 6.5 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Control Pins Symbol IIH IIL VIH VIL Parameter Test Conditions High level digital input current Low level digital input current(1) High Level Digital input Voltage low level digital input voltage (1) VIH = 2V or VDD VIL = GND or 0.8V Min. Typ.(1) -10 -10 2.0 0 Max. 10 10 VDD5 0.8 Units µA V DDC I/O Pins Symbol Parameter Test Conditions Min. ILK Input leakage current VI = 0.1 VDD to VDD to isolated DDC inputs -10 CDDC_IO (1) DDC Passive Switch Input/output capacitance VDD = 0V or 3.0V, Frequency = 100kHz RON Switch resistance IO = 3mA, VO = 0.4V Max. Units 10 µA 6 11 pF 25 50 -Ohm Typ.(1) Max. Units Typ.(1) Note: 1. Measured at Vbias = 0V or 5V, Vrms = 0.2V; Vbias = 1.65V, Vrms = 0.9V; Vbias = 2.5V, Vrms = 1.2V. HPD Path Symbol Parameter Test Conditions IIH High level digital input current VIH = 2V or VDD IIL VOH VOL Low level digital input current Single-ended high level output voltage Single-ended low level output voltage VIL = GND or 0.8V IOH = -100µA IOL = 100µA 10-0228 9 Min. -10 10 -10 2.4 GND 10 VDD 0.4 PS9068A µA V 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Recommended Power Supply Decoupling Circuit Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitors on each VDD pins of our part, there are four 0.1µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1µF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1µF decoupling capacitors on each VDD pins, it is recommended to put a 10µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. 10µF Ferrite Bead From main power supply 0.1µF V DD 0.1µF V DD P e r ic o m P a r t 0.1µF V DD 0.1µF V DD Figure 1 Recommended Power Supply Decoupling Circuit Diagram 10-0228 10 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Requirements on the Decoupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. Layout and Decoupling CapacitorPlacement Consideration i. Each 0.1µF decoupling capacitor should be placed as close as possible to each VDD pin. ii. VDD and GND planes should be used to provide a low impedance path for power and ground. iii. Via holes should be placed to connect to VDD and GND planes directly. iv. Trace should be as wide as possible v. Trace should be as short as possible. vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. vii. 10µF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1µF capacitors. viii.Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Bypass noise V DD P la ne Power Flow G N D P la ne 0 .1 uF P e r ic o m P a r t Figure 2 Layout and Decoupling Capacitor Placement Diagram 10-0228 11 PS9068A 09/24/10 PI3HDMI221-A 2:1 ActiveEye™ HDMI™ Switch with Automatic Power Down and Dual SEL Control for Source Applications Package Mechanical: 56-pin, Low Profile Quad Flat Package (ZF56) 1 DATE: 05/15/08 DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 REVISION: C DOCUMENT CONTROL #: PD-2024 08-0208 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code PI3HDMI221-AZFE ZFE Package Description 56-pin, Pb-free & Green TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel • HDMI & Deep Color are trademarks of Silicon Image Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 10-0228 All trademarks are property of their respective owners. 12 PS9068A 09/24/10