PI3HDX412BD HDMI 1.4b 1:2 Splitter/Demux for 3.4Gbps Data Rate with Equalization & Pre-emphasis Features General Description Pericom Semiconductor’s PI3HDX412BD, active-drive switch solution is targeted for high-resolution video networks that are based on HDMITM/DVI standards, and TMDS signal processing. yySupport up to 3.4Gbps TMDS Serial Link Compliant with HDMI 1.4b requirement yyHDMI 1-to-2 Splitter or 1-to-2 DeMux with Equalization & Pre-emphasis up to 340 MHz Clock The PI3HDX412BD is an active single TMDS channel to two TMDS channel Splitter and DeMux with Hi-Z outputs. The device drives differential signals to multiple video display units. yyAC or DC Coupled Differential Signaling Input yyConfigurable TMDS Output Signal with Port Selection, Pre-emphasis, Voltage Swing, Slew Rate Control yySupport Squelch Mode with Built-in Clock detector yyControl Status Register controlled by Pin strap or mode programming It provides controllable output swing levels that can be controlled through pin control or I2C control, depending on the mode select pin. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times. I2C yyESD Protection on I/O pins to connector: 8KV Contact per IEC6100-4-2 and 2KV HBM The maximum HDMITM/DVI data rate of 3.4Gbps provides a 1920x1080 @60Hz resolution or 4K @30Hz required for 4K HDTV and PC graphics products. Due to its active unidirectional feature, this switch is designed for usage only for the video driver’s side. For PC graphics application, the device sits at the driver’s side to switch between multiple display units, such as PC LCD monitor, projector, TV, etc. yySupply Voltage: 3.3V yyIndustrial Temperature Range: -40oC to 85oC (Pb-free & Green): 56-contact TQFN 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PI3HDX412BD TQFN- 56 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD D0P1 D0N1 GND CLKP1 CLKN1 VDD D2P2 D2N2 GND D1P2 D1N2 VDD D0P2 HDMI Input PI3HDX412BD Package & Pinout All trademarks are property of their respective owners. 14-0020 Port_A HDMI Outputs Port_B PI3HDX414 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD SEL_OUT ROUT_SEL VDD18 EQ2/SCL_CTL EQ1/SDA_CTL GND VDD GND VDD CLKN2 CLKP2 GND D0N2 MS VDD GND D2P D2N VDD D1P D1N D0P D0N VDD CLKP CLKN GND PI3HDX414 PI3HDX412BD ensures transmitting high bandwidth video streams from PC graphics source to end display units. It will also provide enhanced robust ESD/EOS protection, which is required by many consumer video networks today. OE SEL1 DR GND EMP2/I2C_ADR3 EMP1/I2C_ADR2 SW2/I2C_ADR1 SW1/I2C_ADR0 VDD D2P1 D2N1 GND D1P1 D1N1 (ZB56) PI3HDX412B yyPackaging Application Block Diagram 1 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis TMDS In/Out Pin Assignment Pin # Pin Name Type 4 D2P I 5 D2N I 7 D1P I 8 D1N I 9 D0P I 10 D0N I 12 CLKP I 13 CLKN I 25 CLKN2 O 26 CLKP2 O 28 D0N2 O 29 D0P2 O 31 D1N2 O 32 D1P2 O 34 D2N2 O 35 D2P2 O 37 CLKN1 O 38 CLKP1 O 40 D0N1 O 41 D0P1 O 43 D1N1 O 44 D1P1 O 46 D2N1 O 47 D2P1 O Description Input Port. TMDS Clock and Data Input pins. When Input Termination Resistor (Rt = 50 Ohm) tied to VDD or GND, Rpd=200 kOhm shall be "OFF" state. I2C registers can control Rt and Rpd ON/OFF state. Output Port 1. TMDS Clock and Data Output pins. ROUT_SEL pin enables Output Termination Resistor (Rout=50 Ohm). Output Port 2. TMDS Clock and Data Output pins. ROUT_SEL pin enables Output Termination Resistor (Rout=50 Ohm). Note: In TMDS Data and Clock Differential Pair, the polarity +/- (or P/N) of each pair can use interchangeably. When input TMDS Input Clock polarity +/pin swaps, output TMDS Clock of port 1 and port 2 shall swapped accordingly. All trademarks are property of their respective owners. 14-0020 2 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Control Pins Pin # Pin Name Type Description Mode Selection Pin. Internal pull-up at 100K Ohm. 1 MS I "High" : I2C Control Mode Selection "Low" : Pin Control Mode Selection Shared Pin. EQ2 pin or I2C Clock pin. I2C pin is compatible with standard I2CBus specification, up to 400 Kbps. Pin#1 MS sets "High" : Pin#19 assigns to SCL_CTL pin Pin#1 MS sets "Low" : Pin#19 assigns to EQ2 pin Internally Pull-Up at 100 Kohm and Pull-Down at 100 Kohm. Pin Control EQ setting table is shown below. "M" is Tri-state. 19 20 EQ2/SCL_CTL EQ1/SDA_CTL IO Pin#1 MS = "Low" EQ2 (Pin# 19) EQ1 (Pin# 20) Equalization Setting (dB) 0 M 2.5 0 0 5 M 0 7.5 0 1 10 M M 12.5 1 0 15 1 M 17.5 1 1 20 Shared Pin. SW or EMP or I2C_ADR pins. When Pin#1 MS="High" : These Shared Pins assign to I2C_ADR[3:0] When Pin#1 MS="Low" : These Shared Pins assign to SW1/2 and EMP1/2 49 SW1/I2C_ADR0 50 SW2/I2C_ADR1 51 EMP1/I2C_ADR2 52 EMP2/I2C_ADR3 I All trademarks are property of their respective owners. 14-0020 These SW2 and SW1 pins control output voltage swing adjustment as following table. These SW pins have internal Pull-Up 100K Ohm. SW2 (Pin#50) SW1 (Pin#49) Output Voltage Swing 0 0 500 mV 0 1 -10 % 1 0 +10 % 1 1 +20 % 3 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Pin # Pin Name Type Description EMP2 and EMP1 pins control output voltage pre-emphasis. These pins have internally Pull-Up 100 Kohm. 49 50 51 EMP2 (Pin#52) (Continued) I 52 EMP1 (Pin#51) Pre-emphasis Setting (dB) 0 0 0 0 1 1.5 1 0 2.5 1 1 3.5 Output Enable Control pin. Internally pull-up at 100 Kohm. 56 OE I "High" : Output Port Enable "Low" : Turn off Rout and Rt(termination resistor). TMDS Receiver and TMDS Output Drivers are "OFF" state. Direction Control pin 54 DR I "High" : All ports are Active at same time "Low" : Output Ports are controlled by SEL1 (Pin#55) control Port 1 or Port 2 Output Enable Selection pin. Internal pull-up at 100 Kohm. 55 SEL1 I "High" : Enable Output Port 2 "Low" : Enable Output Port 1 SEL_OUT pin. I2C Register Offset 0x00 Bit[5] can control this pin status. 16 SEL_OUT O Offset 0x00 Bit[5] ="1" : Enable Output Port 1 Output Offset 0x00 Bit[5] ="0" : Disable Output Port 1 Output Source termination selection pin. Internal pull-up at 100K Ohm. 17 ROUT_SEL I "High" : Source Termination Output (Rout) Resistor is "ON", connect to VDD in Output Driver "Low" : Source Termination Output (Rout) Resistor is "OFF". Open-Drain Output Driver is open drain All trademarks are property of their respective owners. 14-0020 4 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Power/Ground Pins Pin # Pin Name Type Description 18 VDD18 Power LDO Output Pin for internal core supplier. Add external 4.7 uF capacitor to GND 3,14,21,23,27,33,39,45,53 GND Ground Ground Pins 2,6,11,15,24,30,36,42,48 VDD Power 3.3V Power Supply All trademarks are property of their respective owners. 14-0020 5 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Block Diagram VDD VDD18 VDD Rout LDO VDD or GND CLKP/N D[0:2]P/N Rt VDD DeMux Rout Rpd GND Control & Status Register I2C Controller SCL_CTL SDA_CTL EQ#,MS,DR, SEl# SW.EMP# Control Pins All trademarks are property of their respective owners. 14-0020 6 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Functional Description Squelch Mode: Output Disable (Squelch) Mode uses TMDS Clock channel signal detection. When low voltage levels on the TMDS input clock signals are detected, Squelch state enables and TMDS output port signals shall disable; when the TMDS clock input signal levels are above a pre-determined threshold voltage, output ports shall return to the normal voltage swing levels. When enable Squelch mode, input termination resistor will be enabled together. When Squelch is disabled through I2C register programming RX_SET[1]="1" and no TMDS input signal condition, TMDS D[0:2]P/N will be undetermined status. In Squelch state, TMDS output is high impedance state or TMDS output port shall 50 Ohm pull-up at source termination output. Function Control Table OE MS DR SEL1 HDMI Outputs 0 x x x All Port Disable Pin Cotrol Mode 1 0 1 x All Ports Enable 1 0 0 0 Enable Port 1 1 0 0 1 Enable Port 2 x x I2C Programming Mode I2C Control Mode 1 1 All trademarks are property of their respective owners. 14-0020 7 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis I2C Register Control Programming I2C Register Control Pin Name I/O Description SCL_CTL I I2C Clock, compatible with I2C-bus specification, up to 400 kb/s SDA_CTL IO I2C Data, compatible with I2C-bus specification, up to 400 kb/s I2C_ADR[3:0] I I2C Control Address Setting Byte output : 0x00 - 0x07 O I2C Control registers output I2C Address Byte b[7] MSB b[6] b[5] b[4] b[3] b[2] b[1] b[0] (R/W) 1 0 1 A3 A2 A1 A0 1/0* Address Byte Note: Read "1", Write "0" All trademarks are property of their respective owners. 14-0020 8 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Offset 0x00 Name CONFIG[7:0] Description [7] Enable TMDS Standby mode. In standby mode, TMDS equalizer and output driver shall power down. "0": Standby mode "1": Normal mode [6] Reserved [5] Output TMDS Port 1 Select "0": Disable "1": Enable [4] Output TMDS Port 2 Selected "0": Disable "1": Enable [3] Reserved [2:0] Reserved Power Up Condition Type 0xFF R/W 0x00 R/W 0x00 R/W TMDS Receiver Equalization Setting Registers [7] Disable Input Port input termination resistors "0" : Enable Rpd connection "1" : Disable Rpd connection [6] TMDS Input termination V-bias selection "0": Connect to GND "1": Connect to VDD [5] V-bias register selection enable "0": bit[6] control disable "1": bit[6] control enable [4:2] EQ programmable setting b[4:2] 0x01 RX_SET[7:0] EQ Setting (dB) 000 2.5 001 5 010 7.5 011 10 100 12.5 101 15 110 17.5 111 [1] Squelch Control Bit "0": Squelch enable "1": Squelch disable [0] Reserved 0x02 Reserved [7:0] Reserved All trademarks are property of their respective owners. 14-0020 20 9 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Offset Name Description Power Up Condition Type 0x00 R/W 0x00 R/W TMDS Port 1 Output setting [7] TMDS output control "0": Open drain "1": Double termination 0x03 TX_SET[7:0] for port1 [6:4] TMDS output Pre-emphasis control "000": 0 dB "001": 1.5 dB "010": 2.5 dB "011": 3.5 dB "1xx": 6 dB (750 mVpp swing) [3:2] TMDS output swing setting "00": 500 mV as default "01": -10% "10": +10% "11": +20% [1:0] TMDS output slew rate setting "00": as default "01" / "10": + 5% "11": +10% TMDS Port 2 Output setting [7] TMDS output control "0": Open drain "1": Double termination 0x04 TX_SET[7:0] for port2 [6:4] TMDS output Pre-emphasis control "000" : 0 dB "001" : 1.5 dB "010" : 2.5 dB "011" : 3.5 dB "1xx" : 6 dB ( 750 mVpp swing) [3:2] TMDS output swing setting "00" : 500 mV as default setting "01" : -10% "10" : +10% "11" : +20% [1:0] TMDS output slew rate setting "00" : Default setting "01" / "10" : + 5% "11" : +10% 0x05 Reserved [7:0] Reserved 0x00 R/W 0x06 Reserved [7:0] Reserved 0x0F R/W 0x07 Reserved [7:0] Reserved 0x00 R/W All trademarks are property of their respective owners. 14-0020 10 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis I2C Data Transfer 1. Read Sequence ACK DEV SEL ACK ACK DATA OUT 1 NO ACK DATA OUT N Stop Start R/W 2. Write Sequence ACK DATA IN 1 14-0020 ACK DATA IN N R/W All trademarks are property of their respective owners. ACK Stop Start DEV SEL ACK 11 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Absolute Maximum Ratings Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VDD+0.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Thermal Characteristics Symbol Parameter Ratings TJmax Junction Temperature RθJC Thermal Resistance, Junction to Case 5 RθJA Thermal Resistance, Junction to Ambient 24 Electrical Characteristics DC Specifications Units °C 125 °C/W TJ=25 °C unless otherwise noted VDD=3.3V +/- 10% Symbol Parameter VDD Operation Voltage IDD VDD Supply Current IDDQ VDD Quiescent Current ISTB Standby mode Test Conditions Min. Typ. Max. Units 3.0 3.3 3.6 V 250 290 mA OE = 1, No input signal 50 80 mA OE = 0 1 5 mA VDD-10 VDD+10 mV VDD-600 VDD–400 mV 400 600 mV TMDS Differential Pins VDD = 3.3 V, Rout=50 Ω VOH Single-ended high level output voltage VOL Single-ended low level output voltage Vswing Single-ended output swing voltage VOD(O) Overshoot of output differential voltage 180 mV VOD(U) Undershoot of output differential voltage 200 mV VOC(SS) Change in steady-state common- mode output voltage between logic states 5 mV IOS Short Circuit output current -12 12 mA IOS Short Circuit output current at double termination mode -24 24 mA All trademarks are property of their respective owners. 14-0020 12 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Symbol Parameter Test Conditions VI(open) Single-ended input voltage under high impedance input or open input IL = 10 uA RT Input termination resistance VIN = 2.9 V IOZ Leakage current with Hi-Z I/O VDD = 3.6 V, OE = 0 Min. Typ. VDD-10 45 Max. VDD+10 Units mV 50 55 Ohm 30 100 μA Control pins (OE, SEL1, EMP2, EMP1, SW2, SW1, MS) IIH High level digital input current VIH =VDD -10 10 μA IIL Low level digital input current VIL = GND -50 10 μA VIH High level digital input voltage 2.4 VIL Low level digital input voltage 0 AC Specifications V 0.8 V Symbol Parameter Test Conditions Min. Typ. tpd Propagation delay tr Differential output signal rise time (20% VDD=3.3V, - 80%), 0 dB / Open drain ROUT=50 ohm 117 ps tf Differential output signal fall time (20% - 80%), 0 dB / Open drain 117 ps tsk(p) Pulse skew 15 50 ps tsk(D) Intra-pair differential skew 25 50 ps tsk(O) Inter-pair differential skew 100 ps tsx Select to switch output 550 ns ten Enable time 10 us tdis Disable time 50 ns tjit_clk(pp) Peak-to-peak output jitter CLK residual jitter tjit_data(pp) Peak-to-peak output jitter Date residual jitter 1 Max. Units 2000 ps Data: 3.4 Gbps data pattern 10 ps Clock: 340 MHz 28 ps Note: 1. Overshoot of output differential voltage VOD(O) = (VSWING(MAX) *2) * 15% 2. Undershoot of output differential voltage VOD(O) = (VSWING(MIN) *2) * 25% All trademarks are property of their respective owners. 14-0020 13 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Inter-pair Skew Definition Intra-pair Skew Definition Test Setup of DC-coupled TMDS Input Measurement All trademarks are property of their respective owners. 14-0020 14 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Rise/Fall Time and Single-ended Swing Voltage Typical Splitter Application All trademarks are property of their respective owners. 14-0020 15 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Power Supply Decoupling Circuit It is recommended to put 0.1 µF decoupling capacitors on each VDD pins of our part, there are four 0.1 µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1 µF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1 µF decoupling capacitors on each VDD pins, it is recommended to put a 10 µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. Recommended Power Supply Decoupling Capacitor Diagram Requirements on the De-coupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. All trademarks are property of their respective owners. 14-0020 16 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Layout and Decoupling Capacitor Placement Consideration yyEach 0.1 µF decoupling capacitor should be placed as close as possible to each VDD pin. yyVDD and GND planes should be used to provide a low impedance path for power and ground. yyVia holes should be placed to connect to VDD and GND planes directly. yyTrace should be as wide as possible yyTrace should be as short as possible. yyThe placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. yy10 µF Capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 µF capacitors. yyAvoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Decoupling Capacitor Placement Diagram All trademarks are property of their respective owners. 14-0020 17 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Package Mechanical: 56-pin TQFN (ZB56) 1 DATE: 03/18/09 DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZB (ZB56) DOCUMENT CONTROL #: PD-2008 REVISION: E Note: For latest package info, please check: http://www.pericom.com/products/packaging Ordering Information Ordering Code PI3HDX412BDZBE Package Code ZB Package Description 56-pin, Pb-free & Green TQFN, Source Termination Type Notes: Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ PI3HDX412B : Root Part Number -D/E : D= Source Termination TMDS Top Mount Type, E = Source Termination TMDS Bottom Mount Type -ZB = 56-pin TQFN Package Type -E = Pb-free and Green Adding an -X Suffix = Tape/Reel Type All trademarks are property of their respective owners. 14-0020 18 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis Related Products Information Part Number Product Description PI3HDX414 HDMI 1.4b 3.4Gbps Splitter 1:4 with Signal Conditioning PI3HDX1204 HDMI 2.0 Redriver for 6Gbps Application PI3HDS20412 Wide Voltage Range DisplayPort & HDMI 2.0 Video Switch PI3HDX511A HDMI 1.4b 3.4Gbps Redriver and DP++ Level Shifter PI3EQXDP1201 DisplayPort 1.2 Re-driver with Built-in AUX Listener PI3VDP1430 Dual Mode DisplayPort to HDMI Level Shifter and Re-driver PI3VDP3212 2-Lane DisplayPort1.2 Compliant Passive Switch PI3VDP12412 4-Lane DisplayPort1.2 Compliant Passive Switch PI3HDMI521 HDMI 1.4b 3.4Gbps 2:1 Switch/Re-driver with built-in ARC and Fast Switching support PI3HDMI336 Active HDMI 3:1 Switch/Re-driver with I2C control and ARC Transmitter DISCLAIMER INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PERICOM PRODUCT. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN PERICOM’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Pericom may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Pericom reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specification. Current characterized errata are available on request. Contact your local Pericom Sales office or your distributor to obtain the latest specifications and before placing your product order. Copyright 2014 Pericom Corporation. All rights reserved. Pericom and the Pericom logo are trademarks of Pericom Corporation in the U.S. and other countries. All trademarks are property of their respective owners. 14-0020 19 www.pericom.com 03/24/14 PI3HDX412BD 3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis PRODUCT STATUS DEFINITIONS Datasheet Identification Product Status Definition Advanced Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Pericom Semiconductor reserves the right to make changes at any time without notice to improve design. Preliminary No Identification Needed Full Production Obsolete Not In Production All trademarks are property of their respective owners. 14-0020 Datasheet contains final specifications. Pericom Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Pericom Semiconductor. The datasheet is for reference information only. 20 www.pericom.com 03/24/14