PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Outputs Features Description ÎÎPCIe® 3.0 compliant The PI6C557-01B is a spread spectrum clock generator compliant to PCI Express® 3.0 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce Electromagnetic Interference (EMI). àà Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible output ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency The PI6C557-01B provides one differential (HCSL) or LVDS spread spectrum output. Using Pericom's patented Phase-Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces one pair of differential outputs (HCSL) at 100MHz. It also provides spread selection of -0.5% and no spread. ÎÎHCSL outputs, 0.8V Current mode differential pair ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎSpread of -0.5% and no spread ÎÎIndustrial temperature range ÎÎSpread Bypass option available ÎÎSpread selection via external pins ÎÎPackaging: (Pb-free and Green) àà 16-pin TQFN GND Control Logic Phase Lock Loop CLK CLK X1/CLK NC CLK X2 GND NC 9 5 VDDA All trademarks are property of their respective owners. 14-0045 1 NC RR (IREF) GND IREF Pulling Capacitors Crystal Driver CLK X1 GND 25 MHz crystal or clock X2 13 1 SS1 SS1 NC NC VDD VDD Pin Configuration (16-Pin TQFN) Block Diagram PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output Pin Description Pin # Pin Name I/O Type Description 1 GND Power Connect to ground 2 X1 Input Crystal or reference clock in 3 X2 Output Xtal out. Leave unconnected for clock input. 4 NC - No connect. Must not be connected to GND 5 GND Power Connect to ground 6 SS1 Input Spread select 1. Internall pull up resistor 7 IREF Output 475Ω precision resistor attached to this pin is connected to the internal current reference. 8 NC - No connect. Must not be connected to GND 9 VDDA Power Connect to 3.3V source 10 GND Power Connect to ground 11 CLK Output HCSL complimentary clock output 12 CLK Output HCSL clock output 13 NC - No connect. Must not be connected to GND 14 NC - No connect. Must not be connected to GND 15 VDD Power Connect to 3.3V source for OSC and core 16 NC - No connect. Must not be connected to GND Table 1: Spread Selection Table SS1 Spread 0 Down -0.5% 1 No Spread All trademarks are property of their respective owners. 14-0045 2 PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output Application Information Output Structures Decoupling Capacitors Decoupling capacitors of 0.01μF should be connected between each VDD pin and the ground plane and placed as close to the VDD pin as possible. IREF =2.3mA 6*IREF Crystal Use a 25MHz fundamental mode parallel resonant crystal with less than 300PPM of error across temperature. Crystal Capacitors CL = Crystals's load capacitance in pF Crystal Capacitors (pF) = (CL - 8) *2 R R=475 Ω For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pF. (16-8)*2=16. See Output Termination Sections Current Source (IREF) Reference Resistor - R R If board target trace impedance is 50Ω, then R R = 475Ω providing an IREF of 2.32 mA. The output current (IOH) is 6*IREF. Output Termination The PCI Express differential clock outputs of the PI6C557-01B are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI Express Layout Guidelines section. The PI6C557-01B can be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. All trademarks are property of their respective owners. 14-0045 3 PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output PCI Express Layout Guidelines Common Recommendations for Differential Routing Dimension or Value Unit L1 length, route as non-coupled 50Ω trace. 0.5 max inch L2 length, route as non-coupled 50Ω trace. 0.2 max inch L3 length, route as non-coupled 50Ω trace. 0.2 max inch RS 33 Ω RT 49.9 Ω Differential Routing on a Single PCB Dimension or Value Unit L4 length, route as coupled microstrip 100Ω differential trace. 2 min to 16 max inch L4 length, route as coupled stripline 100Ω differential trace. 1.8 min to 14.4 max inch Differential Routing to a PCI Express connector Dimension or Value Unit L4 length, route as coupled microstrip 100Ω differential trace. 0.25 min to 14 max inch L4 length, route as coupled stripline 100Ω differential trace. 0.225 min to 12.6 max inch PCI Express Device Routing L1 L2 RS L1’ L4 L4’ L2’ RS RT PI6C557-01B Output Clock L3’ RT PCI-Express Load or Connector L3 Typical PCI Express (HCSL) Waveform 800 mV 0 tOR 250 ps 400 ps 0.52 V 0.175 V All trademarks are property of their respective owners. 14-0045 tOF 0.52 V 0.175 V 4 PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output Application Information LVDS Recommendations for Differential Routing Dimension or Value Unit L1 length, route as non-coupled 50Ω trace. 0.5 max inch L2 length, route as non-coupled 50Ω trace. 0.2 max inch RP 100 Ω RQ 100 Ω RT 150 Ω L3 length, route as 100Ω differential trace. L3 length, route as 100Ω differential trace. LVDS Device Routing L1 L3 RQ L3’ L1’ RT PI6C557-01B Clock Output All trademarks are property of their respective owners. RT L2’ 14-0045 RP L2 5 LVDS Device Load PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . 5.5V All Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . -40 to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. EDS Protection (Input) . . . . . . . . . . . . . . . . . . . . . 2000 V min (HBM) Electrical Specifications Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Max. Unit -40 +85 °C +3.0 +3.6 V DC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C) Symbol Parameter VDD Supply Voltage Voltage(1) VIH Input High VIL Input Low Voltage(1) IIL Conditions Input Leakage Current 0 < Vin < VDD With input pull-up and pull-downs Min. Typ. Max. Unit 3.0 3.3 3.6 V 2.0 VDD +0.3 V GND -0.3 0.8 V -20 20 Without input pull-up -5 and pull-downs µA 5 IDD Operating Supply Current R L = 50Ω, CL = 2pF 95 mA CIN Input Capacitance @ 55MHz 7 pF COUT Output Capacitance @ 55MHz 6 pF LPIN Pin Inductance 5 nH ROUT Output Resistance CLK Outputs 3.0 kΩ Notes: 1. Single edge is monotonic when transitioning through region. All trademarks are property of their respective owners. 14-0045 6 PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output HCSL Output AC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C) Symbol Parameter FIN Input Frequency 25 MHz FOUT Output Frequency 100 MHz VOH Output High Voltage (1,2) VOL Output Low Voltage(1,2) VCPA Crossing Point Voltage(1,2) Absolute VCN Crossing Point Voltage Variation over all edges JCC Jitter, Cycle-to-Cycle(1,3) JRMS PCIe 2.0 RMS Jitter JRMS3.0 Conditions (1,2,4) 100 MHz HCSL output @ VDD = 3.3V Min. Typ. 660 800 -150 0 250 350 35 PCIe 2.0 Test Method @ 100MHz Output PCIe 3.0 RMS Jitter Max. 900 Unit mV mV 550 mV 140 mV 60 ps 3.1 ps PLL L-BW @ 2M & 5M 1st H3 1.75 3 ps PLL L-BW @ 2M & 4M 1st H3 2.18 3 ps PLL H-BW @ 2M & 5M 1st H3 0.45 1 ps PLL H-BW @ 2M & 4M 1st H3 0.45 1 ps 31.5 33 kHz MF Modulation Frequency Spread Spectrum 30 tOR Rise Time(1,2) From 0.175V to 0.525V 175 500 ps tOF Fall Time(1,2) From 0.525V to 0.175V 175 500 ps TDUTY-CYCLE Duty Cycle 45 55 % tSTABLE From power-up to VDD =3.3V From Power-up VDD =3.3V 3.0 ms tSPREAD Setting period after spread change Setting period after spread change 3.0 ms (1,3) Notes: 1. RL = 50-Ohm with CL = 2 pF 2. Single-ended waveform 3. Differential waveform 4. Measured at the crossing point Thermal Characteristics Symbol Parameter Conditions θJA Thermal Resistance Junction to Ambient Still air θJC Thermal Resistance Junction to Case Min. Typ. Max. Unit 57.70 °C/W 32.20 °C/W Recomended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500107, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500038, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm http://www.pericom.com/pdf/datasheets/se/FL.pdf All trademarks are property of their respective owners. 14-0045 7 PI6C557-01B RevB04/07/2014 PI6C557-01B PCIe 3.0 Clock Generator with 1 HCSL Output Packaging Mechanical: 16-Pin TQFN (ZH) DATE:12/26/13 DESCRIPTION: 16-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH (ZH16) REVISION: E DOCUMENT CONTROL #: PD-2047 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 14-0244 Ordering Information Ordering Code Package Code Package Type Operating Temperature PI6C557-01BZHIE ZH Pb-free & Green, 16-pin TQFN Industrial Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging All trademarks are property of their respective owners. 14-0045 8 PI6C557-01B RevB04/07/2014