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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS FIELD EFFECT TRANSISTOR NP109N04PUG SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION The NP109N04PUG is N-channel MOS Field Effect Transistor designed for high current switching applications. ORDERING INFORMATION PART NUMBER NP109N04PUG-E1-AY NP109N04PUG-E2-AY LEAD PLATING PACKING PACKAGE Pure Sn (Tin) Tape 800 p/reel TO-263 (MP-25ZP) typ. 1.5 g Note Note Note Pb-free (This product does not contain Pb in external electrode). FEATURES • Super low on-state resistance RDS(on) = 2.3 mΩ MAX. (VGS = 10 V, ID = 55 A) • High current rating ID(DC) = ±110 A (TO-263) ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 40 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V Drain Current (DC) (TC = 25°C) ID(DC) ±110 A ID(pulse) ±440 A Total Power Dissipation (TC = 25°C) PT1 220 W Total Power Dissipation (TA = 25°C) PT2 1.8 W Channel Temperature Tch 175 °C Tstg −55 to +175 °C IAR 60 A Drain Current (pulse) Note1 Storage Temperature Repetitive Avalanche Current Note2 Note2 Repetitive Avalanche Energy 360 EAR Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2. Tch ≤ 150°C, VDD = 20 V, RG = 25 Ω, VGS = 20 → 0 V mJ THERMAL RESISTANCE Channel to Case Thermal Resistance Rth(ch-C) 0.68 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) 83.3 °C/W The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D18590EJ2V0DS00 (2nd edition) Date Published December 2007 NS Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2007 NP109N04PUG ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 40 V, VGS = 0 V 1 μA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±100 nA Gate to Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 3.0 4.0 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 55 A 31 63 S Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 55 A <R> Input Capacitance Ciss VDS = 25 V, <R> Output Capacitance Coss VGS = 0 V, 980 1470 pF <R> Reverse Transfer Capacitance Crss f = 1 MHz 630 1140 pF Turn-on Delay Time td(on) VDD = 20 V, ID = 55 A, 47 103 ns Rise Time tr VGS = 10 V, 35 70 ns Turn-off Delay Time td(off) RG = 0 Ω 90 180 ns Fall Time tf 35 70 ns Total Gate Charge QG VDD = 32 V, 180 270 nC Gate to Source Charge QGS VGS = 10 V, 44 nC Gate to Drain Charge QGD ID = 110 A 64 nC Body Diode Forward Voltage VF(S-D) IF = 110 A, VGS = 0 V 0.9 Reverse Recovery Time trr IF = 110 A, VGS = 0 V, 56 ns Reverse Recovery Charge Qrr di/dt = 100 A/μs 80 nC TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω 2.3 mΩ 10500 15750 1.4 pF V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω PG. VGS = 20 → 0 V 1.7 RL RG PG. VDD VGS VGS Wave Form 0 VGS 10% 90% VDD VDS 90% IAS VDS ID VDS τ τ = 1 μs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 2 50 Ω 0 10% 10% tr td(off) Wave Form VDD Starting Tch 90% VDS VGS 0 BVDSS RL VDD Data Sheet D18590EJ2V0DS td(on) ton tf toff NP109N04PUG TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 250 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 120 100 80 60 40 20 200 150 100 50 0 0 0 25 50 75 100 125 150 175 0 25 TC - Case Temperature - °C 50 75 100 125 150 175 TC - Case Temperature - °C FORWARD BIAS SAFE OPERATING AREA 1000 ID(pulse) PW 100 0 μs i s m d it e 1i 0 m Li n s ow m d k 1i a re d B it e y m ar Li nd n co t io Se pa si is D er DC RDS(on) Limited (VGS = 10 V) w Po i 10 1 TC = 25°C Single pulse 0.1 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 100 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A =1 i0 ID(DC) Rth(ch-A) = 83.3°C/Wi 10 1 Rth(ch-C) = 0.68°C/Wi 0.1 Single pulse 0.01 100 μ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet D18590EJ2V0DS 3 NP109N04PUG DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 1000 500 ID - Drain Current - A ID - Drain Current - A 400 300 VGS = 10 V 200 Tch = −55°C 25°C 75°C 150°C 175°C 100 10 1 100 VDS = 10 V Pulsed Pulsed 0.1 0 0.2 0.4 0.6 0.8 0 1 1 2 5 6 GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 3.5 3 2.5 2 1.5 1 VDS = VGS ID = 250 μA 0.5 0 -100 -50 0 50 100 150 100 150°C 175°C 10 Tch = −55°C 25°C 75°C 1 VDS = 10 V Pulsed 0.1 0.1 200 1 Pulsed 3 VGS = 10 V 1 0 1 10 100 100 1000 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ 4 2 10 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT RDS(on) - Drain to Source On-state Resistance - mΩ 4 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C ID - Drain Current - A 4 3 VGS - Gate to Source Voltage - V | yfs | - Forward Transfer Admittance - S VGS(th) - Gate to Source Threshold Voltage - V 0 10 ID = 55 A Pulsed 5 0 0 5 10 15 VGS - Gate to Source Voltage - V Data Sheet D18590EJ2V0DS 20 NP109N04PUG <R> 5 CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 100000 VGS = 10 V ID = 55 A 3 2 1 Pulsed 0 -100 -50 0 50 100 150 Ciss 10000 Coss 1000 VGS = 0 V f = 1 MHz 100 0.01 200 SWITCHING CHARACTERISTICS 1 10 100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 40 1000 tf VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 0.1 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C td(off) 100 td(on) tr 10 VDD = 20 V VGS = 10 V RG = 0 Ω 12 VDD = 32 V 20 V 8V 35 30 9 25 20 10 3 VDS 5 ID = 110 A 0 1 10 0 100 50 100 150 ID - Drain Current - A QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 6 VGS 15 1 0.1 0 200 100 trr - Reverse Recovery Time - ns IF - Diode Forward Current - A Crss VGS - Gate to Source Voltage - V 4 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 100 VGS = 10 V 0V 10 1 Pulsed 0.1 di/dt = 100 A/μs VGS = 0 V 10 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V Data Sheet D18590EJ2V0DS 0.1 1 10 100 1000 IF - Diode Forward Current - A 5 NP109N04PUG PACKAGE DRAWING (Unit: mm) 10.0 ±0.3 7.88 MIN. 4.45 ±0.2 1.3 ±0.2 0.5 9.15 ±0.3 8.0 TYP. 4 15.25 ±0.5 No plating 1.35 ±0.3 TO-263 (MP-25ZP) 0.025 to 0.25 .2 0 to 8 ˚ 0.25 1 2 3 2.5 2.54 1. Gate 2. Drain 3. Source 4. Fin (Drain) 2.54 ±0.25 0.6 ±0 0.75 ±0.2 EQUIVALENT CIRCUIT Drain Body Diode Gate Source Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. 6 Data Sheet D18590EJ2V0DS NP109N04PUG TAPE INFORMATION There are two types (-E1, -E2) of taping depending on the direction of the device. Draw-out side Reel side MARKING INFORMATION NEC 109N04 UG Pb-free plating marking Abbreviation of part number Lot code RECOMMENDED SOLDERING CONDITIONS The NP109N04PUG should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Recommended Soldering Method Soldering Conditions Condition Symbol Infrared reflow Maximum temperature (Package's surface temperature): 260°C or below IR60-00-3 Time at maximum temperature: 10 seconds or less Time of temperature higher than 220°C: 60 seconds or less Preheating time at 160 to 180°C: 60 to 120 seconds Maximum number of reflow processes: 3 times Maximum chlorine content of rosin flux (percentage mass): 0.2% or less Partial heating Maximum temperature (Pin temperature): 350°C or below P350 Time (per side of the device): 3 seconds or less Maximum chlorine content of rosin flux: 0.2% (wt.) or less Caution Do not use different soldering methods together (except for partial heating). Data Sheet D18590EJ2V0DS 7 NP109N04PUG • The information in this document is current as of December, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1