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DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2712GR SWITCHING P-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA2712GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. 8 5 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain FEATURES • Low on-state resistance RDS(on)1 = 13 mΩ MAX. (VGS = −10 V, ID = −5.0 A) RDS(on)2 = 21 mΩ MAX. (VGS = −4.5 V, ID = −5.0 A) RDS(on)3 = 26 mΩ MAX. (VGS = −4.0 V, ID = −5.0 A) • Low Ciss: Ciss = 2000 pF TYP. • Small and surface mount package (Power SOP8) PART NUMBER PACKAGE µPA2712GR 6.0 ±0.3 4 4.4 0.8 +0.10 –0.05 5.37 MAX. 0.15 0.05 MIN. ORDERING INFORMATION 1.44 1.8 MAX. 1 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M Power SOP8 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS −30 V Gate to Source Voltage (VDS = 0 V) VGSS m20 V Drain Current (DC) ID(DC) m10 A Note1 ID(pulse) m40 A Total Power Dissipation Note2 PT1 2 W Total Power Dissipation Note3 PT2 2 W Tch 150 °C Drain Current (pulse) Channel Temperature Tstg −55 to +150 °C Single Avalanche Current Note4 IAS −10 A Single Avalanche Energy Note4 EAS 10 mJ Storage Temperature EQUIVALENT CIRCUIT Drain Body Diode Gate Source Notes 1. 2. 3. 4. PW ≤ 10 µs, Duty Cycle ≤ 1% 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec Starting Tch = 25°C, VDD = −15 V, RG = 25 Ω, L = 100 µH, VGS = −20 → 0 V Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. Document No. G15980EJ2V0DS00 (2nd edition) Date Published November 2002 NS CP(K) Printed in Japan The mark ! shows major revised points. 2002 µPA2712GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = −30 V, VGS = 0 V −1 µA Gate Leakage Current IGSS VGS = m20 V, VDS = 0 V m100 nA VGS(off) VDS = −10 V, ID = −1 mA −1.0 −2.5 V | yfs | VDS = −10 V, ID = −5.0 A 7 RDS(on)1 VGS = −10 V, ID = −5.0 A 10 13 mΩ RDS(on)2 VGS = −4.5 V, ID = −5.0 A 15 21 mΩ RDS(on)3 VGS = −4.0 V, ID = −5.0 A 19 26 mΩ Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance 15 S Input Capacitance Ciss VDS = −10 V 2000 pF Output Capacitance Coss VGS = 0 V 550 pF Reverse Transfer Capacitance Crss f = 1 MHz 340 pF Turn-on Delay Time td(on) VDD = −15 V, ID = −5.0 A 10 ns VGS = −10 V 16 ns RG = 10 Ω 92 ns 51 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDD = −24 V 42 nC Gate to Source Charge QGS VGS = −10 V 6 nC Gate to Drain Charge QGD ID = 10 A 12 nC Body Diode Forward Voltage VF(S-D) IF = 10 A, VGS = 0 V 0.82 V Reverse Recovery Time trr IF = 10 A, VGS = 0 V 46 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 33 nC TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = −20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VDD VGS(−) RL Wave Form RG PG. VGS 0 VGS 10% 90% VDD VDS(−) 90% BVDSS IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE 2 10% 0 10% Wave Form VDD PG. 90% VDS VGS(−) 0 D.U.T. IG = −2 mA RL 50 Ω VDD Data Sheet G15980EJ2V0DS td(on) tr ton td(off) tf toff µPA2712GR TYPICAL CHARACTERISTICS (TA = 25°C) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 120 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on ceramic substrate of 2 1200 mm x 2.2 mm 2.4 2 1.6 1.2 0.8 0.4 0 0 0 25 50 75 100 125 150 175 0 25 TA - Ambient Temperature - °C 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA - 100 ID - Drain Current - A ID(pulse) PW = 100 µs ID(DC) - 10 1 ms RDS(on) Limited (at VGS = 10 V) 10 ms -1 100 ms Power Dissipation Limited - 0.1 DC TA = 25°C Single Pulse Mounted on ceramic substrate of 2 1200 mm x 2.2 mm - 0.01 - 0.01 - 0.1 -1 - 10 - 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH ★ rth(t) - Transient Thermal Resistance - °C/W 1000 Rth(ch-A) = 62.5°C/W 100 10 1 0.1 Single Pulse 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm TA = 25°C 0.01 100 µ 1m 10 m 100 m 1 PW - Pulse Width - s Data Sheet G15980EJ2V0DS 10 100 1000 3 µPA2712GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS - 100 - 40 VGS = −10 V ID - Drain Current - A ID - Drain Current - A - 50 −4.5 V −4.0 V - 30 - 20 - 10 Tch = −55°C 25°C 75°C 150°C -1 - 0.1 - 10 VDS = −10 V Pulsed Pulsed 0 - 0.01 0 - 0.2 - 0.4 - 0.6 - 0.8 -1 - 1.2 0 -5 100 - 2.5 -2 - 1.5 -1 - 0.5 VDS = −10 V ID = −1 mA 0 50 100 150 | yfs | - Forward Transfer Admittance - S VGS(off) - Gate Cut-off Voltage - V -4 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT -50 Tch = −55°C 25°C 75°C 150°C 10 1 VDS = −10 V Pulsed 0.1 - 0.1 Tch - Channel Temperature - °C DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed 30 20 VGS = −4.0 V −4.5 V 10 −10 V 0 - 0.1 -1 - 10 -1 - 10 - 100 ID - Drain Current - A - 100 RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ -3 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 0 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 Pulsed 30 20 ID = −5.0 A 10 0 ID - Drain Current - A 4 -2 VGS - Gate to Source Voltage - V -3 40 -1 VDS - Drain to Source Voltage - V Data Sheet G15980EJ2V0DS 0 -5 - 10 - 15 VGS - Gate to Source Voltage - V - 20 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 30 10000 Ciss, Coss, Crss - Capacitance - pF VGS = −4.0 V 25 20 −4.5 V 15 −10 V 10 5 1000 Coss Crss 100 ID = −5.0 A Pulsed VGS = 0 V f = 1 MHz 0 -50 0 50 100 10 - 0.01 150 Tch - Channel Temperature - °C SWITCHING CHARACTERISTICS -1 - 10 - 100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS - 15 VDS - Drain to Source Voltage - V - 30 td(off) 100 tf tr 10 td(on) VDD = −15 V VGS = −10 V RG = 10 Ω 1 - 0.1 -1 - 10 VDD = −24 V −15 V −6 V - 20 - 10 VGS -5 - 10 VDS 0 0 - 100 0 ID - Drain Current - A 10 20 30 40 50 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 1000 100 trr - Reverse Recovery Time - ns IF - Diode Forward Current - A - 0.1 VDS - Drain to Source Voltage - V 1000 td(on), tr, td(off), tf - Switching Time - ns Ciss VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ µPA2712GR VGS = −10 V 0V 10 1 0.1 100 10 di/dt = 100 A/µs VGS = 0 V Pulsed 0.01 1 0 0.2 0.4 0.6 0.8 1 1.2 0.1 1.4 VF(S-D) - Source to Drain Voltage - V 1 10 100 IF - Diode Forward Current - A Data Sheet G15980EJ2V0DS 5 µPA2712GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 100 IAS = −10 A - 10 EAS = 10 mJ -1 VDD = −15 V RG = 25 Ω VGS = −20 → 0 V Starting Tch = 25°C - 0.1 0.01 VDD = −15 V RG = 25 Ω VGS = −20 → 0 V IAS ≤ −10 A 80 60 40 20 0 0.1 1 L - Inductive Load - mH 6 Energy Derating Factor - % IAS - Single Avalanche Current - A - 100 25 10 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C Data Sheet G15980EJ2V0DS µPA2712GR [MEMO] Data Sheet G15980EJ2V0DS 7 µPA2712GR • The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11