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DATA SHEET MOS INTEGRATED CIRCUIT µPD703177(A) / µPD703445(A) V850E/CG2TM CarGate-F / V850E/CG5TMCarGate-S 32-/16-BIT ROMLESS MICROCONTROLLER DESCRIPTION The V850E/CG2 (“CarGate-F“) and V850E/CG5 (“CarGate-S”) ROM-less microcontroller, are members of NEC's V850 32-bit RISC family, which match the performance gains attainable with RISC-based controllers to the needs of embedded control applications. The V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs. The V850E/CG2 (“CarGate-F“) and V850E/CG5 (“CarGate-S”) are specially designed for the high performance requirements of sophisticated algorithms and calculations. They combine a powerful CPU-Core with a 32-bit wide external memory interface and iCache. The V850E/CG2 (“CarGate-F“) has an additional hardware FPU. Furthermore, they offer an excellent combination of general purpose peripheral functions, like serial communication interfaces (UART, clocked SI) and measurement inputs (A/D converter), with dedicated CAN network support. Thus equipped, the V850E/CG2 (“CarGate-F“) and V850E/CG5 (“CarGate-S”) are ideally suited for automotive applications, like CAN Gateways. They are also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required. FEATURES • • • • • • • 32-bit RISC CPU with Harvard Architecture 8 K iCache (2-way associative) Full-CAN Interface: 5 channels Serial Interfaces: 5 channels - 3-wire mode: 3 channels - UART mode: 2 channels Timers: 2 channels - 16-bit multi purpose timer/event counter: channels: 2 channels 10-bit resolution A/D Converter: 6 channels External Bus Interface (32- / 16- / 8-bit data / 24-bit address) • • • • • • • • I/O lines: max. 71 - 5 V tolerant: 13 × Power supply voltage range: - +3.0 V ≤ VDD3 ≤ +3.6 V Frequency range: up to 40 MHz Built-in low power saving mode Built-in clock oscillator circuit with internal PLL Built-in clock oscillator circuit with internal spread spectrum PLL for CPU/ BCU clock operation Temperature range: - -40 °C to +85 °C Package: - 144 LQFP, 0.5 mm pin-pitch (20 × 20 mm) ORDERING INFORMATION Device Part Number V850E/CG2 µPD703177(A) V850E/CG5 µPD703445(A) RAM FCAN Option Operating Temperature (TA) LQFP144 20 × 20 mm ROM-less 32 K 5 Channels -40°C ~ +85°C LQFP144 20 × 20 mm ROM-less 32 K 5 Channels -40°C ~ +85°C Package ROM The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. NEC Electronics Corporation 2006 Document No. U16637EE1V0DS00 Data Published: February 2006 µPD703177(A) / µPD703445(A) INTERNAL BLOCK DIAGRAM Figure IN-1: NMI INTP0-9 V850E/CG2 CarGate-F / V850E/CG5 CarGate-S Internal Block Diagram Interrupt Controller CPU Core PC TIC00, TIC01 TOC0 TIC10, TIC11 TOC1 FCRxD01 16-bit timer TMC 0 8 kB iCache barrel shifter hardware multiplier general registers 32 kB RAM A L U External Memory Controller (MEMC) FCTxD01 FCRxD02 FCAN 02 FCTxD02 FCRxD03 FCTxD03 FCRxD11 Note system registers 16-bit timer TMC 1 FCAN 01 FPU FCAN 03 Bus control Unit (BCU) internal peripheral bus FCAN 11 FCTxD11 power supply FCAN 12 FCTxD12 TXD61 BRG UART61 BRG SI00 SO00 SCK00 CSI00 SI01 SO01 SCK01 CSI01 SI02 SO02 SCK02 CSI02 BRG0 BRG1 AVSS RXD61 Bootstrap Loader Oscillator and clock generator with Spread Spectrum PLL, PLL System control CVSS CVDD PCLKOUT X1 X2 RESET MODE2 MODE1 MODE0 Note: The Floating Point Unit is only available on V850E/CG2 (“CarGate-F”) 2 VDD VSS AVDD TXD60 Ports UART60 ANI0 to ANI5 RXD60 10-bit A/D 6 channels AVRef FCRxD12 DATA SHEET U16637EE1V0DS00 bus interface µPD703177(A) / µPD703445(A) PIN IDENTIFICATION A0 to A23 Address Bus PCLKOUT Peripheral Clock Output D0 to D31 Data Bus PCM0 Port CM0 ANI0 to ANI5 Analog Input PCS0-PCS4, PCS6 Port CS AVDD Analog Power Supply PCT0, PCT1, PCT4, PCT5 Port CT AVREF Analog Reference Voltage PCD2 to PCD5 Port CD AVSS Analog Ground PDH0 to PDH16 Port DH CVDD Clock Generator Power Supply RXD60 to RXD61 Receive Data Input CVSS Clock Generator Ground SCK00 to SCK02 Serial Clock FCRXD01 to FCRXD03 CAN Receive Line Input 0 SI00 to SI02 Serial Input FCTXD01 to FCTXD03 CAN Transmit Line Output0 SO00 to SO02 Serial Output FCRXD11 to FCRXD12 CAN Receive Line Input 1 TIC00, TIC01, TIC10, TIC11 Timer Input FCTXD11 to FCTXD12 CAN Transmit Line Output1 TOC0, TOC1 Timer Output GND3 Ground for 3 V Power Supply TXD60 to TXD61 Transmit Data Output INTP0 to INTP9 External interrupt request VDD3 3 V Power Supply MODE0 to MODE2 Mode Inputs RESET Reset NMI Non-Maskable Interrupt Request WAIT Wait P10 to P17 Port 1 WRZ, WRZ0, WRZ1 Write Enable P20 to P27 Port 2 RDZ Read P30 to P37 Port 3 CS0-CS4, CS6 Chip Select P40 to P47 Port 4 X1, X2 Crystal (Main-OSC) P70 to P75 Port 7 DATA SHEET U16637EE1V0DS00 3 µPD703177(A) / µPD703445(A) PIN CONFIGURATION (Top View) • 144 pin QFP (fine pitch) (20 × 20 × 1.4 mm) - µPD703177(A) - µPD703445(A) V850E/CG2 CarGate-F / V850E/CG5 CarGate-S Pin Configuration 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 MODE2 MODE1 MODE0 D31/PDH15 D30/PDH14 D29/PDH13 D28/PDH12 D27/PDH11 VSS311 VDD311 D26/PDH10 D25/PDH9 D24/PDH8 D23/PDH7 D22/PDH6 D21/PDH5 D20/PDH4 VSS310 VDD310 D19/PDH3 D18/PDH2 D17/PDH1 D16/PDH0 D15 D14 D13 VSS39 VDD39 D12 D11 Figure IN-2: 1 2 3 4Note 5Note 6Note 7Note 8Note 9Note 10Note 11 12 13Note 14Note 15Note 16Note 17Note 18Note 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 V850E/CG2 " CarGate-F" V850E/CG5 " CarGate-S" P23/SI01 P32/TOC0/INTP2 P27/TXD60 P26/RXD60/INTP8 P31/TIC01/INTP1 CVDD CVSS X1 X2 RESET PCM0/WAIT PCD5/BEN3 PCD4/BEN2 PCD3/BEN1 PCD2/BEN0 PCT5/WR PCT4/RD VDD33 VSS33 PCT1/WR1 PCT0/WR0 PCS6/CS6 PCS4/CS4 PCS3/CS3 PCS2/CS2 VDD34 VSS34 PCS1/CS1 PCS0/CS0 A0 A1 A2 A3 A4 VDD35 VSS35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 AVREF AVDD AVSS P33/TIC10/INTP3 P34/TIC11/INTP4 P36/INTP6 P37/INTP7 P47/NMI P10/CRXD01 P11/CTXD01 VDD30 VSS30 P35/TOC1/INTP5 P41/CTXD11 P40/CRXD11 P46/SCK02 P45/SO02 P44/SI02 VDD31 VSS31 P16/RXD61/INTP9 P17/TXD61 P12/CRXD02 P13/CTXD02 P14/CRXD03 P15/CTXD03 P42/CRXD12 P43/CTXD12 VDD32 VSS32 P30/TIC00/INTP0/PCLKOUT P22/SCK00 P21/SO00 P20/SI00 P25/SCK01 P24/SO01 Note: Marked Pins are 5 V tolerant 4 DATA SHEET U16637EE1V0DS00 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 D10 D9 D8 D7 D6 D5 D4 VSS38 VDD38 D3 D2 D1 D0 A23 A22 A21 A20 VSS37 VDD37 A19 A18 A17 A16 A15 A14 A13 A12 VSS36 VDD36 A11 A10 A9 A8 A7 A6 A5 µPD703177(A) / µPD703445(A) Table of Contents INTERNAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PIN IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONFIGURATION (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 1.3 2. Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Non-Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Programming External Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 3.2 3.3 3.4 3.5 3.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 Oscillator recommendations (main system clock oscillator) . . . . . . . . . . . . . . . . . . 18 3.2.2 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 Peripheral PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 Spread spectrum PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.5 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 Peripheral clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.2 CPU/BCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.2 AC test load condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.3 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.4 External memory access read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.5 External memory access write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.6 RESET (power up/down sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.7 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Peripheral Function Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.1 Timer C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.2 CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.3 UART6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.4 FCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.5 Serial flash programming operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.6 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4. Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5. Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DATA SHEET U16637EE1V0DS00 5 µPD703177(A) / µPD703445(A) List of Figures Figure IN-1: Figure IN-2: Figure 1-1: Figure 2-1: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 3-11: Figure 3-12: Figure 4-1: 6 V850E/CG2 CarGate-F / V850E/CG5 CarGate-S Internal Block Diagram.................... 2 V850E/CG2 CarGate-F / V850E/CG5 CarGate-S Pin Configuration ............................ 4 Input / Output Circuits (1/2) ......................................................................................... 14 Programming Mode Selection Format......................................................................... 16 Main Oscillator Recommendations.............................................................................. 18 AC Test Input/Output Waveform SCHMITT ................................................................ 24 AC Test Input/Output Waveform CMOS...................................................................... 24 AC Test Load Condition .............................................................................................. 24 Clock Timing................................................................................................................ 25 External Memory Access Read Timing ....................................................................... 27 External Memory Access Write Timing........................................................................ 29 RESET Timing............................................................................................................. 30 Interrupt Timing ........................................................................................................... 31 Timer C Characteristics ............................................................................................... 32 CSI Slave Mode Characteristics.................................................................................. 34 Serial Flash Programming Operating Characteristics ................................................. 35 Package Drawing ........................................................................................................ 37 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) List of Tables Table 1-1: Table 1-2: Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 3-7: Table 3-8: Table 3-9: Table 3-10: Table 3-11: Table 3-12: Table 3-13: Table 3-14: Table 3-15: Table 3-16: Table 3-17: Table 3-18: Table 3-19: Table 3-20: Table 3-21: Table 5-1: Pin Function...................................................................................................................... 9 Non-Port Pins ................................................................................................................. 11 Absolute Maximum Ratings (TA = 25°C, VSS3x = 0 V) ................................................... 17 Main Oscillator Characteristics ....................................................................................... 19 Peripheral PLL Characteristics ....................................................................................... 19 Spread Spectrum PLL Characteristics ........................................................................... 19 Capacitances.................................................................................................................. 20 Peripheral Clock ............................................................................................................. 21 CPU/BCU Clock ............................................................................................................. 21 DC Characteristics Conditions........................................................................................ 22 Power Supply Currents................................................................................................... 23 Clock Timing................................................................................................................... 25 External Memory Access Read Timing .......................................................................... 26 External Memory Access Write Timing........................................................................... 28 RESET Timing................................................................................................................ 30 Interrupt Timing .............................................................................................................. 31 Timer C Characteristics .................................................................................................. 32 CSI Master Mode Characteristics................................................................................... 33 CSI Slave Mode Characteristics..................................................................................... 33 UART Characteristics ..................................................................................................... 34 FCAN Characteristics ..................................................................................................... 34 Serial Flash Programming Operating Characteristics .................................................... 35 A/D Converter Characteristics ........................................................................................ 36 Soldering Conditions ...................................................................................................... 38 DATA SHEET U16637EE1V0DS00 7 µPD703177(A) / µPD703445(A) 8 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 1. Pin Functions 1.1 Port Pins Table 1-1: Port I/O Function Pin Function (1/2) Port Type Alternate P10 5-K CRXD01Note P11 5-K/ 19 CTXD01Note P12 5-K CRXD02 5-K CTXD02 5-K CRXD03 P15 5-K CTXD03 P16 5-K RXD61/INTP9 P17 5-K TXD61 P20 5-K SI00 P21 5-K SO00 P22 5-K SCK00 5-K SI01 5-K SO01 P25 5-K SCK01 P26 5-K RXD60/INTP8 P27 5-K TXD60 P30 5-K TIC00/INTP0/ PCLKOUT P31 5-K TIC01/ INTP1 P32 5-K TOC0 / INTP2 5-K TIC10/INTP3Note 5-K TIC11 / INTP4Note P35 5-K TOC1 / INTP5Note P36 5-K INTP6Note P37 5-K INTP7Note P40 5-K CRXD11Note P41 5-K / 19 CTXD11Note P42 5-K CRXD12 5-K CTXD12 5-K SI02Note P45 5-K SO02Note P46 5-K SCK02Note P47 5-K NMINote P13 I/O P14 P23 P24 P33 I/O I/O P34 P43 P44 I/O Port 1 8-bit input/output port Port 2 8-bit input/output port Port 3 8-bit input/output port Port 4 8-bit input/output port Note: Marked pins are 5 V tolerant DATA SHEET U16637EE1V0DS00 9 µPD703177(A) / µPD703445(A) Table 1-1: Port I/O Pin Function (2/2) Function Port Type Alternate P70 ANI0 P71 ANI1 P72 P73 I Port 7 6-bit input port 9-C ANI2 ANI3 P74 ANI4 P75 ANI5 PDH0 D16 PDH1 D17 PDH2 D18 PDH3 D19 PDH4 D20 PDH5 D21 PDH6 D22 PDH7 PDH8 I/O Port DHNote 16-bit input/output port 5 D23 D24 PDH9 D25 PDH10 D26 PDH11 D27 PDH12 D28 PDH13 D29 PDH14 D30 PDH15 D31 PCS0 CS0 PCS1 CS1 PCS2 PCS3 I/O Port CS 6-bit input/output port 5 CS2 CS3 PCS4 CS4 PCS6 CS6 PCD2 BEN0 PCD3 PCD4 I/O Port CD 4-bit input/output port 5 PCD5 PCM0 PCT4 I/O Port CM 1-bit input/output port 5 WAIT WR0 I/O Port CT 4-bit input/output port 5 PCT5 WR1 RD WR Note: PDH is only available for ROM-less mode 1 (16-bit wide external bus at reset) 10 BEN2 BEN3 PCT0 PCT1 BEN1 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 1.2 Non-Port Pins Table 1-2: Non-Port Pins (1/3) Pin Name I/O VDD30-VDD36Note 2 – Power supply 3.3 V - - VSS30-VSS36 – GND potential for 3.3 V power supply - - CVDDNote 3 – Connection for 3.3 V clock oscillator power supply - - GND potential for 3.3 V clock oscillator power supply - - 16 - 16 - CVSS Function X1 input X2 output PCKLOUT output Peripheral clock output System clock oscillator connection pins. Port Type 5-K Alternate P30 / INTP0 MODE0-MODE2 input Selects operating mode 2 - RESET input System reset input 2 - AVDD – Power supply for A/D converter - - AVSS – Ground potential for A/D converter - - AVREF input reference voltage input for A/D converter - - NMINote 1 input non maskable interrupt input 5-K P47 ANI0-ANI5 input analog input to A/D converter 9-C P70 to P75 5-K P20 5-K P23 SI02Note 1 5-K P44 SO00 5-K P21 5-K P24 SO02Note 1 5-K P45 SCK00 5-K P22 5-K P25 5-K P46 5-K P26 / INTP8 5-K P16 / INTP9 5-K P27 5-K P17 5-K P10 5-K P12 5-K P14 5-K P40 5-K P42 SI00 SI01 input SO01 serial receive data input to CSI00-CSI02 output serial transmit data output from CSI00-CSI02 SCK01 I/O serial clock I/O from/to CSI00-CSI02 SCK02Note 1 RXD60 input RXD61 TXD60 serial receive data input to UART60-UART61 output serial transmit data output from UART60-UART61 TXD61 CRXD01Note 1 CRXD02 input serial receive data input to FCAN01-FCAN03 CRXD03 CRXD11Note 1 input serial receive data input to FCAN11-FCAN12 CRXD12 Notes: 1. Marked pins are 5 V tolerant 2. All VDD3 pins have to be connected to each other. On each pin VDD3, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin 3. On CVDD, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin. VDD3 and CVDD must be connected to each other 4. PDH is only available for ROM-less mode 1 (16-bit wide ext. bus at reset) DATA SHEET U16637EE1V0DS00 11 µPD703177(A) / µPD703445(A) Table 1-2: Pin Name CTXD01Note 1 I/O Non-Port Pins (2/3) Function output serial transmit data output to FCAN01-FCAN03 CTXD02 CTXD03 CTXD11Note 1 output serial transmit data output to FCAN01-FCAN03 CTXD12 Port Type Alternate 5-K / 19 P11 5-K P13 5-K P15 5-K / 19 P41 5-K P43 INTP0 P30 / TIC00/ PCKLOUT INTP1 P31 / TIC01 INTP2 P32 / TOC0 Note 1 P33 / TIC10 INTP3 INTP4Note 1 input external interrupt request 5-K P34 / TIC11 INTP5Note 1 P35 / TOC1 INTP6Note 1 P36 INTP7Note 1 P37 INTP8 P26/RXD60 INTP9 P16/RXD61 TIC00 input Timer C 0 capture input 0 5-K P30/INTP0/ PCKLOUT TIC01 input Timer C 0 capture input 1 5-K P31/INTP1 TOC0 output Timer C 0 compare output 1 5-K P32/INTP2 TIC10Note 1 input Timer C 1 capture input 0 5-K P33/INTP3 TIC11Note 1 input Timer C 1 capture input 1 5-K P34/INTP4 TOC1Note 1 output Timer C 1 compare output 1 5-K P35/INTP5 D0-D15 I/O D16-D31 I/O Data bus of external busNote 4 5 - 5 PDH0-PDH15 A0-A7 - A8-A15 output Address bus of external bus 3 - A16-A23 - WR0 output Write strobe signal for lower byte (bit 0 - bit 7) 5 PCT0 WR1 output Write strobe signal for upper byte (bit 0 - bit 7) 5 PCT1 RD output Read strobe signal for external bus 5 PCT4 WR output Write strobe signal for external bus 5 PCT5 WAIT input Control signal input for external bus 5 PCM0 Notes: 1. Marked pins are 5 V tolerant 2. All VDD3 pins have to be connected to each other. On each pin VDD3, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin 3. On CVDD, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin. VDD3 and CVDD must be connected to each other 4. PDH is only available for ROM-less mode 1 (16-bit wide ext. bus at reset) 12 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) Table 1-2: Pin Name I/O Non-Port Pins (3/3) Function Port Type Alternate CS0 PCS0 CS1 PCS1 CS2 CS3 output Chip select output for external bus 5 PCS2 PCS3 CS4 PCS4 CS6 PCS6 BEN0 PCD2 BEN1 BEN2 output Byte enable for external bus BEN3 5 PCD3 PCD4 PCD5 Notes: 1. Marked pins are 5 V tolerant 2. All VDD3 pins have to be connected to each other. On each pin VDD3, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin 3. On CVDD, a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin. VDD3 and CVDD must be connected to each other 4. PDH is only available for ROM-less mode 1 (16-bit wide ext. bus at reset) DATA SHEET U16637EE1V0DS00 13 µPD703177(A) / µPD703445(A) 1.3 I/O Circuits Figure 1-1: Input / Output Circuits (1/2) Type 2 Type 3 V DD P-ch Data IN OUT N-ch Type 5 Type 4 VDD V DD Data data IN/OUT P-ch IN/OUT Output disable output disable N-ch input enable 14 P-ch DATA SHEET U16637EE1V0DS00 N-ch µPD703177(A) / µPD703445(A) Figure 1-1: Input / Output Circuits (2/2) Type 9-C Type 5-K V DD Data P-ch P-ch IN/OUT Output disable Comparator + - IN N-ch N-ch AVSS VREF (threshold voltage) V SS Input enable Input enable Type 16 Type 19 feedback cut-off P-ch OUT N-ch Input Output DATA SHEET U16637EE1V0DS00 15 µPD703177(A) / µPD703445(A) 2. Programming External Flash Memory The devices µPD703177(A) and µPD703445(A) support the programming of external flash memories using 2 dedicated flash-programming mode (ROM-less mode0 & ROM-less mode1), dependent on the used bus width for external flash access. These modes will be entered if the MODE pins have been configured accordingly and in addition a system reset has been performed. In the flash-programming mode, an integrated Boot-Loader is enabled to download the programming and control algorithms to the CarGate-F’s and CarGate-S’s iRAM. This feature offers a high flexibility to be able to program various external flash memories. Naturally, it is also possible to program the external flash memory by performing self-programming software functions and I/O communications. For programming details, see the User’s Manual. Figure 2-1: Programming Mode Selection Format VDD3 VDD3 0V ROM-less mode1 VDD3 MODE0 ROM-less mode0 0V VDD3 MODE1 0V VDD3 RESET(input) 0V Note: Refer to the chapter “RESET (power up/down sequence)” on page 30. 16 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 3. Electrical Specifications 3.1 Absolute Maximum Ratings Table 3-1: Absolute Maximum Ratings (TA = 25°C, VSS3x = 0 V) Parameter Symbol Supply voltage Input voltage Test Conditions Unit -0.5 ~ +4.6 V AVSS -0.5 ~ +0.5 V VDD3 -0.5 ~ +4.6 V CVDD -0.5 ~ +4.6 V CVSS -0.5 ~ +0.5 V 5 V tolerant pinsNote 1 VI4 VI4 < VDD3 + 3.0 V -0.5 ~ +6.6 V 3.3 V pinsNote 2 VI3 VI3 < VDD3 + 0.5 V -0.5 ~+4.6 V VIAVREF < AVDD +0.3 V -0.3 ~ +4.6 V VIA < AVDD + 0.3 V -0.3 ~ +4.6 V AVREF VIAVREF P7 VIA 1 pin IOL0 4.0 mA All pins IOL1 50 mA 1 pin IOH0 -4.0 mA All pins IOH1 -50 mA -0.5 ~ +4.6 V Output current low Output current high Output voltage Ratings AVDD 3.3 V pinsNote 2 VO1 VO1 < VDD3 + 0.5 V Operating temperature TOPR -40 ~ +85 °C Storage temperature TSTGB -55 ~ +150 °C Notes: 1. 5 V tolerant pins are P10, P11, P33, P34, P35, P36, P37, P40, P41, P44, P45, P46, P47 2. 3.3 V pins are Ax, Dx, PCSx, PCM0, PCTx, MODEx, PCDx, P12~P17, P2x, P30~P32, P42, P43, RESET DATA SHEET U16637EE1V0DS00 17 µPD703177(A) / µPD703445(A) 3.2 General Characteristics 3.2.1 Oscillator recommendations (main system clock oscillator) (1) Ceramic resonator or crystal resonator connection Figure 3-1: Main Oscillator Recommendations X1 X2 QU C1' Remark: R1' C2' Values of capacitors C1’, C2’ and R1’ depend on used resonator and must be specified in cooperation with the manufacturer. Cautions: 1. External clock input is prohibited. 2. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. • 18 Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always make the ground point of the oscillator capacitor the same potential as VSS. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 3.2.2 Oscillator characteristics (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-2: Parameter Symbol Main Oscillator Characteristics Test Conditions MIN. Oscillation stabilization time TOST 500Note Main oscillator frequency fOSC 4 TYP. MAX. Unit ns 5 MHz Note: The above specified value is the time needed to stabilize internally. It does not include the stabilization time of the external crystal. This value is specified for an external quartz which reached 10% / 90% maximum oscillation level. The oscillation stabilization time for the external crystal has to be added to above specified value. 3.2.3 Peripheral PLL characteristics (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-3: Parameter Symbol PLL lock time TPLL Peripheral PLL Characteristics Test Conditions MIN. TYP. MAX. Unit 1 ms 3.2.4 Spread spectrum PLL characteristics (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-4: Parameter Spread Spectrum PLL Characteristics Symbol SSCG lock time TSSCG Frequency multiplicationNote 1 MSSCG Frequency modulationNote 2 Test Conditions MIN. TYP. MAX. Unit 3 ms FOSC = 4 MHz 60/3 - FOSC = 5 MHz 48/3 - Dithering enabled 1 % Notes: 1. Frequency multiplication is given as n/m where n means setup values for register SCFC0/SCFC1and m means divider factor determined by register SCFMC Please refer to CarGate-F UM. 2. Frequency modulation is determined by register values of SCFC0 and SCFC1. DATA SHEET U16637EE1V0DS00 19 µPD703177(A) / µPD703445(A) 3.2.5 Capacitances (TA = 25°C, VDD3x = VSS3x = CVDD = CVSS = AVDD = AVSS = 0 V) Table 3-5: Parameter Input capacitance Symbol CI Input/output capacitance CIO Output capacitance CO 20 Capacitances Test Conditions MIN. fC = 1 MHz Unmeasured pins returned to 0 V DATA SHEET U16637EE1V0DS00 TYP. MAX. Unit 15 pF 15 pF 15 pF µPD703177(A) / µPD703445(A) 3.3 Operating Conditions 3.3.1 Peripheral clock (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-6: Peripheral Clock Clock Mode Inside Peripheral Operation Clock Frequency PLL on Note 1 16 to 20 MHz PLL off Note 2 4 to 5 MHz Notes: 1. The inside peripheral operation clock frequency is the crystal frequency multiplied with the multiplication factor ×4. 2. The inside peripheral operation clock frequency is the crystal frequency. 3.3.2 CPU/BCU clock (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-7: CPU/BCU Clock Clock Mode Inside Operation Clock Frequency SSCG on Note 1 20 & 40 MHz PLL on Note 2 16 to 20 MHz 32 to 40 MHz SSCG off, PLL off Note 3 4 to 5 MHz Notes: 1. The max. inside operation clock frequency is the crystal frequency multiplied with a multiplication factor configured in the SSCG Frequency Control Register 1 (SCFC1) and divided by a factor configured in the SSCG Frequency Modulation Control Register (SCFMC). 2. The inside operation clock frequency is the crystal frequency multiplied with the multiplication factor ×4 or ×8 according to the setting of the Processor Clock Control Register (PCC). 3. The inside operation clock frequency is the crystal frequency. DATA SHEET U16637EE1V0DS00 21 µPD703177(A) / µPD703445(A) 3.4 DC Characteristics (TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V) Table 3-8: Parameter DC Characteristics Conditions Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage high Pin group 1 VIH1 0.7 VDD3 VDD3 V Input voltage low Pin group 1 VIL1 0 0.3 VDD3 V Input voltage high Pin group 2 VIH3 0.8 VDD3 VDD3 V Input voltage low Pin group 3 VIL3 0 0.2 VDD3 V Input voltage high Pin group 4 VIH7 0.8 VDD3 5.5 V Input voltage high P7x VIHA 0.7 AVDD AVDD V Input voltage low P7x VILA 0 0.3 AVDD V Pin group 5 Output voltage high Pin group 4 Output voltage low Input leakage current high Input leakage current low VOH1 IOH = -2.5 mA VDD3 - 1 V V IOH = -1.0 mA VDD3 - 1 V V Pin group 6 VOL1 IOL = 2.5 mA 0.4 V Pin group 7 ILIH1 VI = VDD3 5 µA Pin group 4 ILIH2 VI = 5.5 V 5 µA P7x ILIHA AVIN = AVDD 5 µA Pin group 8 ILIL1 VI = 0 V -5 µA P7x ILILA AVIN = 0 V -5 µA Remarks: 1. Pin group 1: D0-15, PDHx, PCSx, PCM0, PCTx (All pins with CMOS input characteristic) 2. Pin group 2: MODEx, P12~17, P2x, P30~P32, P42, P43, RESET (All 3.3 V pins with SCHMITT input characteristic) 3. Pin group 3: P1x, P2x, P3x, P4x, MODEx, RESET (All pins with SCHMITT input characteristic) 4. Pin group 4: P10, P11, P33, P34, P35, P36, P37, P40, P41, P44, P45, P46, P47 (All 5 V tolerant pins) 5. Pin group 5: Ax, Dx, PDHx, PCSx, PCM0, PCTx, PCDx, P12~P17, P2x, P30~P32, P42, P43 (All 3.3 V pins with output capability) 6. Pin group 6: Ax, Dx, PDHx, PCSx, PCM0, PCTx, PCDx, P1x, P2x, P3x, P4x (All pins with output capability) 7. Pin group 7: Dx, PDHx, PCSx, PCM0, PCTx, PCDx, MODEx, P12~P17, P2x, P30~P32, P42, P43, RESET (All 3.3 V pins except P7x) 8. Pin group 8: Dx, PDHx, PCSx, PCM0, PCTx, PCDx, MODEx, P1x, P2x, P3x, P4x, RESET (All pins except P7x) 22 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) Table 3-9: Parameter Symbol Test Conditions TYP. MAX. Unit IDD1SC1 Operating (SSCG1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: on; PLL: on 105 158 mA IDD1SC2 Operating (SSCG2) (fCPU = 20 MHz) (fPerph = 20 MHz) SSCG: on; PLL: on 73 110 mA IDD1P1 Operating (PLL1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: off; PLL: on 97 146 mA IDD1O Operating (OSC) (fCPU = 5 MHz) (fPerph = 5 MHz) SSCG: off; PLL: off 16 24 mA IDD2SC1 HALT(SSCG1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: on; PLL: on 70 105 mA IDD2P1 HALT (PLL1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: off; PLL: on 63 95 mA IDD3SC1 IDLE (SSCG1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: on; PLL: on 6.5 10 mA IDD3P1 IDLE (PLL1) (fCPU = 40 MHz) (fPerph = 20 MHz) SSCG: off; PLL: off 2 3 mA IDD5P STOP 100 500 µA Supply current Remark: Power Supply Currents MIN. The current values listed above are valid for current consumed by the chip logic itself, i.e. excluding ADC and I/O buffer power supply. DATA SHEET U16637EE1V0DS00 23 µPD703177(A) / µPD703445(A) 3.5 AC Characteristics TA = -40 ~ +85°C, VDD3x = CVDD = AVDD = 3.0 V ~ 3.6 V, VSS3x = CVSS = AVSS = 0 V, output pin load capacitance: CL= 50 pF 3.5.1 General For pins P1x, P2x, P3x, P4x, MODEx, RESET (All 3.3 V pins with SCHMITT input characteristics) Figure 3-2: AC Test Input/Output Waveform SCHMITT Test Points VDD3 0.8VDD3x 0.2VDD3x 0V For pins D0-D15, PDHx, PCSx, PCM0, PCTx, P7x (All pins with CMOS input characteristics) Figure 3-3: AC Test Input/Output Waveform CMOS Test Points VDD3 0.7VDD3x 0.3VDD3x 0V 3.5.2 AC test load condition Figure 3-4: AC Test Load Condition DUT Load on test CL = 50 pF 24 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 3.5.3 Clock timing Table 3-10: Parameter Clock Timing Symbol Test Conditions MIN. MAX. Unit X1 input cycle tCYX OSC Mode 200 250 ns X1 input high-level width tWXH OSC Mode 95 ns X1 input low-level width tWXL OSC Mode 95 ns Figure 3-5: Clock Timing tCYX tWXH tWXL X1 DATA SHEET U16637EE1V0DS00 25 µPD703177(A) / µPD703445(A) 3.5.4 External memory access read timing Table 3-11: External Memory Access Read Timing Parameter Symbol MIN. MAX. Unit Data input set up time (vs. address) <10> TSAID (2+WT)T-23 ns Data input set up time (vs. RD↓) <11> TSRDID (1.5+WD +W)T-20.5 ns RD Low level width <12> TWRDL (1.5+WD +W)T-5 ns RD High level width <13> TWRDH (0.5+WAS +i)T-5 ns Address, CSn → RD↓ delay time <14> TDARD (0.5+WAS)T-12 ns RD↑ → address delay time <15> TDRDA iT-2 ns Data input hold time (vs. RD↑) <16> THRDID -2 ns RD↑ → data output delay time <17> TDRDOD (0.5+i)T-6 ns WAIT set up time (vs. address) < 31> TSAW WAIT high level width <32> TWWH Remarks: 1. T: (1+WAS)T-22.5 T+10 1/fCPU 2. i: Number of idle states specified by BCC register 3. WT: Total Number of waits, WT=WAS +WD +W 4. WAS: Number of waits specified by ASC register 26 5. WD: Number of waits specified by DWC1, DWC2 register; WD ≥ 1 6. W: Number of waits due to WAIT DATA SHEET U16637EE1V0DS00 ns ns µPD703177(A) / µPD703445(A) Figure 3-6: A0-A23 CSn BEN0-3 (output) WR0 WR1 WR (output) External Memory Access Read Timing <13> RD <12> <15> (output) <14> <11> <17> <16> <10> D0-D31 (in/output) <31> WAIT <32> (input) DATA SHEET U16637EE1V0DS00 27 µPD703177(A) / µPD703445(A) 3.5.5 External memory access write timing Table 3-12: External Memory Access Write Timing Parameter Symbol MIN. MAX. Unit Address, CSn → WR0, WR1↓ delay time <20> TDAWR (0.5+WAS)T-8.5 ns Address set up (vs. WR0, WR1↑) <21> TSAWR (1.5+WT)T-8.5 ns WR0, WR1↑ → address delay time <22> TDWRA (0.5+i)T-10 ns WR0, WR1 High level width <23> TWWRH (0.5+i+WAS)T-10 ns WR0, WR1 Low level width <24> TWWRL (1+W+WD)T-8.0 ns Data output set up time (vs. WR0, WR1↑) <25> TSODWR (0.5+WT)T-6.0 ns Data output hold time (vs. WR0, WR1↑) <26> THWROD (0.5+i)-6.0 ns WAIT set up time (vs. address) <31> TSAW WAIT high level width <32> TWWH Remarks: 1. T: (1+WAS)T-22.5 T+10 1/fCPU 2. i: Number of idle states specified by BCC register 3. WT: Total Number of waits, WT=WAS +WD +W 4. WAS: Number of waits specified by ASC register 28 5. WD: Number of waits specified by DWC1, DWC2 register; WD ≥ 1 6. W: Number of waits due to WAIT DATA SHEET U16637EE1V0DS00 ns ns µPD703177(A) / µPD703445(A) Figure 3-7: A0-A23 CSn BEN0-3 (output) RD (output) External Memory Access Write Timing <21> <20> <23> WR0 WR1 WR <22> <24> (output) <25> <26> D0-D31 (in/output) write → write D0-D31 (in/output) read → write <31> WAIT <32> (input) DATA SHEET U16637EE1V0DS00 29 µPD703177(A) / µPD703445(A) 3.5.6 RESET (power up/down sequence) Table 3-13: Parameter RESET high-level width Symbol RESET Timing Test Conditions MIN. tWRSH MAX. Unit 500 ns TOSTNote ms 500 ns tWRSL0 STOP mode release tWRSL2 except STOP Mode release RESET hold time tDVRR OSC Mode on power-on TOSTNote ms RESET setup time tDVRF OSC Mode on power-off 0 ns RESET low-level width Note: TOST: Oscillation stabilization time of main oscillator Figure 3-8: tWRSH RESET Timing tWRSL RESET VDD3 VDD3 RESET t DVRR Caution: 30 tDVRF RESET must be applied whenever VDD3 is out of operating condition. DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 3.5.7 Interrupt timing Table 3-14: Parameter Symbol Interrupt Timing Test Conditions MIN. MAX. Unit NMI high-level width tWNIH 500 ns NMI low-level width tWNIL 500 ns INTPi Note 1 high-level width tWITH 500 ns INTPi Note 1 low-level width tWITL 500 ns TICmn Note 2 high-level width tWTIH 500 ns TICmn Note 2 low-level width tWTIL 500 ns Notes: 1. i = 0 to 9 2. m & n = 0 to 1 Figure 3-9: tWNIH Interrupt Timing tWNIL NMI tWITH tWITL INTP0-9 tWTIH tWTIL TICnm DATA SHEET U16637EE1V0DS00 31 µPD703177(A) / µPD703445(A) 3.6 Peripheral Function Characteristics 3.6.1 Timer C Table 3-15: Timer C Characteristics Parameter Symbol Test Conditions MIN. MAX. Unit TICmn Note 1 high-level width tWTICH 100 + TT Note 2 ns TICmn Note 1 low-level width tWTICL 100 + TT Note 2 ns Notes: 1. m & n = 0 to 1 2. TT: Depends on selected clock source for the peripheral clock supply and the setup of the respective timer macro clock and timer channel setup Figure 3-10: tWTICH Timer C Characteristics tWTICL TICnm 32 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 3.6.2 CSI Table 3-16: Parameter CSI Master Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSKM Output 200 ns SCK high level width tWSKHM Output 0.5 tCYSK - 15 ns SCK low level width tWSKLM Output 0.5 tCYSK - 15 ns SI set up time (to SCK ↑) tSSISKM 30 ns SI hold time (from SCK ↑) tHSKSIM 30 ns SO output delay time (from SCK ↓) tDSKSOM SO output hold time (from SCK ↑) tHSKSOM Table 3-17: Parameter MAX. 30 0.5 tCYSK - 5 Unit ns ns CSI Slave Mode Characteristics Symbol Test Conditions MIN. SCK cycle time tCYSKS Input 200 ns SCK high level width tWSKHS Input 90 ns SCK low level width tWSKLS Input 90 ns SI set up time (to SCK ↑) tSSISKS 15 ns SI hold time (from SCK ↑) tHSKSIS 15 ns SO output delay time (from SCK ↓) tDSKSOS SO output hold time (from SCK ↑) tHSKSOS DATA SHEET U16637EE1V0DS00 MAX. 30 tWSKH Unit ns ns 33 µPD703177(A) / µPD703445(A) Figure 3-11: CSI Slave Mode Characteristics tCYSK tWSKL tWSKH SCK tSSISK tHSKSI Hi-Z Input Data SI tDSKSO tHSKSO Output Data SO 3.6.3 UART6 Table 3-18: Parameter Transfer rate UART Characteristics Symbol Test Conditions TUART6 fPeripheral ≥ 5 MHz MIN. MAX. Unit 312500 bps MAX. Unit 1 Mbps 3.6.4 FCAN Table 3-19: Parameter Transfer rate 34 FCAN Characteristics Symbol Test Conditions TFCAN fPeripheral ≥ 16 MHz DATA SHEET U16637EE1V0DS00 MIN. µPD703177(A) / µPD703445(A) 3.6.5 Serial flash programming operating characteristics Table 3-20: Serial Flash Programming Operating Characteristics Parameter Symbol Test Conditions MAX. 5TNote 1+ 500 TRFCF Count start setup time from RESET↑ MIN. Unit µs Times of MODE1 counting TCOUNT MODE1 count High/Low level width TCH, TCL 1 µ VDD3↑ setup time MODE1↑ TDRPSR 100 ns VDD3↑ setup time RESET↑ TDRRR TOST ms MODE1↑ setup time RESET↑ TPSRRF TOST ms MODE1Note 2 pulse count for UART0 NPUART0 0 - NPCSI0 8 - MODE1Note 2 pulse count for CSI0 10 ms Notes: 1. T = 1/fOSC 2. MODE1 input pin is a schmitt-trigger input buffer Figure 3-12: Serial Flash Programming Operating Characteristics VDD3 VDD3x 0V TCOUNT, N PUART0, N PCSI0 TRFCF TDRPSR TCH VDD3 MODE1 0V TCL VDD3 RESET TPSRRF TDRRR 0V DATA SHEET U16637EE1V0DS00 35 µPD703177(A) / µPD703445(A) 3.6.6 A/D converter Table 3-21: Parameter Symbol Resolution - Overall error Note 1 - Conversion time Note 2 tCONV Sampling time tSAM Analogue input voltage VIAN Analogue supply current IAVDD Reference voltage AVREF Reference voltage input current operation IAVREF A/D Converter Characteristics Test Conditions MIN. TYP. MAX. 10 AVREF = AVDD 5 Bit ±8 LSB 12 µs TCONV/6 AVSS 3.0 AVREF = AVDD 1 µs AVREF V 3.0 mA AVDD V 2 mA Notes: 1. Quantization error is not included 2. Conversion time is determined by the number of clocks set by the ADM1 register. 36 DATA SHEET U16637EE1V0DS00 Unit µPD703177(A) / µPD703445(A) 4. Package Drawing Figure 4-1: Package Drawing 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 6 3 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C MILLIMETERS 22.0±0.2 20.0±0.2 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N P 0.08 1.4 Q 0.10±0.05 R 3° +4° −3° S 1.5±0.1 S144GJ-50-UEN DATA SHEET U16637EE1V0DS00 37 µPD703177(A) / µPD703445(A) 5. Recommended Soldering Conditions Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device: Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended please consult NEC. Table 5-1: Soldering Method Infrared reflow Soldering Conditions Soldering Condition Symbol of Recommended Soldering Condition Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.), Number of times: 3 max., Number of days: 7 Note IR-35-207-3 Note: After that, prebaking is necessary at 125 °C for 20 hours. The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been opened. Caution: 38 Do not use two or more soldering methods in combination (except partial heating method). DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) 6. Revision History Version Date 0.1 06/01/05 0.2 30/01/06 Author Remarks S.Vollhardt First official released version of this document S. Vollhardt Table 1-1 & 1-2 Port Types inserted Figure 1-1 updated Main system clock crystal recommendation removed Oscillation stabilization time changed Soldering conditions added DATA SHEET U16637EE1V0DS00 39 µPD703177(A) / µPD703445(A) NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 40 DATA SHEET U16637EE1V0DS00 µPD703177(A) / µPD703445(A) • The information in this document is current as of February, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. DATA SHEET U16637EE1V0DS00 41 µPD703177(A) / µPD703445(A) For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Düsseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China TEL: 010-8235-1155 http://www.cn.necel.com/ Hanover Office Podbielski Strasse 166 B 30177 Hannover Tel: 0 511 33 40 2-0 NEC Electronics Shanghai Ltd. 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