uPD78F0988 PDS - Renesas Electronics

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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78F0988
8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD78F0988 is a member of the µPD780988 Subseries of the 78K/0 Series that substitute flash memory for
the internal ROM of the µPD780988. Flash memory can be written or erased electrically without having to remove
it from board. Therefore, the µPD78F0988 is best suited for evaluation in system development, small-scale
production, or systems likely to be upgraded frequently.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780988 Subseries User’s Manual:
U13029E
78K/0 Series Instructions User’s Manual: U12326E
FEATURES
• Pin-compatible with mask ROM version (except VPP pin)
• Flash memory: 60 KbytesNote 1
• Internal high-speed RAM: 1024 bytes
• Internal expansion RAM: 1024 bytesNote 2
• Operable in the same supply voltage range as the mask ROM version (VDD = 4.0 to 5.5 V)
Notes 1.
2.
The capacity of the flash memory can be changed with the internal memory size switching register (IMS).
The capacity of the internal expansion RAM can be changed with the internal expansion RAM size
switching register (IXS).
Remark For the differences between the flash memory versions and the mask ROM versions, refer to
1. DIFFERENCES BETWEEN µPD78F0988 AND MASK ROM VERSIONS.
ORDERING INFORMATION
Part Number
Package
µPD78F0988CW
µPD78F0988GC-AB8
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 14 mm)
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12805EJ1V0DS00 (1st edition)
Date Published June 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 1999
µPD78F0988
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
In mass-production
Under development
Y subseries products are compatible with I2C bus.
For control
100-pin
µPD78075B
100-pin
µPD78078
µ PD78078Y
µPD78054 with timer and enhanced external interface function
100-pin
µPD78070A
µPD78070AY
ROM-less version of the µPD78078
µPD780018AY
µPD78078Y with enhanced serial I/O and restricted function
100-pin
µPD78078 with reduced EMI noise
80-pin
µ PD780058
µPD780058Y
µPD78054 with enhanced serial I/O
80-pin
µ PD78058F
µPD78058FY
µPD78054 with reduced EMI noise
80-pin
µ PD78054
µ PD78054Y
80-pin
µPD78018F with UART and D/A converter, and enhanced I/O
µPD780024A with expanded RAM
64-pin
µ PD780065
µ PD780078
µPD780078Y
µPD780034A with timer and enhanced serial I/O
64-pin
µ PD780034A
µPD780034AY
µPD780024A with enhanced A/D converter
64-pin
µPD780024A
µPD780024AY
µPD78018F with enhanced serial I/O
64-pin
64-pin
µPD78014H
42/44-pin
µPD78018F
µPD78018F with reduced EMI noise
µPD78018FY
µPD78083
Basic subseries for control
On-chip UART and capable of low-voltage (1.8 V) operation
For inverter control
64-pin
µ PD780988
For
78K/0
Series
FIPTM
On-chip inverter control circuit and UART, EMI noise reduced product
driving
100-pin
µ PD780208
µPD78044F with enhanced I/O and FIP C/D, Total display output: 53
100-pin
µ PD780228
µPD78044H with enhanced I/O and FIP C/D, Total display output: 48
80-pin
µ PD780232
For panel control and on-chip FIP C/D, Total display output: 53
80-pin
µ PD78044H
µPD78044F with N-ch open-drain I/O, Total display output: 34
80-pin
µPD78044F
Basic subseries for FIP driving, Total display output: 34
For LCD driving
100-pin
µ PD780308
100-pin
µ PD78064B
100-pin
µPD78064
µPD780308Y
µPD78064 with enhanced SIO and expanded ROM and RAM
µPD78064 with reduced EMI noise
µPD78064Y
Basic subseries for LCD driving and on-chip UART
Call ID supporting
80-pin
µ PD780841
On-chip Call ID function and simple DTMF, EMI noise reduced product
Bus interface supporting
100-pin
µPD780948
On-chip DCAN controller
80-pin
µPD78098B
µPD78054 with IEBusTM controller, EMI noise reduced product
80-pin
µPD780701Y
On-chip DCAN/IEBus controller
80-pin
µPD780833Y
On-chip J1850 (CLASS2) controller
64-pin
µPD780814
Specialized in DCAN controller
For meter control
2
100-pin
µ PD780958
For industrial meter control
80-pin
µ PD780973
On-chip controller/driver for automobile meter driving
80-pin
µ PD780824
For automobile meter driving and on-chip DCAN controller
80-pin
µ PD780955
Ultra low power consumption and on-chip UART
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
The major functional differences among the subseries are listed below.
Function
Timer
ROM
Capacity
I/O
8-bit 16-bit Watch WDT
Subseries Name
For
µPD78075B 32 K to 40 K
control
µPD78078
4 ch
1 ch
1 ch
1 ch
8 ch
–
2 ch
VDD
External
MIN. Expansion
Value
3 ch (UART: 1 ch) 88
1.8 V
61
2.7 V
3 ch (time-division UART: 1 ch) 68
1.8 V
√
48 K to 60 K
µPD78070A
–
µPD780058 24 K to 60 K
2 ch
µPD78058F 48 K to 60 K
µPD78054
Serial
Interface
8-bit 10-bit 8-bit
D/A
A/D
A/D
3 ch (UART: 1 ch) 69
16 K to 60 K
2.7 V
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
8 ch
4 ch (UART: 1 ch) 60
2.7 V
3 ch (UART: 2 ch) 52
1.8 V
3 ch (UART: 1 ch) 51
µPD780024A
8 ch
–
µPD78014H
2 ch
53
µPD78018F 8 K to 60 K
µPD78083
–
–
µPD780988 16 K to 60 K
3 ch
Note
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch) 47
4.0 V
√
For FIP µPD780208 32 K to 60 K
2 ch
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
µPD780228 48 K to 60 K
3 ch
–
–
4.5 V
For
8 K to 16 K
1 ch (UART: 1 ch) 33
–
inverter
control
driving
µPD780232 16 K to 24 K
µPD78044H 32 K to 48 K
2 ch
1 ch
1 ch
1 ch
72
4 ch
2 ch
40
8 ch
1 ch
68
2.7 V
3 ch (time-division UART: 1 ch) 57
2.0 V
–
µPD78044F 16 K to 40 K
For LCD µPD780308 48 K to 60 K
driving
2 ch
1 ch
1 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
Call ID
2 ch
2 ch (UART: 1 ch)
16 K to 32 K
µPD780841 24 K to 32 K
2 ch
–
1 ch
1 ch
2 ch
–
–
2 ch (UART: 1 ch) 61
2.7 V
–
µPD780948 60 K
2 ch
2 ch
1 ch
1 ch
8 ch
–
–
3 ch (UART: 1 ch) 79
4.0 V
√
–
supporting
Bus
interface µPD78098B 40 K to 60 K
1 ch
supporting µPD780814 32 K to 60 K
2 ch
2 ch
12 ch
For meter µPD780958 48 K to 60 K
4 ch
2 ch
–
µPD780973 24 K to 32 K
3 ch
1 ch
1 ch
control
1 ch
–
–
69
2.7 V
–
2 ch (UART: 1 ch) 46
4.0 V
–
2 ch (UART: 1 ch) 69
2.2 V
56
4.5 V
5 ch
µPD780824 32 K to 60 K
µPD780955 40 K
6 ch
–
1 ch
59
4.0 V
2 ch (UART: 2 ch) 50
2.2 V
–
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
Preliminary Data Sheet U12805EJ1V0DS00
3
µPD78F0988
OVERVIEW OF FUNCTIONS
Item
Function
60 KbytesNote 1
1024 bytes
1024 bytesNote 2
64 Kbytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip instruction execution time variable function
0.24 µs/0.48 µs/0.96 µs/1.9 µs/3.8 µs (@ 8.38-MHz operation with system clock)
Instruction set
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
47
• CMOS inputs:
8
• CMOS I/Os:
39
Real-time output ports
• 8 bits × 1 or 4 bits × 2
• 6 bits × 1 or 4 bits × 1
A/D converter
• 10-bit resolution × 8 channels
• Power supply voltage: AVDD = 4.0 to 5.5 V
Serial interface
• UART mode: 2 channels
• 3-wire serial I/O mode: 1 channel
Timer
• 16 bit timer/event counter: 2 channels
• 8-bit timer/event counter:
3 channels
• 10-bit inverter control timer: 1 channel
• Watchdog timer:
1 channel
Timer output
11 (general-purpose outputs: 5 and inverter control outputs: 6)
Vectored
Maskable
Internal: 16, external: 8
interrupt
Non-maskable
Internal: 1
sources
Software
1
Power supply voltage
VDD = 4.0 to 5.5 V
Operating ambient temperature TA = –40 to +85°C
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 14 mm)
Internal
memory
Flash memory
High-speed RAM
Expansion RAM
Memory space
General-purpose register
Instruction cycle
Notes 1.
The capacity of the flash memory can be changed with the internal memory size switching register
2.
(IMS).
The capacity of the internal expansion RAM can be changed with the internal expansion RAM size
switching register (IXS).
4
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
PIN CONFIGURATION (Top View)
• 64-Pin Plastic Shrink DIP (750 mil)
µPD78F0988CW
P40/AD0
1
64
P67/ASTB
P41/AD1
2
63
P66/WAIT
P42/AD2
3
62
P65/WR
P43/AD3
4
61
P64/RD
P44/AD4
5
60
P37/RTP7
P45/AD5
6
59
P36/RTP6
P46/AD6
7
58
P35/RTP5
P47/AD7
8
57
P34/RTP4
P50
9
56
P33/RTP3
P51/SCK
10
55
P32/RTP2
P52/SI
11
54
P31/RTP1
P53/SO
12
53
P30/RTP0
P54/TI000/TO00/INTP4
13
52
P01/INTP1
P55/TI010/INTP5
14
51
P00/INTP0/TOFF7
P56/TI001/TO01/INTP6
15
50
VSS1
P57/TI011/INTP7
16
49
X1
VSS0
17
48
X2
VDD0
18
47
TEST
TO70
19
46
P03/INTP3/ADTRG
TO71
20
45
P02/INTP2
TO72
21
44
RESET
TO73
22
43
AVDD
TO74
23
42
AVREF
TO75
24
41
P10/ANI0
P20/RxD00
25
40
P11/ANI1
P21/TxD00
26
39
P12/ANI2
P22/RxD01
27
38
P13/ANI3
P23/TxD01
28
37
P14/ANI4
P24/TI50/TO50
29
36
P15/ANI5
P25/TI51/TO51
30
35
P16/ANI6
P26/TI52/TO52
31
34
P17/ANI7
VDD1
32
33
AVSS
Caution
In the normal operation mode, connect the VPP pin directly to VSS0.
Remark
When the µPD78F0988 is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to
VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
Preliminary Data Sheet U12805EJ1V0DS00
5
µPD78F0988
P34/RTP4
P35/RTP5
P36/RTP6
P37/RTP7
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
• 64-Pin Plastic QFP (14 × 14 mm)
µPD78F0988GC-AB8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P50
1
48
P33/RTP3
P51/SCK
2
47
P32/RTP2
P52/SI
3
46
P31/RTP1
P53/SO
4
45
P30/RTP0
P54/TI000/TO00/INTP4
5
44
P01/INTP1
P55/TI010/INTP5
6
43
P00/INTP0/TOFF7
P56/TI001/TO01/INTP6
7
42
VSS1
P57/TI011/INTP7
8
41
X1
VSS0
9
40
X2
VDD0
10
39
TEST
TO70
11
38
P03/INTP3/ADTRG
TO71
12
37
P02/INTP2
TO72
13
36
RESET
TO73
14
35
AVDD
TO74
15
34
AVREF
TO75
16
33
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
VDD1
P26/TI52/TO52
P25/TI51/TO51
P24/TI50/TO50
P23/TxD01
P22/RxD01
P21/TxD00
P20/RxD00
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Caution
In the normal operation mode, connect the VPP pin directly to VSS0.
Remark
When the µPD78F0988 is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to
VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
6
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
AD0 to AD7:
ADTRG:
ANI0 to ANI7:
ASTB:
AVDD:
AVREF:
AVSS:
INTP0 to INTP7:
P00 to P03:
P10 to P17:
P20 to P26:
P30 to P37:
P40 to P47:
P50 to P57:
P64 to P67:
RD:
RESET:
RTP0 to RTP7:
Address/Data Bus
AD Trigger Input
Analog Input
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
External Interrupt Input
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Read Strobe
Reset
Real-time Port
RxD00, RxD01:
SCK:
SI:
SO:
TI000, TI001,
TI010, TI011,
TI50 to TI52:
TO00, TO01,
TO50 to TO52,
TO70 to TO75:
TOFF7:
TxD00, TxD01:
VDD0, VDD1:
VPP:
VSS0, VSS1:
WAIT:
WR:
X1, X2:
Preliminary Data Sheet U12805EJ1V0DS00
Receive Data
Serial Clock
Serial Input
Serial Output
Timer Input
Timer Output
Timer Output Off
Transmit Data
Power Supply
Programming Power Supply
Ground
Wait
Write Strobe
Crystal
7
µPD78F0988
BLOCK DIAGRAM
TI000/TO00/INTP4/P54
TI010/INTP5/P55
TI001/TO01/INTP6/P56
TI011/INTP7/P57
16-bit timer/
event counter 00
8-bit timer/
event counter 50
TO51/TI51/P25
8-bit timer/
event counter 51
P10 to P17
Port 2
P20 to P26
Port 3
P30 to P37
78K/0
CPU core
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P64 to P67
Flash
memory
(60 Kbytes)
Real-time
output port
TxD00/P21
RxD00/P20
UART00
TxD01/P23
RxD01/P22
UART01
RAM
(1024 bytes)
SCK/P51
SI/P52
Port 1
8-bit timer/
event counter 52
Watchdog timer
RTP0/P30 to
RTP7/P37
P00 to P03
16-bit timer/
event counter 01
TO50/TI50/P24
TO52/TI52/P26
Port 0
SIO3
SO/P53
ANI0/P10 to
ANI7/P17
AVDD
A/D converter
AVSS
AVREF
AD0/P40 to
AD7/P47
RD/P64
INTP0/TOFF7/P00
INTP1/P01 and
INTP2/P02
INTP3/ADTRG/P03
INTP4/TI000/TO00/P54
INTP5/TI010/P55
INTP6/TI001/TO01/P56
INTP7/TI011/P57
Interrrupt
control
TO70 to TO75
Real-time
pulse unit
External
access
WR/P65
WAIT/P66
ASTB/P67
RESET
8
VDD0,
VDD1
VSS0,
VSS1
VPP
Preliminary Data Sheet U12805EJ1V0DS00
System
control
X1
X2
µPD78F0988
CONTENTS
1. DIFFERENCES BETWEEN µPD78F0988 AND MASK ROM VERSIONS ...................................... 10
2. PIN FUNCTIONS ................................................................................................................................ 11
2.1
Port Pins .................................................................................................................................................... 11
2.2
2.3
Non-Port Pins ........................................................................................................................................... 12
Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 14
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................... 16
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 17
5. FLASH MEMORY PROGRAMMING ................................................................................................. 18
5.1
5.2
Selection of Communication Mode ....................................................................................................... 18
Flash Memory Programming Functions ............................................................................................... 19
5.3
Connection of Flashpro II and Flashpro III .......................................................................................... 19
6. ELECTRICAL SPECIFICATIONS ...................................................................................................... 21
7. PACKAGE DRAWINGS ..................................................................................................................... 36
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 38
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 40
Preliminary Data Sheet U12805EJ1V0DS00
9
µPD78F0988
1. DIFFERENCES BETWEEN µPD78F0988 AND MASK ROM VERSIONS
The µPD78F0988 is a product with a flash memory which enables on-board writing, erasing and rewriting of
programs.
Except for flash memory specifications, the same functions as those of mask ROM versions can be obtained by
setting the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS).
Table 1-1 shows the differences between the flash memory version (µPD78F0988) and mask ROM versions
(µPD780982, 780983, 780984, 780986, 780988).
Table 1-1. Differences between µPD78F0988 and Mask ROM Versions
µPD78F0988
Item
Mask ROM Versions
Internal ROM structure
Flash memory
Mask ROM
Internal ROM capacities
60 Kbytes
µPD780982:
µPD780983:
µPD780984:
µPD780986:
µPD780988:
16 Kbytes
24 Kbytes
32 Kbytes
48 Kbytes
60 Kbytes
Internal expansion RAM capacities
1024 bytes
µPD780982:
µPD780983:
µPD780984:
µPD780986:
µPD780988:
None
None
None
1024 bytes
1024 bytes
Change of internal ROM capacity with internal
memory size switching register (IMS)
AvailableNote 1
Not available
Change of internal expansion RAM capacity with
internal expansion RAM size switching register (IXS)
AvailableNote 2
Not available
TEST pin
Not provided
Provided
VPP pin
Provided
Not provided
Notes 1. Flash memory capacity becomes 60 Kbytes by RESET input.
2. Internal expansion RAM capacity becomes 0 byte by RESET input.
Caution
There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM versions.
10
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
2. PIN FUNCTIONS
2.1
Port Pins
Pin Name
P00
I/O
I/O
Function
Port 0
Alternate
Function
After Reset
Input
INTP0/TOFF7
P01
4-bit I/O port
INTP1
P02
Input/output can be specified in 1-bit units.
INTP2
An on-chip pull-up resistor can be specified by means of
INTP3/ADTRG
P03
software.
P10 to P17
Input
Port 1
Input
ANI0 to ANI7
Input
RxD00
8-bit input only port
P20
I/O
Port 2
P21
7-bit I/O port
TxD00
P22
Input/output can be specified in 1-bit units.
RxD01
P23
An on-chip pull-up resistor can be specified by means of
TxD01
P24
software.
TI50/TO50
P25
TI51/TO51
P26
P30 to P37
TI52/TO52
I/O
Port 3
Input
RTP0 to RTP7
Input
AD0 to AD7
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
P40 to P47
I/O
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
P50
I/O
Port 5
Input
—
P51
8-bit I/O port
SCK
P52
Input/output can be specified in 1-bit units.
SI
P53
LEDs can be driven directly.
SO
P54
An on-chip pull-up resistor can be specified by means of
INTP4/TI000/TO00
P55
software.
INTP5/TI010
P56
INTP6/TI001/TO01
P57
INTP7/TI011
P64
I/O
Port 6
Input
RD
P65
4-bit I/O port
WR
P66
Input/output can be specified in 1-bit units.
WAIT
An on-chip pull-up resistor can be specified by means of
ASTB
P67
software.
Preliminary Data Sheet U12805EJ1V0DS00
11
µPD78F0988
2.2
Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
Function
External interrupt request input for which the valid edge
After Reset
Input
Alternate
Function
P00/TOFF7
INTP1
(rising edge, falling edge, or both rising and falling
Input
P01
INTP2
edges) can be specified
Input
P02
Input
P03/ADTRG
INTP3
INTP4
Input
P54/TI000/TO00
INTP5
Input
P55/TI010
INTP6
Input
P56/TI001/TO01
INTP7
Input
P57/TI011
External count clock input to 8-bit timer (TM50)
Input
P24/TO50
TI51
External count clock input to 8-bit timer (TM51)
Input
P25/TO51
TI52
External count clock input to 8-bit timer (TM52)
Input
P26/TO52
TI000
External count clock input to 16-bit timer (TM00)
Input
P54/INTP4/TO00
Input
P55/INTP5
Input
P56/INTP6/TO01
Input
P57/INTP7
8-bit timer (TM50) output
Input
P24/TI50
TO51
8-bit timer (TM51) output
Input
P25/TI51
TO52
8-bit timer (TM52) output
Input
P26/TI52
TO00
16-bit timer (TM00) output
Input
P54/INTP4/TI000
TO01
16-bit timer (TM01) output
Input
P56/INTP6/TI001
RTP0 to RTP7 Output
Real-time output port that outputs pulses in synchronization
Input
P30 to P37
TI50
Input
Capture trigger input to capture register (CR000, CR010) of
16-bit timer (TM00)
TI010
Capture trigger input to capture register (CR000) of 16-bit
timer (TM00)
TI001
External count clock input to 16-bit timer (TM01)
Capture trigger input to capture register (CR001, CR011) of
16-bit timer (TM01)
TI011
Capture trigger input to capture register (CR001) of 16-bit
timer (TM01)
TO50
Output
with trigger signals outputs from the real-time pulse unit
TxD00
Output
Asynchronous serial interface serial data output
TxD01
RxD00
Input
Asynchronous serial interface serial data input
RxD01
Input
P21
Input
P23
Input
P20
Input
P22
SCK
I/O
Serial interface serial clock input/output
Input
P51
SI
Input
Serial interface serial data input
Input
P52
SO
Output
Serial interface serial data output
Input
P53
ANI0 to ANI7 Input
A/D converter analog input
Input
P10 to P17
ADTRG
P03/INTP3
External trigger signal input to the A/D converter
Input
TO70 to TO75 Output
Input
Timer output for the 3-phase PWM inverter control
Hi-Z
TOFF7
Input
Timer output (TO70 to TO75) stop external input
Input
P00/INTP0
AD0 to AD7
I/O
Address/data bus for expanding memory externally
Input
P40 to P47
RD
Output
Strobe signal output for reading from external memory
Input
P64
Strobe signal output for writing to external memory
Input
P65
WAIT
Input
Wait insertion at external memory access
Input
P66
ASTB
Output
Strobe output that externally latches address information
Input
P67
AVREF
Input
A/D converter reference voltage input
–
–
A/D converter analog power supply
–
–
WR
–
output to ports 4 and 5 to access external memory
AVDD
12
–
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
2.2
Non-Port Pins (2/2)
Pin Name
AVSS
I/O
–
Function
After Reset
Alternate
Function
A/D converter ground potential
–
–
RESET
Input
System reset input
–
–
X1
Input
Connecting crystal resonator for system clock oscillation
–
–
–
–
X2
–
VDD0
–
Positive power supply for ports
–
–
VSS0
–
Ground potential for ports
–
–
VDD1
–
Positive power supply except for ports
–
–
VSS1
–
Ground potential except for ports
–
–
VPP
–
High-voltage application during program write/verify.
–
–
In the normal operation mode, connect directly to VSS0.
Preliminary Data Sheet U12805EJ1V0DS00
13
µPD78F0988
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, refer to Figure 2-1.
Table 2-1. Types of Pin Input/Output Circuits
Pin Name
P00/INTP0/TOFF7
Input/Output
Circuit Type
I/O
Recommended Connection of Unused Pins
8-C
Input/output
Independently connect to VSS0 via a resistor.
P10/ANI0 to P17/ANI7
25
Input
Independently connect to VDD0 or VSS0 via a resistor.
P20/RxD00
8-C
Input/output
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P21/TxD00
5-H
P22/RxD01
8-C
P23/TxD01
5-H
P24/TI50/TO50
8-C
P25/TI51/TO51
P26/TI52/TO52
P30/RTP0 to P37/RTP7
5-H
P40/AD0 to P47/AD7
P50
P51/SCK
8-C
P52/SI
5-H
P53/SO
P54/INTP4/TI000/TO00
P55/INTP5/TI010
P56/INTP6/TI001/TO01
P57/INTP7/TI011
P64/RD
P65/WR
P66/WAIT
P67/ASTB
TO70 to TO75
4
Output
RESET
2
Input
AVDD
–
AVREF
Leave open.
–
–
Connect to VDD0.
Connect to VSS0.
AVSS
VPP
14
Connect directly to VSS0.
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
Figure 2-1. Pin Input/Output Circuits
Type 2
Type 8-C
VDD0
pullup
enable
P-ch
VDD0
data
IN
P-ch
IN/OUT
output
disable
N-ch
VSS0
Schmitt-triggered input with hysteresis characteristics
Type 4
Type 25
VDD0
data
P-ch
P-ch
Comparator
+
OUT
output
disable
–
N-ch
VSS0
VREF (threshold voltage)
N-ch
VSS0
Push-pull output that enables high-impedance output
IN
input
enable
(both P-ch and N-ch are off)
Type 5-H
pullup
enable
data
VDD0
P-ch
VDD0
P-ch
IN/OUT
output
disable
N-ch
VSS0
input
enable
Preliminary Data Sheet U12805EJ1V0DS00
15
µPD78F0988
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is set by software not to use a part of internal memory. The memory mapping can be made the same
as that of mask ROM versions with different types of internal memory capacity by setting IMS.
IMS is set with an 8-bit memory manipulation instruction.
IMS is set to CFH by RESET input.
Figure 3-1. Format of Internal Memory Size Switching Register
7
IMS
6
5
RAM2 RAM1 RAM0
4
0
3
2
1
0
ROM3 ROM2 ROM1 ROM0
Address
After reset
R/W
FFF0H
CFH
R/W
ROM3 ROM2 ROM1 ROM0
Selection of Internal
ROM Capacity
0
1
0
0
16 Kbytes
0
1
1
0
24 Kbytes
1
0
0
0
32 Kbytes
1
1
0
0
48 Kbytes
1
1
1
1
60 Kbytes
Other than above
RAM2 RAM1 RAM0
1
1
0
Other than above
Setting prohibited
Selection of Internal
High-Speed RAM Capacity
1024 bytes
Setting prohibited
Table 3-1 shows the IMS setting values to make the memory mapping the same as those of mask ROM versions.
Table 3-1. Setting Value of Internal Memory Size Switching Register
Target Mask ROM Versions
16
IMS Setting Value
µPD780982
C4H
µPD780983
C6H
µPD780984
C8H
µPD780986
CCH
µPD780988
CFH
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to set internal expansion RAM capacity by software. The memory mapping can be made
the same as that of mask ROM versions with different types of internal expansion RAM capacity by setting IXS.
IXS is set with an 8-bit memory manipulation instruction.
IXS is set to 0CH by RESET input.
Figure 4-1. Format of Internal Expansion RAM Size Switching Register
IXS
7
6
5
0
0
0
4
3
2
1
0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
Address
After reset
R/W
FFF4H
0CH
R/W
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of Internal
Expansion RAM Capacity
0
1
0
1
0
1024 bytes
0
1
1
0
0
No internal expansion RAM
Other than above
Setting prohibited
Table 4-1 shows the IXS setting values to make the memory mapping the same as those of mask ROM versions.
Table 4-1. Setting Value of Internal Expansion RAM Size Switching Register
Target Mask ROM Versions
µPD780982
IXS Setting Value
0CH
µPD780983
µPD780984
µPD780986
0AH
µPD780988
Preliminary Data Sheet U12805EJ1V0DS00
17
µPD78F0988
5. FLASH MEMORY PROGRAMMING
On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done
after connecting a dedicated flash programmer (Flashpro II (part number FL-PR2), Flashpro III (part numbers FL-PR3
and PG-FP3)) to the host machine and target system. Moreover, writing to flash memory can also be performed using
a flash memory writing adapter connected to Flashpro II or Flashpro III.
Remark
FL-PR2 and FL-PR3 are products of NAITO DENSEI MACHIDA MFG. CO., LTD.
5.1 Selection of Communication Mode
Writing to flash memory is performed using Flashpro II and III with a serial communication mode. Select the
communication mode for writing from Table 5-1. For the selection of the communication mode, a format like the one
shown in Figure 5-1 is used. The communication modes are selected using the VPP pulse numbers shown in Table
5-1.
Table 5-1. Communication Mode List
Communication Mode
Number of
Channels
Number of
VPP Pulses
Pin Used
3-wire serial I/O
1
SCK/P51
SI/P52
SO/P53
0
UART
1
RxD00/P20
TxD00/P21
8
Pseudo 3-wire serial I/O
modeNote
1
P24/TI50/TO50 (Serial data input)
P25/TI51/TO51 (Serial data output)
P26/TI52/TO52 (Serial clock input)
12
Note
Serial transfer is performed by controlling ports with software.
Caution
Always select the communication mode according to the number of VPP pulses shown in Table 51.
Figure 5-1. Communication Mode Selection Format
VPP pulses
10 V
VPP
VDD
VSS
1
2
n
VDD
RESET
VSS
Flash memory write mode
18
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
5.2 Flash Memory Programming Functions
Flash memory writing is performed through command and data transmit/receive operations using the selected
communication mode. The main functions are listed in Table 5-2.
Table 5-2. Main Functions of Flash Memory Programming
Function
Description
Batch erase
Erases the contents of the entire memory.
Batch blank check
Checks that the entire memory has been deleted.
Data write
Performs writing to flash memory according to the write start address and the
number of the data to be written (the number of bytes).
Batch verify
Compares the contents of the entire memory and the input data.
5.3 Connection of Flashpro II and Flashpro III
The connection of the Flashpro II, Flashpro III and the µPD78F0988 differs depending on the communication mode.
Each type of connection is shown in Figures 5-2, 5-3, and 5-4, respectively.
Figure 5-2. Connection of Flashpro II and Flashpro III Using 3-Wire Serial I/O Mode
Flashpro II, III
VPP
µ PD78F0988
VDD
VPP
VDD1
VDD0
CLK
X1
RESET
SCK
Note
RESET
SCK
SO
SI
SI
SO
VSS1
GND
Note
VSS0
For input to X1, not CLK but a normal oscillator can also be used.
Preliminary Data Sheet U12805EJ1V0DS00
19
µPD78F0988
Figure 5-3. Connection of Flashpro II and Flashpro III Using UART Mode
Flashpro II, III
VPP
µ PD78F0988
VPP
VDD1
VDD
VDD0
CLK
X1Note
RESET
RESET
SO
RxD00
SI
TxD00
VSS1
VSS
Note
VSS0
For input to X1, not CLK but a normal oscillator can also be used.
Figure 5-4. Connection of Flashpro II and Flashpro III Using Pseudo 3-Wire Serial I/O Mode
Flashpro II, III
VPP
µ PD78F0988
VPP
VDD1
VDD
VDD0
CLK
X1Note
RESET
P26
(Serial clock input)
SO
P24
(Serial data input)
P25
(Serial data output)
VSS1
VSS0
SI
VSS
Note
20
RESET
SCK
For input to X1, not CLK but a normal oscillator can also be used.
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Ratings
Unit
–0.3 to +6.5
–0.3 to +10.5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
–0.3 to VDD + 0.3
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
°C
Supply voltage
VDD
Input voltage
VPP
AVDD
AVREF
AVSS
VI
Output voltage
Analog input voltage
VO
VAN
Output current, high
IOH
Output current, low
IOLNote
Operating ambient
temperature
Storage temperature
TA
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF + 0.3
and –0.3 to VDD + 0.3
–10
–15
–15
20
10
30
15
50
20
30
15
100
70
100
70
–40 to +85
Tstg
–40 to +125
P00 to P03, P10 to P17, P20 to P26, P30 to P37, P50
to P57, P64 to P67, TO70 to TO75, X1, X2, RESET
P10 to P17
Analog input pin
Per pin
P00, P01, P30 to P37, P40 to P47, P50 to P57, P64 to P67 total
P02, P03, P20 to P26, TO70 to TO75 total
P00 to P03, P10 to P17, P20 to P26, Peak value
P30 to P37, P40 to P47, P64 to P67 per pin rms value
P50 to P57, TO70 to TO75 per pin
Peak value
rms value
P00, P01, P30 to P37, P40 to P47, P64 to P67 Peak value
total
rms value
P02, P03, P20 to P26 total
Peak value
rms value
TO70 to TO75 total
Peak value
rms value
P50 to P57 total
Peak value
rms value
The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
Note
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
f = 1 MHz Unmeasured pins returned to 0 V
15
pF
I/O capacitance
CIO
f = 1 MHz
P00 to P03, P20 to P26, P30
Unmeasured pins to P37, P40 to P47, P50 to
returned to 0 V
P57, P64 to P67, TO70 to TO75
15
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Preliminary Data Sheet U12805EJ1V0DS00
21
µPD78F0988
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Resonator
Ceramic
resonator
Recommended
Circuit
VPP X2
C1
Crystal
resonator
X1
C2
VPP X2
C1
X1
C2
External clock
X2
µPD74HCU04
X1
Parameter
Conditions
Oscillation
frequency (fX)Note 1
Oscillation
stabilization
timeNote 2
1.0
After VDD reaches
oscillation
voltage range MIN.
Oscillation
frequency (fX)Note 1
Oscillation
stabilization
timeNote 2
MIN.
1.0
After VDD reaches
oscillation
voltage range MIN.
TYP.
MAX.
Unit
8.38
MHz
4
ms
8.38
MHz
10
ms
X1 input frequency
(fX)Note 1
1.0
8.38
MHz
X1 input high-/lowlevel width (tXH, tXL)
50
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
22
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
Recommended Oscillator Constant
System clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
(MHz)
Murata Mfg.
Co., Ltd.
Caution
Recommended Circuit Constant
C1 (pF)
C2 (pF)
Oscillation Voltage Range
MIN. (V)
MAX. (V)
CSA2.00MG040
2.00
100
100
4.0
5.5
CST2.00MG040
2.00
On-chip
On-chip
4.0
5.5
CSA3.58MG
3.58
30
30
4.0
5.5
CST3.58MGW
3.58
On-chip
On-chip
4.0
5.5
CSA4.00MG
4.00
30
30
4.0
5.5
CST4.00MGW
4.00
On-chip
On-chip
4.0
5.5
CSA4.19MG
4.19
30
30
4.0
5.5
CST4.19MGW
4.19
On-chip
On-chip
4.0
5.5
CSA4.91MG
4.91
30
30
4.0
5.5
CST4.91MGW
4.91
On-chip
On-chip
4.0
5.5
CSA5.00MG
5.00
30
30
4.0
5.5
CST5.00MGW
5.00
On-chip
On-chip
4.0
5.5
CSA7.37MTZ
7.37
30
30
4.0
5.5
CST7.37MTW
7.37
On-chip
On-chip
4.0
5.5
CSA8.00MTZ
8.00
30
30
4.0
5.5
CST8.00MTW
8.00
On-chip
On-chip
4.0
5.5
CSA8.38MTZ
8.38
30
30
4.0
5.5
CST8.38MTW
8.38
On-chip
On-chip
4.0
5.5
CSA10.0MTZ
10.0
30
30
4.0
5.5
CST10.0MTW
10.0
On-chip
On-chip
4.0
5.5
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
Preliminary Data Sheet U12805EJ1V0DS00
23
µPD78F0988
DC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Input voltage,
high
Symbol
Conditions
MIN.
MAX.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
VDD – 0.5
0
VDD
0.3VDD
V
V
0
0.2VDD
V
0
VDD – 1.0
VDD – 0.5
0.4
VDD
VDD
2.0
V
V
V
V
0.4
V
0.5
3
V
µA
20
–3
µA
µA
ILIL2
ILOH
P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53,
P64 to P67
RESET, P00 to P03, P20, P22, P24 to P26, P51, P52,
P54 to P57
X1, X2
P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53,
P64 to P67
RESET, P00 to P03, P20, P22, P24 to P26, P51, P52,
P54 to P57
X1, X2
4.5 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
IOH = –100 µA
P50 to P57, TO70 to TO75
5.0 V ≤ VDD ≤ 5.5 V,
IOL = 15 mA
P00 to P03, P20 to P26,
5.0 V ≤ VDD ≤ 5.5 V,
P30 to P37, P40 to P47,
IOL = 1.6 mA
P64 to P67
IOL = 400 µA
VIN = VDD
P00 to P03, P10 to P17,
P20 to P26, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67,
TO70 to TO75, RESET
X1, X2
VIN = 0 V
P00 to P03, P10 to P17,
P20 to P26, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67,
TO70 to TO75, RESET
X1, X2
VOUT = VDD
–20
3
µA
µA
ILOL
VOUT = 0 V
–3
µA
R2
VIN = 0 V
P00 to P03, P20 to P26, P30 to P37, P40 to P47, P50 to
P57, P64 to P67
8.38-MHz crystal
VDD = 5.0 V ±10%Note 2 When A/D
oscillation
converter
operating mode
stopped
When A/D
converter
operating
8.38-MHz crystal
VDD = 5.0 V ±10%Note 2 When peripheral
oscillation HALT
function
mode
stopped
When peripheral
function operating
30
90
kΩ
15
30
mA
16
32
mA
1.3
2.6
mA
7.3
mA
30
µA
VIH1
VIH2
Input voltage, low
VIH3
VIL1
VIL2
Output voltage,
high
Output voltage,
low
Input leakage
current, high
Input leakage
current, low
Output leakage
current, high
Output leakage
current, low
Software pull-up
resistor
Power supply
currentNote 1
VIL3
VOH1
VOL1
VOL2
ILIH1
ILIH2
ILIL1
IDD1
IDD2
IDD3
STOP mode
VDD = 5.0 V ±10%
TYP.
0.4
15
0.1
Notes 1. Refers to the total current flowing to the internal power supply (VDD0 and VDD1). The peripheral operation
current is included however, the current flowing to the pull-up resistor of ports and AVREF pin is not included.
2. High-speed mode operation (when processor clock control register (PCC) is set to 00H).
Remark
24
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Cycle time
(Min. instruction
execution time)
TI000, TI001,
TI010, TI011
input frequency
TI000, TI001,
TI010, TI011
input high-/
low-level width
TI50, TI51, TI52
input frequency
TI50, TI51, TI52
input high-/
low-level width
Interrupt request
input high-/
low-level width
TOFF input
high-/low-level
width
RESET input
low-level width
Note
Symbol
MAX.
Unit
0.24
32
µs
fTI0
0
fX/64
MHz
tTIH0
tTIL0
2/fsam +
0.1Note
TCY
Conditions
Operating with system clock
MIN.
TYP.
µs
fTI5
8-/16-bit precision
0
4
MHz
tTIH5
tTIL5
8-/16-bit precision
100
ns
tINTH
tINTL
INTP0 to INTP7
1
µs
tTOFFH
tTOFFL
2
µs
tRSL
10
µs
Selection of fsam = fX, fX/4, fX/32 is possible with bits 0 and 1 (PRM000, PRM001) of prescaler mode register
00 (PRM00) or with bits 0 and 1 (PRM010, PRM011) of prescaler mode register 01 (PRM01). Note that when
selecting TI000 (TM00) or TI001 (TM01) valid edge as the count clock, fsam = fX/16.
Preliminary Data Sheet U12805EJ1V0DS00
25
µPD78F0988
TCY
VS
VDD (System clock operation)
32.0
Cycle time TCY [ µ s]
10.0
Guaranteed
operation
range
5.0
2.0
1.0
0.24
0.1
0
1.0
2.0
3.0
4.0
5.0 5.5 6.0
Supply voltage VDD [V]
26
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
ASTB high-level width
Symbol
Conditions
MIN.
MAX.
Unit
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
Address output time from RD↓
tRDAD
Data input time from RD↓
tRDD1
0
tRDD2
Read data hold time
RD low-level width
WAIT↓ input time from RD↓
100
ns
(2 + 2n)tCY – 87
ns
(3 + 2n)tCY – 93
ns
tRDH
0
ns
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
0.5tCY – 25
ns
(2 + 2n)tCY
ns
WAIT↓ input time from WR↓
tWRWT
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL
(1.5 + 2n)tCY – 15
ns
RD↓ delay time from ASTB↓
tASTRD
6
ns
WR↓ delay time from ASTB↓
tASTWR
2tCY – 15
ASTB↑ delay time from RD↑ at external fetch
tRDAST
0.8tCY – 15
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
RD↑ delay time from WAIT↑
tWTRD
0.8tCY
2.5tCY + 25
ns
WR↑ delay time from WAIT↑
tWTWR
0.8tCY
2.5tCY + 25
ns
Remarks
ns
1.2t CY
ns
ns
1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of AD0 to AD7, RD, WR, WAIT, and ASTB pins.)
Preliminary Data Sheet U12805EJ1V0DS00
27
µPD78F0988
(3) Serial interface (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
(a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
tKCY1
954
ns
SCK high-/low-level width
tKH1
tKCY1/2 – 50
ns
SI setup time (to SCK↑)
tSIK1
100
ns
SI hold time (from SCK↑)
tKSI1
SO output delay time
tKSO1
tKL1
400
ns
C = 100 pFNote
300
ns
MAX.
Unit
from SCK↓
Note
C is the load capacitance of the SCK and SO output lines.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter
SCK cycle time
SCK high-/low-level width
Symbol
Conditions
MIN.
TYP.
tKCY2
800
ns
tKH2
400
ns
ns
tKL2
SI setup time (to SCK↑)
tSIK2
100
SI hold time (from SCK↑)
tKSI2
400
SO output delay time
tKSO2
ns
C = 100 pFNote
300
ns
MAX.
Unit
125000
bps
MAX.
Unit
115200
bps
from SCK↓
Note
C is the load capacitance of the SCK and SO output lines.
(c) UART mode (UART00) (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
(d) UART mode (UART00) (Infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
TYP.
Transfer rate
Bit rate allowable error
Output pulse width
1.2
Input pulse width
4/fX
Note
±0.87
%
0.24/fbrNote
µs
µs
fbr: Set baud rate
(e) UART mode (UART01) (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
Transfer rate
28
Preliminary Data Sheet U12805EJ1V0DS00
MIN.
TYP.
MAX.
Unit
38400
bps
µPD78F0988
AC Timing Test Points (excluding X1 input)
0.8VDD
0.8VDD
Test points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH3 (MIN.)
VIL3 (MAX.)
X1 input
TI Timing
1/fTI0
tTIL0
tTIH0
TI000, TI001,
TI010, TI011
1/fTI5
tTIL5
tTIH5
TI50, TI51, TI52
TOFF Timing
tTOFFL
tTOFFH
TOFF7
Preliminary Data Sheet U12805EJ1V0DS00
29
µPD78F0988
Read/Write Operation
External fetch (no wait):
tADD1
AD0 to AD7
8-bit address
tADS
tADH
Hi-Z
Operation code
tRDAD
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
tADD1
AD0 to AD7
Hi-Z
8-bit address
tADS
tADH
tRDAD
Operation code
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
30
tWTL
Preliminary Data Sheet U12805EJ1V0DS00
tWTRD
µPD78F0988
External data access (no wait):
tADD2
AD0 to AD7
8-bit address
tADS
tADH
Hi-Z
tRDAD
tRDD2
Read data
tASTH
Hi-Z
Write data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRWD
WR
tASTWR
tWRL
External data access (wait insertion):
AD0 to AD7
8-bit
address
tADS tADH
tASTH
tADD2
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDS
tWDH
tWRWD
WR
tASTWR
tWRL
WAIT
tRDWT2
tWTL
tWTRD
Preliminary Data Sheet U12805EJ1V0DS00
tWRWT
tWTL
tWTWR
31
µPD78F0988
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
SCK
tSIKm
SI
tKSIm
Input data
tKSOm
SO
Output data
m = 1, 2
32
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
Resolution
Overall error
MIN.
10
4.0 V ≤ AVREF ≤ 5.5 V
Note
2.7 V ≤ AVREF < 4.0 V
Conversion time
tCONV
Zero-scale offsetNote
Full-scale
offsetNote
Non-linearity error
Differential non-linearity error
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF
and AVSS
RREF
Note
TYP.
MAX.
Unit
10
10
bit
±0.2
±0.4
%FSR
±0.3
±0.6
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
14
96
µs
2.7 V ≤ AVREF < 4.0 V
19
96
µs
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
4.0 V ≤ AVREF ≤ 5.5 V
±2.5
LSB
2.7 V ≤ AVREF < 4.0 V
±4.5
LSB
4.0 V ≤ AVREF ≤ 5.5 V
±1.5
LSB
2.7 V ≤ AVREF < 4.0 V
±2.0
LSB
0
AVREF
V
2.7
AVDD
V
When A/D converter is not operating
20
40
kΩ
Excludes quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention
power supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
wait time
Note
Conditions
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.1
MAX.
Unit
5.5
V
10
µA
µs
0
Release by RESET
217/fX
ms
Release by interrupt request
Note
ms
Selection of 212/fX and 214/fX to 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time select register (OSTS).
Preliminary Data Sheet U12805EJ1V0DS00
33
µPD78F0988
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
Operation
mode
STOP mode
Data retention mode
VDD
tSREL
VDDDR
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
HALT mode
Operation
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
Interrupt Request Input Timing
tINTH
tINTL
INTP0 to INTP7
RESET Input Timing
tRSL
RESET
34
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
Flash Memory Programming Characteristics (VDD = 4.0 to 5.5 V, VSS = 0 V, VPP = 9.7 to 10.3 V)
(1) Basic characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Operation frequency
fX
1.0
8.38
MHz
Supply voltage
VDD
4.0
5.5
V
0.2VDD
V
VPPL
When VPP low-level is detected
0
VPP
When VPP high-level is detected
0.8VDD
VDD
1.2VDD
V
VPPH
When VPP high-voltage is detected
9.0
10.0
10.5
V
When programming
9.7
10.0
10.3
V
50
100
mA
VPP power supply current
IPP
VPP = 10.0 V
Write time (per 1 byte)
TWRT
Number of rewrites
CWRT
Erase time
TERASE
1
20
s
Programming temperature
TPRG
10
40
°C
MAX.
Unit
50
500
µs
20
Times
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
VPP↑ set time from VDD↑
tDRPSR
VPP high voltage
0
µs
RESET↑ set time from VPP↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
VPP high voltage
1.0
µs
Count execution time
tCOUNT
VPP counter high-level width
tCH
8.0
VPP counter low-level width
tCL
8.0
VPP counter noise elimination width
tNFW
20
ms
µs
µs
40
ns
Flash Write Mode Setting Timing
VDD
VDD
0V
tDRPSR
tRFCF
tCH
VPPH
VPP
VPP
tCL
VPPL
tPSRRF
tCOUNT
VDD
RESET (input)
0V
Preliminary Data Sheet U12805EJ1V0DS00
35
µPD78F0988
7. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
J
L
I
H
F
D
C
N
B
M
R
M
G
NOTES
1. Controlling dimension
millimeter.
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
58.0+0.68
–0.20
2.283+0.028
–0.008
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020+0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.05+0.26
–0.20
0.159+0.011
–0.008
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0±0.2
0.669+0.009
–0.008
M
0.25+0.10
–0.05
0.010+0.004
–0.003
N
0.17
0.007
R
0 to 15°
0 to 15°
P64C-70-750A,C-3
36
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
64 PIN PLASTIC QFP ( 14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
17.6±0.4
B
14.0±0.2
0.693±0.016
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
G
1.0
1.0
0.039
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.08
–0.07
0.007 +0.003
–0.004
N
0.10
0.004
P
2.55±0.1
0.100±0.004
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
2.85 MAX.
5°±5°
0.113 MAX.
P64GC-80-AB8-4
Preliminary Data Sheet U12805EJ1V0DS00
37
µPD78F0988
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780988 Subseries.
Also refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K/0
Assembler package common to 78K/0 Series
CC78K/0
C compiler package common to 78K/0 Series
DF780988
Device file for µPD780988 Subseries
CC78K/0-L
C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (part No. FL-PR2),
Flashpro III (part No. FL-PR3,
PG-FP3)
Flash programmer dedicated to on-chip flash memory microcontroller
FA-64CW
FA-64GC
Adapter for flash memory writing
(3) Debugging Tools
• When IE-78K0-NS in-circuit emulator is used
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PANote
Performance board for enhancement and expansion of IE-78K0-NS function
IE-70000-98-IF-C
Interface adapter when PC-9800 series PC (except notebook type) is used as
host machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when notebook PC is used as host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/ATTM or compatible as host machine
(ISA bus supported)
IE-70000-PCI-IF
Adapter necessary when using PCI bus incorporated personal computer as host machine
IE-780988-NS-EM4
Emulation board to emulate µPD780988 Subseries
IE-78K0-NS-P01
I/O board necessary to emulate µPD780988 Subseries
NP-64CW
Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC
NP-64GC-TQ
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EV-9200GC-64
Conversion socket to connect the NP-64GC and a target system board on which
the 64-pin plastic QFP (GC-AB8 type) can be mounted
TGC-064SAP
Conversion adapter to connect the NP-64GC-TQ and a target system board on which
the 64-pin plastic QFP (GC-AB8 type) can be mounted
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780988
Device file for µPD780988 Subseries
Note
38
Under development
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
• When IE-78001-R-A in-circuit emulator is used
IE-78001-R-A
IE-70000-98-IF-C
In-circuit emulator common to 78K/0 Series
Interface adapter when PC-9800 series PC (except notebook type) is used as
host machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine
(ISA bus supported)
IE-70000-PCI-IF
Adapter necessary when using PCI bus incorporated personal computer as host machine
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-780988-NS-EM4
Emulation board to emulate µPD780988 Subseries
IE-78K0-NS-P01
I/O board necessary to emulate µPD780988 Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780988-NS-EM4
and IE-78K0-NS-P01 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EV-9200GC-64
Socket to be mounted on a target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780988
Device file for µPD780988 Subseries
(4) Real-time OS
RX78K/0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780988.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 or DF780988.
• The FL-PR2, FL-PR3, FA-64CW, FA-64GC, NP-64CW, NP-64GC, and NP-64GC-TQ are products made by
NAITO DENSEI MACHIDA MFG. CO., LTD. (TEL +81-44-822-3813). Contact an NEC distributor regarding
the purchase of these products.
• The TGC-064SAP is a product made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
• For third-party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machine and OS suitable for each software are as follows.
Host Machine
[OS]
Software
PC
PC-9800 series [WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
EWS
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K/0
√Note
√
CC78K/0
√Note
√
ID78K0-NS
√
–
ID78K0
√
√
SM78K0
√
–
RX78K/0
MX78K0
√Note
√Note
√
√
Note
DOS-based software
Preliminary Data Sheet U12805EJ1V0DS00
39
µPD78F0988
APPENDIX B. RELATED DOCUMENTS
• Documents Related to Devices
Document Name
Document No.
English
µPD780988 Subseries User’s Manual
Japanese
U13029E
U13029J
µPD780982, 780983, 780984, 780986, 780988 Data Sheet
U12804E
U12804J
µPD78F0988 Data Sheet
This manual
U12805J
µPD780988 Subseries Inverter Control Application Note
U13119E
U13119J
µPD780988 Subseries Special Function Register Table
–
U12806J
78K/0 Series Instruction Table
–
U10903J
78K/0 Series Instruction Set
–
U10904J
78K/0 Series Instructions User’s Manual
U12326E
U12326J
• Documents Related to Development Tools (User’s Manuals)
Document No.
Document Name
English
RA78K0 Assembler Package
Japanese
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
RA78K Series Structured Assembler Preprocessor
EEU-1402
U12323J
CC78K0 C Compiler
Operation
U11517E
U11517J
Language
U11518E
U11518J
CC78K0 C Compiler Application Note
U13034E
U13034J
IE-78K0-NS
Programming Know-How
To be prepared
To be prepared
IE-78001-R-A
To be prepared
To be prepared
IE-780988-NS-EM4
To be prepared
To be prepared
EP-78240
U10332E
EEU-986
SM78K0 System Simulator Windows Based Reference
U10181E
U10181J
SM78K Series System Simulator
U10092E
U10092J
U12900E
U12900J
External Part User Open
Interface Specifications
ID78K0-NS Integrated Debugger Windows Based
Reference
ID78K0 Integrated Debugger EWS Based
Reference
ID78K0 Integrated Debugger PC Based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger Windows Based
Guide
U11649E
U11649J
Caution
–
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
40
U11151J
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
• Documents Related to Embedded Software (User’s Manuals)
Document No.
Document Name
English
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Japanese
Fundamental
U11537E
U11537J
Installation
U11536E
U11536J
Fundamental
U12257E
U12257J
• Other Related Documents
Document Name
Document No.
English
Japanese
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
C11892J
Guide to Microcomputer-Related Products by Third Party
Caution
–
U11416J
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Preliminary Data Sheet U12805EJ1V0DS00
41
µPD78F0988
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
42
Preliminary Data Sheet U12805EJ1V0DS00
µPD78F0988
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U12805EJ1V0DS00
43
µPD78F0988
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8