To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. “Standard”: 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. “Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT μPD720102 USB 2.0 HOST CONTROLLER The μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed signaling and works up to 480 Mbps. The μPD720102 is integrated 2 host controller cores with PCI interface and USB 2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. μPD720102 User’s Manual: S17999E FEATURES • • • • • • • • • • • • • • • • Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps) Compliant with open host controller interface specification for USB release 1.0a Compliant with enhanced host controller interface specification for USB revision 1.0 PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host controller core for high-speed signaling Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction Supports hyper-speed transfer mode using HSMODE signal 32-bit 33 MHz host interface compliant with PCI specification revision 2.2 Supports PCI mobile design guide version 1.1 Supports PCI-bus power management interface specification revision 1.1 PCI bus bus-master access Supports 3.3 V PCI System clock is generated by 30 MHz crystal or 48 MHz clock input Operational registers direct-mapped to PCI memory space 3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator On chip Rs and Rpd resistors for USB signals ORDERING INFORMATION Part Number <R> μPD720102GC-YEB-A μPD720102F1-CA7-A Package Remark 120-pin plastic TQFP (fine pitch) (14 × 14) Lead-free product 121-pin plastic FBGA (8 × 8) Lead-free product The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17998EJ4V0DS00 (4th edition) Date Published March 2007 NS CP (N) Printed in Japan The mark "<R>" shows major revised points. 2006 μPD720102 BLOCK DIAGRAM PCI Bus PME0 INTA0 PCI Bus Interface WakeUp_Event WakeUp_Event Arbiter EHCI Host Controller OHCI Host Controller SMI0 Root Hub PHY Port 1 Port 2 USB Bus 2 Data Sheet S17998EJ4V0DS Port 3 μPD720102 PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification revision 2.2. The number of enabled ports is set by bit in configuration space. Arbiter : arbitrates among two OHCI host controller cores and one EHCI host controller core. OHCI Host Controller : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling. EHCI Host Controller : handles high- (480 Mbps) signaling. Root Hub : handles USB hub function in host controller and controls connection (routing) between host controller core and port. PHY : consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer, etc. INTA0 : is the PCI interrupt signal for OHCI Host Controller. SMI0 : is the interrupt signal which is specified by open host controller interface specification for USB release 1.0a and enhanced host controller interface specification revision 1.0. The SMI signal of each OHCI host controller and EHCI host controller appears at this signal. PME0 : is the interrupt signal which is specified by PCI-bus power management interface specification revision 1.1. Wakeup signal of each host controller core appears at this signal. Data Sheet S17998EJ4V0DS 3 μPD720102 PIN CONFIGURATION • 120-pin plastic TQFP (fine pitch) (14 × 14) μPD720102GC-YEB-A 95 100 105 110 1 120 90 5 85 10 80 15 75 20 70 25 65 60 55 50 45 VSS AD23 AD22 AD21 AD20 AD19 VDD AD18 VSS AD17 AD16 CBE20 FRAME0 IRDY0 VSS N.C. TRDY0 VDD DEVSEL0 STOP0 PERR0 SERR0 PAR VSS CBE10 AD15 VDD AD14 AD13 VSS 40 30 35 PPON1 OCI20 VSS PPON2 OCI30 PPON3 VDD VCCRST0 PME0 N.C. PCLK VSS VBBRST0 INTA0 GNT0 REQ0 AD31 VDD AD30 AD29 VSS AD28 AD27 AD26 AD25 AD24 VDD CBE30 IDSEL VDD15 115 OCI10 TEST3 TEST4 VDD VDD VDD15OUT VSS N.C. VDD VSS DP3 DM3 VDD VDD DP2 DM2 VSS VSS DP1 DM1 VDD15 VSS AVSS AVDD15 AVDD33 RREF AVSS(R) TESTEN HSMODE CLKSEL Top View 4 Data Sheet S17998EJ4V0DS SRDTA SRMOD SRCLK VSS SMI0 CRUN0 VDD XT2 N.C. XT1/SCLK VSS AD0 AD1 AD2 AD3 VDD AD4 AD5 AD6 VSS AD7 N.C. CBE00 AD8 AD9 VDD AD10 AD11 AD12 VDD15 μPD720102 Pin Name • 120-pin plastic TQFP (fine pitch) (14 × 14) μPD720102GC-YEB-A Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 PPON1 31 VSS 61 VDD15 91 CLKSEL 2 OCI20 32 AD23 62 AD12 92 HSMODE 3 VSS 33 AD22 63 AD11 93 TESTEN 4 PPON2 34 AD21 64 AD10 94 AVSS(R) 5 OCI30 35 AD20 65 VDD 95 RREF 6 PPON3 36 AD19 66 AD9 96 AVDD33 7 VDD 37 VDD 67 AD8 97 AVDD15 8 VCCRST0 38 AD18 68 CBE00 98 AVSS 9 PME0 39 VSS 69 N.C. 99 VSS 10 N.C. 40 AD17 70 AD7 100 VDD15 11 PCLK 41 AD16 71 VSS 101 DM1 12 VSS 42 CBE20 72 AD6 102 DP1 13 VBBRST0 43 FRAME0 73 AD5 103 VSS 14 INTA0 44 IRDY0 74 AD4 104 VSS 15 GNT0 45 VSS 75 VDD 105 DM2 16 REQ0 46 N.C. 76 AD3 106 DP2 17 AD31 47 TRDY0 77 AD2 107 VDD 18 VDD 48 VDD 78 AD1 108 VDD 19 AD30 49 DEVSEL0 79 AD0 109 DM3 20 AD29 50 STOP0 80 VSS 110 DP3 21 VSS 51 PERR0 81 XT1/SCLK 111 VSS 22 AD28 52 SERR0 82 N.C. 112 VDD 23 AD27 53 PAR 83 XT2 113 N.C. 24 AD26 54 VSS 84 VDD 114 VSS 25 AD25 55 CBE10 85 CRUN0 115 VDD15OUT 26 AD24 56 AD15 86 SMI0 116 VDD 27 VDD 57 VDD 87 VSS 117 VDD 28 CBE30 58 AD14 88 SRCLK 118 TEST4 29 IDSEL 59 AD13 89 SRMOD 119 TEST3 30 VDD15 60 VSS 90 SRDTA 120 OCI10 Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 1.6 kΩ. Data Sheet S17998EJ4V0DS 5 μPD720102 <R> PIN CONFIGURATION • 121-pin plastic FBGA (8 × 8) μ PD720102F1-CA7-A Bottom View 6 21 22 23 24 25 26 27 28 29 30 31 11 20 57 58 59 60 61 62 63 64 65 32 10 19 56 85 86 87 88 89 90 91 66 33 9 18 55 84 105 106 107 108 109 92 67 34 8 17 54 83 104 117 118 119 110 93 68 35 7 16 53 82 103 116 121 120 111 94 69 36 6 15 52 81 102 115 114 113 112 95 70 37 5 14 51 80 101 100 99 98 97 96 71 38 4 13 50 79 78 77 76 75 74 73 72 39 3 12 49 48 47 46 45 44 43 42 41 40 2 11 10 9 8 7 6 5 4 3 2 1 1 L K J H G F E D C B A Data Sheet S17998EJ4V0DS μPD720102 <R> Pin name • 121-pin plastic FBGA (8 × 8) μ PD720102F1-CA7-A Pin No. 1 Pin Name DP3 Pin No. 32 Pin Name RREF Pin No. 63 Pin Name Pin No. Pin Name VSS 94 VDD 2 PPON1 33 VDD15 64 SMI0 95 VDD15OUT 3 OCI30 34 DM1 65 AVSS(R) 96 TEST3 4 VCCRST0 35 DP1 66 AVDD33 97 VDD 5 PCLK 36 VSS 67 VSS 98 VDD 6 GNT0 37 DM2 68 VSS 99 VDD 7 AD30 38 DP2 69 VSS 100 VDD 8 AD28 39 VDD 70 VSS 101 VDD15 9 AD25 40 DM3 71 VSS 102 VDD15 10 CBE30 41 TEST4 72 VSS 103 VSS 11 VSS 42 OCI20 73 OCI10 104 VSS 12 AD23 43 PPON3 74 PPON2 105 VDD15 13 AD21 44 PME0 75 VBBRST0 106 VDD15 14 AD18 45 INTA0 76 AD31 107 VSS 15 CBE20 46 REQ0 77 AD27 108 VSS 16 TRDY0 47 AD29 78 IDSEL 109 VSS 17 STOP0 48 AD26 79 VSS 110 AVSS 18 PAR 49 AD24 80 AD19 111 VDD 19 AD14 50 AD22 81 AD16 112 VDD 20 VSS 51 AD20 82 IRDY0 113 VDD 21 AD12 52 AD17 83 SERR0 114 VSS 22 AD11 53 FRAME0 84 CBE10 115 VSS 23 CBE00 54 DEVSEL0 85 AD9 116 VDD 24 AD6 55 PERR0 86 AD8 117 VDD 25 AD3 56 AD15 87 AD4 118 VDD 26 AD1 57 AD13 88 AD0 119 VDD 27 XT1/SCLK 58 AD10 89 CRUN0 120 VDD 28 XT2 59 AD7 90 SCLK 121 VDD 29 SRMOD 60 AD5 91 SRDTA 30 HSMODE 61 AD2 92 CLKSEL 31 TESTEN 62 VSS 93 AVDD15 Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 1.6 kΩ. Data Sheet S17998EJ4V0DS 7 μPD720102 1. PIN INFORMATION (1/2) Pin Name I/O Buffer Type Active Function Level Normal (Test) AD (31:0) I/O 3.3 V PCI I/O with OR input PCI “AD [31:0]” signal CBE (3:0)0 I/O 3.3 V PCI I/O with OR input PCI “C/BE [3:0]” signal PAR I/O 3.3 V PCI I/O with OR input PCI “PAR” signal FRAME0 I/O 3.3 V PCI I/O with OR input Low PCI “FRAME#” signal IRDY0 I/O 3.3 V PCI I/O with OR input Low PCI “IRDY#” signal TRDY0 I/O 3.3 V PCI I/O with OR input Low PCI “TRDY#” signal STOP0 I/O 3.3 V PCI I/O with OR input Low PCI “STOP#” signal IDSEL I 3.3 V PCI input with OR input High PCI “IDSEL” signal I/O 3.3 V PCI I/O with OR input Low PCI “DEVSEL#” signal REQ0 O (I/O) 3.3 V PCI I/O with OR input Low PCI “REQ#” signal GNT0 I 3.3 V PCI input with OR input Low PCI “GNT#” signal 3.3 V PCI I/O with OR input Low PCI “PERR#” signal Low PCI “SERR#” signal Low PCI “INTA#” signal DEVSEL0 PERR0 I/O SERR0 O (I/O) 3.3 V PCI I/O with OR input 3.3 V PCI I/O with OR input Note 1 Note 1 INTA0 O (I/O) PCLK I 3.3 V PCI input with OR input VBBRST0 I 3.3 V schmitt input Low PCI “RST#” signal PCI “CLK” signal CRUN0 I/O 3.3 V PCI I/O with OR input Low PCI “CLKRUN#” signal PME0 O N-ch open drain buffer Low PCI “PME#” signal VCCRST0 I 3.3 V schmitt input Low PCI “RST#” signal for D3cold support 3.3 V I/O buffer Low System management interrupt output SMI0 O (I/O) XT1/SCLK I OSC block System clock input or oscillator in XT2 O OSC block Oscillator out CLKSEL I 3.3 V Input Input clock frequency select signal HSMODE I 3.3 V Input High Hyper-Speed transfer mode enable signal SRCLK O (I/O) 3.3 V I/O buffer Serial ROM clock out SRDTA I/O 3.3 V I/O buffer Serial ROM data SRMOD TESTEN TEST3 TEST4 Note 2 Note 2 Note 2 I 3.3 V Input with pull down resistor High Serial ROM input enable I 3.3 V Input with pull down resistor High Test enable pin I 3.3 V Input with pull down resistor High Test control I 3.3 V Input with pull down resistor High Test control Notes 1. These signals become N-ch open drain buffers in normal operation. 2. These pins must be open on board. 8 Data Sheet S17998EJ4V0DS μPD720102 (2/2) Pin Name I/O Buffer Type Active Function Level Normal (Test) OCI (3:1)0 I (I/O) 3.3 V I/O buffer with OR input Low USB port’s overcurrent status input PPON (3:1) O (I/O) 3.3 V I/O buffer High USB port’s power supply control output DP (3:1) I/O USB high speed D+ I/O USB high speed D+ signal DM (3:1) I/O USB high speed D− I/O USB high speed D− signal RREF A Analog Reference resistor VDD15OUT O Internal regulator output 1.5 V voltage output from internal regulator VDD15 1.5 V VDD from VDD15OUT VDD 3.3 V VDD AVDD15 1.5 V VDD for analog circuit AVDD33 3.3 V VDD for analog circuit VSS VSS AVSS VSS for analog circuit AVSS(R) VSS for RREF circuit N.C. No connection Remark The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. Data Sheet S17998EJ4V0DS 9 μPD720102 2. HOW TO CONNECT TO EXTERNAL ELEMENTS 2.1 Handling Unused Pins To realize less than 3 ports host controller implementation, appropriate value shall be set to Port No field in EXT1 register. And unused pins shall be connected as shown below. Table 2-1. Unused Pin Connection Pin Direction Connection Method DPx I/O No connection (Open) DMx I/O No connection (Open) OCIx I “H” clamp PPONx O No connection (Open) 2.2 USB Port Connection Figure 2–1. USB Downstream Port Connection μ PD720102 from Power switch output Downstream port USB A receptacle connector VBUS D− D+ DMn DPn GND 10 Data Sheet S17998EJ4V0DS 1 2 3 4 μPD720102 2.3 Internal Regulator Circuit Connection Figure 2–2. Internal Regulator Circuit Connection μ DD15 DD15 DD15 3.3 μ F (Ceramic type only) Caution VDD15OUT must be routed to only VDD15 (and AVDD15). In case that VDD15OUT is also used for power supply of other ICs, this may cause unstable operation of the μPD720102. Remark VDD15 is powered by VDD15OUT from internal regulator. It is not necessary to use external regulator for VDD15. 2.4 Analog Circuit Connection Figure 2–3. Analog Circuit Connection μ 1.6 kΩ+1 − % 55 55 <R> Remark The board layout should minimize the total path length from RREF through the resistor to AVSS(R) and path length to AVSS (analog ground). AVSS must be stable. Data Sheet S17998EJ4V0DS 11 μPD720102 2.5 Crystal Connection Figure 2–4. Crystal Connection μ Crystal The following crystals are evaluated on our reference design board. Table 2-2 shows the external parameters. Table 2-2. External Parameters Vender KDS NDK Note 1 Note 2 Crystal R C1 C2 AT-49 30.000 MHz 100 Ω 12 pF 12 pF AT-41 30.000 MHz 470 Ω 10 pF 10 pF Notes 1. DAISHINKU CORP. 2. NIHON DEMPA KOGYO CO., LTD. In using these crystals, contact KDS or NDK to get the specification on external components to be used in conjunction with the crystal. KDS's home page: http://www.kds.info/english.html NDK's home page: http://www.ndk.com/ 12 Data Sheet S17998EJ4V0DS μPD720102 2.6 External Serial ROM Connection Figure 2–5. External Serial ROM Connection 3.3 V μ 1.5 kΩ ,, The following serial ROM is used on our reference design board. Table 2-3. External Parameters Vender Atmel Corporation Product name AT24C01A-10SC-2.7 Size 128 bytes SRMOD/SRCLK/SRDTA can be opened, when serial ROM is not necessary on board. Data Sheet S17998EJ4V0DS 13 μPD720102 3. ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 3.3 V input buffer • CLKSEL, HSMODE 3.3 V input buffer with pull down resistor • SRMOD, TESTEN, TEST3, TEST4 3.3 V input schmitt buffer • VBBRST0, VCCRST0 3.3 V IOL = 9 mA bi-directional buffer • SMI0, PPON(3:1), SRCLK, SRDTA 3.3 V IOL = 9 mA bi-directional buffer with enable (OR type) • OCI(3:1)0 3.3 V PCI input buffer with enable (OR type) • IDSEL, GNT0, PCLK 3.3 V PCI bi-directional buffer with enable (OR type) AD(31:0), CBE(3:0)0, PAR, FRAME0, IRDY0, TRDY0, STOP0, DEVSEL0, REQ0, PERR0, SERR0, INTA0, • CRUN0 N-ch open drain buffer • PME0 3.3 V oscillator interface • XT1/SCLK, XT2 USB interface, analog signal DP(3:1), DM(3:1), RREF 14 Data Sheet S17998EJ4V0DS μPD720102 3.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Symbol Meaning VDD, VDD15, Indicates the voltage range within which damage or reduced reliability will not AVDD33, result when power is applied to a VDD pin. AVDD15 Input voltage VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into output pin. Operating ambient temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD, AVDD33 Indicates the voltage range for normal logic operations occur when VSS = 0 V. High-level input voltage VIH Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Hysteresis voltage VH Input rise time tri Indicates the differential between the positive and the negative trigger voltage. Indicates allowable input rise time to input signal transition time from 0.1 x VDD to 0.9 x VDD. Input fall time tfi Indicates allowable input fall time to input signal transition time from 0.9 x VDD to 0.1 x VDD. Data Sheet S17998EJ4V0DS 15 μPD720102 Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Input leakage current II Indicates the current that flows when the input voltage is supplied to the input pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. 16 Data Sheet S17998EJ4V0DS μPD720102 3.3 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Symbol Condition Rating Unit VDD, AVDD33 −0.5 to +4.6 V VDD15, AVDD15 −0.5 to +2.0 V Input voltage, 3.3 V buffer VI VI < VDD + 0.5 V −0.5 to +4.6 V Output voltage, 3.3 V buffer VO VO < VDD + 0.5 V −0.5 to +4.6 V Output current IO 3.3 V buffer (IOL = 9 mA) 29 mA PCI buffer 58 mA Operating ambient temperature TA −20 to +70 °C Storage temperature Tstg −40 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Symbol Operating voltage VDD, AVDD33 High-level input voltage VIH 3.3 V high-level input voltage Condition Min. Typ. Max. Unit 3.135 3.3 3.465 V VBBRST0, VCCRST0 2.4 VDD V Other input pins 2.0 VDD V VBBRST0, VCCRST0 0 0.6 V Other input pins 0 0.8 V 0.3 1.5 V Normal buffer 0 200 ns Schmitt buffer 0 10 ms Normal buffer 0 200 ns Schmitt buffer 0 10 ms Low-level input voltage VIL 3.3 V low-level input voltage Hysteresis voltage VH 3.3 V hysteresis voltage Input rise time Input fall time tri tfi Data Sheet S17998EJ4V0DS 17 μPD720102 DC Characteristics (VDD = 3.135 to 3.465 V, TA = −20 to +70°C) Control pin block Parameter Symbol Off-state output current IOZ Low-level output current IOL Max. Unit ±10 μA VOL = 0.4 V 9.0 mA VOH = 2.4 V −9.0 mA IOH 3.3 V high-level output current (9 mA) Input leakage current Min. VO = VDD or VSS 3.3 V low-level output current (9 mA) High-level output current Condition II 3.3 V buffer VI = VDD or VSS ±10 μA 3.3 V buffer with pull down resistor VI = VDD 175 μA Min. Max. Unit PCI interface block Parameter Symbol Condition High-level input voltage VIH 0.5VDD VDD+0.5 V Low-level input voltage VIL –0.5 0.3VDD V Low-level output current IOL VOL = 0.1VDD 1.5 mA High-level output current IOH VOH = 0.9VDD –0.5 mA Input leakage current Iil 0 < VIN < VDD PME0 leakage current IOFF VO < 3.6 V VDD off or floating 18 Data Sheet S17998EJ4V0DS ±10 μA 1 μA μPD720102 USB interface block Parameter Min. Max. Unit ZHSDRV 40.5 49.5 Ω High-level input voltage (drive) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI ⏐(D+) − (D−)⏐ 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V VHSSQ 100 150 mV VHSDSC 525 625 mV VHSCM −50 +500 mV Output pin impedance Symbol Conditions Input Levels for Low-/full-speed: V 3.6 V 0.8 V V Output Levels for Low-/full-speed: V Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level See Figure 3–2. Output Levels for High-speed: High-speed idle state VHSOI −10 +10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10 +10 mV Chirp J level (differential signal) VCHIRPJ 700 1100 mV Chirp K level (differential signal) VCHIRPK −900 −500 mV Data Sheet S17998EJ4V0DS 19 μPD720102 Figure 3–1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Input Voltage Range (V) Figure 3–2. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 1 Point 4 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3–3. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ D− Gnd 15.8 Ω 143 Ω 20 50 Ω Coax 50 Ω Coax 143 Ω Data Sheet S17998EJ4V0DS + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 4.6 μPD720102 Power consumption Parameter Symbol Power PWD0-0 Consumption Condition With 30 MHz With 48 MHz Crystal Oscillator Unit Typ. Max. Typ. Max. 11.0 16.0 3.0 7.0 mA Full- or low-speed device is on the port. 15.6 22.6 7.7 13.5 mA High-speed device is on the port. 60.3 70.8 60.7 71.3 mA Full- or low-speed devices are on the port. 17.4 31.6 9.5 22.4 mA High-speed devices are on the port. 96.1 111.8 96.6 112.4 mA Full- or low-speed devices are on the port. 18.8 40.0 10.8 31.5 mA High-speed devices are on the port. 130.7 151.8 131.2 152.2 mA 11.0 16.0 3.0 7.0 mA 2.1 5.9 3.0 7.0 mA 2.1 5.9 3.0 7.0 mA 2.1 5.9 3.0 7.0 mA 0.03 3.0 1.38 5.2 mA Device state = D0, All the ports does not connect to any function, and each OHCI controller is under USB suspend Note 1 and EHCI controller is stopped. PWD0-1 PWD0-2 PWD0-3 PWD0_C The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 1. The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 2. The power consumption under the state without suspend. Note 2 Device state = D0, The number of active ports is 3. The power consumption under suspend state during PCI clock is stopped by CRUN0. Device state = D0. PWD1 Device state = D1, Analog PLL output is stopped. Note 3 Note 3 PWD2 Device state = D2, Analog PLL output is stopped. PWD3H Device state = D3hot, VCCRST0 = High, Analog PLL Note 3 output is stopped. PWD3C Device state = D3cold, VCCRST0 = Low. Note 4 Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No Field in PCI configuration space EXT register. 3. This is the case when PCI bus state is B0. 4. This is the case when PCI bus state is B3. Remark These are estimated value on Windows™ XP environment. Pin capacitance Parameter Symbol Condition Min. Max. Unit Input capacitance CI VDD = 0 V, TA = 25°C 8 pF Output capacitance CO fC = 1 MHz 8 pF I/O capacitance CIO Unmeasured pins returned to 0 V 8 pF PCI input pin capacitance Cin 8 pF PCI clock input pin capacitance Cclk 8 pF CIDSEL 8 pF PCI IDSEL input pin capacitance Data Sheet S17998EJ4V0DS 21 μPD720102 AC Characteristics (VDD = 3.135 to 3.465 V, TA = −20 to +70°C) System clock ratings Parameter Symbol Clock frequency fCLK Condition Crystal Min. Typ. Max. Unit −500 30 +500 MHz ppm ppm −500 Oscillator block +500 48 Clock duty cycle tDUTY 40 MHz ppm ppm 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of crystal or oscillator block is including initial frequency accuracy, the spread of crystal capacitor loading, supply voltage, temperature, and aging, etc. PCI interface block Parameter Min. Max. Unit tcyc 30 33 ns PCI clock pulse, high-level width thigh 11 ns PCI clock pulse, low-level width tlow 11 ns PCI clock, rise slew rate Scr 0.2VDD to 0.6VDD 1 4 V/ns PCI clock, fall slew rate Scf 0.2VDD to 0.6VDD 1 4 V/ns PCI reset active time (vs. power supply stability) trst PCI reset active time (vs. CLK start) trst-clk Output float delay time (vs. RST0↓) trst-off PCI reset rise slew rate Srr 50 PCI bus signal output time (vs. PCLK↑) tval 2 11 ns PCI point-to-point signal output time (vs. PCLK↑) tval (ptp) 2 12 ns Output delay time (vs. PCLK↑) ton Output float delay time (vs. PCLK↑) toff Input setup time (vs. PCLK↑) tsu Point-to-point input setup time (vs. PCLK↑) tsu (ptp) Input hold time th <R> PCI clock cycle time 22 Symbol Condition 1 ms 100 μs 40 REQ0 mV/ns 2 ns 28 GNT0 Data Sheet S17998EJ4V0DS ns ns 7 ns 10 ns 0 ns μPD720102 USB interface block (1/2) Parameter Symbol Conditions Min. Max. Unit Low-speed Source Electrical Characteristics Rise time (10 to 90%) tLR CL = 200 to 600 pF, RS = 36 Ω 75 300 ns Fall time (90 to 10%) tLF CL = 200 to 600 pF, RS = 36 Ω 75 300 ns Differential rise and fall time matching tLRFM (tLR/tLF) 80 125 % Low-speed data rate tLDRATHS Average bit rate 1.49925 1.50075 Mbps Source jitter total (including frequency tolerance): To next transition tDDJ1 −25 +25 ns For paired transitions tDDJ2 −14 +14 ns tLDEOP −40 +100 ns tUJR1 −152 +152 ns For paired transitions tUJR2 −200 +200 ns Source SE0 interval of EOP tLEOPT 1.25 1.50 μs Receiver SE0 interval of EOP tLEOPR 670 Width of SE0 interval during differential tFST Source jitter for differential transition to SE0 transition Receiver jitter: To next transition ns 210 ns transition Full-speed Source Electrical Characteristics Rise time (10 to 90%) tFR CL = 50 pF 4 20 ns Fall time (90 to 10%) tFF CL = 50 pF 4 20 ns Differential rise and fall time matching tFRFM (tFR/tFF) 90 111.11 % Full-speed data rate tFDRATHS Average bit rate 11.9940 12.0060 Mbps Frame interval tFRAME 0.9995 1.0005 ms Consecutive frame interval jitter tRFI 42 ns No clock adjustment Source jitter total (including frequency tolerance): To next transition tDJ1 −3.5 +3.5 ns For paired transitions tDJ2 −4.0 +4.0 ns −2 +5 ns Source jitter for differential transition to tFDEOP SE0 transition Receiver jitter: To next transition tJR1 −18.5 +18.5 ns For paired transitions tJR2 −9 +9 ns Source SE0 interval of EOP tFEOPT 160 175 ns Receiver SE0 interval of EOP tFEOPR 82 Width of SE0 interval during differential tFST ns 14 ns transition Data Sheet S17998EJ4V0DS 23 μPD720102 (2/2) Parameter Symbol Conditions Min. Max. Unit High-speed Source Electrical Characteristics Rise time (10 to 90%) tHSR 500 ps Fall time (90 to 10%) tHSF 500 ps Driver waveform See Figure 3–4. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 μs Consecutive microframe interval difference tHSRFI Data source jitter See Figure 3–4. Receiver jitter tolerance See Figure 3–2. 4 high- Bit speed times Hub Event Timings Time to detect a downstream facing port tDCNN 2.5 2000 μs tDDIS 2.0 2.5 μs connect event Time to detect a disconnect event at a hub’s downstream facing port Duration of driving resume to a tDRSMDN Nominal 20 ms downstream port Time from detecting downstream resume tURSM 1.0 ms to rebroadcast Inter-packet delay for packets traveling in tHSIPDSD 88 Bit same direction for high-speed Inter-packet delay for packets traveling in times tHSIPDOD 8 Bit opposite direction for high-speed Inter-packet delay for root hub response for times tHSRSPIPD1 192 high-speed Time for which a Chirp J or Chirp K must Bit times μs 2.5 tFILT be continuously detected during reset handshake Time after end of device Chirp K by which tWTDCH 100 μs hub must start driving first Chirp K Time for which each individual Chirp J or tDCHBIT 40 60 μs tDCHSE0 100 500 μs Chirp K in the chirp sequence is driven downstream during reset Time before end of reset by which a hub must end its downstream chirp sequence 24 Data Sheet S17998EJ4V0DS μPD720102 Figure 3–4. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3–5. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ D− Gnd 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Data Sheet S17998EJ4V0DS 25 μPD720102 3.4 Timing Diagram PCI clock tcyc thigh tlow 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD 0.4VDD (ptp: Min.) PCI reset PCLK 100 ms (Typ.) PWR_GOOD trst-clk trst VBBRST0 trst-off PCI Signals 26 Valid Data Sheet S17998EJ4V0DS μPD720102 PCI output timing measurement condition 0.6VDD PCLK 0.4VDD 0.2VDD tval, tval (ptp) 0.615VDD (for falling edge) Output delay 0.285VDD (for falling edge) 3-state output delay ton toff PCI input timing measurement condition 0.6VDD 0.4VDD PCLK 0.2VDD tsu, tsu (ptp) th 0.6VDD Input 0.4VDD 0.2VDD Data Sheet S17998EJ4V0DS 27 μPD720102 USB differential data jitter for full-speed tPERIOD Crossover Points Differential Data Lines Consecutive Transitions N × tPERIOD + txDJ1 Paired Transitions N × tPERIOD + txDJ2 USB differential-to-EOP transition skew and EOP width for low-/full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff. Data-toSE0 Skew N × tPERIOD + txDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR USB receiver jitter tolerance for low-/full-speed tPERIOD Differential Data Lines txJR txJR1 Consecutive Transitions N × tPERIOD + txJR1 Paired Transitions N × tPERIOD + txJR2 28 Data Sheet S17998EJ4V0DS txJR2 μPD720102 Low-/full-speed disconnect detection D+/D− VIZH (Min.) VIL D−/D+ VSS tDDIS Device Disconnected Disconnect Detected Full-/high-speed device connect detection D+ VIH D− VSS tDCNN Device Connected Connect Detected Low-speed device connect detection D− VIH D+ VSS tDCNN Device Connected Connect Detected Data Sheet S17998EJ4V0DS 29 μPD720102 4. PACKAGE DRAWINGS • μPD720102GC-YEB-A 120-PIN PLASTIC TQFP (FINE PITCH) (14x14) A B 90 91 61 60 detail of lead end C D S P T 120 1 R 31 30 U F G L Q H I J M K S N S M ITEM MILLIMETERS NOTE A 16.00±0.20 Each lead centerline is located within 0.07 mm of its true position (T.P.) at maximum material condition. B 14.00±0.20 C D 14.00±0.20 16.00±0.20 F 1.20 G H 1.20 0.18±0.05 I 0.07 J 0.40 (T.P.) K 1.00±0.20 L 0.50 M 0.17 +0.03 −0.07 N 0.08 P 1.00±0.05 Q 0.10±0.05 R +4° 3° −3° S 1.20MAX. T 0.25 U 30 Data Sheet S17998EJ4V0DS 0.60±0.15 P120GC-40-YEB-1 μPD720102 <R> • μ PD720102F1-CA7-A 121-PIN PLASTIC FBGA (8x8) w S A D ZE ZD A 11 10 9 8 7 6 5 4 3 2 1 B E L K J H G F E D C B A w S B INDEX MARK INDEX MARK A y1 A2 S (UNIT:mm) S y e S φb φx M A1 S AB ITEM D DIMENSIONS 8.00±0.10 E 8.00±0.10 w 0.20 A 0.99±0.10 A1 0.30±0.05 A2 0.69 e 0.65 b 0.40 ±0.05 x 0.08 y 0.10 y1 0.20 ZD 0.75 ZE Data Sheet S17998EJ4V0DS 0.75 P121F1-65-CA7 31 μPD720102 5. RECOMMENDED SOLDERING CONDITIONS The μPD720102 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) • μPD720102GC-YEB-A: 120-pin plastic TQFP (Fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Peak package’s surface temperature: 260 °C, Reflow time: 60 seconds or less Symbol IR60-107-3 (220 °C or higher), Maximum allowable number of reflow processes: 3, Exposure limit Note : 7 days (10 to 72 hours pre-backing is required at 125C° afterwards), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Partial heating method Pin temperature: 350°C or below, – Heat time: 3 seconds or less (per each side of the device) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Note The Maximum number of days during which the product can be stored at a temperature of 5 to 25°C and a relative humidity of 20 to 65% after dry-pack package is opened. <R> • μPD720102F1-CA7-A: 121-pin plastic FBGA (8 × 8) Soldering Method Infrared reflow Soldering Conditions Peak package’s surface temperature: 260 °C, Reflow time: 60 seconds or less Symbol IR60-107-3 (220 °C or higher), Maximum allowable number of reflow processes: 3, Exposure limit Note : 7 days (10 to 72 hours pre-backing is required at 125C° afterwards), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Note The Maximum number of days during which the product can be stored at a temperature of 5 to 25°C and a relative humidity of 20 to 65% after dry-pack package is opened. 32 Data Sheet S17998EJ4V0DS μPD720102 [MEMO] Data Sheet S17998EJ4V0DS 33 μPD720102 [MEMO] 34 Data Sheet S17998EJ4V0DS μPD720102 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17998EJ4V0DS 35 μPD720102 USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is current as of March, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1