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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT μPD720114 ECOUSBTM Series USB 2.0 HUB CONTROLLER The μPD720114 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision 2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports. The μPD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1 compliant host. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. μPD720114 User’s Manual: S17463E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • High-speed or full-speed packet protocol sequencer for Endpoint 0/1 • 4 (Max.) downstream facing ports • Low power consumption (10 μA when hub in idle status, 149 mA when all parts run in HS mode) • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when Hub controller is working in high-speed mode. • One Transaction Translator per Hub and supports four non-periodic buffers • Supports self-powered and bus-powered mode • Supports individual or global over-current detection and individual or ganged power control • Supports downstream port status with LED • Supports non-removable devices by I/O pin configuration • Support Energy Star for PC peripheral system • On chip Rpu, Rpd resistors and regulator (for core logic) • Use 30 MHz crystal • 3.3 V power supply The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17462EJ6V0DS00 (6th edition) Date Published December 2009 NS Printed in Japan The mark "<R>" shows major revised points. 2005 μPD720114 ORDERING INFORMATION Part Number Package μPD720114GA-9EU-A μPD720114GA-YEU-A <R> μPD720114K9-4E4-A Remark 48-pin plastic TQFP (Fine pitch) (7 × 7) Lead-free product 48-pin plastic TQFP (Fine pitch) (7 × 7) Lead-free product 40-pin plastic QFN (6 × 6) Lead-free product BLOCK DIAGRAM To Host/Hub downstream facing port Upstream facing port UP_PHY CDR SERDES UPC FS_REP SIE_2H CDR ALL_TT F_TIM EP1 DP(1)_PHY Downstream facing port #1 To Hub/Function upstream facing port EP0 DP(2)_PHY Downstream facing port #2 To Hub/Function upstream facing port APLL DP(3)_PHY Downstream facing port #3 X1/X2 To Hub/Function upstream facing port OSB DP(4)_PHY Downstream facing port #4 2.5V REG 2 Data Sheet S17462EJ6V0DS To Hub/Function upstream facing port μPD720114 APLL : Generates all clocks of Hub. ALL_TT : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. ALL_TT buffers the data transfer from either upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/low-speed to high-speed. CDR : Data & clock recovery circuit DPC : Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and DP(n)_PHY : Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and EP0 : Endpoint 0 controller EP1 : Endpoint 1 controller F_TIM (Frame Timer) : Manages hub’s synchronization by using micro-SOF which is received at upstream Resume low-speed (1.5 Mbps) transaction port, and generates SOF packet when full/low-speed device is attached to downstream facing port. FS_REP : Full/low-speed repeater is enabled when the μPD720114 are worked at full-speed mode OSB : Oscillator Block 2.5V REG : On chip 2.5V regulator SERDES : Serializer and Deserializer SIE_2H : Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer. UP_PHY : Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps) transaction UPC : Upstream Port Controller handles Suspend and Resume Data Sheet S17462EJ6V0DS 3 μPD720114 PIN CONFIGURATION (TOP VIEW) • 48-pin plastic TQFP (Fine pitch) (7 × 7) VDD33REG VBUSM CSB1 PPB1 CSB2 PPB2 VSS CSB3 PPB3 CSB4 PPB4 SYSRSTB μPD720114GA-9EU-A μPD720114GA-YEU-A 48 47 46 45 44 43 42 41 40 39 38 37 VDD25OUT VSSREG LED4 LED3 LED2 LED1 GREEN AMBER VDD33 X1 X2 VDD25 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 BUS_B TEST RREF AVSS(R) AVDD AVSS AVDD VDD33 DMU DPU VSS VDD25 13 14 15 16 17 18 19 20 21 22 23 24 4 Data Sheet S17462EJ6V0DS VSS DP4 DM4 VDD25 DP3 DM3 VDD33 DP2 DM2 VSS DP1 DM1 μPD720114 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD25OUT 13 BUS_B 25 DM1 37 SYSRSTB 2 VSSREG 14 TEST 26 DP1 38 PPB4 3 LED4 15 RREF 27 VSS 39 CSB4 4 LED3 16 AVSS(R) 28 DM2 40 PPB3 5 LED2 17 AVDD 29 DP2 41 CSB3 6 LED1 18 AVSS 30 VDD33 42 VSS 7 GREEN 19 AVDD 31 DM3 43 PPB2 8 AMBER 20 VDD33 32 DP3 44 CSB2 9 VDD33 21 DMU 33 VDD25 45 PPB1 10 X1 22 DPU 34 DM4 46 CSB1 11 X2 23 VSS 35 DP4 47 VBUSM 12 VDD25 24 VDD25 36 VSS 48 VDD33REG Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ. Data Sheet S17462EJ6V0DS 5 μPD720114 • 40-pin plastic QFN (6 × 6) <R> VDD33REG VBUSM CSB1 PPB1 CSB2 PPB2 CSB3 PPB3 CSB4 PPB4 μPD720114K9-4E4-A 40 39 38 37 36 35 34 33 32 31 VDD25OUT LED4 LED3 LED2 LED1 GREEN AMBER VDD33 X1 X2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 GND area SYSRSTB DP4 DM4 VDD25 DP3 DM3 VDD33 DP2 DM2 DP1 BUS_B TEST RREF AVDD AVDD VDD33 DMU DPU VDD25 DM1 11 12 13 14 15 16 17 18 19 20 Pin No. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VDD25OUT 11 BUS_B 21 DP1 31 PPB4 2 LED4 12 TEST 22 DM2 32 CSB4 3 LED3 13 RREF 23 DP2 33 PPB3 4 LED2 14 AVDD 24 VDD33 34 CSB3 5 LED1 15 AVDD 25 DM3 35 PPB2 6 GREEN 16 VDD33 26 DP3 36 CSB2 7 AMBER 17 DMU 27 VDD25 37 PPB1 8 VDD33 18 DPU 28 DM4 38 CSB1 9 X1 19 VDD25 29 DP4 39 VBUSM 10 X2 20 DM1 30 SYSRSTB 40 VDD33REG Remark 6 Pin Name RREF should be connected to ground through 1% precision reference resistor of 2.43 kΩ. Data Sheet S17462EJ6V0DS μPD720114 1. PIN INFORMATION Pin Name I/O Buffer Type Active Level Function X1 I 2.5 V input 30 MHz Crystal oscillator in X2 O 2.5 V output 30 MHz Crystal oscillator out SYSRSTB I 3.3 V Schmitt input DP(4:1) I/O USB D+ signal I/O USB’s downstream facing port D+ signal DM(4:1) I/O USB D− signal I/O USB’s downstream facing port D− signal DPU I/O USB D+ signal I/O USB’s upstream facing port D+ signal DMU I/O USB D− signal I/O USB’s upstream facing port D− signal BUS_B I 3.3 V Schmitt input Power mode select RREF A (O) Analog Reference resistor connection CSB1 I 5 V tolerant Schmitt input Low Port’s over-current status input. CSB(4:2) I 3.3 V Schmitt input Low Port’s over-current status input PPB(4:1) I/O 3.3 V output / input Low Low Asynchronous chip hardware reset Port’s power supply control output or hub configuration input VBUSM I AMBER I/O 5 V tolerant Schmitt input Upstream VBUS monitor 3.3V output / input Amber colored LED control output or port indicator select GREEN O 3.3V output Green colored LED control output or port indicator select LED(4:1) I/O 3.3V output / input Low LED indicator output show downstream port status or Removable/Non-removable select TEST I 3.3 V Schmitt input Test signal VDD25OUT On chip 2.5 V regulator output, it must have a 22 μF (or greater) capacitor to VSSREG VDD33 3.3 V VDD VDD33REG 3.3 V VDD for on chip 2.5 V regulator input, it must have a 4.7 μF ( or greater) capacitor to VSSREG VDD25 2.5 V VDD. These pins must be supplied from VDD25OUT, output from internal regulator AVDD 2.5 V VDD for analog circuit VSS VSS VSSREG On chip 2.5 V regulator VSS AVSS VSS for analog circuit AVSS(R) VSS for reference resistor, Connect to AVSS. Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. Data Sheet S17462EJ6V0DS 7 μPD720114 2. ELECTRICAL SPECIFICATIONS 2.1 Buffer List • 2.5 V Oscillator interface • 5 V tolerant Schmitt input buffer • 3.3 V Schmitt input buffer • 3.3 V IOL = 12 mA output buffer • 3.3 V input and 3.3 V IOL = 3 mA output buffer • 3.3 V input and IOL = 12 mA output buffer • USB2.0 interface X1, X2 CSB1, VBUSM CSB(4:2),BUS_B, SYSRSTB, TEST GREEN PPB(4:1), LED(4:1) AMBER DPU, DMU, DP(4:1), DM(4:1), RREF Above, “5 V” refers to a 3 V input buffer that is 5 V tolerant (has 5 V maximum input voltage). Therefore, it is possible to have a 5 V connection for an external bus. 8 Data Sheet S17462EJ6V0DS μPD720114 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage VDD33, VDD33REG Input voltage VI Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Output voltage VO Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Output current IO Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into an output pin. Operating temperature TA Indicates the ambient temperature range for normal logic operations. Storage temperature Tstg Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. Terms Used in Recommended Operating Range Parameter Symbol Meaning Power supply voltage VDD33, VDD33REG Indicates the voltage range for normal logic operations to occur when VSS = 0 V. High-level input voltage VIH Indicates the voltage, applied to the input pins of the device, which indicates the high level state for normal operation of the input buffer. * If a voltage that is equal to or greater than the “Min.” value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, applied to the input pins of the device, which indicates the low level state for normal operation of the input buffer. * If a voltage that is equal to or less than the “Max.” value is applied, the input voltage is guaranteed as low level voltage. Hysteresis voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage. Input rise time tri Indicates allowable input rise time to input signal transition time from 0.1 × VDD to 0.9 × VDD. Input fall time tfi Indicates allowable input fall time to input signal transition time from 0.9 × VDD to 0.1 × VDD. Data Sheet S17462EJ6V0DS 9 μPD720114 Terms Used in DC Characteristics Parameter Off-state output leakage current Symbol IOZ Meaning Indicates the current that flows into a 3-state output pin when it is in a highimpedance state and a voltage is applied to the pin. Output short circuit current IOS Indicates the current that flows from an output pin when it is shorted to GND pins. Input leakage current II Indicates the current that flows into an input pin when a voltage is applied to the pin. Low-level output current IOL Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. High-level output current IOH Indicates the current that can flow out of an output pin in the high-level state without reducing the output voltage below the specified VOH. (A negative current indicates current flowing out of the pin.) 10 Data Sheet S17462EJ6V0DS μPD720114 2.3 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage VDD33,VDD33REG Input/output voltage VI/VO Condition 3.0 V ≤ VDD33 ≤ 3.6 V 3.3 V input/output voltage Rating Unit −0.5 to +4.6 V −0.5 to +4.6 V −0.5 to +6.6 V 10 40 mA mA VI /VO < VDD33 + 1.0 V 3.0 V ≤ VDD33 ≤ 3.6 V 5 V input/out voltage VI /VO < VDD33 + 3.0 V Output current IO IOL = 3 mA IOL = 12 mA Operating temperature TA 0 to +85 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges Parameter Symbol Operating voltage VDD33,VDD33REG High-level input voltage VIH Condition Min. Typ. Max. Unit 3.3 V for VDD33 pins 3.14 3.30 3.46 V 3.3 V High-level input voltage 2.0 VDD33 V 5.0 V High-level input voltage 2.0 5.5 V 3.3 V Low-level input voltage 0 0.8 V 5.0 V Low-level input voltage 0 0.8 V 5 V Hysteresis voltage 0.3 1.5 V 3.3 V Hysteresis voltage 0.2 1.0 V 10 ms Low-level input voltage Hysteresis voltage VIL VH Input rise time for SYSRSTB trst Input rise time tri Normal buffer 0 200 ns Schmitt buffer 0 10 ms Normal buffer 0 200 ns Schmitt buffer 0 10 ms Input fall time tfi Data Sheet S17462EJ6V0DS 11 μPD720114 DC Characteristics (VDD33 = 3.14 to 3.46 V, TA = 0 to +70 °C) Control Pin Block Parameter Off-state output leakage current Symbol IOZ Output short circuit current IOS Low-level output current IOL Condition Min. VO = VDD33, VDD25 or VSS Note Max. Unit ±10 μA −250 mA 3.3 V low-level output current (3 mA) VOL = 0.4 V 3 mA 3.3 V low-level output current (12 mA) VOL = 0.4 V 12 mA 3.3 V high-level output current (3 mA) VOH = 2.4 V −3 mA 3.3 V high-level output current (12 VOH = 2.4 V −12 mA High-level output current IOH mA) Input leakage current II 3.3 V buffer VI = VDD or VSS ±10 μA 5.0 V buffer VI = VDD or VSS ±10 μA Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI. 12 Data Sheet S17462EJ6V0DS μPD720114 USB Interface Block Parameter Symbol Conditions Includes RS resistor Min. Max. Unit 40.5 49.5 Ω 3.6 V Output pin impedance ZHSDRV Termination voltage for upstream facing port pullup (full-speed) VTERM 3.0 High-level input voltage (drive) VIH 2.0 High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI ⏐(D+) − (D−)⏐ 0.2 Differential common mode range VCM Includes VDI range 0.8 2.5 V High-level output voltage VOH RL of 14.25 kΩ to GND 2.8 3.6 V Low-level output voltage VOL RL of 1.425 kΩ to 3.6 V 0.0 0.3 V SE1 VOSE1 0.8 Output signal crossover point voltage VCRS 1.3 2.0 V High-speed squelch detection threshold (differential signal) VHSSQ 100 150 mV High-speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV High-speed data signaling common mode voltage range VHSCM −50 +500 mV High-speed differential input signaling levels See Figure 2-4. Input Levels for Low-/full-speed: V 3.6 V 0.8 V V Output Levels for Low-/full-speed: V Input Levels for High-speed: Output Levels for High-speed: High-speed idle state VHSOI −10.0 +10 mV High-speed data signaling high VHSOH 360 440 mV High-speed data signaling low VHSOL −10.0 +10 mV Chirp J level (different signal) VCHIRPJ 700 1100 mV Chirp K level (different signal) VCHIRPK −900 −500 mV Data Sheet S17462EJ6V0DS 13 μPD720114 Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range -1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Input Voltage Range (Volts) Figure 2-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD−3.3 VDD−2.8 VDD−2.3 VDD−1.8 VDD−1.3 VDD−0.8 VDD−0.3 VDD 0 IOUT (mA) −20 −40 Min. −60 Max. −80 VOUT (V) Figure 2-3. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver 80 Max. IOUT (mA) 60 Min. 40 20 0 0 0.5 1 1.5 2 VOUT (V) 14 Data Sheet S17462EJ6V0DS 2.5 3 4.6 μPD720114 Figure 2-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 1 Point 4 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 0% 100% Unit Interval Figure 2-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device VBUS D+ DGND 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Data Sheet S17462EJ6V0DS 15 μPD720114 Power Consumption Parameter Power Consumption Symbol PW-0 Condition Typ. Unit 31 86 mA mA Hub controller is operating at full-speed mode. 36 mA Hub controller is operating at high-speed mode. 120 mA Hub controller is operating at full-speed mode. 38 mA Hub controller is operating at high-speed mode. 134 mA Hub controller is operating at full-speed mode. 41 mA Hub controller is operating at high-speed mode. 149 mA 10 μA 220 μA The power consumption under the state without suspend. All the ports do not connect to any function. Note 1 Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-2 The power consumption under the state without suspend. The number of active ports is 2. PW-3 The power consumption under the state without suspend. The number of active ports is 3. PW-4 Note 2 The power consumption under unplug and the hub in idle state. PW_S Note 2 The power consumption under the state without suspend. The number of active ports is 4. PW-UNP Note 2 Note 3 The power consumption under plug (VBUS ON) and the hub in suspend state. Note 4 Notes 1. Ports available but inactive or unplugged do not add to the power consumption. 2. The power consumption depends on the number of ports available and actively operating. 3. If the μPD720114 is locally powered and the upstream facing port is unplugged, μPD720114 goes into suspend state and downstream facing port VBUS goes down. 4. If the upstream VBUS in OFF state, the power consumption is same as PW-UNP. 16 Data Sheet S17462EJ6V0DS μPD720114 AC Characteristics (VDD33 = 3.14 to 3.46 V, TA = 0 to +70 °C) Pin capacitance Parameter Symbol Condition Min. Max. Unit Input capacitance CI VDD = 0 V, TA = 25 °C 6 pF Output capacitance CO fC = 1 MHz 6 pF I/O capacitance CIO Unmeasured pins returned to 0 V 6 pF System Clock Ratings Parameter Symbol Clock frequency fCLK Condition Crystal Min. Typ. Max. Unit −500 30 +500 MHz ppm Clock Duty cycle tDUTY 40 ppm 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc. System Reset Timing Parameter Reset active time (Figure 2-6) Symbol Conditions trst Min. 5 Max. Unit μs Figure 2-6. System Reset Timing trst SYSRSTB Data Sheet S17462EJ6V0DS 17 μPD720114 Over-current Response Timing Parameter Symbol Condition Min. Over-current response time from CSB low tOC Typ. 4 Max. Unit 5 ms to PPB high (Figure 2-7) Figure 2-7. Over-current Response Timing CSB(4:1) tOC PPB(4:1) Figure 2-8. CSB/PPB Timing 4 ms Hub power supply 4 ms 4 ms 4 ms Bus reset Up port D+ line PPB pin output CSB pin input Output cut-off Device connection inrush current Port power supply ON Overcurrent generation CSB pin operation region Bus power: Up port connection Self power: Power supply ON Remark CSB detection delay time The active period of the CSB pin is in effect only when the PPB pin is ON. There is a delay time of approximately 4 ms duration at the CSB pin. 18 Data Sheet S17462EJ6V0DS CSB active period μPD720114 USB Interface Block (1/4) Parameter Symbol Conditions Min. Max. Unit Low-speed Electrical Characteristics Rise time (10% to 90%) tLR CL = 200 pF to 600 pF 75 300 ns Fall time (90% to 10%) tLF CL = 200 pF to 600 pF 75 300 ns 80 125 % 1.49925 1.50075 Mbps tDDJ1 tDDJ2 −25 −14 +25 +14 ns ns tUJR1 tUJR2 −152 −200 +152 +200 ns ns Source SE0 interval of EOP (Figure 2-14) tLEOPT 1.25 1.5 μs Receiver SE0 interval of EOP (Figure 2-14) tLEOPR 670 Note Differential rise and fall time matching tLRFM (tLR/tLF) Low-speed data rate tLDRATHS Average bit rate Downstream facing port source jitter total (including frequency tolerance) (Figure 2-13): To next transition For paired transitions Downstream facing port differential receiver jitter total (including frequency tolerance) (Figure 2-15): To next transition For paired transitions ns Width of SE0 interval during differential transition tLST 210 ns Hub differential data delay (Figure 2-11) tLHDD 300 ns Hub differential driver jitter (including cable) (Figure 2-11): Downstream facing port tLDHJ1 tLDHJ2 −45 −15 +45 +15 ns ns tLUHJ1 tLUHJ2 −45 −45 +45 +45 ns ns tLSOP −60 +60 ns Hub EOP delay relative to tHDD (Figure 2-12) tLEOPD 0 200 ns Hub EOP output width skew (Figure 2-12) tLHESK −300 +300 ns 4 20 ns 4 20 ns 90 111.11 % 11.9940 12.0060 Mbps 0.9995 1.0005 ms To next transition For paired transitions Upstream facing port To next transition For paired transitions Data bit width distortion after SOP (Figure 2-11) Full-speed Electrical Characteristics Rise time (10% to 90%) tFR CL = 50 pF, RS = 36 Ω Fall time (90% to 10%) tFF CL = 50 pF, RS = 36 Ω Differential rise and fall time matching tFRFM (tFR/tFF) Full-speed data rate tFDRATHS Average bit rate Frame interval tFRAME Note Excluding the first transition from the Idle state. Data Sheet S17462EJ6V0DS 19 μPD720114 (2/4) Parameter Symbol Conditions Min. Max. Unit 42 ns −3.5 −4.0 +3.5 +4.0 ns ns −2 +5 ns −18.5 −9 +18.5 +9 ns ns 175 ns Full-speed Electrical Characteristics (Continued) Consecutive frame interval jitter tRFI No clock adjustment Note Source jitter total (including frequency tolerance) (Figure 2-13): To next transition For paired transitions Source jitter for differential transition to SE0 transition (Figure 2-14) tDJ1 tDJ2 tFDEOP Receiver jitter (Figure 2-15): To Next Transition For Paired Transitions tJR1 tJR2 Source SE0 interval of EOP (Figure 2-14) tFEOPT 160 Receiver SE0 interval of EOP (Figure 2-14) tFEOPR 82 Width of SE0 interval during differential transition tFST 14 ns tHDD1 tHDD2 70 44 ns ns ns Hub differential data delay (Figure 2-11) (with cable) (without cable) Hub differential driver jitter (including cable) (Figure 2-11): tHDJ1 tHDJ2 −3 −1 +3 +1 ns ns Data bit width distortion after SOP (Figure 2-11) tFSOP −5 +5 ns Hub EOP delay relative to tHDD (Figure 2-12) tFEOPD 0 15 ns Hub EOP output width skew (Figure 2-12) tFHESK −15 +15 ns Rise time (10% to 90%) tHSR 500 ps Fall time (90% to 10%) tHSF 500 ps Driver waveform See Figure 2-9. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 μs Consecutive microframe interval difference tHSRFI 4 highspeed Bit times Data source jitter See Figure 2-9. Receiver jitter tolerance See Figure 2-4. Hub data delay (without cable) tHSHDD 36 highspeed+4 ns Bit times Hub data jitter See Figure 2-4, Figure 2-9. Hub delay variation range tHSHDV 5 highspeed Bit times To next transition For paired transitions High-speed Electrical Characteristics Note Excluding the first transition from the Idle state. 20 Data Sheet S17462EJ6V0DS μPD720114 (3/4) Parameter Symbol Conditions Min. Max. Unit 2.5 2.5 2000 12000 μs μs 2.5 μs Hub Event Timings Time to detect a downstream facing port tDCNN connect event (Figure 2-17): Awake hub Suspended hub Time to detect a disconnect event at a hub’s downstream facing port (Figure 2-16) tDDIS 2.0 Duration of driving resume to a downstream port (only from a controlling hub) tDRSMDN 20 Time from detecting downstream resume to rebroadcast tURSM Duration of driving reset to a downstream facing port (Figure 2-18) tDRST Time to detect a long K from upstream ms 1.0 ms 10 20 ms tURLK 2.5 100 μs Time to detect a long SE0 from upstream tURLSE0 2.5 10000 μs Duration of repeating SE0 upstream (for low-/full-speed repeater) tURPSE0 23 FS Bit times Inter-packet delay (for high-speed) of packets traveling in same direction tHSIPDSD 88 Bit times Inter-packet delay (for high-speed) of packets traveling in opposite direction tHSIPDOD 8 Bit times Inter-packet delay for device/root hub tHSRSPIPD1 Only for a SetPortFeature (PORT_RESET) request 192 response with detachable cable for highspeed Time of which a Chirp J or Chirp K must be tFILT Bit times μs 2.5 continuously detected (filtered) by hub or device during Reset handshake Time after end of device Chirp K by which tWTDCH 100 μs hub must start driving first Chirp K in the hub’s chirp sequence tDCHBIT 40 60 μs Time before end of reset by which a hub must end its downstream chirp sequence tDCHSE0 100 500 μs Time from internal power good to device pulling D+ beyond VIHZ (Figure 2-18) tSIGATT 100 ms Debounce interval provided by USB system software after attach (Figure 2-18) tATTDB 100 ms Maximum duration of suspend averaging interval tSUSAVGI 1 s Period of idle bus before device can initiate resume tWTRSM 5 Duration of driving resume upstream tDRSMUP 1 Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset Data Sheet S17462EJ6V0DS ms 15 ms 21 μPD720114 (4/4) Parameter Symbol Conditions Min. Max. Unit Hub Event Timings (Continued) Resume recovery time tRSMRCY Remote-wakeup is enabled 10 Time to detect a reset from upstream for non high-speed capable devices tDETRST Reset recovery time (Figure 2-18) tRSTRCY Inter-packet delay for full-speed tIPD Inter-packet delay for device response with detachable cable for full-speed tRSPIPD1 6.5 Bit times SetAddress() completion time tDSETADDR 50 ms Time to complete standard request with no data tDRQCMPLTND 50 ms Time to deliver first and subsequent (except last) data for standard request tDRETDATA1 500 ms Time to deliver last data for standard request tDRETDATAN 50 ms Time for which a suspended hub will see a tFILTSE0 2.5 tWTRSTFS 2.5 3000 ms tWTREV 3.0 3.125 ms tWTRSTHS 100 875 ms Minimum duration of a Chirp K on upstream from a hub within the reset protocol tUCH 1.0 Time after start of SE0 on upstream by tUCHEND 7.0 ms Time between detection of downstream chip and entering high-speed state tWTHS 500 μs Time after end of upstream Chirp at which tWTFS 2.5 ms 2.5 ms 10000 μs 10 ms 2 Bit times μs continuous SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in non-suspended fullspeed will wait after start of SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in high-speed will wait after start of SE0 on upstream before reverting to full-speed Time a hub will wait after reverting to fullspeed before sampling the bus state on upstream and beginning the high-speed will wait after start of SE0 on upstream before reverting to full-speed ms which a hub will complete its Chirp K within the reset protocol hub reverts to full-speed default state if no downstream Chirp is detected 22 Data Sheet S17462EJ6V0DS 1.0 μPD720114 Figure 2-9. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 2-10. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device VBUS D+ DGND 15.8 Ω 143 Ω 50 Ω Coax 50 Ω Coax + To 50 Ω Inputs of a High Speed Differential Oscilloscope, or 50 Ω Outputs of a High Speed Differential Data Generator − 143 Ω Data Sheet S17462EJ6V0DS 23 μPD720114 Timing Diagram Figure 2-11. Hub Differential Delay, Differential Jitter, and SOP Distortion Upstream End of Cable Crossover Point Upstream Port of Hub 50% Point of Initial Swing VSS VSS Downstream Port of Hub Hub Delay Downstream tHDD1 VSS 50% Point of Initial Swing Hub Delay Downstream tHDD2 Downstream Port of Hub VSS A. Downstream Hub Delay with Cable B. Downstream Hub Delay without Cable Downstream Port of Hub Crossover Point VSS Upstream Port or End of Cable Hub Delay Upstream tHDD1 tHDD2 VSS Crossover Point C. Upstream Hub Delay with or without Cable Upstream end of cable Upstream port Downstream port Receptacle Plug Host or Hub Hub Function Downstream signaling Upstream signaling D. Measurement Points Hub Differential Jitter: tHDJ1 = tHDDx(J) − tHDDx(K) or tHDDx(K) − tHDDx(J) Consecutive Transitions tHDJ2 = tHDDx(J) − tHDDx(J) or tHDDx(K) − tHDDx(K) Paired Transitions Bit after SOP Width Distortion (same as data jitter for SOP and next J transition): tFSOP = tHDDx(next J) − tHDDx(SOP) Low-speed timings are determined in the same way for: tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP 24 Data Sheet S17462EJ6V0DS μPD720114 Figure 2-12. Hub EOP Delay and EOP Skew Upstream End of Cable 50% Point of Initial Swing Upstream Port of Hub VSS Crossover Point Extended VSS tEOP- tEOP+ tEOP- tEOP+ Downstream Port of Hub Downstream Port of Hub VSS VSS A. Downstream EOP Delay with Cable B. Downstream EOP Delay without Cable Crossover Point Extended Downstream Port of Hub VSS tEOP- tEOP+ Crossover Point Extended Upstream Port or End of Cable VSS C. Upstream EOP Delay with or without Cable EOP Delay: tFEOPD = tEOPy − tHDDx (tEOPy means that this equation applies to tEOP- and tEOP+) EOP Skew: tFHESK = tEOP+ − tEOPLow-speed timings are determined in the same way for: tLEOPD and tLHESK Data Sheet S17462EJ6V0DS 25 μPD720114 Figure 2-13. USB Differential Data Jitter for Low-/full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + txDJ1 Paired Transitions N × tPERIOD + txDJ2 Figure 2-14. USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff. Data-toSE0 Skew N × tPERIOD + txDEOP Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR Figure 2-15. USB Receiver Jitter Tolerance for Low-/full-speed tPERIOD Differential Data Lines txJR txJR1 Consecutive Transitions N × tPERIOD + txJR1 Paired Transitions N × tPERIOD + txJR2 26 Data Sheet S17462EJ6V0DS txJR2 μPD720114 Figure 2-16. Low-/full-speed Disconnect Detection D+/D− VIHZ (min) VIL D−/D+ VSS tDDIS Device Disconnected Disconnect Detected Figure 2-17. Full-/high-speed Device Connect Detection D+ VIH D− VSS tDCNN Device Connected Connect Detected Figure 2-18. Power-on and Connection Events Timing Hub port power OK Reset recovery time Attatch detected Hub port power-on ≥ 4.01 V t2SUSP VBUS VIH (min) VIH D+ or D− Δt1 tSIGATT tATTDB Data Sheet S17462EJ6V0DS tDRST USB system software reads device speed tRSTRCY 27 μPD720114 3. PACKAGE DRAWINGS • μPD720114GA-9EU-A 48-PIN PLASTIC TQFP (FINE PITCH) (7x7) A B detail of lead end 25 24 36 37 S P C T D R 48 13 12 1 L U Q F G J H I M K S N S M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A B MILLIMETERS 9.0±0.2 7.0±0.2 C 7.0±0.2 D F 9.0±0.2 0.75 G 0.75 H 0.22 +0.05 −0.04 I 0.10 J 0.5 (T.P.) K L 1.0±0.2 0.5 0.17 +0.03 −0.07 M N 0.08 P 1.0±0.1 Q 0.1±0.05 3°+4° −3° R S 1.27 MAX. T 0.25 (T.P.) U 0.6±0.15 P48GA-50-9EU-1 28 Data Sheet S17462EJ6V0DS μPD720114 • μPD720114GA-YEU-A 48-PIN PLASTIC TQFP (FINE PITCH)(7x7) HD D detail of lead end 36 A3 25 37 24 c θ E L Lp HE L1 13 48 1 12 (UNIT:mm) ZE e ZD b x M S A A2 ITEM D DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.20 MAX. A1 0.10±0.05 A2 1.00±0.05 A3 b S c L y A1 S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. Lp 0.60±0.15 L1 θ 1.00±0.20 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 0.75 ZE Data Sheet S17462EJ6V0DS 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 0.75 P48GA-50-YEU 29 μPD720114 <R> • μPD720114K9-4E4-A 40-PIN PLASTIC VQFN(6x6) x4 t S A B B HD D DETAIL OF E HE A PART A2 A A1 A c x4 f S A B y1 S (UNIT:mm) A ITEM S y S EXPOSED DIE PAD D2 1 10 D 5.75 E 5.75 HD 6.00 HE 6.00 A 0.85 ± 0.05 A1 0.00 to 0.05 A2 c 0.65 ± 0.05 + 0.23 0.07 0.05 0.20 e 0.50 b 11 40 E2 31 20 21 30 Lp e b 30 x1 M S A B x2 M S DIMENSIONS f 0.10 Lp 0.40 ± 0.10 t 0.10 x1 0.10 x2 0.05 y 0.05 y1 0.10 D2 4.30 ± 0.10 E2 4.30 ± 0.10 P40K9-50-4E4 NEC Electronics Corporation 2009 Data Sheet S17462EJ6V0DS μPD720114 4. RECOMMENDED SOLDERING CONDITIONS The μPD720114 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) • μPD720114GA-9EU-A: 48-pin plastic TQFP (Fine pitch) (7 × 7) <R> • μPD720114GA-YEU-A: 48-pin plastic TQFP (Fine pitch) (7 × 7) • μPD720114K9-4E4-A: 40-pin plastic QFN (6 × 6) Soldering Method Infrared reflow Soldering Conditions Peak package’s surface temperature: 260 °C, Reflow time: 60 seconds or less (220 °C or higher), Maximum allowable number of reflow processes: 3, Exposure limit Note Symbol IR60-107-3 : 7 days (10 to 72 hours pre-backing is required at 125C° afterwards), Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. <Caution> Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before unpacking. Partial heating method Pin temperature: 300°C or below, – Heat time: 3 seconds or less (per each side of the device) , Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Note The Maximum number of days during which the product can be stored at a temperature of 5 to 25°C and a relative humidity of 20 to 65% after dry-pack package is opened. Data Sheet S17462EJ6V0DS 31 μPD720114 [MEMO] 32 Data Sheet S17462EJ6V0DS μPD720114 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S17462EJ6V0DS 33 μPD720114 ECOUSB is a trademark of NEC Electronics Corporation. • The information in this document is current as of December, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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