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DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2756GR SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µ PA2756GR is Dual N-channel MOS Field Effect Transistor designed for switching applications. 8 5 1 : Source 1 2 : Gate 1 7, 8: Drain 1 FEATURES • Low on-state resistance RDS(on)1 = 105 mΩ MAX. (VGS = 10 V, ID = 2.0 A) RDS(on)2 = 150 mΩ MAX. (VGS = 4.0 V, ID = 2.0 A) • Low Ciss: Ciss = 260 pF TYP. • Built-in G-S protection diode against ESD • Small and surface mount package (Power SOP8) 3 : Source 2 4 : Gate 2 5, 6: Drain 2 PART NUMBER PACKAGE µ PA2756GR Power SOP8 6.0 ±0.3 4 4.4 0.8 +0.10 –0.05 5.37 MAX. 0.15 0.05 MIN. ORDERING INFORMATION 1.44 1.8 MAX. 1 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 60 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V ID(DC) ±4.0 A ID(pulse) ±16 A PT1 1.6 W PT2 2.0 W Channel Temperature Tch 150 °C Storage Temperature Drain Current (DC) Note1 Drain Current (pulse) Note2 Total Power Dissipation (1 unit) Note1 Total Power Dissipation (2 units) Note1 Tstg −55 to +150 °C Single Avalanche Current Note3 IAS 4.0 A Single Avalanche Energy Note3 EAS 1.6 mJ EAR 1.6 mJ Repetitive Avalanche Energy Notes 1. 2. 3. 4. Note4 EQUIVALENT CIRCUIT Drain 1 Body Diode Gate 2 Gate 1 Gate Protection Diode Drain 2 Source 1 Gate Protection Diode Body Diode Source 2 Mounted on ceramic substrate of 2000 mm2 x 2.2 mm PW ≤ 10 µs, Duty Cycle ≤ 1% Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 → 0 V IAR ≤ 4.0 A, Tch ≤ 150°C Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G17407EJ1V0DS00 (1st edition) Date Published January 2005 NS CP(K) Printed in Japan 2005 µ PA2756GR ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±18 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 1.5 2.5 V | yfs | VDS = 10 V, ID = 2.0 A 2.0 RDS(on)1 VGS = 10 V, ID = 2.0 A 85 105 mΩ RDS(on)2 VGS = 4.0 V, ID = 2.0 A 106 150 mΩ Gate Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note 2.0 S Input Capacitance Ciss VDS = 10 V 260 pF Output Capacitance Coss VGS = 0 V 65 pF Reverse Transfer Capacitance Crss f = 1 MHz 20 pF Turn-on Delay Time td(on) VDD = 30 V, ID = 2.0 A 14 ns tr VGS = 10 V 5 ns td(off) RG = 10 Ω 80 ns 30 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 48 V 6 nC Gate to Source Charge QGS VGS = 10 V 1 nC QGD ID = 4.0 A 1.5 nC VF(S-D) IF = 4.0 A, VGS = 0 V 0.9 V Reverse Recovery Time trr IF = 4.0 A, VGS = 0 V 24 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 22 nC Gate to Drain Charge Body Diode Forward Voltage Note Note Pulsed TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE PG. 2 50 Ω 10% 0 10% Wave Form VDD D.U.T. IG = 2 mA 90% VDS VGS 0 BVDSS RL VDD Data Sheet G17407EJ1V0DS td(on) tr ton td(off) tf toff µ PA2756GR TYPICAL CHARACTERISTICS (TA = 25°C) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 120 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on ceramic substrate of 2000 mm2 x 2.2 mm 2.4 2 units 2 1 unit 1.6 1.2 0.8 0.4 0 0 0 20 40 60 80 0 100 120 140 160 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 PW = 100 µs 10 ID(DC) 1 ms 1 RDS(on) Limited (at VGS = 10 V) 0.1 Power Dissipation Limited Single pulse, 1unit TA = 25°C Mounted on ceramic substrate 10 ms 100 ms 2 of 2000 mm x 2.2 mm 0.01 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A ID(pulse) Rth(ch-A) = 78.1°C/W 100 10 1 0.1 100 µ Single pulse, 1unit TA = 25°C Mounted on ceramic substrate of 2000 mm2 x 2.2 mm 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G17407EJ1V0DS 3 µ PA2756GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 20 VDS = 10 V Pulsed Pulsed ID - Drain Current - A ID - Drain Current - A 10 15 VGS = 10 V 10 4.0 V 5 TA = −40°C 25°C 75°C 125°C 150°C 1 0.1 0.01 0.001 0.0001 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 0.5 -50 -25 0 25 50 | yfs | - Forward Transfer Admittance - S 1.5 0 75 100 125 150 175 10 VDS = 10 V Pulsed TA = −40°C 25°C 75°C 125°C 150°C 1 0.1 0.01 0.01 0.1 200 Pulsed 180 160 140 VGS = 4.0 V 100 10 V 60 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 1 1 10 100 ID - Drain Current - A Tch - Channel Temperature - °C DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 200 Pulsed 180 160 ID = 4.0 A 2.0 A 0.8 A 140 120 100 80 60 0 1 2 3 4 5 6 7 8 9 10 11 12 VGS - Gate to Source Voltage - V ID - Drain Current – A 4 5 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 2 0.1 4 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 2.5 80 3 VGS - Gate to Source Voltage - V VDS = 10 V ID = 1 mA 120 2 VDS - Drain to Source Voltage - V 3 VGS(off) - Gate Cut-off Voltage - V 1 Data Sheet G17407EJ1V0DS DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 200 1000 ID = 2.0 A Pulsed 180 160 140 Ciss, Coss, Crss - Capacitance - pF VGS = 4.0 V 120 100 10 V 80 60 40 Ciss 100 Coss 10 Crss VGS = 0 V f = 1 MHz 20 1 0 -50 -25 0 25 50 0.1 75 100 125 150 175 1 SWITCHING CHARACTERISTICS DYNAMIC INPUT/OUTPUT CHARACTERISTICS 1000 60 VDD = 30 V VGS = 10 V RG = 10 Ω VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 100 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C 100 td(off) tf td(on) 10 tr 12 ID = 4.0 A VDD = 48 V 30 V 12 V 50 40 10 8 30 6 VGS 20 10 4 2 VDS 0 1 0.1 1 10 0 0 100 SOURCE TO DRAIN DIODE FORWARD VOLTAGE 100 2 3 4 5 6 7 REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 trr - Reverse Recovery Time - ns Pulsed 10 1 QG - Gate Charge - nC ID - Drain Current - A IF - Diode Forward Current - A 10 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ µ PA2756GR VGS = 10 V 4.0 V 0V 1 0.1 VGS = 0 V di/dt = 100 A/µs 100 10 1 0.01 0 0.5 1 1.5 0.1 1 10 100 IF - Diode Forward Current - A VF(S-D) - Source to Drain Voltage - V Data Sheet G17407EJ1V0DS 5 µ PA2756GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 120 Energy Derating Factor - % IAS - Single Avalanche Current - A 100 10 IAS = 4.0 A EAS = 1.6 mJ 1 VDD = 30 V RG = 25 Ω VGS = 20→0 V Starting Tch = 25°C 80 60 40 20 0.1 0 10 µ 100 µ 1m 10 m 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C L - Inductive Load - H 6 VDD = 30 V RG = 25 Ω VGS = 20→0 V IAS ≤ 4.0 A 100 Data Sheet G17407EJ1V0DS µ PA2756GR • The information in this document is current as of January, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1