ETC UPD78F9116A

DATA SHEET
MOS INTEGRATED CIRCUITS
µPD78F9116A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD78F9116A is a µPD789114A Subseries product of the 78K/0S Series.
The µPD78F9116A replaces the internal masked ROM of the µPD789111A,789112A and 789114A with flash
memory, which enables the writing/erasing of a program while the device is mounted on the board.
Because the device can be programmed by the user, it is ideally suited to the evaluation stages of system
development, the manufacture of small batches of multiple products, and the rapid development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual: To be prepared
78K/0S Series User's Manual Instruction: U11047E
FEATURES
• Pin-compatible with masked ROM version (excluding VPP pin)
• Flash memory: 16K bytes
• Internal High-Speed RAM: 256 bytes
• On-chip multiplier: 8 bits × 8 bits = 16 bits
• Minimum instruction execution time can be changed from high-speed (0.4 µs) to low-speed (1.6 µs) (@ 5.0-MHz
operation with system clock)
• I/O ports: 20
• Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes
• 10-bit resolution A/D converter: 4 channels
• Timers: 3 channels
• 16-bit timer: 1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
• Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Cleaners, washing machines, refrigerators and battery-charger
ORDERING INFORMATION
Part number
µ PD78F9116AMC-5A4
Package
30-pin plastic SSOP (7.62mm (300))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14667EJ1V1DS00 (1st edition)
Date Published March 2000 NS CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µPD78F9116A
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under mass production
Products under development
Y subseries supports SMB.
Small, general-purpose
44 pins
42/44 pins
28 pins
µ PD789026 with subsystem clock added
µ PD789014 with timer reinforced and ROM and RAM expanded
µ PD789046
µ PD789026
µ PD789014
UART. Low-voltage (1.8-V) operation
Small, general-purpose + A/D
µ PD789177
µ PD789167
µ PD789156
µ PD789146
µ PD789134A
µ PD789124A
µ PD789114A
µ PD789104A
44 pins
44 pins
30 pins
30 pins
30 pins
30 pins
30 pins
30 pins
µ PD789177Y
µ PD789167Y
µ PD789167 with improved A/D
µ PD789104A with improved timer
µ PD789146 with improved A/D
µ PD789104A with EEPROM added
µ PD789124A with improved A/D
RC oscillation model of µ PD789104A
µ PD789104A with improved A/D
µ PD789026 with A/D and multiplier added
For inverter control
µ PD789842
44 pins
78K/0S
series
Internal inverter control circuit and UART
For driving LCD
80 pins
80 pins
64 pins
64 pins
64 pins
64 pins
64 pins
64 pins
µ PD789417A
µ PD789407A
µ PD789456
µ PD789446
µ PD789436
µ PD789426
µ PD789316
µ PD789306
µ PD789407A with improved A/D
µ PD789456 with improved I/O
µ PD789446 with improved A/D
µ PD789426 with improved display output
µ PD789426 with improved A/D
µ PD789306 with A/D added
RC oscillation model of µ PD789306
Basic subseries for driving LCD
For driving Dot LCD
144 pins
88 pins
µ PD789835
µ PD789830
Segment/common output: 96 pins
Segment: 40 pins, common: 16 pins
For ASSP
52 pins
52 pins
44 pins
44 pins
20 pins
20 pins
2
µ PD789467
µ PD789327
µ PD789800
µ PD789840
µ PD789861
µ PD789860
µ PD789327 with A/D added
For remote controller. Internal LCD controller/driver
For PC keyboard. Internal USB function
For key pad. Internal POC
RC oscillation model of µPD789860
For keyless entry. Internal POC and key return circuit
Data Sheet U14667EJ1V1DS00
µPD78F9116A
The major differences between subseries are shown below.
Function
ROM
Capacity
Subseries Name
Small,
µPD789046 16 K
generalµPD789026 4 K-16 K
purpose
µPD789014 2 K-4 K
Small,
µPD789177 16 K-24 K
generalµPD789167
purpose
µPD789156 8 K-16 K
+ A/D
Timer
8-bit
1 ch
16-bit
1 ch
Watch WDT
1 ch
1 ch
8-bit
A/D
10-bit
A/D
Serial Interface
I/O
VDD
MIN
Value
Remark
−
−
1 ch (UART:1 ch)
34 pins
1.8 V
−
1.8 V
−
−
2 ch
−
3 ch
1 ch
22 pins
1 ch
1 ch
−
1 ch
µPD789146
−
8 ch
8 ch
−
−
4 ch
4 ch
−
µPD789134A 2 K-8 K
20 pins
Internal
EEPROM
4 ch
RC oscillation
version
µPD789124A
4 ch
−
µPD789114A
−
4 ch
µPD789104A
4 ch
−
8 ch
−
1 ch (UART: 1 ch) 30 pins
4.0 V
−
7 ch
1 ch (UART: 1 ch) 43 pins
1.8 V
−
µPD789842 8 K-16 K
3 ch
Note
1 ch
1 ch
For LCD µPD789417A 12 K-24 K
driving
µPD789407A
3 ch
1 ch
1 ch
1 ch
µPD789456 12 K-16 K
2 ch
For
inverter
control
1 ch (UART: 1 ch) 31 pins
7 ch
−
−
6 ch
µPD789446
6 ch
−
µPD789436
−
6 ch
µPD789426
6 ch
−
µPD789316 8 K to
16K
−
−
30 pins
40 pins
2 ch (UART: 1 ch) 23 pins
RC oscillation
version
µPD789306
−
For Dot
LCD
driving
µPD789835 24 K-60 K
6 ch
−
µPD789830 24 K
1 ch
1 ch
ASSP
µPD789467 4 K-24 K
2 ch
−
1 ch
1 ch
2 ch
1 ch
µPD789840
µPD789861 4 K
−
−
1 ch
1 ch
µPD789327
µPD789800 8 K
2 ch
−
1 ch
1 ch
27 pins
1.8 V
1 ch (UART: 1 ch) 30 pins
2.7 V
−
−
18 pins
1.8 V
−
1 ch
21 pins
−
2 ch (USB: 1 ch)
31 pins
4.0 V
1 ch
29 pins
2.8 V
14 pins
1.8 V
4 ch
−
1 ch
−
µPD789860
−
−
Internal
LCD
−
RC oscillation
version,
Internal
EEPROM
Internal
EEPROM
Note 10-bit timer: 1 channel
Data Sheet U14667EJ1V1DS00
3
µPD78F9116A
OVERVIEW OF FUNCTIONS
Item
Internal memory
Flash memory
16 Kbytes
High-speed RAM
256 bytes
Minimum instruction execution time
0.4/1.6 µs (@ 5.0-MHz operation with system clock)
General-purpose registers
8 bits × 8 registers
Instruction set
• 16-bit operations
• Bit manipulations (set, reset, and test)
Multiplier
8 bits × 8 bits = 16 bits
I/O ports
Total:
20
• CMOS input:
• CMOS I/O:
• N-ch open-drain (12-V withstand voltage):
4
12
4
A/D converters
10-bit resolution × 4 channels
Serial interface
Switchable between 3-wire serial I/O and UART modes
Timer
• 16-bit timer: 1 channel
• 8-bit timer/event counter: 1 channel
• Watchdog timer: 1 channel
Timer output
1 output (16-bit/8-bit timer alternate function)
Vectored interrupt
sources
4
function
Maskable
Internal: 6, External: 3
Non-maskable
Internal: 1
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
30-pin plastic SSOP (7.62 mm (300))
Data Sheet U14667EJ1V1DS00
µPD78F9116A
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW)..............................................................................................
6
2.
BLOCK DIAGRAM ...........................................................................................................................
7
3.
DIFFERENCES BETWEEN µPD78F9116A AND MASKED ROM VERSION ..................................
8
4.
PIN FUNCTIONS ..............................................................................................................................
9
5.
6.
7.
4.1
Port Pins..................................................................................................................................................
9
4.2
Non-Port Pins..........................................................................................................................................
10
4.3
Pin I/O Circuits and Recommended Connection of Unused Pins......................................................
11
MEMORY SPACE.............................................................................................................................
13
FLASH MEMORY PROGRAMMING .................................................................................................
14
6.1
Selecting Communication Mode ...........................................................................................................
14
6.2
Function of Flash Memory Programming ............................................................................................
15
6.3
Flashpro III Connection..........................................................................................................................
15
6.4
Example of Settings for Flashpro III (PG-FP3) .....................................................................................
17
INSTRUCTION SET OVERVIEW ....................................................................................................
18
7.1
Conventions............................................................................................................................................
18
7.2
Operations ..............................................................................................................................................
20
8.
ELECTRICAL SPECIFICATIONS ....................................................................................................
25
9.
PACKAGE DRAWING......................................................................................................................
37
10. RECOMMENDED SOLDERING CONDITIONS ..............................................................................
38
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................
39
APPENDIX B RELATED DOCUMENTS..............................................................................................
41
Data Sheet U14667EJ1V1DS00
5
µPD78F9116A
1. PIN CONFIGURATION (TOP VIEW)
• 30-pin plastic SSOP (7.62 mm (300))
µPD78F9116AMC-5A4
P23/INTP0/CPT20/SS20
1
30
P22/SI20/RXD20
P24/INTP1/TO80/TO20
2
29
P21/SO20/TXD20
P25/INTP2/TI80
3
28
P20/SCK20/ASCK20
AVDD
4
27
P11
P60/ANI0
5
26
P10
P61/ANI1
6
25
VDD
P62/ANI2
7
24
VSS
P63/ANI3
8
23
X1
AVSS
9
22
X2
IC0
10
21
IC0
P50
11
20
VPP
P51
12
19
RESET
P52
13
18
P03
P53
14
17
P02
P00
15
16
P01
Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS.
2. Connect the VPP pin directry to VSS in normal operation mode.
3. Connect the AVDD pin to VDD.
4. Connect the AVSS pin to VSS.
6
ANI0 to ANI3:
Analog Input
RESET:
Reset
ASCK20:
Asynchronous Serial Input
RXD20:
Receive Data
AVDD:
Analog Power Supply
SCK20:
Serial Clock Input/Output
AVSS:
Analog Ground
SI20:
Serial Data Input
CPT20:
Capture Trigger Input
SO20:
Serial Data Output
IC0:
Internally Connected
SS20:
Chip Select Input
INTP0 to INTP2:
Interrupt from Peripherals
TI80:
Timer Input
P00 to P03:
Port0
TO20, TO80:
Timer Output
P10, P11:
Port1
TXD20:
Transmit Data
P20 to P25:
Port2
VDD:
Power Supply
P50 to P53:
Port5
VPP:
Programing Power Supply
P60 to P63:
Port6
VSS:
Ground
X1, X2:
Crystal 1, 2
Data Sheet U14667EJ1V1DS00
µPD78F9116A
2. BLOCK DIAGRAM
TI80/INTP2/P25
TO80/TO20
/INTP1/P24
TO20/TO80
/INTP1/P24
8-BIT TIMER/
EVENT COUNTER 80
16-BIT TIMER 20
PORT 0
P00 to P03
PORT 1
P10, P11
PORT 2
P20 to P25
PORT 5
P50 to P53
PORT 6
P60 to P63
CPT20/INTP0
/SS20/P23
WATCHDOG TIMER
78K/0S
CPU CORE
FLASH
MEMORY
SCK20/ASCK20
/P20
SO20/TxD20/P21
SI20/RxD20/P22
SERIAL
INTERFACE 20
SS20/INTP0
/CPT20/P23
RAM
ANI0/P60 to
ANI3/P63
AVDD
AVSS
A/D CONVERTER
SYSTEM
CONTROL
INTERRUPT
CONTROL
VDD VSS VPP IC0
Remark
RESET
X1
X2
INTP0/CPT20
/P23/SS20
INTP1/TO80
/TO20/P24
INTP2/TI80/P25
The internal ROM capacity varies depending on the product.
Data Sheet U14667EJ1V1DS00
7
µPD78F9116A
3. DIFFERENCES BETWEEN µPD78F9116A AND MASKED ROM VERSION
The µPD78F9116A is a product that substitutes flash memory for the internal ROM of the masked ROM version.
The differences between the µPD78F9116A and the masked ROM versions are shown in Table 3-1.
Table 3-1. Types of Pin Input/Output Circuits
Flash memory version
Item
Internal
memory
µ PD78F9116A
ROM
16Kbytes (Flash memory)
High-speed RAM
256 bytes
Masked ROM version
µ PD789111A
2 Kbytes
µ PD789112A
4 Kbytes
µ PD789114A
8 Kbytes
Pull-up resistor
12 ( software control only )
16 ( software control : 12, mask option specification : 4 )
VPP pin
Provided
Not provided
Electric characteristics
See the relevant data sheet
Caution
There are differences in the amount of noise tolerance and noise radiation between flash
memory versions and masked ROM versions.
When considering changing from a flash
memory version to a masked ROM version during process from experimental
manufacturing to mass production, make sure to sufficiently evaluate the masked ROM
versions using commercial samples (CS) (not engineering samples (ES)).
8
Data Sheet U14667EJ1V1DS00
µPD78F9116A
4. PIN FUNCTIONS
4.1
Port Pins
Pin Name
I/O
P00 to
P03
I/O
Function
Port 0
After Reset
Alternate Function
Input
–
Input
–
4-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P10, P11
I/O
Port 1
2-bit input/output port
Input/output can be specified in 1-bit units
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P20
I/O
Input
Port 2
6-bit input/output port
P21
SO20/TxD20
Input/output can be specified in 1-bit units
P22
SI20/RxD20
When used as an input port, an on-chip pull-up resistor can be
P23
SCK20/ASCK20
INTP0/CPT20
/SS20
specified by means of software.
P24
INTP1/TO80/TO20
P25
INTP2/TI80
P50 to
P53
I/O
Input
Port 5
–
4-bit N-ch open-drain input/output port
Input/output can be specified in 1-bit units
An on-chip pull-up resistor can be specified by the mask option.
P60 to
P63
Input
Port 6
4-bit input-only port
Input
Data Sheet U14667EJ1V1DS00
ANI0 to ANI3
9
µPD78F9116A
4.2
Non-Port Pins
Pin Name
INTP0
I/O
Input
INTP1
INTP2
Function
After Reset
Alternate Function
External interrupt request input for which the valid edge
(rising edge, falling edge, or both rising and falling edges) can
be specified
Input
P23/CPT20/SS20
P24/TO80/TO20
P25/TI80
SI20
Input
Serial interface serial data input
Input
P22/RxD20
SO20
Output
Serial interface serial data output
Input
P21/TxD20
SCK20
I/O
Serial interface serial clock input/output
Input
P20/ASCK20
ASCK20
Input
Serial clock input for asynchronous serial interface
Input
P20/SCK20
SS20
Input
Chip select input for serial interface
Input
P23/CPT20/INTP0
RxD20
Input
Serial data input for asynchronous serial interface
Input
P22/SI20
TxD20
Output
Serial data output for asynchronous serial interface
Input
P21/SO20
TI80
Input
External count clock input to 8-bit timer/event counter 80
Input
P25/INTP2
TO80
Output
8-bit timer/event counter 80 output
Input
P24/INTP1/TO20
TO20
Output
16-bit timer 20 output
Input
P24/INTP1/TO80
CPT20
Input
Capture edge input
Input
P23/INTP0/SS20
ANI0 to ANI3
Input
A/D converter analog input
Input
P60 to P63
AVDD
AVSS
X1
X2
RESET
Input
A/D converter analog power supply
–
A/D converter ground potential
–
–
Connecting crystal resonator for main system clock oscillation
–
–
–
–
-
Input
–
VDD
-
Positive power supply
–
–
VSS
-
Ground potential
–
–
VPP
-
Sets flash memory programming mode. Applies high voltage
when a program is written or verified. Connect directly to VSS
in normal operation mode.
–
–
IC0
-
Internally connected. Connect directly to VSS.
–
–
10
Input
–
System reset input
Data Sheet U14667EJ1V1DS00
µPD78F9116A
4.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.
For the input/output circuit configuration of each type, refer to Figure 4-1.
Table 4-1. Types of Pin Input/Output Circuits
Pin Name
P00 to P03
Input/Output
Circuit Type
I/O
5-A
I/O
P10, P11
P20/SCK20/ASCK20
Recommended Connection of Unused Pins
Input:
Independently connect to VDD or VSS via a resistor.
Output: Leave open
8-A
P21/SO20/TXD20
P22/SI20/RXD20
P23/INTP0/CPT20/SS20
Input:
Independently connect to VSS via a resistor.
Output: Leave open
P24/INTP1/TO80/TO20
P25/INTP2/TI80
P50 to P53
13-V
P60/ANI0 to P63/ANI3
9-C
Input
–
–
AVDD
Input:
Independently connect to VDD via a resistor.
Output: Leave open
Connect directly to VDD or VSS.
Connect to VDD.
Connect to VSS.
AVSS
RESET
2
Input
VPP
–
–
–
Connect directly to VSS.
IC0
Data Sheet U14667EJ1V1DS00
11
µPD78F9116A
Figure 4-1. Pin Input/Output Circuits
Type 2
Type 9-C
IN
Comparator
P-ch
N-ch
IN
+
–
AVSS
VREF
(Threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Type 5-A
Type 13-V
VDD
Pull-up
enable
Input
enable
P-ch
IN/OUT
VDD
Data
Output data
Output disable
P-ch
IN/OUT
Output
disable
N-ch
N-ch
VSS
Input enable
VSS
Middle-voltage input buffer
Input
enable
Type 8-A
VDD
Pull-up
enable
P-ch
VDD
Data
P-ch
IN/OUT
Output
disable
12
N-ch
VSS
Data Sheet U14667EJ1V1DS00
µPD78F9116A
5. MEMORY SPACE
Figure 5-1 shows the memory map of the µPD78F9116A.
Figure 5-1. Memory Map
FFFFH
Special function registers
256 × 8 bits
FF00H
FEFFH
Internal high-speed RAM
256 × 8 bits
FE00H
FDFFH
Reserved
Data memory space
3FFFH
4000H
3FFFH
Program area
Program memory
space
Flash memory
16384 × 8 bits
0080H
007FH
CALLT table area
0040H
003FH
0016H
0015H
Program area
Vector table area
0000H
0000H
Data Sheet U14667EJ1V1DS00
13
µPD78F9116A
6. FLASH MEMORY PROGRAMMING
The on-chip program memory in the µPD78F9116A is a flash memory.
The flash memory can be written with the µPD78F9116A mounted on the target system (on-board). Connect the
dedicated flash programmer (Flashpro III (model number: FL-PR3, PG-FP3)) to the host machine and target system
to write the flash memory.
Remark
6.1
FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd..
Selecting Communication Mode
The flash memory is written by using Flashpro III and by means of serial communication. Select a communication
mode from those listed in Table 6-1. To select a communication mode, the format shown in Figure 6-1 is used. Each
communication mode is selected by the number of VPP pulses shown in Table 6-1.
Table 6-1. Communication Mode List
Communication mode
Pins used
Number of VPP pulses
3-wired serial I/O mode
SCK20/ASCK20/P20
SO20/TxD20/P21
SI20/RxD20/P22
0
UART
TxD20/SO20/P21
RxD/SI20/P22
8
P00 (Serial clock input)
P01 (Serial data output)
P02 (Serial data input)
12
Note
Pseudo 3-wire mode
Note Serial transfer is performed by controlling a port by software.
Caution
Be sure to select a communication mode depending on the VPP pulse number shown in Table 6-1.
Figure 6-1. Communication Mode Selection Format
10 V
VPP
VDD
1
VSS
VDD
RESET
VSS
14
Data Sheet U14667EJ1V1DS00
2
n
µPD78F9116A
6.2
Function of Flash Memory Programming
By transmitting/receiving commands and data in the selected communication mode, operations such as writing to
the flash memory are performed. Table 6-2 shows the major functions of flash memory programming.
Table 6-2. Functions of Flash Memory Programming
Function
Description
Batch erase
Erases all contents of memory
Batch blank check
Checks erased state of entire memory
Data write
Write to flash memory based on write start address and number of data written (number of bytes)
Batch verify
Compares all contents of memory with input data
6.3
Flashpro III Connection
How the Flashpro III is connected to the µPD78F9116A differs depending on the communication mode (3-wired
serial I/O or pseudo 3-wire mode). Figures 6-2 to 6-4 show the connection in the respective mode.
Figure 6-2. Flashpro III Connection in 3-wired Serial I/O Mode
µPD78F9116A
Flashpro III
VPPnNote
VPP
VDD
VDD, AVDD
RESET
RESET
CLK
X1
SCK
SCK20
SO
SI20
SI
SO20
GND
VSS, AVSS
Note n = 1, 2
Data Sheet U14667EJ1V1DS00
15
µPD78F9116A
Figure 6-3. Flashpro III Connection in UART Mode
µPD78F9116A
Flashpro III
VPPnNote
VPP
VDD
VDD, AVDD
RESET
RESET
CLK
X1
SO
RxD20
SI
TxD20
GND
VSS, AVSS
Note n= 1, 2
Figure 6-4. Flashpro III Connection in Pseudo 3-Wire Mode (When Port 0 is Used)
µPD78F9116A
Flashpro III
VPPnNote
VPP
VDD
VDD, AVDD
RESET
RESET
CLK
X1
SCK
P00 (Serial clock)
SO
P02 (Serial input)
SI
P01 (Serial output)
GND
VSS, AVSS
Note n= 1, 2
16
Data Sheet U14667EJ1V1DS00
µPD78F9116A
6.4
Example of Settings for Flashpro III (PG-FP3)
Set as follows when writing to flash memory using the Flashpro III (PG-FP3).
<1> Download the parameter file.
<2> Select the serial mode and the serial clock using the type command.
<3> The following is a setting example using the PG-FP3.
Table 6-3. Example Using PG-FP3
Communication mode
3-wired serial I/O mode
Number of VPP pulses
Setting example using PG-FP3
COMM PORT
SIO ch-0
CPU CLK
On target board
Note1
0
In Flashpro
UART
On target board
4.1943 MHz
SIO CLK
1.0 MHz
In Flashpro
4.0 MHz
SIO CLK
1.0 MHz
COMM PORT
UART-ch0
CPU CLK
On target board
8
In Flashpro
Pseudo 3-wire mode
On target board
4.1943 MHz
UART BPS
9600 bps
COMM PORT
Port B
CPU CLK
On target board
Note2
12
In Flashpro
Notes
On target board
4.1943 MHz
SIO CLK
1 kHz
In Flashpro
4.0 MHz
SIO CLK
1 kHz
1. The number of VPP pulses supplied from the Flashpro III during serial communication initialization. The
pins to be used in communication are determined by this number of pulses.
2. Select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps.
Remark
COMM PORT: Selection of serial port
SIO CLK
: Selection of serial clock frequency
CPU CLK
: Selection of CPU clock source to be input
Data Sheet U14667EJ1V1DS00
17
µPD78F9116A
7. INSTRUCTION SET OVERVIEW
The instruction set for the µPD78F9116A is listed later.
7.1
Conventions
7.1.1 Operand identifiers and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more
description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords
and must be described as they are. Each symbol has the following meaning.
•
#: Immediate data specification
•
$:
•
!:
•
[ ]: Indirect address specification
Absolute address specification
Relative address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #,!, $, or [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 7-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
saddr
saddrp
FE20H to FF1FH immediate data or label
FE20H to FF1FH immediate data or label (even address only)
addr16
addr5
0000H to FFFFH immediate data or label
(Only even addresses for 16-bit data transfer instructions)
0040H to 007FH immediate data or label (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
18
Data Sheet U14667EJ1V1DS00
µPD78F9116A
7.1.2 Descriptions of the operation field
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
AX register pair; 16-bit accumulator
BC:
BC register pair
DE:
DE register pair
HL:
HL register pair
PC:
Program counter
SP:
Stack pointer
PSW:
Program status word
CY:
Carry flag
AC:
Auxiliary carry flag
Z:
Zero flag
IE:
Interrupt request enable flag
NMIS:
Non-maskable interrupt servicing flag
( ):
Memory contents indicated by address or register contents in parentheses
XH, XL:
Higher 8 bits and lower 8 bits of 16-bit register
∧:
Logical product (AND)
∨:
Logical sum (OR)
∨:
Exclusive OR
:
Inverted data
addr16:
16-bit immediate data or label
jdisp8:
Signed 8-bit data (displacement value)
7.1.3 Description of the flag operation field
(Blank):
Not affected
0:
Cleared to 0
1:
Set to 1
×:
Set/cleared according to the result
R:
Previously saved value is restored
Data Sheet U14667EJ1V1DS00
19
µPD78F9116A
7.2
Operations
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
MOV
r, #byte
3
6
r ← byte
saddr , #byte
3
6
(addr) ← byte
3
6
sfr ← byte
A, r
Note 1
2
4
A←r
r, A
Note 1
2
4
r←A
A, saddr
2
4
A ← (saddr)
saddr, A
2
4
(saddr) ← A
A, sfr
2
4
A ← sfr
sfr, A
2
4
sfr ← A
A, !addr16
3
8
A ← (addr16)
!addr16, A
3
8
(addr16) ← A
PSW, #byte
3
6
PSW ← byte
A, PSW
2
4
A ← PSW
PSW, A
2
4
PSW ← A
A, [DE]
1
6
A ← (DE)
[DE], A
1
6
(DE) ← A
A, [HL]
1
6
A ← (HL)
[HL], A
1
6
(HL) ← A
A, [HL + byte]
2
6
A ← (HL + byte)
[HL + byte], A
2
6
(HL + byte) ← A
1
4
A ↔X
2
6
A ↔r
A, saddr
2
6
A ↔ (saddr)
A, sfr
2
6
A ↔ (sfr)
A, [DE]
1
8
A ↔ (DE)
A, [HL]
1
8
A ↔ (HL)
A, [HL + byte]
2
8
A ↔ (HL + byte)
rp, #word
3
6
rp ← word
AX, saddrp
2
6
AX ← (saddrp)
sfr, #byte
XCH
A, X
A, r
MOVW
Note 2
2
8
(saddrp) ← AX
AX, rp
Note 3
1
4
AX ← rp
rp, AX
Note 3
1
4
rp ← AX
AX, rp
Note 3
1
8
AX ↔ rp
saddrp, AX
XCHW
× × ×
× × ×
Notes 1. Except r = A
2. Except r = A or X
3. Only when rp = BC, DE, HL
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
20
Data Sheet U14667EJ1V1DS00
µPD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
ADD
ADDC
SUB
SUBC
AND
Remark
A, #byte
2
4
A, CY ← A + byte
×
×
×
saddr, #byte
3
6
(saddr), CY ← (saddr) + byte
×
×
×
A, r
2
4
A ,CY ← A + r
×
×
×
A, saddr
2
4
A, CY ← A + (saddr)
×
×
×
A, !addr16
3
8
A, CY ← A + (addr16)
×
×
×
A, [HL]
1
6
A, CY ← A + (HL)
×
×
×
A, [HL + byte]
2
6
A, CY ← A + (HL + byte)
×
×
×
A, #byte
2
4
A, CY ← A + byte + CY
×
×
×
saddr, #byte
3
6
(saddr), CY ← (saddr) + byte + CY
×
×
×
A, r
2
4
A, CY ← A + r + CY
×
×
×
A, saddr
2
4
A, CY ← A + (saddr) + CY
×
×
×
A, !addr16
3
8
A, CY ← A + (addr16) + CY
×
×
×
A, [HL]
1
6
A, CY ← A + (HL) + CY
×
×
×
A, [HL + byte]
2
6
A, CY ← A + (HL + byte) + CY
×
×
×
A, #byte
2
4
A, CY ← A – byte
×
×
×
saddr, #byte
3
6
(saddr), CY ← (saddr) – byte
×
×
×
A, r
2
4
A, CY ← A – r
×
×
×
A, saddr
2
4
A, CY ← A – (saddr)
×
×
×
A, !addr16
3
8
A, CY ← A – (addr16)
×
×
×
A, [HL]
1
6
A, CY ← A – (HL)
×
×
×
A, [HL + byte]
2
6
A, CY ← A – (HL + byte)
×
×
×
A, #byte
2
4
A, CY ← A – byte – CY
×
×
×
saddr, #byte
3
6
(saddr), CY ← (saddr) – byte – CY
×
×
×
A, r
2
4
A, CY ← A – r – CY
×
×
×
A, saddr
2
4
A, CY ← A – (saddr) – CY
×
×
×
A, !addr16
3
8
A, CY ← A – (addr16) – CY
×
×
×
A, [HL]
1
6
A, CY ← A – (HL) – CY
×
×
×
A, [HL + byte]
2
6
A, CY ← A – (HL + byte) – CY
×
×
×
A, #byte
2
4
A ← A ∧ byte
×
saddr, #byte
3
6
(saddr) ← (saddr) ∧ byte
×
A, r
2
4
A←A∧r
×
A, saddr
2
4
A ← A ∧ (saddr)
×
A, !addr16
3
8
A ← A ∧ (addr16)
×
A, [HL]
1
6
A ← A ∧ (HL)
×
A, [HL + byte]
2
6
A ← A ∧ (HL + byte)
×
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
Data Sheet U14667EJ1V1DS00
21
µPD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
A, #byte
2
4
A ← A ∨ byte
×
saddr, #byte
3
6
(saddr) ← (saddr) ∨ byte
×
A, r
2
4
A←A∨r
×
A, saddr
2
4
A ← A ∨ (saddr)
×
A, !addr16
3
8
A ← A ∨ (addr16)
×
A, [HL]
1
6
A ← A ∨ (HL)
×
A, [HL + byte]
2
6
A ← A ∨ (HL + byte)
×
A, #byte
2
4
A ← A ∨ byte
×
saddr, #byte
3
6
(saddr) ← (saddr) ∨ byte
×
A, r
2
4
A←A∨r
×
A, saddr
2
4
A ← A ∨ (saddr)
×
A, !addr16
3
8
A ← A ∨ (addr16)
×
A, [HL]
1
6
A ← A ∨ (HL)
×
A, [HL + byte]
2
6
A ← A ∨ (HL + byte)
×
A, #byte
2
4
A – byte
×
×
×
saddr, #byte
3
6
(saddr) – byte
×
×
×
A, r
2
4
A–r
×
×
×
A, saddr
2
4
A – (saddr)
×
×
×
A, !addr16
3
8
A – (addr16)
×
×
×
A, [HL]
1
6
A – (HL)
×
×
×
A, [HL + byte]
2
6
A – (HL + byte)
×
×
×
ADDW
AX, #word
3
6
AX, CY ← AX + word
×
×
×
SUBW
AX, #word
3
6
AX, CY ← AX – word
×
×
×
CMPW
AX, #word
3
6
AX – word
×
×
×
INC
r
2
4
r←r+1
×
×
saddr
2
4
(saddr) ← (saddr) + 1
×
×
r
2
4
r←r–1
×
×
saddr
2
4
(saddr) ← (saddr) – 1
×
×
INCW
rp
1
4
rp ← rp + 1
DECW
rp
1
4
rp ← rp – 1
ROR
A, 1
1
2
(CY, A7 ← A0, Am – 1 ← Am) × 1
×
ROL
A, 1
1
2
(CY, A0 ← A7, Am + 1 ← Am) × 1
×
RORC
A, 1
1
2
(CY ← A0, A7 ← CY, Am – 1 ← Am) × 1
×
ROLC
A, 1
1
2
(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1
×
OR
XOR
CMP
DEC
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
22
Data Sheet U14667EJ1V1DS00
µPD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
saddr. bit
3
6
(saddr. bit) ← 1
sfr. bit
3
6
sfr. bit ← 1
A. bit
2
4
A. bit ← 1
PSW. bit
3
6
PSW. bit ← 1
[HL]. bit
2
10
(HL) . bit ← 1
saddr. bit
3
6
(saddr. bit) ← 0
sfr. bit
3
6
sfr. bit ← 0
A. bit
2
4
A. bit ← 0
PSW. bit
3
6
PSW. bit ← 0
[HL]. bit
2
10
(HL) . bit ← 0
SET1
CY
1
2
CY ← 1
1
CLR1
CY
1
2
CY ← 0
0
NOT1
CY
1
2
CY ← CY
×
CALL
!addr16
3
6
(SP – 1) ← (PC + 3)H,(SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLT
[addr5]
1
8
(SP – 1) ← (PC + 1)H,(SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
RET
1
6
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
1
8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
PSW
1
2
(SP – 1) ← PSW, SP ← SP – 1
rp
1
4
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
PSW
1
4
PSW ← (SP), SP ← SP + 1
rp
1
6
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, AX
2
8
SP ← AX
AX, SP
2
6
AX ← SP
!addr16
3
6
PC ← addr16
$addr16
2
6
PC ← PC + 2 + jdisp8
AX
1
6
PCH ← A, PCL ← X
SET1
CLR1
PUSH
POP
MOVW
BR
Remark
×
×
×
×
×
×
R R R
R R R
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
Data Sheet U14667EJ1V1DS00
23
µPD78F9116A
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z AC CY
BC
$addr16
2
6
PC ← PC + 2 + jdisp8 if CY = 1
BNC
$addr16
2
6
PC ← PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
6
PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
6
PC ← PC + 2 + jdisp8 if Z = 0
BT
saddr. bit, $addr16
4
10
PC ← PC + 4 + jdisp8
if (saddr. bit) = 1
sfr. bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if sfr. bit = 1
A. bit , $addr16
3
8
PC ← PC + 3 + jdisp8 if A. bit = 1
PSW. bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if PSW. bit = 1
saddr. bit, $addr16
4
10
PC ← PC + 4 + jdisp8
if (saddr. bit) = 0
sfr. bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if sfr. bit = 0
A. bit, $addr16
3
8
PC ← PC + 3 + jdisp8 if A. bit = 0
PSW. bit, $addr16
4
10
PC ← PC + 4 + jdisp8 if PSW. bit = 0
B, $addr16
2
6
B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
C ← C – 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
3
8
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
NOP
1
2
No Operation
EI
3
6
IE ← 1(Enable Interrupt)
DI
3
6
IE ← 0(Disable Interrupt)
HALT
1
2
Set HALT Mode
STOP
1
2
Set STOP Mode
BF
DBNZ
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
24
Data Sheet U14667EJ1V1DS00
µPD78F9116A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Supply voltage
Symbol
VDD, AVDD
Conditions
Ratings
Unit
–0.3 to +6.5
V
–0.3 to +10.5
V
–0.3 to VDD + 0.3
V
–0.3 to +13
V
–0.3 to VDD + 0.3
V
Per pin
–10
mA
Total for all pins
–30
mA
Per pin
30
mA
Total for all pins
160
mA
–40 to +85
°C
10 to 40
°C
–40 to +125
°C
VDD = AVDD
VPP
Input voltage
VI1
Pins other than P50 to P53
VI2
P50 to P53
Output voltage
VO
Output current, high
IOH
Output current, low
Operating ambient temperature
IOL
TA
With N-ch open drain
In normal operation mode
During flash memory programming
Storage temperature
Caution
Tstg
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U14667EJ1V1DS00
25
µPD78F9116A
System Clock Oscillator Characteristics
(TA = –40 to +85°°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Circuit
Parameter
Conditions
Note 1
Ceramic
resonator
VPP X1
C1
VPP X1
Crystal
resonator
C1
External
clock
X1
X1
X2
C2
X2
Oscillation frequency (fX)
VDD = oscillation voltage
range
Oscillation stabilization
Note 2
time
After VDD reaches
oscillation voltage range
MIN.
Note 1
Oscillation frequency (fX)
Oscillation stabilization
Note 2
time
C2
X2
MIN.
1.0
1.0
VDD = 4.5 to 5.5 V
TYP.
MAX.
Unit
5.0
MHz
4
ms
5.0
MHz
10
ms
30
Note 1
X1 input frequency (fX)
1.0
5.0
MHz
X1 input high-/low-level
width (tXH, tXL)
85
500
ns
1.0
5.0
MHz
85
500
ns
Note 1
X2
X1 input frequency (fX)
OPEN
X1 input high-/low-level
width (tXH, tXL)
VDD = 2.7 to 5.5 V
Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time.
2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that
stabilizes oscillation during the oscillation wait time.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
26
Data Sheet U14667EJ1V1DS00
µPD78F9116A
DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter
Output current, high
Output current, low
Input voltage, high
Symbol
IOH
IOL
VIH1
VIH2
Conditions
MAX.
Unit
Per pin
–1
mA
Total for all pins
–15
mA
Per pin
10
mA
Total for all pins
80
mA
0.7 VDD
VDD
V
0.9 VDD
VDD
V
0.7 VDD
12
V
VDD = 1.8 to 5.5 V, 0.9 VDD
12
V
0.8 VDD
VDD
V
0.9 VDD
VDD
V
VDD–0.5
VDD
V
VDD–0.1
VDD
V
0
0.3 VDD
V
0
0.1 VDD
V
VDD = 2.7 to 5.5 V
0
0.3 VDD
V
VDD = 1.8 to 5.5 V,
0
0.1 VDD
V
0
0.2 VDD
V
0
0.1 VDD
V
0
0.4
V
0
0.1
V
Pins other than described
below
P50 to P53
N-ch open drain
MIN.
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
TYP.
TA = 25 to 85 °C
VIH3
VIH4
Input voltage, low
VIL1
VIL2
RESET, P20 to P25
X1, X2
VDD = 4.5 to 5.5 V
Pins other than described
below
P50 to P53
VDD = 2.7 to 5.5 V
N-ch open drain
VDD = 2.7 to 5.5 V
TA = 25 to 85 °C
VIL3
VIL4
Output voltage, high
Output voltage, low
X1, X2
VDD = 2.7 to 5.5 V
VDD = 4.5 to 5.5 V
VOH1
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD–1.0
V
VOH2
VDD = 1.8 to 5.5 V, IOH = –100 µA
VDD–0.5
V
VOL1
Pins other
than P50 to
P53
VOL2
Remark
RESET, P20 to P25
P50 to P53
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
V
VDD = 1.8 to 5.5 V, IOL = 400 µA
0.5
V
VDD = 4.5 to 5.5 V, IOL = 10 mA
1.0
V
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
0.4
V
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U14667EJ1V1DS00
27
µPD78F9116A
DC Characteristics (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter
Input leakage current,
high
Input leakage current,
low
Symbol
Conditions
MIN.
TYP.
VIN = VDD
MAX.
Unit
3
µA
20
µA
ILIH1
Pins other than X1, X2,
or P50 to P53
ILIH2
X1, X2
ILIH3
P50 to P53 (N-ch open
drain)
VIN = 12 V
20
µA
ILIL1
Pins other than X1, X2,
or P50 to P53
VIN = 0 V
–3
µA
ILIL2
X1, X2
–20
µA
Note 1
µA
ILIL3
P50 to P53 (N-ch open
drain)
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Software pull-up
resistor
R1
VIN = 0 V, for pins other than P50 to P53
100
200
kΩ
Power supply
current
IDD1
Note 4
5.0
15.0
mA
Note 5
1.9
4.9
mA
Note 5
1.5
3.0
mA
Note 4
2.5
5.0
mA
Note 5
1.0
2.0
mA
Note 5
VDD = 2.0 V±10%
0.75
1.5
mA
VDD = 5.0 V±10%
0.1
30
µA
VDD = 3.0 V±10%
0.05
10
µA
VDD = 2.0 V±10%
Note 2
5.0-MHz crystal
oscillation operating
mode (C1 = C2 = 22pF)
–3
50
VDD = 5.0 V±10%
VDD = 3.0 V±10%
VDD = 2.0 V±10%
Note 2
IDD2
Note 2
IDD3
Note 3
IDD4
5.0-MHz crystal
oscillation HALT mode
(C1 = C2 = 22pF)
STOP mode
5.0-MHz crystal
oscillation A/D operating
mode (C1 = C2 = 22pF)
VDD = 5.0 V±10%
VDD = 3.0 V±10%
0.05
10
µA
Note 4
6.2
17.3
mA
Note 5
3.1
7.2
mA
Note 5
2.5
5.0
mA
VDD = 5.0 V±10%
VDD = 3.0 V±10%
VDD = 2.0 V±10%
Notes 1. When port 5 is in input mode, a low-level input leakage current of –60 µA (MAX.) flows only for 1 cycle
time after a read instruction has been executed to port 5.
2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and
AVDD current are not included.
3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not
included.
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.)
5. Low-speed mode operation (when PCC is set to 02H).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
28
Data Sheet U14667EJ1V1DS00
µPD78F9116A
FLASH MEMORY WRITE/DELETE CHARACTERISTICS (TA = 10°°C to 40°°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
18
mA
22.5
mA
Write current
Note
(VDD pin)
IDDW
When VPP supply voltage = VPP1
( 5.0-MHz crystal oscillation operating mode )
Write current
Note
(VPP pin)
IPPW
When VPP supply voltage = VPP1
Delete current
Note
(VDD pin)
IDDE
When VPP supply voltage = VPP1
( 5.0-MHz crystal oscillation operating mode )
18
mA
Delete current
Note
(VPP pin)
IPPE
When VPP supply voltage = VPP1
115
mA
Unit delete time
ter
1
s
Total delete time
tera
Write count
VPP supply voltage
0.5
1
Delete/write are regarded as 1 cycle
VPP0
In normal operation
VPP1
During flash memory programming
0
9.7
10.0
20
s
20
Times
0.2VDD
V
10.3
V
Note The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and AVDD
current are not included.
Data Sheet U14667EJ1V1DS00
29
µPD78F9116A
AC Characteristics
(1) Basic operation (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
Cycle time
(minimum instruction
execution time)
TCY
TI80 input high-/lowlevel width
tTIH,
tTIL
VDD = 2.7 to 5.5 V
TI80 input frequency
fTI
VDD = 2.7 to 5.5 V
MIN.
VDD = 2.7 to 5.5 V
MAX.
Unit
0.4
8
µs
1.6
8
µs
0.1
µs
1.8
µs
0
4
MHz
0
275
kHz
10
µs
tRSL
10
µs
tCPH,
tCPL
10
µs
Interrupt input high/low-level width
tINTH,
tINTL
RESET low-level
width
CPT20 input high/low-level width
INTP0 to INTP2
TCY vs VDD
60
Cycle time TCY [ µ s]
10
Guaranteed
operation range
2.0
1.0
0.5
0.4
0.1
1
2
3
4
5
Supply voltage VDD [V]
30
TYP.
Data Sheet U14667EJ1V1DS00
6
µPD78F9116A
(2) Serial interface (TA = –40 to +85°°C, VDD = 1.8 to 5.5 V)
(i) 3-wire serial I/O mode (SCK20...Internal clock output)
Parameter
SCK20 cycle time
Symbol
tKCY1
Conditions
VDD = 2.7 to 5.5 V
SCK20 high-/lowlevel width
tKH1,
tKL1
VDD = 2.7 to 5.5 V
SI20 setup time
(to SCK20↑)
tSIK1
VDD = 2.7 to 5.5 V
SI20 hold time
(from SCK20↑)
tKSI1
SO20 output delay
time from SCK20↓
tKSO1
VDD = 2.7 to 5.5 V
R = 1 k Ω,
Note
C = 100 pF
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
tKCY1/2 – 50
ns
tKCY1/2 – 150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
MAX.
Unit
Note R and C are the load resistance and load capacitance of the SO output line.
(ii) 3-wire serial I/O mode (SCK20...External clock input)
Parameter
SCK20 cycle time
Symbol
tKCY2
Conditions
VDD = 2.7 to 5.5 V
SCK20 high-/lowlevel width
tKH2,
tKL2
VDD = 2.7 to 5.5 V
SI20 setup time
(to SCK20↑)
tSIK2
VDD = 2.7 to 5.5 V
SI20 hold time
(from SCK20↑)
tKSI2
SO20 output delay
time from SCK20↓
tKSO2
SO20 setup time
(for SS20↓ when
SS20 is used)
tKAS2
SO20 disable time
(for SS20↑ when
SS20 is used)
tKDS2
VDD = 2.7 to 5.5 V
R = 1 kΩ,
Note
C = 100 pF
VDD = 2.7 to 5.5 V
MIN.
TYP.
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
120
ns
400
ns
240
ns
800
ns
MAX.
Unit
78125
bps
19531
bps
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
Note R and C are the load resistance and load capacitance of the SO output line.
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
VDD = 2.7 to 5.5 V
Data Sheet U14667EJ1V1DS00
MIN.
TYP.
31
µPD78F9116A
(iv) UART mode (external clock input)
Parameter
ASCK20 cycle time
ASCK20 high-/lowlevel width
Symbol
tKCY3
tKH3,
tKL3
Transfer rate
ASCK20 rise/fall time
32
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tR,
tF
Data Sheet U14667EJ1V1DS00
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
39063
bps
9766
bps
1
µs
µPD78F9116A
AC Timing Test Points (excluding X1 input)
0.8VDD
0.8VDD
Test points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
X1 input
VIL4 (MAX.)
TI Timing
1/fTI
tTIL
tTIH
TI80
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP2
RESET Input Timing
tRSL
RESET
Data Sheet U14667EJ1V1DS00
33
µPD78F9116A
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKHm
tKLm
SCK20
tSIKm
tKSIm
Input data
SI20
tKSOm
Output data
SO20
m = 1, 2
3-wire serial I/O mode (when SS20 is used):
SS20
tKAS2
tKDS2
SO20
Output data
UART mode (external clock input):
tKCY3
tKL3
tKH3
tR
ASCK20
34
Data Sheet U14667EJ1V1DS00
tF
µPD78F9116A
10-Bit A/D Converter Characteristics
(TA = −40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
4.5 V ≤ VDD ≤ 5.5 V
±0.2
±0.4
%FSR
2.7 V ≤ VDD < 4.5 V
±0.4
±0.6
%FSR
1.8 V ≤ VDD < 2.7 V
±0.8
±1.2
%FSR
Resolution
Note1,2
Overall error
Conversion time
Zero-scale error
tCONV
Note1,2
Note1,2
Full-scale error
Integral linearity
Note1
error
Differential linearity
Note1
error
Analog input voltage
ILE
DLE
2.7 V ≤ VDD ≤ 5.5 V
14
100
µs
1.8 V ≤ VDD < 2.7 V
28
100
µs
4.5 V ≤ VDD ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ VDD < 4.5 V
±0.6
%FSR
1.8 V ≤ VDD < 2.7 V
±1.2
%FSR
4.5 V ≤ VDD ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ VDD < 4.5 V
±0.6
%FSR
1.8 V ≤ VDD < 2.7 V
±1.2
%FSR
4.5 V ≤ VDD ≤ 5.5 V
±2.5
LSB
2.7 V ≤ VDD < 4.5 V
±4.5
LSB
1.8 V ≤ VDD < 2.7 V
±8.5
LSB
4.5 V ≤ VDD ≤ 5.5 V
±1.5
LSB
2.7 V ≤ VDD < 4.5 V
±2.0
LSB
1.8 V ≤ VDD < 2.7 V
±3.5
LSB
AVDD
V
VIAN
0
Notes 1. Excludes quantization error (±0.05%FSR).
2. It is indicated as a ratio to the full-scale value (%FSR).
Data Sheet U14667EJ1V1DS00
35
µPD78F9116A
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°°C)
Parameter
Symbol
Conditions
MIN.
Data retention
supply voltage
VDDDR
1.8
Release signal
set time
tSREL
0
Oscillation
stabilization wait
Note 1
time
tWAIT
TYP.
MAX.
Unit
5.5
V
µs
15
Release by RESET
Release by interrupt request
2 /fX
ms
Note 2
ms
Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
12
15
17
2. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register.
Remark
fX: System clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
tSREL
VDDDR
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
36
Data Sheet U14667EJ1V1DS00
µPD78F9116A
9. PACKAGE DRAWING
30-PIN PLASTIC SSOP (7.62 mm (300))
30
16
detail of lead end
F
G
T
P
1
L
15
U
E
A
H
I
J
S
C
D
N
M
S
B
K
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
9.85±0.15
B
0.45 MAX.
C
0.65 (T.P.)
D
0.24 +0.08
−0.07
E
0.1±0.05
F
1.3±0.1
G
1.2
H
8.1±0.2
I
6.1±0.2
J
1.0±0.2
K
0.17±0.03
L
0.5
M
0.13
N
0.10
P
3° +5°
−3°
T
0.25
U
0.6±0.15
S30MC-65-5A4-2
Data Sheet U14667EJ1V1DS00
37
µPD78F9116A
10. RECOMMENDED SOLDERING CONDITIONS
The µPD78F9116A should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended
below, contact your NEC sales representative.
Table 10-1. Surface Mounting Type Soldering Conditions
µPD78F9116AMC-5A4: 30-pin plastic SSOP (7.62 mm (300))
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Reflow time: 30 seconds or below (at 210°C
Note
or higher), Number of reflow processes : 3 max., Exposure limit : 7days
Recommended
Condition Symbol
IR35-107-3
(after that, prebaking is necessary at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Reflow time: 40 seconds or below (at 200°C
Note
or higher), Number of reflow processes : 3 max., Exposure limit : 7days
VP15-107-3
(after that, prebaking is necessary at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C or below, Flow time: 10 seconds or below,
Number of flow processes: 1
Preheating temperature: 120°C or below (package surface temperature),
Note
Exposure limit : 7days (after that, prebaking is necessary at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
38
WS60-107-1
–
Note
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
Data Sheet U14667EJ1V1DS00
µPD78F9116A
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78F9116A.
Language Processing Software
RA78K0S
Notes 1, 2, 3
Assembler package common to 78K/0S Series
Notes 1, 2, 3
C compiler package common to 78K/0S Series
CC78K0S
DF789136
Notes 1, 2, 3
Device file for µPD78F9116A
Flash Memory Writing Tools
Flashpro lIl
Note 4
(Model number: FL-PR3 ,
Dedicated flash programmer for on-chip flash memory
PG-FP3)
Note 4
FA-30MC
Flash memory writing adapter
Debugging Tools (1/2)
IE-78K0S-NS
In-circuit emulator
In-circuit emulator serves to debug hardware and software when developing application systems
using a 78K/0S Series product. It supports the ID78K0S-NS integrated debugger. Used in
combination with an AC adapter, emulation probe, and interface adapter connecting to the host
machine.
IE-70000-MC-PS-B
AC adapter
Adapter used to supply power from a power outlet of 100 V AC to 240 V AC.
IE-70000-98-IF-C
Interface adapter
Adapter when PC-9800 series PC (except notebook type) is used as the IE-78K0S-NS host
machine (C bus supported).
IE-70000-CD-IF-A
PC card interface
PC card and interface cable when notebook PC is used as the IE-78K0S-NS host machine
(PCMCIA socket supported).
IE-70000-PC-IF-C
Interface adapter
Adapter when using an IBM PC/AT™ or compatible as the IE-78K0S-NS host machine.
IE-70000-PCI-IF
Interface adapter
Adapter when using PC that includes a PCI bus as the IE-78K0S-NS host machine.
IE-789136-NS-EM1
Emulation board
Board for emulation of the peripheral hardware peculiar to a device. Used in combination with
an in-circuit emulator.
NP-36GS
Note 4
Board used to connect the in-circuit emulator to the target system. For a 30-pin plastic SSOP
(MC-5A4 type), used in combination with NGS-30.
Note 4
NGS-30
Conversion socket
Conversion socket used to connect the NP-36GS to the target system board designed to mount
a 30-pin plastic SSOP (MC-5A4 type).
Notes 1. PC-9800 series (Japanese Windows™) based
2. IBM PC/AT or compatibles (Japanese/English Windows) based
3. HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™ (NEWS-OS™)
based.
4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813).
Remark
RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136.
Data Sheet U14667EJ1V1DS00
39
µPD78F9116A
Debugging Tools (2/2)
SM78K0S
Notes 1, 2
ID78K0S-NS
DF789136
Notes 1, 2
Notes 1, 2
System simulator common to 78K/0S Series
Integrated debugger common to 78K/0S Series
Device file for µPD78F9116A
Real-time OS
MX78K0S
Notes 1, 2
OS for 78K/0S Series
Notes 1. PC-9800 series (Japanese Windows) based.
2. IBM PC/AT or compatibles (Japanese/English Windows) based.
40
Data Sheet U14667EJ1V1DS00
µPD78F9116A
APPENDIX B RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document No.
Document Name
Japanese
English
µPD789101A, 102A, 104A, 111A, 112A, 114A, 101A(A), 102A(A), 104A(A), 111A(A),
112A(A), 114A(A) Data Sheet
U14590J
U14590E
µPD78F9116A Data Sheet
U14667J
This manual
µPD789104A, 789114A, 789124A, 789134A Subseries User’s Manual
U14643J
To be prepared
78K/0S Series User’s Manual Instruction
U11047J
U11047E
78K/0, 78K/0S Series Application Note Flash Memory Write
U14458J
U14458E
Documents Related to Development Tools (User’s Manuals)
Document No.
Document Name
Japanese
RA78K0S Assembler Package
English
Operation
U11622J
U11622E
Assembly Language
U11599J
U11599E
Structured Assembly
Language
U11623J
U11623E
Operation
U11816J
U11816E
Language
U11817J
U11817E
SM78K0S System Simulator Windows Based
Reference
U11489J
U11489E
SM78K Series System Simulator
External Parts User Open
Interface Specifications
U10092J
U10092E
ID78K0S-NS Integrated Debugger Windows Based
Reference
U12901J
U12901E
IE-78K0S-NS In-circuit Emulator
U13549J
U13549E
IE-789136-NS-EM1 Emulation Board
U14363J
U14363E
CC78K0S C Compiler
Documents Related to Embedded Software (User’s Manuals)
Document No.
Document Name
Japanese
78K/0S Series OS MX78K0S
Caution
Fundamental
U12938J
English
U12938E
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Data Sheet U14667EJ1V1DS00
41
µPD78F9116A
Other Related Documents
Document No.
Document Name
Japanese
English
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Guide to Microcomputer-Related Products by Third Party
U11416J
−
Caution
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
42
Data Sheet U14667EJ1V1DS00
µPD78F9116A
[ MEMO ]
Data Sheet U14667EJ1V1DS00
43
µPD78F9116A
[ MEMO ]
44
Data Sheet U14667EJ1V1DS00
µPD78F9116A
[ MEMO ]
Data Sheet U14667EJ1V1DS00
45
µPD78F9116A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
46
Data Sheet U14667EJ1V1DS00
µPD78F9116A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U14667EJ1V1DS00
47
µPD78F9116A
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8