ETC UPD78F0058YGC-8BT

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78F0058,78F0058Y
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD78F0058 is a product of the µPD780058 Subseries in the 78K/0 Series and equivalent to the µPD780058
with a flash memory in place of internal ROM. This device is incorporated with a flash memory which can be
programmed without being removed from the substrate.
The µPD78F0058Y is a products based on the µPD78F0058, with an I2C bus interface supporting multimaster.
Functions are described in detail in the following user’s manuals, which should be read when carrying out
design work.
FEATURES
• Pin-compatible with mask
• Flash memory
• Internal high-speed RAM
• Internal expansion RAM
• Buffer RAM
• Power supply voltage
µPD780058, 780058Y Subseries User’s Manual
:U12013E
78K/0 Series User’s Manual Instruction
:U12326E
ROM version (except VPP pin)
: 60 KbytesNote 1
: 1024 bytes
: 1024 bytesNote 2
: 32 bytes
: VDD = 2.7 to 5.5 V
Notes 1. The flash memory capacity can be changed with the memory size switching register (IMS).
2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching
register (IXS).
Remark For the differences between the flash memory versions and the mask ROM versions, refer to
1. DIFFERENCES BETWEEN µPD78F0058, 78F0058Y, AND MASK ROM VERSION.
APPLICATION FIELDS
Car audio systems, cellular phones, pagers, printers, AV equipment, cameras, PPCs, vending machines, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12092EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µPD78F0058, 78F0058Y
ORDERING INFORMATION
Part Number
µPD78F0058GC-8BT
80-pin plastic QFP (14 × 14 mm)
µPD78F0058GK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)
µPD78F0058GK-9EUNote
80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.0 mm)
µPD78F0058YGC-8BT
80-pin plastic QFP (14 × 14 mm)
µPD78F0058YGK-BE9
80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)
µPD78F0058YGK-9EUNote
80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.0 mm)
Note
2
Package
Under development
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name.
Products under development
Products in mass production
Y subseries products supports the I2C bus.
Control
100-pin
µPD78075B
100-pin
µ PD78078
µ PD78070A
EMI-noise reduced version of the µ PD78078
µPD78078Y
µPD78054 with timer and enhanced external interface
µPD78070AY
ROM-less version of the µPD78078
µPD780018AY
µ PD78078Y with enhanced serial I/O and limited functions
µ PD780058
µPD78058F
µPD780058Y
µ PD78058FY
µ PD78054 with enhanced serial I/O
80-pin
µPD78054
µ PD78054Y
80-pin
64-pin
µPD780065
µPD780078
µ PD780078Y
µPD780034A with timer and enhanced serial I/O
64-pin
µPD780034A
µPD780034AY
µ PD780024A with enhanced A/D converter
64-pin
µ PD780024A
µ PD780024AY
µPD78018F with enhanced serial I/O
64-pin
64-pin
µ PD78014H
100-pin
100-pin
80-pin
80-pin
42/44-pin
µ PD78018F
EMI-noise reduced version of the µ PD78054
µ PD78018F with UART and D/A converter and enhanced I/O
µPD780024A with expanded RAM
EMI-noise reduced version of the µPD78018F
µPD78018FY
µ PD78083
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
µ PD780988
On-chip inverter control circuit and UART. EMI-noise reduced version.
FIPTM drive
µ PD780208
µ PD78044F with enhanced I/O and FIP C/D. Display output total: 53
100-pin
µPD780228
µPD78044H with enhanced I/O and FIP C/D. Display output total: 48
80-pin
µ PD780232
For panel control. On-chip FIP C/D. Display output total: 53
80-pin
µ PD78044H
µPD78044F with N-ch open drain I/O. Display output total: 34
80-pin
µPD78044F
Basic subseries for FIP drive. Display output total: 34
100-pin
78K/0
Series
LCD drive
µPD780308
µPD78064B
µPD780308Y
100-pin
µPD78064 with enhanced SIO and expanded ROM and RAM
EMI-noise reduced version of the µ PD78064
100-pin
µ PD78064
µ PD78064Y
Basic subseries for LCD drive, on-chip UART
100-pin
Call ID
80-pin
µ PD780841
On-chip Call ID function, simplified DTMF. EMI-noise reduced version.
Bus interface
100-pin
µ PD780948
On-chip DCAN controller
80-pin
µPD78098B
µPD78054 with IEBusTM controller. EMI-noise reduced version.
80-pin
µ PD780701Y
On-chip DCAN/IEBus controller
80-pin
µPD780833Y
On-chip J1850 (CLASS2) controller
64-pin
µPD780814
Special in DCAN controller function
Meter control
100-pin
µ PD780958
Industrial meter control
80-pin
Ultra low-power consumption. On-chip UART.
80-pin
µ PD780955
µ PD780852
80-pin
µ PD780824
For automotive meter drive. On-chip DCAN controller
On-chip controller/driver for automotive meter drive
Data Sheet U12092EJ1V0DS00
3
µPD78F0058, 78F0058Y
The major functional differences among the subseries are listed below.
Function
Subseries Name
Control
ROM
Capacity
Timer
8-Bit 10-Bit 8-Bit
8-bit 16-bit Watch WDT A/D A/D D/A
µPD78075B
32 K to 40K 4 ch
µPD78078
48 K to 60K
µPD78070A
1 ch
1 ch
1 ch
8 ch
–
2 ch
3 ch (UART: 1 ch)
–
I/O
VDD MIN. External
Value Expansion
88
1.8 V
61
2.7 V
µPD780058
24 K to 60 K 2 ch
3 ch (time-division
UART: 1 ch)
68
1.8 V
µPD78058F
48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
16 K to 60 K
µPD780065
40 K to 48 K
µPD780078
48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
√
2.0 V
–
–
µPD780024A
8 ch
8 ch
µPD78018F
8 K to 60 K
µPD78083
8 K to 16 K
µPD780988
16 K to 60 K 3 ch Note
FIP
µPD780208
32 K to 60 K 2 ch
drive
µPD780228
48 K to 60 K 3 ch
µPD780232
16 K to 24 K
µPD78044H
32 K to 48 K 2 ch
µPD78044F
16 K to 40 K
µPD780308
48 K to 60 K 2 ch
µPD78064B
32 K
µPD78064
16 K to 32 K
Call ID
µPD780841
24 K to 32 K 1 ch
1 ch
1 ch
1 ch
2 ch
–
–
Bus
µPD780948
60 K
2 ch
1 ch
1 ch
8 ch
–
–
interface
µPD78098B
40 K to 60 K
1 ch
supported
µPD780814
32 K to 60 K
2 ch
Meter
µPD780958
48 K to 60 K 4 ch
2 ch
control
µPD780955
40 K
1 ch
µPD780852
32 K to 40 K 3 ch
µPD780824
32 K to 60 K
–
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
2 ch
53
1 ch (UART: 1 ch)
33
–
µPD78014H
Inverter
Serial
Interface
–
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
–
–
1 ch
72
4.5 V
4 ch
2 ch
40
8 ch
1 ch
68
2.7 V
57
2.0 V
–
2 ch (UART: 1 ch)
57
2.7 V
–
3 ch (UART: 1 ch)
79
4.0 V
√
69
2.7 V
–
control
LCD
drive
1 ch
1ch
2 ch
1 ch
1ch
1 ch
8 ch
–
–
2 ch (UART: 1 ch)
2 ch
6 ch
2 ch
12 ch
–
1 ch
1 ch
–
2 ch (UART: 1 ch)
46
4.0 V
–
2 ch (UART: 1 ch)
69
2.2 V
1 ch
2 ch (UART: 2 ch)
50
5 ch
3 ch (UART: 1 ch)
56
4.0 V
2 ch (UART: 1 ch)
59
4.0 V
–
–
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
4
3 ch (time-division
UART: 1 ch)
Data Sheet U12092EJ1V0DS00
–
µPD78F0058, 78F0058Y
The major functional differences among the Y subseries are shown below.
Function ROM Capacity
Configuration of Serial Interface
I/O
Subseries Name
Control
µPD78078Y
µPD78070AY
Value
48 K to 60 K
−
2
3-wire/2-wire/I C
: 1 ch
3-wire with automatic transmit/receive function : 1 ch
3-wire/UART
: 1 ch
88
1.8 V
61
2.7 V
µPD780018AY
48 K to 60 K
3-wire with automatic transmit/receive function : 1 ch
Time-division 3-wire
: 1 ch
I2C bus (multimaster supported)
: 1 ch
88
µPD780058Y
24 K to 60 K
3-wire/2-wire/I2C
: 1 ch
3-wire with automatic transmit/receive function : 1 ch
3-wire/time-division UART
: 1 ch
68
1.8 V
µPD78058FY
48 K to 60 K
3-wire/2-wire/I2C
: 1 ch
3-wire with automatic transmit/receive function : 1 ch
3-wire/UART
: 1 ch
69
2.7 V
µPD78054Y
16 K to 60 K
2.0 V
µPD780078Y
48 K to 60 K
3-wire
UART
3-wire/UART
I2C bus (multimaster supported)
: 1 ch
: 1 ch
: 1 ch
: 1 ch
52
1.8 V
µPD780034AY
8 K to 32 K
UART
3-wire
I2C bus (multimaster supported)
: 1 ch
: 1 ch
: 1 ch
51
1.8 V
µPD78018FY
8 K to 60 K
3-wire/2-wire/I2C
: 1 ch
3-wire with automatic transmit/receive function : 1 ch
53
µPD780308Y
48 K to 60 K
3-wire/2-wire/I2C
3-wire/time-division UART
3-wire
: 1 ch
: 1 ch
: 1 ch
57
µPD78064Y
16 K to 32 K
3-wire/2-wire/I2C
3-wire/UART
: 1 ch
: 1 ch
µPD780024AY
LCD
VDD MIN.
drive
2.0 V
Remark The functions other than the serial interface are common to the Subseries without Y.
Data Sheet U12092EJ1V0DS00
5
µPD78F0058, 78F0058Y
OVERVIEW OF FUNCTIONS
µPD78F0058
Product Name
µPD78F0058Y
Item
Internal
memory
Flash memory
60 Kbytes
High-speed RAM
1,024 bytes
Buffer RAM
32 bytes
Expanded RAM
1,024 bytes
Memory space
64 Kbytes
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum
instruction
execution
time
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0 MHz operation)
When main system
clock is selected
When subsystem
clock is selected
122 µs (@32.768 kHz operation)
Instruction set
•
•
•
•
I/O ports
Total:
• CMOS input:
• CMOS I/O:
• N-ch open-drain I/O:
A/D converter
• 8-bit resolution × 8 channels (VDD = 2.7 to 5.5 V)
D/A converter
• 8-bit resolution × 2 channels (VDD = 2.7 to 5.5 V)
Serial interface
• 3-wire serial I/O/2-wire serial I/O/
• 3-wire serial I/O/SBI/2-wire serial
I2C mode selectable: 1 channel
I/O mode selectable: 1 channel
• 3-wire serial I/O mode (automatic data transmit/receive function for up to 32 bytes
provided on chip): 1 channel
• 3-wire/serial I/O/UART mode (time division transfer function provided on chip)
selectable: 1 channel
Timers
•
•
•
•
Timer outputs
3 (14-bit PWM output × 1)
Clock output
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(@5.0 MHz operation with main system clock)
32.768 kHz (@32.768 kHz operation with subsystem clock)
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
68
2
62
4
1
2
1
1
channel
channels
channel
channel
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@5.0 MHz operation with main system clock)
Buzzer output
Vectored
interrupt
sources
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
Maskable
Internal: 13, External: 6
Non-maskable
Internal: 1
Software
1
Test inputs
Internal: 1, External: 1
Supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.0 mm)
6
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ...........................................................................................
8
2. BLOCK DIAGRAM .......................................................................................................................... 10
3. DIFFERENCES BETWEEN µPD78F0058, 78F0058Y, AND MASK ROM VERSIONS ............... 11
3.1 Memory Size Switching Register (IMS) ................................................................................................ 12
3.2 Internal Expansion RAM Size Switching Register (IXS) .................................................................... 13
4. PIN FUNCTIONS ............................................................................................................................. 14
4.1 Port Pins ................................................................................................................................................... 14
4.2 Non-Port Pins ........................................................................................................................................... 16
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 18
5. MEMORY SPACE ........................................................................................................................... 22
6. FLASH MEMORY PROGRAMMING ............................................................................................... 23
6.1 Selection of Transmission Mode ........................................................................................................... 23
6.2 Function of Flash Memory Programming ............................................................................................ 24
6.3 Connection of Flashpro III ...................................................................................................................... 24
6.4 Example of Settings for Flashpro III (PG-FP3) .................................................................................... 26
7. ELECTRICAL SPECIFICATIONS .................................................................................................. 27
8.
PACKAGE DRAWINGS ................................................................................................................. 56
9.
RECOMMENDED SOLDERING CONDITIONS ........................................................................... 59
APPENDIX A. DEVELOPMENT TOOLS .......................................................................................... 61
APPENDIX B. RELATED DOCUMENTS .......................................................................................... 64
Data Sheet U12092EJ1V0DS00
7
µPD78F0058, 78F0058Y
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 14 mm)
µPD78F0058GC-8BT, 78F0058YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)
µPD78F0058GK-BE9, 78F0058YGK-BE9
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.0 mm)
µPD78F0058GK-9EUNote, 78F0058YGK-9EUNote
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
VSS0
VDD1
X2
X1
VPP
XT2
XT1/P07
VDD0
AV REF0
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
Note Under development
7
54
P122/RTP2
P70/SI2/RxD0
8
53
P121/RTP1
P71/SO2/TxD0
9
52
P120/RTP0
P72/SCK2/ASCK
10
51
P37
P20/SI1
11
50
P36/BUZ
P21/SO1
12
49
P35/PCL
P22/SCK1
13
48
P34/TI2
P23/STB/TxD1
14
47
P33/TI1
P24/BUSY/RxD1
15
46
P32/TO2
P25/SI0/SB0 [/SDA0]
16
45
P31/TO1
P26/SO0/SB1 [/SDA1]
17
44
P30/TO0
P27/SCK0 [/SCL]
18
43
P67/ASTB
P40/AD0
19
42
P66/WAIT
P41/AD1
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1.
2.
RESET
P65/WR
P64/RD
P63
P123/RTP3
AV REF1
P62
55
P61
6
P60
P124/RTP4
P131/ANO1
P57/A15
56
P56/A14
5
VSS1
P125/RTP5
P130/ANO0
P55/A13
57
P54/A12
4
P53/A11
P126/RTP6
AV SS
P52/A10
58
P51/A9
3
P50/A8
P127/RTP7
P17/ANI7
P47/AD7
59
P46/AD6
2
P45/AD5
P16/ANI6
P44/AD4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
P43/AD3
1
P42/AD2
P15/ANI5
Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
Connect the AVSS pin to VSS0.
Remarks 1. [
]: µPD78F0058Y only.
2. When the microcontroller is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage
to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
PIN IDENTIFICATION
A8 to A15
: Address Bus
RD
: Read Strobe
AD0 to AD7
: Address/Data Bus
RESET
: Reset
ANI0 to ANI7
: Analog Input
RTP0 to RTP7
: Real-Time Output Port
ANO0, ANO1
: Analog Output
RxD0, RxD1
: Receive Data
ASCK
: Asychronous Serial Clock
SB0, SB1
: Serial Bus
ASTB
: Address Strobe
SCK0 to SCK2
: Serial Clock
AVREF0, AVREF1
: Analog Reference Voltage
SCL
: Serial Clock
AVSS
: Analog Ground
SDA0, SDA1
: Serial Data
BUSY
: Busy
SI0 to SI2
: Serial Input
BUZ
: Buzzer Clock
SO0 to SO2
: Serial Output
INTP0 to INTP5 : Interrupt from Peripherals
STB
: Strobe
P00 to P05, P07 : Port 0
TI00, TI01
: Timer Input
P10 to P17
: Port 1
TI1, TI2
: Timer Input
P20 to P27
: Port 2
TO0 to TO2
: Timer Output
P30 to P37
: Port 3
TxD0, TxD1
: Transmit Data
P40 to P47
: Port 4
VDD0, VDD1
: Power Supply
P50 to P57
: Port 5
VPP
: Programming Power Supply
P60 to P67
: Port 6
VSS0, VSS1
: Ground
P70 to P72
: Port 7
WAIT
: Wait
P120 to P127
: Port 12
WR
: Write Strobe
P130, P131
: Port 13
X1, X2
: Crystal (Main System Clock)
PCL
: Programmable Clock
XT1, XT2
: Crystal (Subsystem Clock)
Data Sheet U12092EJ1V0DS00
9
µPD78F0058, 78F0058Y
2. BLOCK DIAGRAM
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
16-bit timer/
event counter
TO1/P31
TI1/P33
8-bit timer/
event counter 1
TO2/P32
TI2/P34
8-bit timer/
event counter 2
Port 0
P00
P01 to P05
P07
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 12
P120 to P127
Port 13
P130, P131
Watchdog timer
Watch timer
SI0/SB0 [/SDA0] /P25
SO0/SB1 [/SDA1] /P26
SCK0 [/SCL] /P27
Serial
interface 0
78K/0
CPU core
SI1/P20
SO1/P21
SCK1/P22
STB/TxD1/P23
BUSY/RxD1/P24
Serial
interface 1
BUSY/RxD1/P24
STB/TxD1/P23
SI2/RxD0/P70
SO2/TxD0/P71
SCK2/ASCK/P72
Serial
interface 2
FLASH
MEMORY
RAM
ANI0/P10 to
ANI7/P17
AV SS
AVREF0
ANO0/P130,
ANO1/P131
AV SS
Real-time
output port
A/D converter
D/A converter
External access
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
System control
RESET
X1
X2
XT1/P07
XT2
AV REF1
INTP0/P00 to
INTP5/P05
Buzzer output
PCL/P35
Clock output
control
Remark [
10
Interrupt
control
BUZ/P36
VDD0,
VDD1
VSS0,
VSS1
VPP
]: µPD78F0058Y only.
Data Sheet U12092EJ1V0DS00
RTP0/P120 to
RTP7/P127
µPD78F0058, 78F0058Y
3. DIFFERENCES BETWEEN µPD78F0058, 78F0058Y, AND MASK ROM VERSIONS
The µ PD78F0058 and 78F0058Y are products provided with a flash memory which enables on-board reading,
erasing, and rewriting of programs with device mounted on target system. The functions of the µ PD78F0058
and 78F0058Y (except the functions specified for flash memory and mask option of P60 to P63 pins) can be
made the same as those of the mask ROM versions by setting the memory size switching register (IMS) and
internal expansion RAM size switching register (IXS).
Table 3-1 shows the differences between the flash memory version ( µ PD78F0058, 78F0058Y) and the mask
ROM versions ( µ PD780053, 780054, 780055, 780056, 780058, 780053Y, 780054Y, 780055Y,780056Y, and
780058Y).
Table 3-1. Differences between µ PD78F0058, 78F0058Y and Mask ROM Versions
Item
µPD78F0058
µPD78F0058Y
Mask ROM Versions
µPD780058
Subseries
µPD780058Y
Subseries
Internal ROM structure
Flash memory
Mask ROM
Internal ROM capacity
60 Kbytes
µPD780053,
µPD780054,
µPD780055,
µPD780056,
µPD780058,
780053Y
780054Y
780055Y
780056Y
780058Y
:
:
:
:
:
24
32
40
48
60
Internal expansion RAM capacity
1024 bytes
µPD780053,
µPD780054,
µPD780055,
µPD780056,
µPD780058,
780053Y
780054Y
780055Y
780056Y
780058Y
:
:
:
:
:
None
None
None
None
1024 bytes
Internal ROM capacity changeable/not
changeable with memory size switching
register (IMS)
ChangeableNote 1
Not changeable
Internal expansion RAM capacity
changeable/not changeable with internal
expansion RAM size switching register (IXS)
ChangeableNote 2
Not changeable
Supply voltage
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
IC pin
Not provided
Provided
VPP pin
Provided
P60 to P63 pin mask option with internal
pull-up resistors
Not provided
Serial interface (SBI)
2
Serial interface (I C)
Kbytes
Kbytes
Kbytes
Kbytes
Kbytes
Not provided
Provided
Provided
Not provided
Provided
Not provided
Not provided
Provided
Not provided
Provided
Notes 1. Flash memory is set to 60 Kbytes by RESET input.
2. Internal expansion RAM is set to 1024 bytes by RESET input.
Caution
The noise resistance and noise radiation differ between flash memory versions and mask ROM
versions. When considering the replacement of flash memory versions with mask ROM versions
in the process from trial manufacturing to mass production, adequate evaluation should be
carried out using CS products (not ES products) of mask ROM versions.
Remark
Only the µPD780058, 780058Y, 78F0058, and 78F0058Y are provided with IXS.
Data Sheet U12092EJ1V0DS00
11
µPD78F0058, 78F0058Y
3.1 Memory Size Switching Register (IMS)
This register sets a part of internal memory unused by software. The memory mapping can be made the same
as that of mask ROM versions with different types of internal memory (ROM and RAM) by setting the memory
size switching register (IMS).
The IMS is set with an 8-bit memory manipulation instruction.
RESET input sets the IMS to CFH.
Figure 3-1. Format of Memory Size Switching Register
Symbol
7
IMS
RAM2
6
5
4
RAM1 RAM0
0
3
2
1
0
ROM3 ROM2 ROM1 ROM0
Address
At reset
R/W
FFF0H
CFH
R/W
ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity
0
1
1
0
24 Kbytes
1
0
0
0
32 Kbytes
1
0
1
0
40 Kbytes
1
1
0
0
48 Kbytes
1
1
1
0
56 KbytesNote
1
1
1
1
60 Kbytes
Setting prohibited
Others
RAM2 RAM1 RAM0
1
1
0
Others
Selection of Internal High-speed RAM Capacity
1024 bytes
Setting prohibited
Note When using external device expansion function, set the internal ROM capacity to less than 56 Kbytes.
Table 3-2 shows the IMS set value to make the memory mapping the same as those of mask ROM versions.
Table 3-2. Set Value of Memory Size Switching Register
12
Target Mask ROM Versions
IMS Set Value
µPD780053, 780053Y
C6H
µPD780054, 780054Y
C8H
µPD780055, 780055Y
CAH
µPD780056, 780056Y
CCH
µPD780058, 780058Y
CFH
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
3.2 Internal Expansion RAM Size Switching Register (IXS)
This register sets the internal expansion RAM capacity by software. The memory mapping can be made the
same as that of mask ROM versions with different types of internal expansion RAM by setting the internal
expansion RAM size switching register (IXS).
The IXS is set with an 8-bit memory manipulation instruction.
RESET input sets the IXS to 0AH.
Figure 3-2. Format of Internal Expansion RAM Size Switching Register
Symbol
7
6
5
4
IXS
0
0
0
0
3
2
1
0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Address
At reset
R/W
FFF4H
0AH
W
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of Internal Expansion RAM Capacity
1
1
0
0
0 bytes
1
0
1
0
1024 bytes
Others
Setting prohibited
Table 3-3 shows the IXS set value to make the memory mapping the same as those of mask ROM versions.
Table 3-3. Set Value of Internal Expansion RAM Size Switching Register
Target Mask ROM Versions
IMS Set Value
µPD780053, 780053Y
0CH
µPD780054, 780054Y
µPD780055, 780055Y
µPD780056, 780056Y
µPD780058, 780058Y
0AH
Data Sheet U12092EJ1V0DS00
13
µPD78F0058, 78F0058Y
4. PIN FUNCTIONS
4.1 Port Pins (1/2)
Pin Name
P00
Input
P01
I/O
After
Reset
Alternate
Function
Input only
Input
INTP0/TI00
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up
resistor can be specified by means of software.
Input
INTP1/TI01
Function
I/O
Port 0
7-bit input/output port
P02
INTP2
P03
INTP3
P04
INTP4
P05
INTP5
P07Note 1
Input
Input only
Input
XT1
P10 to P17
I/O
Port 1
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of softwareNote 2.
Input
ANI0 to ANI7
P20
I/O
Port 2
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
Input
SI1
P21
P22
P23
SO1
SCK1
STB/TxD1
P24
BUSY/RxD1
P25
SI0/SB0 [/SDA0]
P26
SO0/SB1 [/SDA1]
P27
SCK0 [/SCL]
I/O
P30
P31
P32
P33
Port 3
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified
by means of software.
Input
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
–
P40 to P47
I/O
Port 4
8-bit input/output port
Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software. The test input flag (KRIF) is set to 1
by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P07/XT1 pins as an input port, set bit 6 (FRC) of the processor clock control register
(PCC) to 1. Do not use the on-chip feedback resistor of the subsystem clock oscillator.
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the
input mode. At this time, on-chip pull-up resistors are automatically disconnected.
Remark [
14
]: µPD78F0058Y only.
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
4.1 Port Pins (2/2)
Pin Name
I/O
Function
After
Reset
P50 to P57
I/O
Port 5
8-bit input/output port
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
means of software.
Input
P60
I/O
N-ch open-drain input/output port
Port 6
LEDs can be driven directly.
8-bit input/outport port
Input/output can be specified
in 1-bit units.
Input
P61
P62
Alternate
Function
A8 to A15
–
P63
P64
When used as an input port, an on-chip
pull-up resistor can be specified by means
of software.
P65
P66
RD
WR
WAIT
P67
P70
ASTB
I/O
P71
P72
Port 7
3-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
means of software.
Input
SI2/RxD0
SO2/TxD0
SCK2/ASCK
P120 to P127
I/O
Port 12
8-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistor can be specified by
means of software.
Input
RTP0 to RTP7
P130, P131
I/O
Port 13
2-bit input/output port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified by
means of software.
Input
ANO0, ANO1
Data Sheet U12092EJ1V0DS00
15
µPD78F0058, 78F0058Y
4.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1
Function
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising edge and falling edges) can be specified.
After
Reset
Input
Alternate
Function
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
SI0
Input
Serial interface serial data input
Input
P25/SB0 [/SDA0]
SI1
P20
SI2
P70/RxD
SO0
Output
Input
Serial interface serial data output
P26/SB1 [/SDA1]
SO1
P21
SO2
P71/TxD
SB0
I/O
Serial interface serial data input/output
Input
SB1
P26/SO0 [/SDA1]
µPD78F0058Y only
SDA0
P25/SI0/SB0
SDA1
SCK0
P25/SI0 [/SDA0]
P26/SO0/SB1
I/O
Serial interface serial clock input/output
Input
P27 [/SCL]
SCK1
P22
SCK2
P72/ASCK
µPD78F0058Y only
SCL
STB
Output
P27/SCK0
Serial interface automatic transmit/receive strobe output
Input
P23/TxD1
BUSY
Input
Serial interface automatic transmit/receive busy input
Input
P24/RxD1
RxD0
Input
Asynchronous serial interface serial data input
Input
P70/SI2
RxD1
TxD0
P24/BUSY
Output
Asynchronous serial interface serial data output
Input
TxD1
P71/SO2
P23/STB
ASCK
Input
Asynchronous serial interface serial clock input
Input
P72/SCK2
TI00
Input
External count clock input to the 16-bit timer (TM0)
Input
P00/INTP0
TI01
Capture trigger signal input to the capture register (CR00)
P01/INTP1
TI1
External count clock input to the 8-bit timer (TM1)
P33
TI2
External count clock input to the 8-bit timer (TM2)
P34
TO0
Output
16-bit timer (TM0) output (also used for 14-bit PWM output)
Input
P30
TO1
8-bit timer (TM1) output
P31
TO2
8-bit timer (TM2) output
P32
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P35
BUZ
Output
Buzzer output
Input
P36
RTP0 to RTP7
Output
Real-time output port from which data is output in synchronization with a trigger
Input
P120 to P127
Lower address/data bus for expanding memory externally
Input
P40 to P47
AD0 to AD7
Remark [
16
I/O
]: µPD78F0058Y only.
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
4.2 Non-Port Pins (2/2)
Pin Name
Function
I/O
After
Reset
Alternate
Function
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
Strobe signal output for writing to external memory
WR
WAIT
Input
ASTB
Output
ANI0 to ANI7
Input
ANO0, ANO1
Output
P65
Wait insertion at external memory access
Input
P66
Strobe output that externally latches address information output to ports 4
and 5 to access external memory.
Input
P67
A/D converter analog input
Input
P10 to P17
D/A converter analog output
Input
P130, P131
AVREF0
Input
A/D converter reference voltage input (also used for analog power supply)
–
–
AVREF1
Input
D/A converter reference voltage input
–
–
A/D converter and D/A converter ground potential
Use at the same potential as VSS0.
–
–
AVSS
–
RESET
Input
System reset input
–
–
X1
Input
Connecting crystal resonator for main system clock oscillation
–
–
X2
–
–
–
XT1
Input
XT2
–
VDD0
–
VSS0
Connecting crystal resonator for subsystem clock oscillation
Input
P07
–
–
Port block positive power supply
–
–
–
Port block ground potential
–
–
VDD1
–
Positive power supply (except for port and analog blocks)
–
–
VSS1
–
Ground potential (except for port and analog blocks)
–
–
VPP
–
Setting flash memory programming mode.
Applying high voltage for program write/verify.
Connect directly to VSS0 or VSS1 in normal operation mode.
–
–
Data Sheet U12092EJ1V0DS00
17
µPD78F0058, 78F0058Y
4.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.
For the input/output circuit configuration of each type, see Figure 4-1.
Table 4-1. Input/Output Circuit Type of Each Pin (1/2)
Pin Name
Input/Output
Circuit Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-C
I/O
16
Input
11-D
I/O
P02/INTP2
Recommended Connection
Connect to VSS0.
Input : Independently connect to VSS0 via a resistor.
Output : Leave open.
P03/INTP3
P04/INTP4
P05/INTP5
P07/XT1
P10/ANI0 to P17/ANI7
P20/SI1
8-C
P21/SO1
5-H
P22/SCK1
8-C
P23/STB/TxD1
5-H
P24/BUSY/RxD1
8-C
P25/SI0/SB0 [/SDA0]
10-B
Connect to VDD0.
Input
: Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
P26/SO0/SB1 [/SDA1]
P27/SCK0 [/SCL]
P30/TO0
5-H
P31/TO1
P32/TO2
P33/TI1
8-C
P34/TI2
P35/PCL
5-H
P36/BUZ
P37
P40/AD0 to P47/AD7
5-N
Input : Independently connect to VDD0 via a resistor.
Output : Leave open.
P50/A8 to P57/A15
5-H
Input : Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
P60 to P63
13-K
Input : Independently connect to VDD0 via a resistor.
Output : Leave open.
P64/RD
5-H
Input : Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
P65/WR
P66/WAIT
P67/ASTB
Remark
18
[
]: µPD78F0058Y only.
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Table 4-1. Input/Output Circuit Type of Each Pin (2/2)
Pin Name
P70/SI2/RxD0
Input/Output
Circuit Type
I/O
8-C
I/O
P71/SO2/TxD0
5-H
P72/SCK2/ASCK
8-C
P120/RTP0 to
5-H
Recommended Connection
Input
: Independently connect to VDD0 or VSS0 via a resistor.
Output : Leave open.
P127/RTP7
P130/ANO0,
Input : Independently connect to VSS0 via a resistor.
Output : Leave open.
12-C
P131/ANO1
RESET
2
Input
XT2
16
–
AVREF0
–
–
Leave open.
Connect to VSS0.
AVREF1
Connect to VDD0.
AVSS
Connect to VSS0.
VPP
Connect directly to VSS0 or VSS1.
Data Sheet U12092EJ1V0DS00
19
µPD78F0058, 78F0058Y
Figure 4-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8-C
VDD0
Pullup
enable
P-ch
IN
VDD0
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristic
VDD0
Type 5-H
Pullup
enable
Output
disable
N-ch
VSS0
VDD0
Type 10-B
Pullup
enable
P-ch
P-ch
VDD0
Data
VDD0
Data
P-ch
P-ch
IN/OUT
Output
disable
IN/OUT
Open drain
Output disable
N-ch
VSS0
N-ch
VSS0
Input
enable
Type 5-N
Pullup
enable
Pullup
enable
P-ch
IN/OUT
N-ch
Output
disable
Comparator
VSS0
Input
enable
20
P-ch
P-ch
IN/OUT
Output
disable
P-ch
VDD0
Data
VDD0
Data
VDD0
Type 11-D
VDD0
Data Sheet U12092EJ1V0DS00
N-ch
P-ch
+
−
VSS0
N-ch
VSS0
VREF (Threshold voltage)
µPD78F0058, 78F0058Y
Figure 4-1. Pin Input/Output Circuits (2/2)
VDD0
Type 12-C
Pullup
enable
Type 16
Feedback
P-ch
cut-off
VDD0
Data
P-ch
P-ch
IN/OUT
Output
disable
Input
enable
N-ch
VSS0
P-ch
XT1
Analog output
voltage
N-ch
XT2
VSS0
Type 13-K
IN/OUT
Data
Output disable
N-ch
VSS0
VDD0
RD
P-ch
Middle-voltage input buffer
Data Sheet U12092EJ1V0DS00
21
µPD78F0058, 78F0058Y
5. MEMORY SPACE
Figure 5-1 shows the memory map of the µPD78F0058 and 78F0058Y.
Figure 5-1. Memory Map
FFFFH
Special function register (SFR)
256×8 bits
FF00H
FEFFH
General registers
32×8 bits
FEE0H
FEDFH
Internal high-speed RAM
1024×8 bits
EFFFH
FB00H
FAFFH
Data memory
space
FAE0H
FADFH
Program area
Use prohibited
Internal buffer RAM
32×8 bits
1000H
0FFFH
FAC0H
FABFH
CALLF entry area
Use prohibited
F800H
F7FFH
0800H
07FFH
Program area
Internal expansion RAM
1024×8 bits
0080H
007FH
F400H
F3FFH
Use prohibited Note
CALLT table area
F000H
EFFFH
Program memory
space
Flash memory
61440×8 bits
0000H
0040H
003FH
Vector table area
0000H
Note The area between F000H and F3FFH cannot be used when the flash memory size is 60 Kbytes. This area
can be used by setting the flash memory size to 56 Kbytes or less with the memory size switching register
(IMS).
22
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
6. FLASH MEMORY PROGRAMMING
The program memory provided in the µ PD78F0058 and 78F0058Y is flash memory.
Writing to a flash memory can be performed without removing the memory from the target system (on-board).
Writing is performed connecting the dedicated flash programmer (Flashpro III (part number : FL-PR3, PG-FP3)
to the host machine and the target system.
Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selection of Transmission Mode
Writing to a flash memory is performed using the Flashpro III with a serial transmission mode. One of the
transmission mode is selected from those in Table 6-1. The selection of the transmission mode is made by using
the format shown in Figure 6-1. Each transmission mode is selected by the number of V PP pulses shown in Table
6-1.
Table 6-1. List of Transmission Mode
Transmission Mode
3-wire serial I/O
Channels
3
Pin
P27/SCK0 [/SCL]
VPP Pulses
0
P26/SO0/SB1 [/SDA1]
P25/SI0/SB0 [/SDA0]
P22/SCK1
1
P21/SO1
P20/SI1
P72/SCK2/ASCK
2
P71/SO2/TxD0
P70/SI1/RxD0
UART
2
P71/SO2/TxD0
8
P70/SI2/RxD0
P23/TxD1
9
P24/RxD1
Pseudo 3-wire serial
I/ONote
1
P32/TO2 (serial clock input/output)
12
P31/TO1 (serial data output)
P30/TO0 (serial data input)
Note Serial transmission is performed by controlling the port using software.
Caution
Select a communication mode always using the number of VPP pulses shown in Table
6-1.
Remark
[
] : µ PD78F0058Y only.
Data Sheet U12092EJ1V0DS00
23
µPD78F0058, 78F0058Y
Figure 6-1. Format of Transmission Mode Selection
10 V
VPP
VDD
VSS
1
2
n
VDD
RESET
VSS
6.2 Function of Flash Memory Programming
Operations such as writing to a flash memory are performed by various command/data transmission and
reception operations according to the selected transmission mode. Table 6-2 shows major functions of flash
memory programming.
Table 6-2. Major Functions of Flash Memory Programming
Functions
Descriptions
Batch delete
Deletes the entire memory contents.
Batch blank check
Checks the deletion status of the entire memory.
Data write
Performs write to the flash memory based on the write start address and the number of
data to be written (number of bytes).
Batch verify
Compares the entire memory contents with the input data.
6.3 Connection of Flashpro III
The connection of the Flashpro III and the µ PD78F0058 and 78F0058Y differs according to the transmission
mode (3-wire serial I/O, UART, pseudo 3-wire). The connection for each transmission mode is shown in Figures
6-2 to 6-4.
Figure 6-2. Connection of Flashpro III for 3-wire Serial I/O Mode
µ PD78F0058, 78F0058Y
Flashpro III
VPPnNote
VDD
RESET
VPP
VDD0, VDD1
RESET
CLK
X1
SCK
SCK0, SCK1, SCK2
SO
SI
GND
SI0, SI1, SI2
SO0, SO1, SO2
VSS0, VSS1
Note n = 1, 2
24
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Figure 6-3. Connection of Flashpro III for UART Mode
µ PD78F0058, 78F0058Y
Flashpro III
VPPnNote
VDD
RESET
CLK
VPP
VDD0, VDD1
RESET
X1
SO
RxD0, RxD1
SI
TxD0, TxD1
GND
VSS0, VSS1
Note n = 1, 2
Figure 6-4. Connection of Flashpro III for Pseudo 3-wire Serial I/O Mode
µ PD78F0058, 78F0058Y
Flashpro III
VPPnNote
VDD
RESET
VPP
VDD0, VDD1
RESET
CLK
X1
SCK
P32 (serial clock)
SO
P30 (serial input)
SI
P31(serial output)
GND
VSS0, VSS1
Note n = 1, 2
Data Sheet U12092EJ1V0DS00
25
µPD78F0058, 78F0058Y
6.4 Example of Settings for Flashpro III (PG-FP3)
Make the following setting when writing to flash memory using Flashpro III (PG-FP3)
<1> Load the parameter file.
<2> Select serial mode and serial clock using the type command.
<3> An example of the settings for the PG-FP3 is shown below.
Table 6-3. Example of Settings for PG-FP3
Communication Mode
3-wire serial I/O
Example of Setting for PG-FP3
COMM PORT
SIO-ch0/1/2
CPU CLK
On Target Board
Number of VPP PulsesNote 1
0/1/2
In Flashpro
UART
Pseudo 3-wire
On Target Board
4.1943 MHz
SIO CLK
1.0 MHz
In Flashpro
4.0 MHz
SIO CLK
1.0 MHz
COMM PORT
UART-ch0/1
CPU CLK
On Target Board
On Target Board
4.1943 MHz
UART BPS
9600 bpsNote 2
COMM PORT
PortA
CPU CLK
On Target Board
8/9
12
In Flashpro
On Target Board
4.1943 MHz
SIO CLK
1.0 kHz
In Flashpro
4.0 MHz
SIO CLK
1.0 kHz
Notes 1. The number of VPP pulses supplied from Flashpro III when serial communication is initialized. The pins
to be used for communication are determined according to the number of these pulses.
2. Select one of 9600 bps, 19200 bps, 38400 bps, or 768000 bps.
Remark COMM PORT : Selection of serial port
SIO CLK
: Selection of serial clock frequency
CPU CLK
26
: Selection of source of CPU clock to be input
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
Ratings
VDD
–0.3 to +6.5
V
VPP
–0.3 to +10.5
V
AV REF0
–0.3 to VDD + 0.3
V
AV REF1
–0.3 to VDD + 0.3
V
AV SS
Input voltage
Output voltage
Unit
VI1
P00-P05, P07, P10-P17, P20-P27, P30-P37, P40-P47,
P50-P57, P64-P67, P70-P72, P120-P127, P130, P131,
X1, X2, XT2, RESET
VI2
P60-P63
N-ch open drain
VO
V
V
–0.3 to +16
V
–0.3 to VDD + 0.3
V
AVSS – 0.3 to AVREF0 + 0.3
V
Analog input voltage V AN
P10-P17
Output
current, high
Per pin
–10
mA
Total for P01-P05, P30-P37, P56, P57, P60-P67,
–15
mA
–15
mA
Peak value
30
mA
rms value
15
mA
Peak value
100
mA
rms value
70
mA
100
mA
rms value
70
mA
Total for P10-P17, P20-P27,
P40-P47, P70-P72, P130, P131
Peak value
50
mA
rms value
20
mA
Total for P01-P05, P30-P37,
P64-P67, P120-P127
Peak value
50
mA
rms value
20
mA
–40 to +85
°C
10 to 40
°C
–65 to +125
°C
IOH
Analog input pin
–0.3 to +0.3
–0.3 to VDD + 0.3
P120-P127
Total for P10-P17, P20-P27, P40-P47, P50-P55,
P70-P72, P130, P131
IOLNote
Output
current, low
Per pin
Total for P50-P55
Total for P56, P57, P60-P63
Operating ambient
TA
temperature
Storage
temperature
Note
Peak value
During normal operation
During flash memory programming
T stg
The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Data Sheet U12092EJ1V0DS00
27
µPD78F0058, 78F0058Y
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Resonator
Ceramic
resonator
Recommended Circuit
X2
C2
Crystal
resonator
X2
C2
External
clock
X1 VPP
C1
X1 VPP
C1
X2
µ PD74HCU04
X1
Parameter
Conditions
Oscillation
frequency (fX)Note 1
VDD = Oscillation
voltage range
Oscillation
stabilization timeNote 2
After VDD reaches
oscillation voltage range
MIN.
TYP.
1.0
1.0
Oscillation
frequency (fX)Note 1
Oscillation
stabilization timeNote 2
MIN.
VDD = 4.5 to 5.5 V
MAX.
Unit
5.0
MHz
4
ms
5.0
MHz
10
ms
30
X1 input
frequency (fX)Note 1
1.0
5.0
MHz
X1 input
high-/low-level width
(tXH , tXL)
85
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
28
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
VPP XT2
XT1
R2
C4
External
clock
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
C3
XT1
XT2
µ PD74HCU04
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
VDD = 4.5 to 5.5 V
10
XT1 input
frequency (fXT)Note 1
32
100
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark
For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
capacitance
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
15
pF
I/O
capacitance
CIO
f = 1 MHz
Unmeasured pins returned
to 0 V.
P01-P05, P10-P17,
P20-P27, P30-P37,
P40-P47, P50-P57,
P64-P67, P70-P72,
P120-P127, P130, P131
15
pF
P60-P63
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12092EJ1V0DS00
29
µPD78F0058, 78F0058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Input voltage,
high
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
P10-P17, P21, P23, P30-P32,
P35-P37, P40-P47, P50-P57,
P64-P67, P71, P120-P127,
P130, P131
VDD = 2.7 to 5.5 V
0.7VDD
VDD
V
VIH2
P00-P05, P20, P22, P24-P27,
VDD = 2.7 to 5.5 V
0.8VDD
VDD
V
VDD = 2.7 to 5.5 V
0.7VDD
15
V
P33, P34, P70, P72, RESET
VIH3
P60-P63
(N-ch open drain)
Input voltage,
low
VIH4
X1, X2
VDD = 2.7 to 5.5 V
VDD – 0.5
VDD
V
VIH5
XT1/P07, XT2
4.5 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9VDD
VDD
V
VIL1
P10-P17, P21, P23, P30-P32,
P35-P37, P40-P47, P50-P57,
P64-P67, P71, P120-P127,
P130, P131
VDD = 2.7 to 5.5 V
0
0.3VDD
V
VIL2
P00-P05, P20, P22, P24-P27,
VDD = 2.7 to 5.5 V
0
0.2VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P33, P34, P70, P72, RESET
VIL3
P60-P63
2.7 V ≤ VDD < 4.5 V
0
0.2VDD
V
VIL4
X1, X2
VDD = 2.7 to 5.5 V
0
0.4
V
VIL5
XT1/P07, XT2
4.5 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
0
0.1VDD
V
VOH
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD – 1.0
V
IOH = –100 µA
VDD – 0.5
V
2.7 V ≤ VDD < 4.5 V
Output voltage,
high
Output voltage,
low
VOL1
VOL2
P50-P57, P60-P63
VDD = 4.5 to 5.5 V,
IOL = 15 mA
P01-P05, P10-P17, P20-P27,
P30-P37, P40-P47, P64-P67,
P70-P72, P120-P127, P130, P131
SB0, SB1, SCK0
0.4
2.0
V
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
0.4
V
VDD = 4.5 to 5.5 V,
0.2VDD
V
0.5
V
open drain,
pulled-up (R = 1 kΩ)
VOL3
Remark
30
IOL = 400 µA
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
ILIH2
Input leakage
current, low
MAX.
Unit
P00-P05, P10-P17, P20-P27,
P30-P37, P40-P47, P50-P57,
P60-P67, P70-P72, P120-P127,
P130, P131, RESET
MIN.
TYP.
3
µA
X1, X2, XT1/P07, XT2
20
µA
ILIH3
VIN = 15 V
P60 to P63
80
µA
ILIL1
VIN = 0 V
P00-P05, P10-P17, P20-P27,
P30-P37, P40-P47, P50-P57,
P64-P67, P70-P72, P120-P127,
P130, P131, RESET
–3
µA
X1, X2, XT1/P07, XT2
–20
µA
–3 Note 1
µA
ILIL2
ILIL3
P60-P63
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Software pull-up
R
VIN = 0 V, P01-P05, P10-P17, P20-P27, P30-P37,
P40-P47, P50-P57, P64-P67, P70-P72, P120-P127,
P130, P131
90
kΩ
resistorNote 2
15
30
Notes 1. A low-level input leakage current of –200 µA (MAX.) flows only for 1.5 clocks (without wait) after a read
instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5clock interval, a –3 µA (MAX.) current flows.
2. Software pull-up resistor can only be used within the range VDD = 2.7 to 5.5 V.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U12092EJ1V0DS00
31
µPD78F0058, 78F0058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Power supply
currentNote 5
Symbol
IDD1Note 5
IDD2
Conditions
TYP.
MAX.
±10%Note 1
MIN.
6.2
12.5
mA
VDD = 3.0 V ±10%Note 2
1.3
3.1
mA
VDD = 5.0 V ±10%Note 1
13.1
25.7
mA
±10%Note 2
2.1
4.9
mA
5.6
mA
2.8
mA
2.9
mA
1.1
mA
8.4
mA
3.1
mA
4.5
mA
0.6
1.5
mA
5.0 MHz crystal oscillation
operating mode
(fXX = 2.5 MHz)Note 3
5.0 MHz crystal oscillation
operating mode
(fXX = 5.0 MHz)Note 4
VDD = 5.0 V
5.0 MHz crystal oscillation
HALT mode
(fXX = 2.5 MHz)Note 3
VDD = 5.0 V ±10%
VDD = 3.0 V
Peripheral functions
operating
Peripheral functions
not operating
1.0
Unit
VDD = 3.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
5.0 MHz crystal oscillation
HALT mode
(fXX = 5.0 MHz)Note 4
0.44
VDD = 5.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
1.3
VDD = 3.0 V ±10%
Peripheral functions
operating
Peripheral functions
not operating
IDD3Note 5 32.768 kHz crystal oscillation
operating modeNote 6
VDD = 5.0 V ±10%
110
220
µA
VDD = 3.0 V ±10%
86
172
µA
IDD4Note 5 32.768 kHz crystal oscillation
HALT modeNote 6
VDD = 5.0 V ±10%
22.5
45
µA
VDD = 3.0 V ±10%
3.2
6.4
µA
VDD = 5.0 V ±10%
1.0
30
µA
VDD = 3.0 V ±10%
0.5
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
IDD5Note 5
XT1 = VDD
STOP mode
When feedback resistor is used
IDD6Note 5 XT1 = VDD
STOP mode
When feedback resistor is not
used
Notes 1. High-speed mode operation (when the processor clock control register (PCC) is set to 00H).
2. Low-speed mode operation (when PCC is set to 04H).
3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H)
4. Operation with main system clock fXX = fX (when OSMS is set to 01H)
5. Refers to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A
converter, and on-chip pull-up resistor is not included.
6. When the main system clock operation is stopped.
32
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Conditions
Operating with main system
clock (fXX = 2.5
execution time)
MIN.
Unit
0.8
TYP.
64
µs
3.5 V ≤ VDD ≤ 5.5 V
0.4
32
µs
32
µs
125
µs
MHz)Note 1
Operating with main system
clock (fXX = 5.0
MAX.
VDD = 2.7 to 5.5 V
MHz)Note 2
2.7 V ≤ VDD < 3.5 V
0.8
40Note 3
Operating with subsystem clock
122
2/fsam +
0.1Note 4
µs
2/fsam +
0.2Note 4
µs
tTIH00
3.5 V ≤ VDD ≤ 5.5 V
low-level width
tTIL00
2.7 V ≤ VDD < 3.5 V
TI01 input high-/
tTIH01
VDD = 2.7 to 5.5 V
10
low-level width
tTIL01
TI1, TI2 input
fTI1
VDD = 4.5 to 5.5 V
0
4
MHz
0
275
kHz
TI1, TI2 input
tTIH1
VDD = 4.5 to 5.5 V
100
ns
high-/low-level
tTIL1
1.8
µs
TI00 input high-/
frequency
µs
width
Interrupt request
input high-/
tINTH
tINTL
low-level width
RESET lowlevel width
INTP0
INTP1-INTP5, P40-P47
tRSL
3.5 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1Note 4
µs
2.7 V ≤ VDD < 3.5 V 2/fsam +
µs
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0.2Note 4
10
µs
10
µs
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is set to 00H)
2. Operation with main system clock fXX = fX (when OSMS is set to 01H)
3. Value when external clock is used. When a crystal resonator is used, it is 114 µs (MIN.)
4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling
clock select register (SCS) (when N= 0 to 4).
Data Sheet U12092EJ1V0DS00
33
µPD78F0058, 78F0058Y
TCY vs. VDD (@fXX = fX/2 main system clock operation)
TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
Guaranteed
operation
range
Cycle time TCY [µs]
Cycle time TCY [µs]
10
2.0
1.0
0.5
0.4
Guaranteed
operation
range
2.0
1.0
0.5
0.4
0
0
1
2
3
4
5
6
Supply voltage VDD [V]
34
1
2
3
4
5
Supply voltage VDD [V]
Data Sheet U12092EJ1V0DS00
6
µPD78F0058, 78F0058Y
(2) Read/write operation
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.85tCY – 50
ns
Address setup time
tADS
0.85tCY – 50
ns
Address hold time
tADH
50
ns
Data input time from address
tADD1
(2.85 + 2n)tCY – 80
ns
tADD2
(4 + 2n)tCY – 100
ns
tRDD1
(2 + 2n)tCY – 100
ns
tRDD2
(2.85 + 2n)tCY – 100
ns
Data input time from RD↓
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(2 + 2n)tCY – 60
ns
tRDL2
(2.85 + 2n)tCY – 60
ns
WAIT↓ input time from RD↓
tRDWT1
0.85tCY – 50
ns
tRDWT2
2tCY – 60
ns
WAIT↓ input time from WR↓
tWRWT
2tCY – 60
ns
WAIT low-level width
tWTL
(1.15 + 2n)tCY
(2 + 2n)tCY
ns
Write data setup time
tWDS
(2.85 + 2n)tCY – 100
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.85 + 2n)tCY – 60
ns
RD↓ delay time from ASTB↓
tASTRD
25
ns
WR↓ delay time from ASTB↓
tASTWR
0.85tCY + 20
ns
ASTB↑ delay time from
RD↑ at external fetch
tRDAST
0.85tCY – 10
1.15tCY + 20
ns
Address hold time from
tRDADH
0.85tCY – 50
1.15tCY + 50
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
0
50
ns
Address hold time from WR↑
tWRADH
0.85tCY
1.15tCY + 40
ns
RD↑ delay time from WAIT↑
tWTRD
1.15tCY + 40
3.15tCY + 40
ns
WR↑ delay time from WAIT↑
tWTWR
1.15tCY + 30
3.15tCY + 30
ns
RD↑ at external fetch
Remarks
1.
MCS: Bit 0 of the oscillation mode select register (OSMS)
2.
3.
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
tCY = TCY/4
4.
n indicates the number of waits.
Data Sheet U12092EJ1V0DS00
ns
35
µPD78F0058, 78F0058Y
(b) When MCS = 0 or PCC2 to PCC0 ≠ 000B (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
tCY – 80
ns
Address setup time
tADS
tCY – 80
ns
Address hold time
tADH
0.4tCY – 10
Data input time from address
tADD1
(3 + 2n)tCY – 160
ns
tADD2
(4 + 2n)tCY – 200
ns
tRDD1
(1.4 + 2n)tCY – 70
ns
tRDD2
(2.4 + 2n)tCY – 70
ns
Data input time from RD↓
Read data hold time
RD low-level width
WAIT↓ input time from RD↓
ns
tRDH
0
ns
tRDL1
(1.4 + 2n)tCY – 20
ns
tRDL2
(2.4 + 2n)tCY – 20
ns
tRDWT1
tCY – 100
ns
tRDWT2
2tCY – 100
ns
2tCY – 100
ns
(2 + 2n)tCY
ns
WAIT↓ input time from WR↓
tWRWT
WAIT low-level width
tWTL
(1 + 2n)tCY
Write data setup time
tWDS
(2.4 + 2n)tCY – 60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL
(2.4 + 2n)tCY – 20
ns
RD↓ delay time from ASTB↓
tASTRD
0.4tCY – 30
ns
WR↓ delay time from ASTB↓
tASTWR
1.4tCY – 30
ns
ASTB↑ delay time from RD↑
at external fetch
tRDAST
tCY – 10
tCY + 20
ns
Address hold time from
RD↑ at external fetch
tRDADH
tCY – 50
tCY + 50
ns
Write data output time from
RD↑
tRDWD
0.4tCY – 20
Write data output time from
WR↓
tWRWD
0
60
ns
Address hold time from WR↑
tWRADH
tCY
tCY + 60
ns
RD↑ delay time from WAIT↑
tWTRD
0.6tCY + 180
2.6tCY + 180
ns
WR↑ delay time from WAIT↑
tWTWR
0.6tCY + 120
2.6tCY + 120
ns
Remarks
36
1.
MCS: Bit 0 of the oscillation mode select register (OSMS)
2.
3.
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
tCY = TCY/4
4.
n indicates the number of waits.
Data Sheet U12092EJ1V0DS00
ns
µPD78F0058, 78F0058Y
(3) Serial interface (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level
Symbol
tKCY1
tKH1, tKL1
Conditions
tSIK1
SI0 hold time
(from SCK0↑)
tKSI1
SO0 output delay time
tKSO1
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
VDD = 4.5 to 5.5 V
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
400
ns
width
SI0 setup time
(to SCK0↑)
MIN.
C = 100 pFNote
300
ns
MAX.
Unit
from SCK0↓
Note C is the load capacitance of the SCK0 and SO0 output lines.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
2.7 V ≤ VDD ≤ 5.5 V
100
ns
400
ns
SCK0 cycle time
tKCY2
SCK0 high-/low-level
width
tKH2, tKL2
SI0 setup time
(to SCK0↑)
tSIK2
SI0 hold time
(from SCK0↑)
tKSI2
SO0 output delay time
from SCK0↓
tKSO2
C = 100 pFNote
300
ns
SCK0 rise/fall time
tR2, tF2
When using external device
160
ns
1,000
ns
expansion function
When not using external device
expansion function
Note C is the load capacitance of the SO0 output line.
Data Sheet U12092EJ1V0DS00
37
µPD78F0058, 78F0058Y
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
Conditions
C = 100
MIN.
2.7 V ≤ VDD ≤ 5.5 V
R = 1 kΩ,
pFNote
TYP.
MAX.
Unit
1,600
ns
VDD = 2.7 to 5.5 V
tKCY3/2 – 160
ns
tKCY3/2 – 50
ns
SCK0 high-level width
tKH3
SCK0 low-level width
tKL3
VDD = 4.5 to 5.5 V
tKCY3/2 – 100
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK3
4.5 V ≤ VDD ≤ 5.5 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI3
600
ns
SB0, SB1 output delay
time from SCK0↓
tKSO3
0
300
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY4
2.7 V ≤ VDD ≤ 5.5 V
1,600
ns
SCK0 high-level width
tKH4
2.7 V ≤ VDD ≤ 5.5 V
650
ns
SCK0 low-level width
tKL4
2.7 V ≤ VDD ≤ 5.5 V
800
ns
SB0, SB1 setup time
(to SCK0↑)
tSIK4
VDD = 2.7 to 5.5 V
100
ns
SB0, SB1 hold time
(from SCK0↑)
tKSI4
tKCY4/2
ns
SB0, SB1 output delay
time from SCK0↓
tKSO4
SCK0 rise/fall time
R = 1 kΩ,
C = 100
tR4, tF4
pFNote
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.7 V ≤ VDD < 4.5 V
0
500
ns
160
ns
1,000
ns
When using external device
expansion function
When not using external device
expansion function
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
38
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
(v) SBI mode (SCK0... Internal clock output) (µPD78F0058 only)
Parameter
SCK0 cycle time
Symbol
tKCY5
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
3,200
ns
4.5 V ≤ VDD ≤ 5.5 V
tKCY5/2 – 50
ns
2.7 V ≤ VDD < 4.5 V
tKCY5/2 – 150
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
SCK0 high-/low-level
width
tKH5, tKL5
SB0, SB1 setup time
(to SCK0↑)
tSIK5
SB0, SB1 hold time
(from SCK0↑)
tKSI5
SB0, SB1 output delay
time from SCK0↓
tKSO5
SB0, SB1↓ from SCK0↑
tKSB
tKCY5
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY5
ns
SB0, SB1 high-level width tSBH
tKCY5
ns
SB0, SB1 low-level width
tKCY5
ns
2.7 V ≤ VDD < 4.5 V
R = 1 kΩ,
C = 100 pFNote
300
ns
tKCY5/2
ns
VDD = 4.5 to 5.5 V
tSBL
0
250
ns
0
1,000
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) SBI mode (SCK0... External clock input) (µPD78F0058 only)
Parameter
Symbol
SCK0 cycle time
tKCY6
SCK0 high-/low-level
width
tKH6, tKL6
SB0, SB1 setup time
(to SCK0↑)
tSIK6
SB0, SB1 hold time
(from SCK0↑)
tKSI6
SB0, SB1 output delay
time from SCK0↓
tKSO6
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
3,200
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
300
ns
tKCY6/2
ns
R = 1 kΩ,
C = 100 pFNote
VDD = 4.5 to 5.5 V
0
300
ns
0
1,000
ns
SB0, SB1↓ from SCK0↑ tKSB
tKCY6
ns
SCK0↓ from SB0, SB1↓ tSBK
tKCY6
ns
SB0, SB1 high-level width tSBH
tKCY6
ns
SB0, SB1 low-level width
tSBL
tKCY6
ns
SCK0 rise/fall time
tR6, tF6
When using external device
expansion function
When not using external device
expansion function
160
ns
1,000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
Data Sheet U12092EJ1V0DS00
39
µPD78F0058, 78F0058Y
(vii) I2C bus mode (SCL... Internal clock output) (µPD78F0058Y only)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
10
µs
C = 100 pFNote 2.7 V ≤ VDD < 5.5 V
tKCY7 – 160
µs
4.5 V ≤ VDD < 5.5 V
tKCY7 – 50
ns
2.7 V ≤ VDD < 4.5 V
tKCY7 – 100
ns
2.7 V ≤ VDD < 5.5 V
200
ns
0
ns
SCL cycle time
tKCY7
R = 1 kΩ,
SCL high-level width
tKH7
SCL low-level width
tKL7
SDA0, SDA1 setup time
(to SCL↑)
tSIK7
SDA0, SDA1 hold time
tKSI7
2.7 V ≤ VDD < 5.5 V
(from SCL↓)
4.5 V ≤ VDD < 5.5 V
SDA0, SDA1 output delay tKSO7
time from SCL↓
0
0
300
500
ns
ns
SDA0, SDA1↓ from SCL↑ tKSB
or SDA0, SDA1↑ from SCL↑
200
ns
SCL↓ from SDA0, SDA1↓ tSBK
400
ns
SDA0, SDA1 high-level width tSBH
500
ns
Note
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines.
(viii) I2C bus mode (SCL... External clock input) (µPD78F0058Y only)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCL cycle time
tKCY8
1
µs
SCL high-level width
tKH8
400
ns
SDA0, SDA1 setup time
(to SCL↑)
tSIK8
200
ns
SDA0, SDA1 hold time
tKSI8
0
ns
(from SCL↓)
SDA0, SDA1 output delay tKSO8
time from SCL↓
4.5 V ≤ VDD < 5.5 V
R = 1 kΩ,
C = 100 pFNote
SDA0, SDA1↓ from SCL↑ tKSB
0
300
ns
0
500
ns
200
ns
SCL↓ from SDA0, SDA1↓ tSBK
400
ns
SDA0, SDA1 high-level width tSBH
500
ns
or SDA0, SDA1↑ from SCL↑
Note
40
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1...Internal clock output)
Parameter
Symbol
SCK1 cycle time
tKCY9
SCK1 high-/low-level width
tKH9, tKL9
Conditions
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
tSIK9
TYP.
MAX.
Unit
800
ns
1,600
ns
tKCY9/2 – 50
ns
tKCY9/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
400
ns
VDD = 4.5 to 5.5 V
tKSI9
SO1 output delay time from SCK1↓ tKSO9
MIN.
C = 100
pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1...External clock input)
Parameter
Symbol
SCK1 cycle time
tKCY10
SCK1 high-/low-level width
tKH10, tKL10
SI1 setup time (to SCK1↑)
tSIK10
SI1 hold time (from SCK1↑)
tKIS10
Conditions
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
VDD = 2.7 to 5.5 V
100
ns
400
ns
pFNote
SO1 output delay time from SCK1↓ tKSO10
C = 100
SCK1 rise/fall time
When using external device
expansion function
tR10, tF10
MIN.
VDD = 2.7 to 5.5 V
When not using external device
expansion function
300
ns
160
ns
1,000
ns
Note C is the load capacitance of the SO1 output line.
Data Sheet U12092EJ1V0DS00
41
µPD78F0058, 78F0058Y
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY11
Conditions
1,600
ns
tKCY11/2 – 50
ns
tSIK11
tKCY11/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
tKSI11
tSBD
Strobe signal high-level width
tSBW
Busy signal setup time
(to busy signal detection timing)
tBYS
Busy signal hold time
(from busy signal detection timing)
tBYH
SCK1↓ from busy inactive
tSPS
Unit
2.7 V ≤ VDD < 4.5 V
SI1 setup time (to SCK1↑)
STB↑ from SCK1↑
MAX.
ns
tKH11, tKL11 VDD = 4.5 to 5.5 V
SO1 output delay time from SCK1↓ tKSO11
TYP.
800
SCK1 high-/low-level width
SI1 hold time (from SCK1↑)
MIN.
4.5 V ≤ VDD ≤ 5.5 V
400
ns
C = 100 pFNote
2.7 V ≤ VDD < 5.5 V
300
ns
tKCY11/2 – 100
tKCY11/2 + 100
ns
tKCY11 – 30
tKCY11 + 30
ns
100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2tKCY11
ns
Note C is the load capacitance of the SCK1 and SO1 output lines.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter
SCK1 cycle time
Symbol
tKCY12
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
tKH12,
tKL12
4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
SI1 setup time (to SCK1↑)
tSIK12
VDD = 2.7 to 5.5 V
100
ns
SI1 hold time (from SCK1↑)
tKSI12
400
ns
SCK1 high-/low-level width
SO1 output delay time from SCK1↓ tKSO12
C = 100 pFNote
SCK1 rise/fall time
When using external device
expansion function
tR12, tF12
VDD = 2.7 to 5.5 V
When not using external device
expansion function
Note C is the load capacitance of the SO1 output line.
42
Data Sheet U12092EJ1V0DS00
300
ns
160
ns
1,000
ns
µPD78F0058, 78F0058Y
(c) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2...Internal clock output)
Parameter
SCK2 cycle time
SCK2 high-/low-level width
SI2 setup time (to SCK2↑)
SI2 hold time (from SCK2↑)
Symbol
tKCY13
Conditions
TYP.
MAX.
Unit
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
tKH13,
tKL13
VDD = 4.5 to 5.5 V
tSIK13
tKCY13/2 – 50
ns
tKCY13/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
tKSI13
SO2 output delay time from SCK2↓ tKSO13
MIN.
4.5 V ≤ VDD ≤ 5.5 V
400
ns
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SO2 output line.
(ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter
SCK2 cycle time
Symbol
tKCY14
Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
400
ns
SCK2 high-/low-level width
tKH14,
tKL14
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
800
ns
SI2 setup time (to SCK2↑)
tSIK14
VDD = 2.7 to 5.5 V
100
ns
SI2 hold time (from SCK2↑)
tKSI14
400
ns
SO2 output delay time from SCK2↓ tKSO14
C = 100
SCK2 rise/fall time
tR14,
tF14
pFNote
VDD = 2.7 to 5.5 V
300
ns
Other than below
160
ns
VDD = 4.5 to 5.5 V
1
µs
When not using external device
expansion function
Note C is the load capacitance of the SO2 output line.
Data Sheet U12092EJ1V0DS00
43
µPD78F0058, 78F0058Y
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
78,125
bps
2.7 V ≤ VDD < 4.5 V
39,063
bps
MAX.
Unit
(iv) UART mode (External clock input)
Parameter
ASCK cycle time
ASCK high-/low-level width
Symbol
tKCY15
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1,600
ns
tKH15, tKL15 4.5 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.5 V
800
ns
Transfer rate
ASCK rise/fall time
Conditions
tR15, tF15
4.5 V ≤ VDD ≤ 5.5 V
39,063
bps
2.7 V ≤ VDD < 4.5 V
19,531
bps
VDD = 4.5 to 5.5 V,
1,000
ns
160
ns
when not using external device
expansion function.
44
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of
measurement
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 input
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
Data Sheet U12092EJ1V0DS00
45
µPD78F0058, 78F0058Y
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP5
RESET Input Timing
tRSL
RESET
46
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
Lower
8-bit
address
AD0 to AD7
Hi-Z
Operation
code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tRDL1
tASTRD
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
Lower
8-bit
address
AD0 to AD7
Hi-Z
Operation
code
tRDADH
tRDD1
tADS
tASTH
tADH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
tWTL
Data Sheet U12092EJ1V0DS00
tWTRD
47
µPD78F0058, 78F0058Y
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
Lower
8-bit
address
AD0 to AD7
Hi-Z
Hi-Z
Read data
Hi-Z
Write data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDH
tWDS
tWRADH
tWRWD
WR
tASTWR
tWRL
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
Lower
8-bit
address
AD0 to AD7
Hi-Z
Hi-Z
Read data
Hi-Z
Write data
tRDD2
tADS
tADH
tRDH
tASTH
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTRD
tWTL
48
Data Sheet U12092EJ1V0DS00
tWRWT
tWTL
tWTWR
µPD78F0058, 78F0058Y
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0 to SCK2
tSIKm
SI0 to SI2
tKSIm
Input data
tKSOm
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14
n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4
tKH3, 4
tF4
tR4
SCK0
tSIK3, 4
tKSI3, 4
tKSO3, 4
SB0, SB1
Data Sheet U12092EJ1V0DS00
49
µPD78F0058, 78F0058Y
SBI mode (bus release signal transfer):
tKCY5, 6
tKL5, 6
tKH5, 6
tF6
tR6
SCK0
tKSB
tSBL
tSBH
tSBK
tSIK5, 6
tKSI5, 6
SB0, SB1
tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6
tR6
tKH5, 6
tF6
SCK0
tSIK5, 6
tSBK
tKSB
tKSI5, 6
SB0, SB1
tKSO5, 6
I2C bus mode :
tKCYm
SCL
tKLm
tKSIm
tSIKm
tKHm
tKSOm
SDA0,
SDA1
tSBH
tSIKm
m = 7, 8
50
Data Sheet U12092EJ1V0DS00
tKSB
tKSB
tSBK
µPD78F0058, 78F0058Y
3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
SI1
D2
D1
D1
D0
D7
D0
D7
tKSI11, 12
tKH11, 12
tF12
tSIK11, 12
tKSO11, 12
SCK1
tR12
tKL11, 12
tSBD
tSBW
tKCY11, 12
STB
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note
10 + nNote
tBYS
tBYH
1
tSPS
BUSY
(Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
t KCY15
t KL15
t KH15
tR15
tF15
ASCK
Data Sheet U12092EJ1V0DS00
51
µPD78F0058, 78F0058Y
A/D Converter Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
Resolution
Overall
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±1.0
%
2.7 V ≤ AVREF0 < 4.5 V
errorNote 1
4.5 V ≤ AVREF0 < 5.5 V
Conversion time
TCONV
Analog input voltage
VIAN
Reference voltage
AVREF0
AVREF0 current
IREF0
2.7 V ≤ AVREF0 < 5.5 V
When A/D converter is
±0.6
%
16
100
µs
AVSS
AVREF0
V
2.7
VDD
V
500
1,500
µA
0
3
µA
operatingNote 2
When A/D converter is not operatingNote 3
Notes 1. Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value.
2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1.
3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
D/A Converter Characteristics (TA = –40 to +85°C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
Overall error
8
bit
R = 2 MΩNote 1
±1.2
%
MΩNote 1
±0.8
%
±0.6
%
R=4
R = 10
Settling time
MΩNote 1
C = 30 pF
Output resistance
RO
Analog reference voltage
AVREF1
AVREF1 current
IREF1
Resistance between AVREF1 and AVSS RAIREF1
Note 1
15
Note 2
8
1.8
Note 2
DACS0, DACS1 = 55HNote 2
4
8
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1
52
Data Sheet U12092EJ1V0DS00
µs
kΩ
VDD
V
2.5
mA
kΩ
µPD78F0058, 78F0058Y
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
wait time
Note
tWAIT
Conditions
MIN.
TYP.
1.8
VDDDR = 1.8 V
Subsystem clock stop and feed-back resistor
disconnected
0.1
MAX.
Unit
5.5
V
10
µA
µs
0
17
Release by RESET
2 /fX
ms
Release by interrupt request
Note
ms
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time select register (OSTS).
Remark
fXX: Main system clock frequency (fX or fX/2)
fX: Main system clock oscillation frequency
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
Data Sheet U12092EJ1V0DS00
53
µPD78F0058, 78F0058Y
Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, TA = 10 to 40°C)
(1) Write/delete characteristics
Parameter
Write current (VDD pin)Note 1
Write current (VPP pin)Note 1
Delete current (VDD pin)Note 1
Symbol
tDDW
IPPW
IDDE
Delete current (VPP pin)Note 1
IPPE
Unit delete time
tER
Total delete time
tERA
Conditions
When VPP = VPP1
When VPP = VPP1
When VPP = VPP1
MAX.
Unit
5.0 MHz crystal oscillation
operation mode
(fXX = 2.5 MHz)Note 2
15.5
mA
5.0 MHz crystal oscillation
operation mode
(fXX = 5.0 MHz)Note 3
28.7
mA
5.0 MHz crystal oscillation
operation mode
(fXX = 2.5 MHz)Note 2
19.5
mA
5.0 MHz crystal oscillation
operation mode
(fXX = 5.0 MHz)Note 3
32.7
mA
5.0 MHz crystal oscillation
operation mode
(fXX = 2.5 MHz)Note 2
15.5
mA
5.0 MHz crystal oscillation
operation mode
(fXX = 5.0 MHz)Note 3
28.7
mA
TYP.
100
mA
1
s
20
s
When VPP = VPP1
0.5
Number of overwrite
CWRT
Delete and write are counted as one cycle
VPP power supply voltage
VPP0
In normal mode
VPP1
At flash memory programming
Notes 1.
MIN.
1
0
9.7
10.0
20
times
0.2 VDD
V
10.3
V
1. AVREF current and Port current (current flowing to internal pull-up resistor) are not included.
2. When main system clock is operating at fXX = fXX/2 (when oscillation mode selection resistor (OSMS)
is set to 00H).
3. When main system clock is operating at fXX = fXX (when OSMS is set to 01H).
2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VPP setup time
tPSRON
VPP high voltage
1.0
µs
VPP↑ setup time from VDD↑
tDRPSR
VPP high voltage
1.0
µs
RESET↑ setup time from VPP↑
tPSRRF
VPP high voltage
1.0
µs
VPP count start time from RESET↑
tRFCF
1.0
µs
Count execution time
tCOUNT
VPP counter high-level width
tCH
8.0
µs
VPP counter low-level width
tCL
8.0
µs
VPP counter noise elimination width
tNFW
54
2.0
40
Data Sheet U12092EJ1V0DS00
ms
ns
µPD78F0058, 78F0058Y
Flash Write Mode Setting Timing
VDD
VDD
0V
tDRPSR
tRFCF
tCH
VPPH
VPP
VPP
tCL
VPPL
tPSRON tPSRRF
tCOUNT
VDD
RESET (input)
0V
Data Sheet U12092EJ1V0DS00
55
µPD78F0058, 78F0058Y
8.
PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
17.20±0.20
B
14.00±0.20
C
14.00±0.20
D
17.20±0.20
F
0.825
G
0.825
H
I
0.32±0.06
0.13
J
0.65 (T.P.)
K
1.60±0.20
L
0.80±0.20
M
0.17 +0.03
−0.07
N
P
0.10
1.40±0.10
Q
0.125±0.075
R
3° +7°
−3°
S
1.70 MAX.
P80GC-65-8BT-1
56
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
Q
R
21
80
1
20
F
G
H
I
J
M
K
P
M
N
S
L
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
S
ITEM
MILLIMETERS
A
14.00±0.20
B
12.00±0.20
C
12.00±0.20
D
F
14.00±0.20
1.25
G
1.25
H
0.22 +0.05
–0.04
I
0.10
J
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.145 +0.055
–0.045
N
0.10
P
1.05±0.07
Q
0.10±0.05
R
5°±5°
S
1.27 MAX.
P80GK-50-BE9-6
Data Sheet U12092EJ1V0DS00
57
µPD78F0058, 78F0058Y
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
P
T
80
R
21
1
20
U
Q
F
G
L
H
I
J
M
K
S
N
S
M
NOTE
ITEM
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
MILLIMETERS
14.0±0.2
B
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
L
1.0±0.2
0.5
M
0.145±0.05
N
0.08
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P80GK-50-9EU-1
58
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
9.
RECOMMENDED SOLDERING CONDITIONS
The µ PD78F0058 and 78F0058Y should be soldered and mounted under the following recommended
conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 9-1. Surface Mounting Type Soldering Conditions
µ PD78F0058GC-8BT
: 80-pin plastic QFP (14 × 14 mm)
µ PD78F0058YGC-8BT : 80-pin plastic QFP (14 × 14 mm)
Soldering
Soldering Conditions
Recommended
Method
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-00-2
Count: Twice or less
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
VP15-00-2
Count: Twice or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
WS60-00-1
Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Caution
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Do not use different soldering methods together (except for partial heating).
µ PD78F0058GK-BE9:
80-pin plastic TQFP (12 × 12 mm, resin thickness 1.05 mm)
µ PD78F0058YGK-BE9:
80-pin plastic TQFP (12 × 12 mm, resin thickness 1.05 mm)
Soldering
Soldering Conditions
Method
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-107-2
Count: Twice or less, Exposure limit: 7 daysNote
(after 7 days, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
VP15-107-2
Count: Twice or less, Exposure limit: 7 daysNote
(after 7 days, prebake at 125°C for 10 hours)
Wave soldering
Partial heating
–
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
Data Sheet U12092EJ1V0DS00
59
µPD78F0058, 78F0058Y
µ PD78F0058GK-9EU : 80-pin plastic TQFP (12 × 12 mm, resin thickness 1.0 mm)
µ PD78F0058YGK-9EU : 80-pin plastic TQFP (12 × 12 mm, resin thickness 1.0 mm)
Soldering
Soldering Conditions
Method
Recommended
Condition Symbol
Infrared reflow
Undefined
Undefined
VPS
Undefined
Undefined
Wave soldering
Undefined
Undefined
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
60
Data Sheet U12092EJ1V0DS00
–
µPD78F0058, 78F0058Y
APPENDIX A.
DEVELOPMENT TOOLS
The following development tools are available for system development using the µ PD780058, 780058Y
Subseries.
Also, refer to (5) Cautions on using development tools.
(1) Language processing software
RA78K0
Assembler package common to the 78K/0 Series
CC78K0
C compiler package common to the 78K/0 Series
DF780058
Device file for the µ PD780058, 780058Y Subseries
CC78K0-L
C compiler library source file common to the 78K/0 Series
(2) Flash memory writing tools
Flashpro III (Part number:
FL-PR3, PG-FL3)
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-80GC-8BT
FA-80GK
FA-80GK-9EU
Adapter for flash memory writing
(3) Debugging tools
• When using the IE-78K0-NS in-circuit emulator
IE-78K0-NS
In-circuit emulator common to the 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance and expand the functions of the IE-78K0-NS
IE-70000-98-IF-C
Adapter used when a PC-9800 series PC (except notebook PC) is used as the host
machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable used when a PC-9800 series notebook PC is used as the
host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter necessary when an IBM PC/AT TM-compatible is used as the host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when using a PC with PCI bus as the host machine
IE-780308-NS-EM1
Emulation board common to the µ PD780308 Subseries
NP-80GC
Emulation probe for 80-pin plastic QFP (GC-8BT type)
NP-80GK
Emulation probe for 80-pin plastic TQFP (GK-BE9, GK-9EU type)
TGK-080SDW
Conversion adapter to connect the NP-80GK and a target system board on which 80-pin
plastic TQFP (GK-BE9, GK-9EU type) can be mounted
EV-9200GC-80
Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT
type)
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to the 78K/0 Series
DF780058
Device file for the µ PD780058, 780058Y Subseries
Data Sheet U12092EJ1V0DS00
61
µPD78F0058, 78F0058Y
• When using the IE-78001-R-A in-circuit emulator
IE-78001-R-A
In-circuit emulator common to the 78K/0 Series
IE-70000-98-IF-C
Adapter used when PC-9800 series PC (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT-compatible as the host machine (ISA bus
supported)
IE-78000-R-SV3
Interface adapter and cable used when EWS is used as the host machine
IE-780308-NS-EM1
IE-780308-R-EM
Emulation board common to the µ PD780308 Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using the IE-780308-NS-EM1 on the
IE-78001-R-A.
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EP-78054GK-R
Emulation probe for 80-pin plastic TQFP (GK-BE9, GK-9EU type)
TGK-080SDW
Conversion adapter to connect the EP-78054GK-R and a target system on which an 80pin plastic TQFP (GK-BE9, GK-9EU type) can be mounted
EV-9200GC-80
Socket to be mounted on a target system board made for 80-pin plastic QFP (GC-8BT
type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
78K/0 Series common system simulator
DF780058
Device file for the µ PD780058, 780058Y Subseries
(4) Real-time OS
RX78K/0
Real-time OS for the 78K/0 Series
MX78K0
OS for the 78K/0 Series
62
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
(5) Cautions on using development tools
•
The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780058.
•
The CC78K0 and RX78K/0 are used in combination with the RA78K0 and DF780058.
•
The FL-PR3, FA-80GC-8BT, FA-80GK, FA80GK-9EU, NP-80GC, and NP-80GK are products of Naito Densei
Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813). Contact an NEC distributor regarding the purchase of these
products.
•
TGK-080SDW is a product made by Tokyo Eletech Corp.
For further information, contact Daimaru Kogyo, Ltd.
Electronics Department (Tokyo) (TEL: +81-3-3820-7112)
Electronics 2nd Department (Osaka) (TEL: +81-6-6244-6672)
•
For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide
(U11069E)
•
The host machine and OS suitable for each software are as follows:
Host Machine [OS]
Software
PC
EWS
PC-9800 Series [Japanese Windows TM ]
IBM PC/AT-compatible
HP9000 series 700 TM [HP-UX TM ]
SPARCstation TM [SunOS TM ,Solaris TM ]
[Japanese/English Windows]
NEWS TM (RISC) [NEWS-OS TM ]
RA78K0
√ Note
√
CC78K0
√ Note
√
ID78K0-NS
√
–
ID78K0
√
√
SM78K0
√
–
RX78K/0
√ Note
√
MX78K0
√ Note
√
Note DOS-based software
Data Sheet U12092EJ1V0DS00
63
µPD78F0058, 78F0058Y
APPENDIX B.
RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked
as such.
Documents Related to Devices
Document Name
Document No.
Japanese
English
µPD780058, 780058Y Subseries User’s Manual
U12013J
U12013E
µPD780053, 780054, 780055, 780056, 780058 Data Sheet
U12182J
U12182E
µPD78F0058, 78F0058Y Data Sheet
U12092J
This document
78K/0 Series User’s Manual - Instruction
U12326J
U12326E
78K/0 Series Instruction Table
U10903J
–
78K/0 Series Instruction Set
U10904J
–
78K/0, 78K/0S Series Flash Memory Write Application Note
U14458J
U14458E
Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
Japanese
RA78K0 Assembler Package
Operation
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
Language
U11789J
U11789E
U12323J
EEU-1402
U11517J
U11517E
RA78K Series Structured Assembler Preprocessor
CC78K0 C Compiler
U11802J
English
Operation
Language
U11518J
U11518E
U13731J
U13731E
IE-78001-R-EM
To be prepared
To be prepared
IE-780308-NS-EM1
To be prepared
To be prepared
IE-78K0-NS
IE-780308-R-EM
U11362J
U11362E
EP-78230
EEU-985
EEU-1515
EP-78054GK-R
U13630J
–
Reference
U10181J
U10181E
External Part User Open
Interface Specifications
U10092J
U10092E
Reference
U12900J
U12900E
SM78K0 System Simulator
Windows Based
SM78K Series System Simulator
ID78K0-NS Integrated Debugger
Windows Based
ID78K0 Integrated Debugger
EWS Based
Reference
U11151J
–
ID78K0 Integrated Debugger
PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger
Windows Based
Guide
U11649J
U11649E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
64
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Document No.
Japanese
English
Fundamentals
U11537J
U11537E
Installation
U11536J
U11536E
Fundamental
U12257J
U12257E
Other Related Documents
Document Name
Document No.
Japanese
English
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Guide to Microcomputer-Related Products by Third Party
U11416J
–
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U12092EJ1V0DS00
65
µPD78F0058, 78F0058Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided thst the system conforms to the I 2C Standard Specification as
defined by Philips.
66
Data Sheet U12092EJ1V0DS00
µPD78F0058, 78F0058Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12092EJ1V0DS00
67
µPD78F0058, 78F0058Y
FIP and IEbus are trademarks of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
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