RNA51xx Series CMOS system–RESET IC REJ03D0505-0300 Rev.3.00 Oct 10, 2008 General Description The RNA51xx series provide system reset signal for microprocessor and electrical systems. Threshold voltage is 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V and accuracy is ±1.0%. The reset output delay time can be set by external capacitor connected to CD pin. Manual reset input is available and input resistance is 2 MΩ typ. This series have two output types (active-low CMOS output and active-low open-drain output). Features • • • • • • • • • • Threshold voltage: 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V Threshold voltage accuracy: ±1.0% Threshold voltage hysteresis: 5% typ. Low supply current: 0.7 µA typ. Capacitor-adjustable output delay time Manual reset VOUT CMOS output, or open-drain output 5-pin SOT-23 package Temperature range: –40°C to 85°C Ordering Information Taping Abbreviation (Quantity) Package Type Package Code Package Abbreviation RNA51A26FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A27FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A28FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A29FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A30FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A31FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A44FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A45FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51A46FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51B14FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51B27FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) RNA51B50FLPEL MPAK-5pin PLSP0005ZB-A LP EL (3,000pcs/Reel) Part Name Applications • • • • • Power supply voltage monitoring for microprocessors Battery-powered portable equipment Computers and notebook computers Wireless Communication Systems Digital still camera, digital video camera, PDA REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 1 of 11 RNA51xx Series Pin Arrangement VOUT 1 5 CD VDD 2 GND 3 4 MR (Top view) Product list Open-Drain output CMOS output Threshold Voltage –VTH [V] Type No. Marking Type No. Marking 1.4 — — RNA51B14FLP 6P 2.6 RNA51A26FLP 5N — — 2.7 RNA51A27FLP 5P RNA51B27FLP 7C 2.8 RNA51A28FLP 5Q — — 2.9 RNA51A29FLP 5R — — 3.0 RNA51A30FLP 5S — — 3.1 RNA51A31FLP 5T — — 4.4 RNA51A44FLP 6G — — 4.5 RNA51A45FLP 6H — — 4.6 RNA51A46FLP 6J — — 5.0 — — RNA51B50FLP 3R Outline and Article Indication • RNA51A26FLP (Example) Marking 5 MPAK-5 REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 2 of 11 N Control Code RNA51xx Series Functional block diagram & typical application circuit (1) RNA51Axx Products Power supply MR VDD 4 Power supply 2 delay 1 VOUT RESET Microprocessor Vref GND 3 5 CD (2) RNA51Bxx Products Power supply MR VDD 4 2 delay 1 VOUT RESET Microprocessor Vref GND 3 5 CD Notes: 1. It is good for stable operation to use a decoupling capacitor with excellent high frequency characteristics between VDD and GND pin. 2. Capacitor value is determined by system conditions. REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 3 of 11 RNA51xx Series Timing Diagram VHYS VTH VDD MR tDLY tDLY tDLY VOUT Absolute Maximum Ratings (1) RNA51Axx Products Temperature condition Ta = 25°C Item Supply voltage Output voltage Input voltage Output current Continuous power dissipation Operating temperature range Storage temperature range Symbol VDD VOUT VIN IOUT PD TOPR TSTG Pin VDD VOUT MR, MD VOUT — — — Ratings 6.0 –0.3 to 6.0 –0.3 to VDD+0.3 ±50 120 –40 to +85 –55 to +125 Unit V V V mA mW °C °C (2) RNA51Bxx Products Temperature condition Ta = 25°C Item Supply voltage Output voltage Input voltage Output current Continuous power dissipation Operating temperature range Storage temperature range Symbol VDD VOUT VIN IOUT PD TOPR TSTG REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 4 of 11 Pin VDD VOUT MR, MD VOUT — — — Ratings 6.0 –0.3 to VDD+0.3 –0.3 to VDD+0.3 ±50 120 –40 to +85 –55 to +125 Unit V V V mA mW °C °C RNA51xx Series Electrical characteristics (1) RNA51Axx Products Temperature condition Ta = 25°C Symbol Min Typ Max Unit Supply voltage Item VDD 1.1 5.5 V Supply current IDD 0.7 4.2 µA Threshold voltage Temperature coefficiency of the thereshold voltage (Reference value) Threshold voltage hysteresis VOUT low-level output current VOUT Output leakage current (open drain output) Note1 Delay time Note2 MR Low-level input voltage MR High-level input voltage MR internal pull-up resistance Conditions pull-up resistor = 470 kΩ VOUT ≤ 0.1×VDD VDD = 5.5 V –VTH –VTH×0.99 –VTH×1.01 V ∆(–VTH) –VTH ⋅∆Ta ±100 ppm/ °C VHYS IOL –VTH×3% 0.2 3.4 –VTH×5% 1.2 7.0 –VTH×8% V mA ILEAK 0.1 µA tDLY 10 20 35 ms VIL VIH RMR VDD×0.75 1 2 VDD×0.25 7 V V MΩ Symbol Min Typ Max Unit VDD 1.1 5.5 V µA Ta = –40 to 85°C VOUT = 0.5 V VDD = 1.3 V VDD = 2.4 V (–VTH ≥ 2.7 V) VDD = VOUT = 5.5 V VDD = 1.1 to 5.5V, tTLH = 1 µs CD = 4.7 nF (2) RNA51Bxx Products Temperature condition Ta = 25°C Item Supply voltage Supply current Threshold voltage Threshold voltage temperature dependency (Reference value for design) Threshold voltage hysteresis VOUT low-level output current VOUT High-level output current (CMOS output) Delay time Note1 Note2 MR Low-level input voltage MR High-level input voltage MR internal pull-up resistance Note: IDD 0.7 4.2 –VTH –VTH×0.99 –VTH×1.01 V ∆(–VTH) –VTH ⋅∆Ta ±100 ppm/ °C VHYS IOL –VTH×3% 0.2 3.4 –VTH×5% 1.2 7.0 –VTH×8% V mA IOH –1.4 –2.7 mA tDLY –1.5 10 –3.0 20 35 ms VIL VIH RMR VDD×0.75 1 2 VDD×0.25 7 V V MΩ Conditions pull-up resistor = 470 kΩ VOUT ≤ 0.1×VDD VDD = 5.5 V Ta = –40 to 85°C VOUT = 0.5 V VDD = 1.3 V VDD = 2.4 V (–VTH ≥ 2.7 V) VOUT = VDD = 4.5 V VDD–0.5 V (–VTH ≤ 4.0 V) VDD = 5.5 V VDD = 1.1 to 5.5 V, tTLH = 1 µs CD = 4.7 nF 1. Delay time is specified when charging starts in the condition that CD pin is completely discharged. When discharging of CD pin is not complete because of immediate stop and other reasons, the delay time is not guaranteed. Therefore, when passing of VDD pin input voltage immediately stops (the period of condition that VDD pin input voltage is lower than the detected voltage is short), discharging of external capacitor CD is inadequate, and the delay time becomes much shorter than the minimum guaranteed value. Be sure to fully check that there are no problems as the system. 2. Minimum value of low-pulse width to be input to MR pin depends on the value of external capacitor CD. Therefore, set the low-pulse width to be input to MR pin to the minimum input low-pulse width shown in figure 1 or more. REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 5 of 11 RNA51xx Series MR pin minimum input low pulse width (µs) 1000 100 10 1 0.1 1 10 100 1000 External Capacitor CD (nF) Figure 1 Dependence of MR pin minimum input low pulse width and external capacitor CD Pin Description PIN 1 NAME VOUT 2 VDD 3 4 GND MR 5 CD FUNCTION VOUT changes from high to low whenever VDD drops below –VTH. A pull-up resistor from 470 kΩ to 1 MΩ should be used on this pin for open-drain output. Supply voltage and input for voltage detector. A decoupling capacitor with excellent high frequency characteristics should be placed near VDD pin and connected between VDD and GND pin. Ground Active-low Manual Reset Input. VOUT is low-level while MR is low. Once MR is disabling, VOUT turn to high-level after delay time. MR pin is internally pulled up to VDD through 2 MΩ. Connect capacitor between CD and GND pin to set programmable delay time. Ceramic capacitor from 100 pF to 0.1 µF is recommended. REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 6 of 11 RNA51xx Series Test Circuit (1) RNA51Axx Products Minimum Supply voltage VDDmin Threshold voltage and Hysteresis ±VTH & VHYS 1 VOUT CD 5 470 k 1 VOUT CD 5 4.7 nF 470 k 5.5 V 2 VDD 0.0 V 4.7 nF 2 VDD 0.0 V 5.5 V 3 GND MR 4 3 GND 5.5 V MR 4 –VTH x 3% ≤ VHYS ≤ –VTH x 8% VHYS VOUT VOUT VOUT = VDD VOUT = VDD VOUT = 0.1 x VDD –VTH 0 Minimum Supply voltage VDD +VTH VDD 0 –VTH : Reset asserted voltage Minimum Supply voltage: VOUT = 0.1 x VDD ≤ 1.1 V +VTH : Reset released voltage Supply current IDD Output leakage current ILEAK ILEAK 1 VOUT CD 5 470 k 1 VOUT CD 5 A IDD A 5.5 V 2 VDD 3 GND 2 VDD 4.7 nF 5.5 V MR 4 Low-level output current IOL MR 4 MR internal pull-up resistance RMR 1 VOUT CD 5 IOL A 3 GND 4.7 nF 1 VOUT CD 5 470 k 2 VDD 2 VDD 0.5 V 1.3 V or 2.4 V 3 GND 4.7 nF 4.7 nF MR 4 –VTH +1 3 GND A IMR RMR = REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 7 of 11 MR 4 –VTH +1 IMR RNA51xx Series Test Circuit (Cont.) (1) RNA51Axx Products Delay time tDLY MR input voltage VIL & VIH 1 VOUT CD 5 470 k 1 VOUT CD 5 4.7 nF 470 k 2 VDD 1.1 V 5.5 V 3 GND 2 VDD MR 4 3 GND VDD 4.7 nF MR 4 0V VDD 5.5 V +VTH VDD 1.1 V VOUT 1 µs VDD tDLY 0.25 x VDD < VLTH < 0.75 x VDD VIL VIH REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 8 of 11 VDD 0.75 x VDD 0V 0 VLTH 2.75 V VOUT 0.25 x VDD 5.5 V VMR RNA51xx Series Test Circuit (Cont.) (2) RNA51Bxx Products Minimum Supply voltage VDDmin Threshold voltage and Hysteresis ±VTH & VHYS 1 VOUT CD 5 1 VOUT CD 5 4.7 nF 470 k 4.7 nF 5.5 V 2 VDD 0.0 V 2 VDD 0.0 V 5.5 V 3 GND MR 4 3 GND 5.5 V MR 4 –VTH x 3% ≤ VHYS ≤ –VTH x 8% VHYS VOUT VOUT VOUT=VDD VOUT = VDD VOUT = 0.1 x VDD –VTH 0 Minimum Supply voltage VDD +VTH VDD 0 –VTH : Reset asserted voltage Minimum Supply voltage: VOUT = 0.1 x VDD ≤ 1.1 V +VTH : Reset released voltage Supply current IDD High-level output current IOH IOH 1 VOUT CD 5 IDD A 5.5 V 4.7 nF 2 VDD 3 GND 4.5 V or 5.5 V MR 4 4.7 nF 2 VDD Low-level output current IOL 3 GND MR 4 MR internal pull-up resistance RMR 1 VOUT CD 5 IOL A 1 VOUT CD 5 A 0.5 V 1 VOUT CD 5 2 VDD 2 VDD 0.5 V 1.3 V or 2.4 V 3 GND 4.7 nF 4.7 nF MR 4 –VTH +1 3 GND A IMR RMR = REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 9 of 11 MR 4 –VTH +1 IMR RNA51xx Series Test Circuit (Cont.) (2) RNA51Bxx Products Delay time tDLY MR input voltage VIL & VIH 1 VOUT CD 5 1 VOUT CD 5 4.7 nF 2 VDD 1.1 V 5.5 V 3 GND 2 VDD MR 4 4.7 nF 3 GND VDD MR 4 0V VDD 5.5 V +VTH VDD 1.1 V VOUT 1 µs VDD tDLY 0.25 x VDD < VLTH < 0.75 x VDD VIL VIH REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 10 of 11 VDD 0.75 x VDD 0V 0 VLTH 2.75 V VOUT 0.25 x VDD 5.5 V VMR RNA51xx Series Delay Time Graph Delay Time vs. External Capacitor 1000 Delay Time (ms) 100 10 1 0.1 0.1 1 10 100 1000 External Capacitor CD (nF) Note: This graph shows simulation results. Package Dimensions Package Name MPAK-5 JEITA Package Code SC-74A RENESAS Code PLSP0005ZB-A Previous Code MPAK-5 / MPAK-5V MASS[Typ.] 0.015g D A e Q E HE LP L A c L1 A3 A x M S A Reference Dimension in Millimeters Symbol Min Nom Max b e A2 A e1 A1 y S S b I1 c b2 A-A Section REJ03D0505-0300 Rev.3.00 Oct 10, 2008 Page 11 of 11 Pattern of terminal position areas A A1 A2 A3 b c D E e HE L L1 LP x y b2 e1 I1 Q 1.0 0 1.0 0.35 0.11 2.8 1.5 2.5 0.3 0.1 0.2 1.1 0.25 0.4 0.16 2.95 1.6 0.95 2.8 1.4 0.1 1.3 0.5 0.26 3.1 1.8 3.0 0.7 0.5 0.6 0.05 0.05 0.55 2.15 0.85 0.3 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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