Silicon-on-Insulator (SOI) Switches for Cellular and

Silicon-on-Insulator (SOI)
Switches for Cellular and WLAN
Front-End Applications
WSO: Advancements in Front End Modules for Mobile and Wireless Applications
Ali Tombak
Acknowledgements
Ali Tombak
Presenter: E-mail: [email protected]
Phone: +1 (336) 664 - 1233
Acknowledgements: Daniel C. Kerr, Philip Mason
RFMD Inc.
Organization: Technology Platforms Organization
Greensboro, NC USA
Outline
• Motivation and Cellular Switch Considerations
• Switch Technology Overview
• SOI Switch Examples
• Design of High Order Switches on SOI
• Nonlinearities, Harmonics and IMD
• Spurious Emissions and ESD Considerations
• Conclusions
Handset Shipments by Mobile Standard
• Ever increasing need for higher
data rates drives the standards
to those of 3G / 4G.
• Market share and volume of
3G / 4G handsets expected to
increase tremendously.
• Many bands and band
combinations considered for
3G / 4G handsets to roam at
different regions.
3G / 4G Front End Architectures
• 3G / 4G system architectures require a complex integration of
switch, filter, and duplex functions in the front-end.
High Power Switch Considerations
• PA output power often represented
by ~36 dBm source
• Antenna port impedance varies
greatly
ANT
PA
• Operating VSWR up to 5:1, functional
into 20:1
• Off-state switch must stand-off high
AC voltages
40-80 Vpp
• Maintain Reliability
• Linearity
• For most IC technologies, several
FETs must be stacked in series
LNA
What is SOI ?
Si device layer
Buried oxide (~1um)
Si handle wafer (~700um)
• SOI = Silicon-on-Insulator
• Thin layer of Si / Buried Oxide / Handle Wafer
• Created using wafer bonding and ion implantation
cleaving process
• SOI (on high resistivity substrates) decouples FET
body terminals, enabling device stacking for high
power switch applications
Thick and Thin-Film SOI
• Thick-film SOI
• Device layer thickness > S/D junction
depth
• Device operation similar to bulk Si
• Circuit blocks can be transferred from
bulk Si with minimal changes
Deep Trench
S
G
n+
D
B
S
n+
p+
n+
PWELL
• More extensive re-design needed for
existing circuit blocks
D
B
n+
p+
~ 1.5 um
PWELL
BURIED OXIDE (~ 1 um)
~1000 Ohm-cm Si substrate
Shallow Trench
• Thin-film SOI
• S/D doping extends to buried oxide 
reduced S/D capacitance (Coff)
G
Shallow Trench
S
n+
G
D
S
n+
n+
G
D
S
n+
n+
G
D
n+
BURIED OXIDE (~ 1 um)
~1000 Ohm-cm Si substrate
~ 0.2 um
Switch Figure of Merit
FOM = Ron * Coff
• “Figure of merit”: trade off between insertion loss (resistance) and
isolation (capacitance)
• FOM is a device size independent measure of how good a switch
device/technology is.
• Lower FOM is better.
Switch Technology Comparison
Ron [Ω-mm] Coff [fF/mm] Ron*Coff [fs]
Process
Device
RFMD FET1H pHEMT
1 single gate
1.4
160
224
RFMD FET1H pHEMT
Two series
triple gate
0.9
300
270
0.18um thick-film SOI
5V NFET
Lg=0.6um
13.0nm gate ox
1.9
255
485
0.18um thin-film SOI
2.5V NFET
Lg=0.32um
5.2nm gate ox
0.8
310
250
0.25um SOS
NFET
5.0nm gate ox
1.6
280
448
0.35um SOS
Source: “Single chip phone RF is possible”,
Electronics Weekly, February 14, 2012.
• 0.18um thin-film SOI offers Ron*Coff similar to pHEMT / SOS.
• Integrated switch controller in the SOI die possible.
253
Switch Branch and Resistor Dimensioning
1
𝑅𝑔𝑎𝑡𝑒 ≫
2𝜋𝑓 𝐶𝑔𝑠 + 𝐶𝑔𝑑
• Use enough number of stacks to handle the specified power.
• Device width should be just right to meet the insertion loss/isolation
specifications.
• Wider widths result in poor isolation, and narrower widths result in poor insertion loss.
• The gate resistors should be large enough to float the gate, but small enough
to have adequate switching time.
• Resistors between source and drain used to provide 0 V DC bias to S/D of
devices. No DC blocking caps needed on RF ports.
Switch Timing Considerations
~ 60 nsec
delay applied between CB and
RF
Control
Bit
Fundamental
~180 nsec
RF
Signal
0 nsec (REF)
• Large signal switching event shown for a WLAN switch that requires stringent switching
times in the order of 100 nsec small signal, 500 nsec large signal (Full Power)
• Accomplished by measuring the time between the time the control bit applied and the time
of a 900 MHz 29 dBm RF signal stabilize in a spectrum analyzer.
• Fundamental reaches full power at 60+180 = ~240 nsec, well below 500 nsec requirement!
• No significant variation observed vs. voltage, temperature.
General Block Diagram for an SOI Switch and
Equivalent Circuit Model
• An RF switch includes multiple series
and shunt branches and a controller
that would provide the necessary bias
voltages to the switch devices for a
given control bit setting.
• In an equivalent circuit model, ON
devices can be considered as
resistors, OFF devices as capacitors
Example: SP9T Switch for Switch Duplexer
Module Applications
pHEMT Switch
TX2
Control
Pins
TX1
SOI Switch (Wire Bond)
TRX3
SOI Switch (Flip Chip)
• SOI integrates the controller and RF section in a
single die vs. pHEMT having a complex two die
TRX2 solution.
ANT
• Wire bond and flip chip SOI SP9T switches
designed for an SDM application.
TRX1 • 2 high power GSM TX,
RX4 RX3 RX2 RX1
• 3 high power WCDMA, and
• 4 low power GSM RX ports.
Measured Insertion Loss, dB
SP9T Insertion / Return Loss
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-1.1
-1.2
-1.3
-1.4
TX2
TX1
TRX3
TRX2
TRX1
RX1
RX2
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
RX3
RX4
Measured Return Loss, dB
Frequency, GHz
-5
TX2
TX1
-10
TRX3
-15
TRX2
-20
TRX1
-25
RX1
RX2
-30
0.5
1
1.5
2
2.5
3
3.5
Frequency, GHz
4
4.5
5
RX3
RX4
• At 915 MHz,
• TX and TRX ports have 0.45 dB,
• RX ports have 0.55 dB insertion
loss.
• At 1990 and 2170 MHz, insertion losses
increase by about 0.2 and 0.25 dB,
respectively.
• No intentional matching employed,
hence less insertion loss achievable
with matching.
TX / TRX to TX / TRX Isolation
dB
915 MHz
1990 MHz
2170 MHz
• TX / TRX to TX / TRX isolation better than 29 dB up to 2170 MHz.
• Lower isolation to one branch due to higher branch-to-antenna and bond
wire coupling. Other combinations achieve better than 34 dB isolation up to
2170 MHz.
• Higher isolation achievable with flip-chip SP9T.
TX / TRX to RX Isolation
dB
915 MHz
1990 MHz
2170 MHz
• TX / TRX to RX isolation better than 32 dB up to 2170 MHz.
• Adjacent TRX / RX and closer RX / ANT combination achieve lower
isolation compared to the rest due to higher branch-to-branch and bond
wire coupling.
• Higher isolation achievable with flip-chip SP9T.
RX to RX Isolation
dB
915 MHz
1990 MHz
2170 MHz
• RX to RX isolation better than 28 dB up to 2170 MHz.
• Adjacent branches achieve lower isolation compared to other
combinations due to higher branch-to-branch and bond wire coupling.
• Higher isolation achievable with flip-chip SP9T.
High Order Switch Design
W_ON
Series branch size = W_OFF =
W_ON
...
W_OFF
.
RF16
• Equivalent circuit model for a symmetric SP16T in one of the active
modes shown above.
• 0.32 um channel length series and shunt devices assumed. Shunt
device size fixed at 1mm.
• Let’s study the effect of series branch size on insertion loss and
isolation at 915, 1910, and 2690 MHz.
Branch Size Study for
High Order Switches (SP16T)
Insertion Loss,
dB
Return Loss, dB
Power Gain, dB
Isolation, dB
• Return loss increases significantly and degrades insertion loss with increased series
branch size. It must be tuned!
• There exists an optimum branch size to give lowest insertion loss if you can match!
Matching Values for SP16T
915 MHz
• Use series L shunt C to match
capacitive loading at antenna.
• Different matching values needed
at different frequencies!
• Choose your device size
considering insertion loss/
isolation specs and matching!
2690 MHz
Example: Design of a Single Chip SOI MIPI Switch System
• Single die flip chip solution for a SP7T+SP5T+SP3T+SP3T switch system
with MIPI interface having 50+ switch states.
• Switch die size = 3 x 1.2 mm2.
• 5 layer evaluation laminate designed to test and tune the switches.
Measured Insertion Loss
Design Targets
Max. Frequency Insertion Loss
(MHz)
(MHz)
Measured Results
(Flip Chip Dies + SMD + Module)
Insertion Loss
(dB)
Return Loss
(dB )
0.30
0.30
0.30
0.27
0.29
0.3
29
34
28
1980
1755
1910
0.35
0.30
0.35
0.41
0.35
0.41
27
32
34
Mode 7
Mode 8
Mode 9
Mode 10
Mode 11
915
894
960
960
960
0.40
0.40
0.40
0.40
0.50
0.35
0.45
0.49
0.45
0.51
32
32
32
29
31
Mode 12
Mode 13
Mode 14
Mode 15
Mode 16
Mode 17
Mode 18
1910
1990
2170
2690
1880
1910
2690
0.50
0.50
0.55
0.60
0.50
0.50
0.60
0.46
0.59
0.72
0.75
0.74
0.7
0.71
16
14
14
13
12
12
12
Switch
Mode
LB SP3T
LB SP3T
LB SP3T
Mode 1
Mode 2
Mode 3
849
915
862
HB SP3T
HB SP3T
HB SP3T
Mode 4
Mode 5
Mode 6
LB SP5T
LB SP5T
LB SP5T
LB SP5T
LB SP5T
HB SP7T
HB SP7T
HB SP7T
HB SP7T
HB SP7T
HB SP7T
HB SP7T
Insertion loss targets
achieved in LB SP3T switch
Up to ~0.05 dB higher loss
in HB SP3T switch
[-0.05,0.10] dB around the
design targets achieved in
LB SP5T switch
[-0.05,0.20] dB around the
design targets achieved in
HB SP7T switch. But, by
further tuning the mismatch,
some of the mismatch loss
can be recovered.
High Resistivity Silicon Substrate Linearity
• A parasitic conduction layer may form
at Si/SiO2 interface below SOI buried
oxide.
• A structure (metal trace or device)
above the oxide with varying potential
may modulate the conductive
characteristic at the interface, creating
a non linear impedance.
• This limited the linearity of SOI
switches, but this issue has been
solved now, making SOI a viable high
power switch technology.
C. Roda Neve, D. Lederer, G. Pailloncy, D. C. Kerr, J. M. Gering,
T. G. McKay, M. S. Carroll and J.-P. Raskin, “Impact of Si
substrate resistivity on the non-linear behaviour of RF CPW
transmission lines”, Proceedings of the 3rd European Microwave
Integrated Circuits Conference, October 2008, Amsterdam, The
Netherlands.
Low Band Harmonics, dBm
Measured Harmonic Distortion
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
900 MHz
3fo
TX1_2fo
2fo
TX1_3fo
TRX1_2fo
TRX1_3fo
20 22 24 26 28 30 32 34 36 38
High Band Harmonics, dBm
-58 and -47 dBm up to 37 dBm input
power, respectively.
• High Band 2fo and 3fo better than
-49 and -46 dBm up to 36 dBm input
Input Power, dBm
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
• Low Band 2fo and 3fo better than
1780 MHz
power, respectively.
TX1_2fo
TX1_3fo
2fo
TRX1_2fo
TRX1_3fo
3fo
20 22 24 26 28 30 32 34 36 38
Input Power, dBm
• Measured harmonic levels considerably
better than most antenna/mode switch
specifications.
SOI Switch Model vs. Measurement Comparison
Insertion/Return
Loss
Red:
Measured
Blue:
Simulated
• Simulations can predict measured
small signal and large signal
performance
– Assures new designs hit performance
targets
– Enables module co-design with proper
matching
SP9T (2fo, 900MHz)
Red: Measured
Blue: Simulated
Red: Measured
Blue: Simulated
SP9T Filter Port S11
Switch Linearity Requirements
• Typical IMD specification is 105 dBm.
• Adequate IMD levels measured
for the UMTS ports as shown
below.
• IMD 45 / IMD 190 improved to
a sufficient level with the shunt
ESD inductor on the SDM.
* T. Ranta et. al., 2005.
Measured SP9T IMD, dBm
Switch Only
SDM
TX Frequency
(F1), MHz
Blocker Frequency
(F2), MHz
Distortion Type
IMD (RX)
Frequency, MHz
1950
1760
2F1-F2
2140
-119
-117
1950
4090
F2-F1
2140
-110
-108
1950
190
F1+F2
2140
-106
-111
836.5
791.5
2F1-F2
881.5
-122
-117
836.5
1718
F2-F1
881.5
-120
-115
836.5
45
F1+F2
881.5
-102
-118
Spurious Emissions
Ref
-100
-105
-110
-115
-120
-125
-130
-135
-140
-145
-150
-100 dBm
-100Offset
* Att
* RBW
30 kHz
* VBW
500 kHz
0 dB
SWT
225 ms
-17 dB
A
-105
RBW=30 kHz
1 SA
-110
LVL
VBW=500 kHz
-115
-120
PRN
-125
SWP
50 of
50
-130
-135
-140
-145
-150
1
1 GHz
0.98
0.96
0.94
Stop
0.92
0.9
10:04:14
0.88
26.JAN.2010
0.86
20 MHz/
0.84
Date:
800 MHz
0.82
Start
0.8
Spurious Level, dBm
AVG
Frequency, GHz
• Measured RX mode spurious emissions better than -123 dBm.
• Measured RX band noise better than -97 dBm (fTX = 915 MHz, PTX = 35
dBm).
ESD Considerations
Series Branch
Switch Branches
Shunt Branch
• Controller must be protected using appropriate ESD diodes and clamp circuits.
• In the RF section, utilization of shunt branches offer very good ESD protection up to 2
kV HBM.
• The mechanism for shunting the ESD current to ground is believed to be that the gate
of the shunt branches couple up through capacitive coupling with the large ESD
voltage transient. This effectively turns the shunt transistors on giving the ESD
energy a path to ground.
SOI Performance Snapshot
Size
Implementation Ease
(TX Port Impedance)
100
Id (mA)
Cost
50
Harmonics
Competitor B
SOI
Insertion Loss
Isolation
IMD
Competitor A
Conclusions
• 3G / 4G smart handsets will dominate the market in the next few years,
which opens a great opportunity for front-end suppliers.
• High resistivity SOI enables FET stacking, allowing the design of high
power antenna / mode switches.
• Low RON*COFF product results in competitive switch insertion loss and
isolation performance.
• High resistivity SOI substrate linearity issues solved, enabling the design
of high throw count SOI antenna switches with excellent harmonic and
intermodulation distortion performance.
• Adequate levels of TX and RX mode spurious emissions measured.
• 2000 V Human Body Model (HBM) ESD tolerance achieved on the RF
ports (no blocking capacitors on the ports).