RF3183 QUAD-BAND/GSM850/EGSM900 /DCS/PCS/POWER AMPLIFIER MODULE Package Style: Module (5mmx5mmx1mm) DCS RFIN 1 10 DCS RFOUT BAND SEL 2 Features TX EN 3 Typical GMSK Efficiency GSM850/900 48/53% DCS/PCS 50/53% Integrated Power Control VBATT 4 Auto VBATT Tracking Circuit avoids Switching Transients at Low Supply Voltage Integrated Power Flattening Circuit Reduces Power and Current into Mismatch GND 5 VRAMP 6 GSM RFIN 7 Integrated VRAMP Rejection Filter Eliminates External Components 9 GSM RFOUT GND 8 Applications Functional Block Diagram Quad-Band GSM Handsets GSM Transmitter Line-ups Portable Battery-Powered Equipment GSM850/EGSM900/DCS/ PCS Products GPRS Class 12 Compatible Products Mobile EDGE/GPRS Data Products Product Description The RF3183 is a high power amplifier module with integrated power control. The input and output terminals are internally matched to 50. The amplifier devices are manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (GaAs HBT) process. The module is designed to be the final amplification stage in a dual-mode GSM/EDGE mobile transmit lineup operating in the 824MHz to 915MHz (low) and 1710MHz to 1910MHz (high) bands (such as a cellular handset). Band selection is controlled by an input on the module which selects either the low or high band. The device is packaged on a 5mmx5mm laminate module with a protective plastic over-mold. The RF3183 features RFMD’s latest integrated power flattening circuit, which significantly reduces current and power variation into load mismatch. The RF3183 provides excellent ESD protection at all the pins. The RF3183 also provides integrated VRAMP rejection filter which improves noise performance and transient spectrum. Ordering Information RF3183Quad-Band/GSM850/EGSM900 /DCS/PCS/Power Amplifier Module RF3183 RF3183PCBA-41X GaAs HBT GaAs MESFET InGaP HBT Quad-Band/GSM850/EGSM900 /DCS/PCS/Power Amplifier Module Power Amplifier Module, 5 Piece Sample Pack Fully Assembled Evaluation Board Optimum Technology Matching® Applied SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT RF MEMS LDMOS RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc. DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 1 of 20 RF3183 Absolute Maximum Ratings Parameter Rating Unit Supply Voltage (VBATT) -0.5 to +6.0 V Power Control Voltage (VRAMP) -0.5 to +3.0 V Band Select 3.0 V TX Enable 3.0 V RF - Input Power 10.0 dBm 50 % Max Duty Cycle Output Load VSWR 10:1 Operating Temperature -30 to +85 °C Storage Temperature -55 to +150 °C Parameter Min. Specification Typ. Max. Caution! ESD sensitive device. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied. RoHS status based on EUDirective2002/95/EC (at time of this document revision). The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. Unit Condition Recommended Operating Conditions VRAMP VRAMP Input Current 40 VRAMP =VRAMP, MAX VRAMP =VRAMP, MIN 2.2 0.25 A VRAMP =VRAMP,MAX V V Band Select Switch BAND_SEL “HIGH” 1.5 V High Band (DCS1800/PCS1900) BAND_SEL “LOW” 0 0.7 V Low Band (GSM850/EGSM900) BAND_SEL Input Current 1 +10 uA TX_EN TX_EN “HIGH” 1.5 V PA “ON” TX_EN “LOW” 0 0.7 V PA “OFF” TX_EN Input Current 1 +10 uA Overall Power Supply VBATT Range 3.0 3.6 Off Current 4.5 V 10 uA TX_EN Low RF Impedance LB_RF IN 50 LB_RF OUT 50 HB_RF IN 50 HB_RF OUT 50 2 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Parameter Min. Specification Typ. Max. Unit Condition Nominal test conditions unless otherwise stated. Temp=25 °C, VBATT =3.6V, Freq=824MHz to 849MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL=“Low”, TX_EN=“High”, VRAMP =VRAMP,MAX Cellular 850MHz Band GMSK Mode Operating Frequency Range 824 849 MHz +4 dBm -2 +1 Maximum Output Power 1 34.5 35.0 dBm Temp=25 °C, VBATT =3.6V Maximum Output Power 2 32.5 33 dBm Temp=85 °C, VBATT =3.0V Input Power Range, PIN Total Efficiency (PAE) 42 Output Noise Power 48 -83 Forward Isolation 1 Forward Isolation 2 % PIN =+1dBm -82 dBm 869MHz to 894MHz, f0 =849MHz, POUT <Rated POUT, RBW=100kHz -32 dBm TX_EN=0V, VRAMP=VRAMP,MIN, PIN =+4dBm -10 dBm VRAMP =VRAMP,MIN, PIN =+4dBm 2f0 Harmonics -15 -10 dBm POUT <Rated POUT 3f0 Harmonics -25 -15 dBm POUT <Rated POUT Fundamental Cross Band Coupling -1 3 dBm Measured at DCS_RFOUT pin, POUT <Rated POUT at GSM_RFOUT pin 2f0, 3f0 Cross Band Coupling -22 -17 dBm Measured at DCS_RFOUT pin, POUT <Rated POUT at GSM_RFOUT pin -36 dBm Over PIN range, POUT <Rated POUT 2:1 3:1 dBm Load VSWR=5.1 All phase angles, Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=5:1, Full PIN Range, RBW=3MHz, no oscillations All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness -36 No damage or permanent degradation to device Load VSWR=10:1, all phase angles. Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=10:1 Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.25V, Rated POUT =34.5dBm DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 3 of 20 RF3183 Parameter Min. Specification Typ. Max. Unit Condition Nominal test conditions unless otherwise stated. Temp=25 °C, VBATT =3.6V, Freq=880MHz to 915MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL=“Low”, TX_EN=“High”, VRAMP =VRAMP,MAX EGSM 900MHz Band GMSK Mode Operating Frequency Range 880 915 MHz +4 dBm -2 +1 Maximum Output Power 1 34.5 35 dBm Temp=25°C, VBATT =3.6V Maximum Output Power 2 32.5 33 dBm Temp=+85°C, VBATT =3.0V Input Power Range, PIN Total Efficiency (PAE) 47 Output Noise Power 53 % PIN =+1dBm -80 -79 dBm 925MHz to 935MHz, f0 =915MHz, POUT <Rated POUT, RBW=100kHz -83 -82 dBm 935MHz to 960MHz, f0 =915MHz, POUT <Rated POUT, RBW=100kHz Forward Isolation 1 -32 dBm TX_EN=0V, VRAMP =VRAMP,MIN, PIN =+4dBm Forward Isolation 2 -10 dBm VRAMP =VRAMP,MIN, PIN =+4dBm 2f0 Harmonics -15 -10 dBm POUT <Rated POUT 3f0 Harmonics -25 -15 dBm POUT <Rated POUT -1 3 dBm Measured at DCS_RFOUT pin, POUT <Rated POUT at GSM_RFOUT pin -22 -17 dBm Measured at DCS_RFOUT pin, POUT <Rated POUT at GSM_RFOUT pin -36 dBm Over PIN range, POUT <Rated POUT dBm Load VSWR=5:1 All phase angles. Set VRAMP where POUT <Rated POUT into 50 load, then load switched to 5:1 VSWR. Full PIN Range, RBW=3MHz, no oscillations Fundamental Cross Band Coupling 2f0, 3f0 Cross Band Coupling All Other Non-harmonic Spurious Input VSWR 2:1 Output Load VSWR Stability Output Load VSWR Ruggedness 3:1 -36 No damage or permanent degradation to device Load VSWR=10:1 All phase angles, Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=10:1 Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.25V, Rated POUT =34.5dBm 4 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Parameter Min. Specification Typ. Max. Unit Nominal test conditions unless otherwise stated. Temp=25 °C, VBATT =3.6V, Freq=1710MHz to 1785MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL=“High”, TX_EN=“High”, VRAMP =VRAMP,MAX DCS 1800MHz Band GMSK Mode Operating Frequency Range Input Power Range, PIN Condition 1710 -2 +1 1785 MHz +4 dBm Maximum Output Power 1 32.0 33 dBm Temp=25°C, VBATT =3.6V Maximum Output Power 2 30 31 dBm Temp=+85oC, VBATT =3.0V Total Efficiency (PAE) 43 50 % Output Noise Power -81 PIN =+1dBm -77 dBm 1805MHz to 1880MHz, f0 =1785MHz, POUT <Rated POUT, RBW=100KHz Forward Isolation 1 -32 dBm TX_EN=0V, VRAMP =VRAMP,MIN, PIN =+4dBm Forward Isolation 2 -10 dBm VRAMP =VRAMP,MIN, PIN =+4dBm 2f0 Harmonics -20 -10 dBm POUT <Rated POUT 3f0 Harmonics -25 -15 dBm POUT <Rated POUT -36 dBm Over PIN range, POUT <Rated POUT 2:1 3:1 dBm Load VSWR=5:1 All phase angles, Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=5:1, Full PIN Range, RBW=3MHz, no oscillations All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness -36 No damage or permanent degradation to device Load VSWR=10:1 All phase angles Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=10:1 Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.25V, Rated POUT =32.0dBm DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 5 of 20 RF3183 Parameter Min. Specification Typ. Max. Unit Nominal test conditions unless otherwise stated. Temp=25 °C, VBATT =3.6V, Freq=1850MHz to 1910MHz, 25% Duty Cycle, Pulse Width=1154s, PIN =-2dBm, BAND_SEL=“High”, TX_EN=“High”, VRAMP =VRAMP,MAX PCS 1900MHz Band GMSK Mode Operating Frequency Range Input Power Range, PIN Condition 1850 -2 +1 1910 MHz +4 dBm Maximum Output Power 1 32.0 33 dBm Temp=25°C, VBATT =3.6V Maximum Output Power 2 30 31 dBm Temp=+85oC, VBATT =3.0V Total Efficiency (PAE) 45 53 % Output Noise Power -81 PIN =+1dBm -77 dBm 1930MHz to 1990MHz, f0 =1910MHz, POUT <Rated POUT, RBW=100kHz Forward Isolation 1 -32 dBm TX_EN=0V, VRAMP =VRAMP,MIN, PIN =+4dBm Forward Isolation 2 -10 dBm VRAMP =VRAMP,MIN, PIN =+4dBm 2f0 Harmonics -20 -10 dBm POUT <Rated POUT 3f0 Harmonics -25 -15 dBm POUT <Rated POUT -36 dBm Over PIN range, POUT <32dBm 2:1 3:1 dBm Load VSWR=5:1 All phase angles, Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=5:1, Full PIN Range, RBW=3MHz, no oscillations All Other Non-harmonic Spurious Input VSWR Output Load VSWR Stability Output Load VSWR Ruggedness -36 No damage or permanent degradation to device Load VSWR=10:1 All phase angles, Set VRAMP where POUT <Rated POUT into 50 load, then load switched to VSWR=10:1 Note: VRAMP,MAX =2.2V, VRAMP,MIN =0.25V, Rated POUT =32.0dBm 6 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Pin 1 2 Function DCS_RFIN BANDSEL 3 TX_EN 4 VBATT 5 6 GND VRAMP 7 8 9 10 11 GSMIN GND GSMOUT DCSOUT GND Description RF input to the high-band PA. It is DC-blocked within the part. Digital input enables either the low band or high band amplifier die within the module. A logic low selects Low Band (GSM850/EGSM900), a logic high selects High Band (DCS1800/PCS1900). This pin is a high impedance CMOS input with no pull-up or pull-down resistors. Digital input enables or disables the internal circuitry. When disabled, the module is in the OFF state, and draws virtually zero current. This pin is a high impedance CMOS input with no pull-up or pull-down resistors. Main DC power supply for all circuitry in the RF3183. Traces to this pin will have high current pulses during operation so proper decoupling and routing should be observed. Ground. Analog signal used to control the output power. The signal also ramps the output power up and down. An internal 300kHz filter reduces switching ORFS resulting from transitions between DAC steps. Most systems will have no need for external VRAMP filtering. This pin provides an impedance of approximately 60k. RF input to the low-band PA. It is DC-blocked within the part. Ground. RF output from the low-band PA. It is DC-blocked within the part. RF output from the high-band PA. It is DC-blocked within the part. Main ground pad in center of part. This pad should be tied to the main ground plane with as little loss as possible for optimum linearity. Pin Out Top View DS100412 DCS IN 1 BAND SELECT 2 TX EN 3 VBATT 4 GND 5 VRAMP 6 GSM IN 7 GND 8 10 DCS OUT 9 GSM OUT 11 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 7 of 20 RF3183 Theory of Operation VBATT TX_EN VRAMP H(s) RF IN RF OUT TX_EN AGC Amplifier Figure 1. RF3183 Power Amplifier Simplified Block Diagram of a Single Band Overview The RF3183 is designed for use as the final RF amplifier in GSM850, EGSM900, DCS and PCS handheld digital cellular equipment, and other applications operating in the 824MHz to 915MHz, and 1710MHz to 1910MHz bands. The RF3183 is a high power, power amplifier module with PowerStar® integrated power control. The integrated power control circuitry provides reliable control of saturated power by a single analog voltage (VRAMP). This control voltage can be driven directly from a DAC output. PowerStar®’s predictable power versus VRAMP relationship allows single-point calibration in each band. Single-point calibration enables handset manufacturers to achieve simple and efficient phone calibration in production. The RF3183 also features an integrated saturation detection circuit, which is an industry first for standard PA module products. The saturation detection circuit automatically monitors battery voltage, and adjusts the power control loop to reduce transient spectrum degradation that would otherwise occur at low battery voltage conditions. Prior to the implementation of the saturation detection circuit, handset designers were required to adjust the ramp voltage within the system software. RFMD’s saturation detection circuit reduces handset design time and ensures robust performance over broad operating conditions. 8 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Power and Current Into Mismatch Transmitters are often designed to operate only under perfect 50 loads. In the real application when a PA is subjected to mismatch conditions, performance degrades most likely in a reduction of output power, increased harmonic levels, increased transient spectrum, and catastrophic failures. RF3183 has an integrated power flattening circuit that reduces the amount of current variation under load mismatch. When a mismatch is presented to the output of the PA, its output impedance is varied and could present a load that will increase output power. As the output power increases, so does current consumption. The current consumption can become very high if not monitored and limited. The power-flattening circuit is integrated onto the CMOS controller and requires no input from the user. Into a mismatch, current varies as phase changes. The power-flattening circuit monitors current through an internal sense resistor. As current changes, the loop is adjusted in order to maintain current. Under nominal conditions, this loop is not activated and is seemingly transparent. The result is flatter power and reduced current into mismatch as shown in the following figures. Test Condition: VBATT =3.6V, RFIN =1dBm, Temperature=25°C, Tx Frequency=915MHz 35.00 2644.01 2644.02 34.50 2644.03 2644.04 34.00 2644.05 2644.06 33.50 2644.07 2644.08 Delivered Power in 33.00 dBm 2644.09 2644.10 2644.11 32.50 2644.12 2644.13 2644.14 32.00 2644.15 2644.21 31.50 2644.22 2644.23 31.00 2644.24 0 30 60 90 120 150 180 210 240 270 300 330 2644.25 Phase Angle Figure 2. RF3183 Power Variation Under Mismatch VSWR 3:1 DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 9 of 20 RF3183 Test Condition: VBATT =3.6V, RFIN =1dBm, Temperature=25°C, Tx Frequency=915MHz 2500.00 2400.00 2644.01 2300.00 2644.02 2200.00 2644.03 2100.00 2644.04 2000.00 2644.05 1900.00 2644.06 1800.00 2644.07 2644.08 Icc in 1700.00 mA 1600.00 2644.09 2644.10 1500.00 2644.11 1400.00 2644.12 1300.00 2644.13 1200.00 2644.15 1100.00 2644.21 1000.00 2644.22 900.00 2644.23 2644.24 800.00 0 30 60 90 120 150 180 210 240 270 300 330 2644.25 Phase Angle Figure 3. RF3183 Current Variation Under Mismatch VSWR 3:1 RF3183 operates as a traditional PowerStar® module. The incorporated control loop regulates the collector voltage of the amplifiers while the stages are held at a constant bias. The basic circuit diagram is shown in Figure 2. VBATT 3 dB BW 300 kHz - VRAMP + - Saturation Detector + H(s) RF IN VCC RF OUT TX ENABLE Figure 4. RF3183 Basic Circuit By regulating the collector voltage (VCC), the stages are held in saturation across all power levels. As VCC is decreased, output power decreases as described by Equation 1. The equation shows that load impedance affects output power, but to a lesser degree than VCC supply variations. Since the RF3183 regulates VCC, the dominant cause of power variation is eliminated. 10 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 2 P OUT dBm 2 V CC – V SAT (Eq. 1) = 10 log ------------------------------------------–3 8 R1 10 RF3183 power is ramped up and down through the VRAMP control voltage which in turn controls the collector voltage of the amplifier stages. The RF signal applied at the RFIN pin must be a constant amplitude signal and should be high enough to saturate the amplifier in the GSM mode. The input power (PIN) range is indicated in the specifications. Power levels below this range will result in reduced maximum output power and the potential for more variation of output power over extreme conditions. Higher input power is unnecessary and will require more current in the circuitry driving the power amplifier and will increase the minimum output power of the RF3183. The saturation detector circuit monitors the VBATT and VCC voltages and adjusts the power control loop to prevent the seriespass FET regulator from entering saturation. If the VCC regulator were to saturate, the response time would increase dramatically. This is undesirable because the VCC regulator must accurately follow the burst ramp up or ramp down applied to the VRAMP pin, or the transient spectrum will degrade. Power Ramping and Timing The RF3183 should be powered on according to the Power-On Sequence provided in the datasheet. The power on sequence is designed to prevent operation of the amplifier under conditions that could cause damage to the device or erratic operation. In the Power-On Sequence, there are some set-up times associated with the control signals of the RF3183. The most important of these is the settling time between TXEN going high and when VRAMP can begin to increase. This time is often referred to as the “pedestal” and is required so that the internal power control loop and bias circuitry can settle after being turned on. The RF3183 requires at least 1.5µs or two quarter bit times for proper settling of the power control loop.. Figure 5. ETSI Time Mask for a Single GSM Time Slot The VRAMP waveform used with the RF3183 must be created such that the output power falls into this power versus time mask. The ability to ramp the RF output power to meet ETSI switching transient and time mask requirements partially depends upon the predictability of output power versus VRAMP response of the power amplifier. The PowerStar® control in the RF3183 is very capable of meeting switching transient requirements with the proper raised cosine waveform applied to the VRAMP input. The ramping waveform on VRAMP must not start until after TX_EN is asserted. A ramp of about 12us is required to control switching transients at high power levels. DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 11 of 20 RF3183 The VRAMP voltage range should be limited to min and max values in the specifications to avoid damage or undesirable operation. At some voltage below 0.3V, the CMOS controller switches off and turns off the PA. The effect of this is a discontinuity in the response curve. In order to guarantee minimum switching transients, it is recommended that the minimum ramp voltage be set slightly above the voltage where this discontinuity occurs (See Figure 3). The VRAMP voltage at which the discontinuity occurs is unique to the design of the part and does not shift significantly across process. Figure 7 shows the power versus VRAMP response curve for five parts which represent typical process variation of the discontinuity Test Condition: 824MHz, 3.6VBATT, 1dBm RFIN, 25°C Temp. 40.00 30.00 2644.01 2644.04 20.00 2644.06 2644.07 2644.08 10.00 2644.09 2644.10 0.00 2644.11 2644.12 ‐10.00 2644.13 2644.14 ‐20.00 2644.15 2644.21 2644.22 ‐30.00 2644.23 2644.24 ‐40.00 2644.25 ‐50.00 Figure 6. RF3183 LB POUT versus VRAMP As the VRAMP voltage approaches its maximum, the linear regulator in the CMOS saturates, the output power reaches its maximum level, and the VRAMP versus Output Power curve levels out. The saturation point of the linear regulator is directly proportional to the VBATT supply voltage applied. The VRAMP voltage can be increased above the saturation level, but the PA will not produce any higher output power. It is not recommended to apply a VRAMP voltage above the absolute maximum specification, as the part could be damaged. When the FET pass-device in the linear regulator saturates, the response time of the regulated voltage slows significantly. If the control voltage changes (as in ramp-down) the saturated linear regulator does not react fast enough to follow the ramp-down curve. The result is a discontinuity in the output power ramp and degraded switching transients. This usually occurs at low VBATT levels where the regulated VCC voltage is very near the supply voltage. The RF3183 incorporates a saturation detection circuit which senses if the FET pass-device is entering saturation and reduces VCC to prevent it. This relieves the requirement of the transceiver controller to adjust the maximum VRAMP when the battery voltage is low. Design Considerations There are several key factors to consider in the implementation of a mobile phone transmitter solution using the RF3183: • System efficiency: The RF output match can be designed to improve system efficiency by presenting a non 50 load. Output matching circuits for the RF3183 should be a compromise between system efficiency and power. • Power variation due to supply voltage: 12 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Output power does not vary due to supply voltage under normal operating conditions. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and VBATT approaches its lower operating limit, the output power from the PA will start to drop. This cannot be avoided as a certain supply voltage is required to produce full output power. System specifications must allow for this power decrease. Switching Transients due to low battery conditions are reduced by the saturation detection circuit in RF3183. The saturation detection circuit consists of a feedback loop which detects FET saturation. As the FET approaches saturation, the circuit adjusts the VCC voltage in order to ensure minimum switching transients. The saturation detection circuit is integrated into the CMOS controller and requires no additional input from the user. • Power variation due to temperature RF3183 output power variation due to temperature is largest at low power levels and decreases at the upper power levels. This follows the ETSI specification limits which allow a larger tolerance over extreme conditions at low power levels. Since output power is controlled by an analog input, factors other than the power amplifier will have an effect on total system power variation. The entire system containing the RF3183 should be tested to determine whether compensation is necessary. At high temperatures and low battery voltages, the PA cannot support as high of an output power. In this condition, increasing VRAMP will not provide more output power, so compensation may not provide the intended result. • Noise Power The bias point of the RF3183 is kept constant and the gain in the first stage is always high. This has the effect of maintaining a consistent noise power which does not increase at reduced output power levels. For that reason, noise power is at its highest when VRAMP is at its maximum. The RF3183 does not create enough noise in the receive band to cause system receive band noise power failures, but it may amplify noise from other sources. Care must be taken to prevent noise from entering the power amplifier. • Loop Stability and Loop Bandwidth variation across power levels The design of a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In nonPowerStar® architectures, backing off power causes gain variation which can affect loop bandwidth. In RF3183 the loop bandwidth is determined by VCC regulator bandwidth and does not change over output power. Loop stability is maintained since amplifier bias voltage is constant. • Transient Spectrum Switching transients occur when the up and down power ramps are not smooth enough, or suddenly change shape. If the control slope of a PA has an inflection point within the output power control range, or if the slope is too steep, switching transients will result. In RF3183 all stages are kept constantly biased and the output power is controlled by changing the collector voltage according to Equation 1. Inflection points are eliminated by this design. In addition, the steepness of the power control slope is reduced because VRAMP actively controls output power over a larger voltage range than many other power amplifiers. • Harmonics Harmonics are natural products of high efficiency, saturated power amplifiers. An ideal, class 'E', saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all saturated power amplifiers, there are other factors that contribute to harmonic content as well. With many power control methods, a peak power detector is used to rectify and sense forward power. Through the rectification process, there is additional squaring of the waveform resulting in higher harmonics. The RF3183 has no need for the detector diode; therefore, the harmonics coming out of the PA should represent maximum power of the harmonics throughout the transmit chain. This is based on proper harmonic termination of the transmit port. The receive port termination on antenna switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. These terminations should be adjusted to correct problems with harmonics. DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 13 of 20 RF3183 GMSK Power On/Off Sequence Power On Sequence: 3.2 Vto 4.5 V VBATT >1.5 VHigh Band BAND_SEL <0.7 V LowBand >1.5 V PA ON 1. Apply VBATT 2. Apply BAND_SEL 3. Apply RFIN 4. Apply minimumVRAMP/VBIAS (~0.25V) 5. Apply TX_EN 6. Ramp VRAMPfor desired output power The Power Down Sequence is the reverse order of the Power On Sequence. TX_EN 2.2V for max POUT VRAMP/VBIAS 14 of 20 ~0.25 Vfor min POUT 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Application Schematic DCS RFIN 1 10 DCS RFOUT BAND SEL 2 TX EN 3 VBATT Supply Bypass Capacitor DS100412 4 GND 5 VRAMP 6 GSM RFIN 7 GND 8 Integrated Power Control GSM RFOUT 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 9 15 of 20 RF3183 Evaluation Board Schematic 50 strip 50 strip DCS RFIN 1 BAND SEL 2 10 DCS OUT TX EN 3 VBATT+ Integrated Power Control 4 + C1 68 F 11 GND 5 GND R4 0 6 50 strip 0402 VRAMP 7 R5 DNI 0402 GSM RFIN 50 strip 9 GSM OUT 8 J2 Red Banana Receptacle J3 Black Banana Receptacle VBATT+ 4 3 2 1 J1 4-pin Board-Edge Header Block BAND SEL R1 100 k 0402 VMODE R2 100 k 0402 16 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 Evaluation Board Layout Board Size 2.0” x 2.0” Board Thickness 0.046”, Board Material Rogers RO4003, Multi-Layer RF3183410(1) Package Drawing DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 17 of 20 RF3183 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land and Solder Mask Pattern 18 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412 RF3183 PCB Stencil DS100412 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. 19 of 20 RF3183 Tape and Reel Carrier tape basic dimensions are based on EIA 481. The pocket is designed to hold the part for shipping and loading onto SMT manufacturing equipment, while protecting the body and the solder terminals from damaging stresses. The individual pocket design can vary from vendor to vendor, but width and pitch will be consistent. Carrier tape is wound or placed onto a shipping reel either 330mm (13 inches) in diameter or 178mm (7 inches) in diameter. The center hub design is large enough to ensure the radius formed by the carrier tape around it does not put unnecessary stress on the parts. Prior to shipping, moisture sensitive parts (MSL level 2a-5a) are baked and placed into the pockets of the carrier tape. A cover tape is sealed over the top of the entire length of the carrier tape. The reel is sealed in a moisture barrier ESD bag with the appropriate units of desiccant and a humidity indicator card, which is placed in a cardboard shipping box. It is important to note that unused moisture sensitive parts need to be resealed in the moisture barrier bag. If the reels exceed the exposure limit and need to be rebaked, most carrier tape and shipping reels are not rated as bakeable at 125°C. If baking is required, devices may be baked according to section 4, table 4-1, of Joint Industry Standard IPC/JEDEC J-STD-033. The table below provides information for carrier tape and reels used for shipping the devices described in this document. Tape and Reel RFMD Part Number RF3183TR13 Reel Diameter Inch (mm) 13 (330) Hub Diameter Inch (mm) Width (mm) 4 (102) 12 Pocket Pitch (mm) 8 Feed Single Units per Reel 2500 Unless otherwise specified, all dimension tolerances per EIA-481. Top View Pin 1 Location Sprocket holes toward rear of reel Part Number YYWW Trace Code Part Number YYWW Trace Code Part Number YYWW Trace Code Part Number YYWW Trace Code Direction of Feed Figure 1. 5mmx5mm (Carrier Tape Drawing with Part Orientation) 20 of 20 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or [email protected]. DS100412