19-2434; Rev 0; 7/02 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust The MAX3910 is a 10.7Gbps transimpedance amplifier designed for SONET OC-192/SDH STM-64, DWDM, and 10Gbps systems employing optical amplifiers. Operating from a single +5V or -5.2V supply, it converts a photodiode current into a measurable differential voltage. This product has a linear gain for an input current up to 950µAP-P, and a soft-limiting feature that provides an increasing output swing for an input current up to the 3.5mAP-P overload. An offset adjust circuit and output-level monitors allow for system threshold adjustment. Additional features include back-terminated 50Ω outputs and an integrated 200Ω filter resistor to bias the photodiode. The MAX3910 has a small-signal bandwidth of 9.1GHz and a small-signal transimpedance of 1.65kΩ. The part achieves an input sensitivity of 15.5µAP-P for a BER of 10-12, translating to an optical sensitivity of 19.3dBm for a PIN (r = 0.9, re = 6.6) photo detector and 28.8dBm for an APD (M = 8, ρ = 0.9, re = 10) photo detector. The MAX3910 is fabricated in Maxim’s in-house SiGe process and is available in die form. Features ♦ 950µAP-P Linear Range ♦ 15.5µAP-P Sensitivity ♦ 3.5mAP-P Overload ♦ 1.65kΩ Transimpedance ♦ 9.1GHz Bandwidth ♦ 110mA Supply Current ♦ Output Offset Adjustment ♦ Soft-Limiting Beyond Linear Input Range ♦ Single +5V or -5.2V Power Supply ♦ ESD Protection Ordering Information PART MAX3910U/D Applications TEMP RANGE 0°C to +85°C PIN-PACKAGE Dice* *Dice are designed to operate over a 0°C to +100°C junction temperature (TJ) range, but are tested and guaranteed at TA = +25°C. DWDM Systems OC-192/STM-64 Transmission Systems 10Gbps Systems Using Optical Amplifiers 10Gbps Optical Receivers Typical Operating Circuit VEE VCC MON+ RFILT MON- FILT OUT+ PIN IN LIMITING AMPLIFIER MONIN OUT - MAX3910 OSADJ CHF VEE ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3910 General Description MAX3910 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust ABSOLUTE MAXIMUM RATINGS Storage Ambient Temperature Range (TSTG) ...-55°C to +150°C Die Attach Temperature ..................................................+400°C Operating Temperature Range (Junction Temperature Range)......................-20°C to +120°C Power-Supply Voltage (VCC - VEE) ........................-0.5V to +6.0V Continuous Input Current (IN)............................................4.2mA Continuous Input Current (FILT) ........................................9.8mA Continuous Output Current (OUT+, OUT-) .........................35mA Voltage at CHF, FILT, MON+, MON-, MONIN, OSADJ .................................(VEE - 0.5V) to the lower of +6.0V and (VCC + 0.5V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = 4.75V to 5.5V, TJ = 0°C to +100°C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25°C, unless otherwise noted.) (Notes 1, 2) TYP MAX UNITS Supply Current PARAMETER IEE VEE2 open (Note 3), Figure 1 95 138 mA Supply Current IEE VEE2 connected to negative supply (Note 3), Figure 1 110 158 mA IIN ≤ 450µAP-P, f ≤ 1MHz 23 IIN ≤ 450µAP-P, f ≤ 10MHz (Note 4) 22 Power-Supply Noise Rejection SYMBOL PSNR CONDITIONS MIN Input Bias Voltage ZF IIN ≤ 450µAP-P IIN = 1.0mAP-P IIN = 2.0mAP-P 1.40 Transimpedance (Note 5) Linear Input Current Range ILIN (Note 5) 450 CHF open, IIN ≤ 450µAP-P Low-Frequency Cutoff Photodiode Filter Resistor RFILT VEE + 0.95 VEE + 1.1 1.65 1.37 0.84 1.87 µAP-P 25 0.5 165 200 V kΩ 950 6 CHF = 0.1µF, IIN ≤ 450µAP-P dB 240 10 kHz Ω Output Monitor Resistance To OUT+ or OUT- Single-Ended Output Resistance To VCC 42 50 59 Ω 1.75 1.90 VP-P 0 V Maximum Differential Output Swing VOD (Note 6) 1.45 Single-Ended Output Range VOS Outputs DC-coupled to 50Ω to VCC (Note 6) -1.3 Output DC Offset IIN = 7.5µA DC -7 +7 IIN = 1.4mA DC -10 +10 OSADJ Input Resistance OSADJ Input Range 15 VOSADJ 2 20 -2.1 OSADJ Voltage for Zero Offset Minimum Differential Output Offset kΩ -1.375 VOSADJ = -0.4V, RL = 50Ω to VCC mV kΩ -0.4 V -1.25 -1.125 V -320 -250 mV _______________________________________________________________________________________ 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust (VCC - VEE = 4.75V to 5.5V, TJ = 0°C to +100°C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS Maximum Output Offset VOSADJ = -2.1V, RL = 50Ω to VCC OSADJ Voltage Control Factor: OUT+ (∆VOSADJ)/∆VOUT+ OSADJ Voltage Control Factor: OUT- (∆VOSADJ)/∆VOUT- MIN 250 -3 TYP MAX 320 mV -2 2 UNITS V/V 3 V/V AC ELECTRICAL CHARACTERISTICS (VCC - VEE = 4.75V to 5.5V, TJ = 0°C to +100°C. Typical values are at VEE = -5.2V, VCC = GND, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER Bandwidth SYMBOL BW3dB Input-Referred Noise IN Input Sensitivity Input Overload IOL CONDITIONS IIN ≤ 450µAP-P (Notes 2, 11) MIN TYP 8.2 9.1 MAX GHz (Notes 2, 7) 1.1 (Notes 2, 8) 15.5 1.62 µAP-P 2.5 3.5 mAP-P DC component (Note 9) 1.4 1.8 mA dB 100MHz - 4GHz, IIN ≤ 450µAP-P (Note 2) ±0.75 Gain Ripple 4GHz - BW3dB, IIN ≤ 450µAP-P (Note 2) 1.5 IIN ≤ 450µAP-P 6.2 10.7 450µAP-P ≤ IIN ≤ 2.5mAP-P 7.5 14.6 ≤7.5GHz 10 Single-Ended Output Return Loss (Note 2) µARMS AC component (Note 9) Gain Flatness Deterministic Jitter (Notes 2, 10) UNITS dB psP-P dB Default test conditions: VEE2 and CHF = open (see Figure 1), RL = 50Ω to VCC, DC-coupled at each output, unless otherwise noted. AC characteristics are guaranteed by design and characterization. Note 2: Source capacitance = 0.25pF, source series resistance = 20Ω, and source series inductance = 0.6nH. Output series inductance = 0.5nH at each of the differential outputs. Note 3: Supply current increases as average signal level increases. Maximum supply current is specified for IIN = 1.4mA average current. Typical supply current is specified for IIN ≤ 225µA average current. Note 4: PSNR is measured by detecting the differential output voltage ∆VOUT while applying ∆VEE = 55mVP-P signal on VEE1. PSNR = 20log(∆VEE/∆VOUT). Output offset adjust feature disabled. Note 5: Transimpedance is defined as VOUT(P-P) / IIN(P-P) at 10MHz. Linear range is defined as the input signal level where the transimpedance deviates from the small-signal transimpedance value by no more than 10%. See Figure 2. Note 6: Input current ≤ 2.5mAP-P and ≤ 1.4mA DC. Note 7: Measured with a 4th-order Bessel-Thompson filter with a cutoff frequency of 8GHz. Note 8: Input sensitivity calculated from S/N ≥ 14.1 (BER ≤ 10-12). Note 9: For input signal less than or equal to the input overload, deterministic jitter is guaranteed to be within specifications. Note 10: Deterministic jitter is characterized with 27 - 1 PRBS + eighty 0s + eighty 1s at 10.7Gbps. Note 11: Bandwidth is measured in an electrical environment and corrected to match the conditions of Note 2. Note 1: _______________________________________________________________________________________ 3 MAX3910 DC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VEE = -5.2V, VCC = GND, TA = +25°C, unless otherwise noted.) 1.4mA DC INPUT 105 95 85 225µA DC INPUT 9 2.5mAP-P INPUT 8 7 6 75 65 1600 450µAP-P INPUT -40 -20 0 20 40 60 100 80 1200 10 800 600 400 200 20 30 40 50 60 70 80 90 0 1500 2000 INPUT-REFERRED NOISE 10 15 20 25 MAX3910 toc05 1.40 1.35 INPUT-REFERED NOISE (µARMS) MAX3910 toc04 5 1000 INPUT CURRENT (µAP-P) POWER-SUPPLY NOISE REJECTION POWER-SUPPLY NOISE REJECTION (dB) 500 AMBIENT TEMPERATURE (°C) 0 30 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 35 0.90 0 1 2 3 4 5 6 7 8 9 10 -60 FREQUENCY (MHz) -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) TRANSIMPEDANCE OFFSET ADJUST CIRCUIT 1.6 300 OUTPUT DC OFFSET (mV) 1.4 1.2 1.0 0.8 0.6 200 100 0 -100 0.4 -200 0.2 -300 0 MAX3910 toc07 400 MAX3910 toc06 1.8 TRANSIMPEDANCE (kΩ) END OF LINEAR RANGE 1000 0 0 AMBIENT TEMPERATURE (°C) -400 0 500 1000 1500 INPUT CURRENT (µAP-P) 4 1400 5 -60 MAX3910 toc03 10 1800 DIFFERENTIAL OUTPUT (mVP-P) 115 MAX3910 toc02 VEE2 = OPEN LINEAR RANGE 11 DETERMINISTIC JITTER (psP-P) 125 DETERMINISTIC JITTER MAX3910 toc01 SUPPLY CURRENT SUPPLY CURRENT (mA) MAX3910 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust 2000 2500 -2.25 -1.85 -1.55 -1.05 -0.65 VOSADJ (V) _______________________________________________________________________________________ -0.25 2500 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust ELECTRICAL EYE DIAGRAM (150µAP-P INPUT) MAX3910 toc08 ELECTRICAL EYE DIAGRAM (1mAP-P INPUT) 13ps/div ELECTRICAL EYE DIAGRAM (2.5mAP-P INPUT) MAX3910 toc10 MAX3910 toc09 13ps/div 13ps/div Pad Description PAD NAME FUNCTION 1, 8–16, 31, 32, 33 VEE1 2 MONIN 3, 4, 7 N.C. 5 IN 6 FILT On-Chip Resistor for Photodiode Biasing. Internally connected to VCC through a 200Ω resistor. 17 VEE2 Separate Power Supply for Output Offset Adjustment. Leave open to disable this feature. Offset adjust feature must be disabled for AC-coupled load.* 18, 19, 21, 23, 24, 26, 30 VCC Positive Power-Supply Voltage* 20 OUT- Inverted Data Output with 50Ω Back Termination 22 OUT+ 25 CHF Main Negative Power-Supply Voltage* Monitor Output Providing Replica Current from DC Offset Loop. Internally connected to VCC through 1kΩ resistor. No Connection Signal Input. Connected to photodiode anode. Noninverted Data Output with 50Ω Back Termination Connect a capacitor to ground to increase the on-chip DC-cancellation loop time constant. 27 MON- Monitors DC Voltage at OUT-. Internally connected to OUT- through a 10kΩ resistor. 28 MON+ Monitors DC Voltage at OUT+. Internally connected to OUT+ through a 10kΩ resistor. 29 OSADJ DC Offset Control. Voltage at this pad sets the output DC offset when the offset adjust feature is enabled. (See Figure 3.) *The MAX3910 can operate with a positive supply (VEE = GND) or a negative supply (VCC = GND). 4.75V ≤ (VCC - VEE) ≤ 5.5V. _______________________________________________________________________________________ 5 MAX3910 Typical Operating Characteristics (continued) (VEE = -5.2V, VCC = GND, TA = +25°C, unless otherwise noted.) MAX3910 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust VCC VCC 50Ω MAX3910 RL = 50Ω 50Ω OUT+ VEE1 FILT 200Ω VCC OUT10kΩ RL = 50Ω MON+ REF PIN 10kΩ MONTIA VCC VCC IN VEE1 1.6pF 30kΩ 1.2kΩ OSADJ DC-CANCELLATION LOOP AND CONTROL gm MONIN 90kΩ -1.25V CHF VEE1 VEE2 VEE1 Figure 1. Functional Diagram Detailed Description Figure 1 is a functional diagram of the MAX3910 linear transimpedance amplifier. It comprises a transimpedance amplifier stage, a gain stage, an output buffer, and a DC-cancellation circuit. An output offset adjust circuit is implemented to perform threshold adjust for systems using optical amplifiers. Transimpedance Amplifier The photodiode current flows into the summing node of a high-gain amplifier and a shunt feedback resistor. A DC-cancellation circuit removes the average current, and the AC component is linearly converted into a voltage over a wide input range. DC-Cancellation Loop The DC-cancellation circuit uses low-frequency feedback to remove the DC component of the input signal. This feature centers the input signal within the transimpedance amplifier’s linear range, thereby reducing pulse-width distortion (PWD) on large input signals. The DC-cancellation circuit has a built-in capacitor to achieve a low-frequency cutoff of 25kHz, and an external capaci6 tor bonded between CHF and VCC can be used to further reduce the cutoff frequency. This circuit minimizes PWD for data sequences that exhibit a 50% duty cycle and mark density. A duty cycle or mark density significantly different from 50% causes the MAX3910 to generate PWD. Voltage Amplifier The single-ended signal from the transimpedance amplifier stage is converted to a differential signal and further amplified. Output Buffer In addition to having a wide linear range, the MAX3910 has a soft-limiting feature. For inputs less than 950µAP-P, the MAX3910 operates linearly. Beyond this range, a soft-limiting feature is implemented so that the differential output swing is proportional to the input current, as shown in Figure 2. The output buffer is back-terminated with 50Ω on-chip resistors and can drive either a DCcoupled 50Ω load to VCC, or a 50Ω AC-coupled load. _______________________________________________________________________________________ 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust MAX3910 toc03 1800 DIFFERENTIAL OUTPUT (mVP-P) 1600 1400 ∆VMONIN = 1000(V / A) ∆IINAVE 1200 END OF LINEAR RANGE 1000 800 The voltage at MONIN (VMONIN) serves as a received signal strength indicator (RSSI). The transimpedance gain of the average input current (IINAVE) to VMONIN is typically: Design Procedure 600 Power Supply 400 200 0 0 500 1000 1500 2000 2500 INPUT CURRENT (µAP-P) The MAX3910 requires wideband power-supply decoupling. Power-supply bypassing should provide low impedance between VEE1 and VCC for frequencies up to 10GHz. If the offset-adjust circuit is enabled, it is recommended that the same filtering be applied to VEE2. Photodiode Filter Figure 2. Linear Range of the MAX3910 Offset Adjust Circuit Connecting VEE2 to the negative supply enables the offset adjust circuit. The circuit compares the external voltage applied to the OSADJ pad to an internal (VCC 1.25V) reference to introduce a DC offset at the differential outputs (Figure 3). This function is useful in systems that need threshold adjust. For AC-coupled loads, the circuit must be disabled. The input network of the offset adjust circuit creates a lowpass filter with a cutoff frequency of approximately 85MHz. If the pad is left unconnected, an internal voltage-divider sets the voltage at the pad to (V CC 1.25V). The input impedance is approximately 20kΩ. Supply-voltage noise at the cathode of the photodiode produces a noise current I = CPD ∆V/∆t, which reduces the receiver sensitivity (CPD is the photodiode capacitance). The MAX3910 contains an internal 200Ω resistor between the FILT pad and V CC. Combining this resistor with an external capacitor connected between the FILT pad and VEE1 creates a lowpass filter, which reduces photodiode noise current and improves receiver sensitivity. Current generated by supply-noise voltage is divided between the external capacitance and the photodiode capacitance. Assuming the filter capacitance is much larger than the photodiode capacitance, the input noise current due to supply noise is: INOISE = OFFSET ADJUST CIRCUIT where CFILT is the external capacitance. If the amount of tolerable noise is known, the filter capacitance can be selected easily. 400 300 OUTPUT DC OFFSET (mV) VNOISE × CPD RFILT × CFILT 200 Wire Bonding 100 For high-current density and reliable operation, the MAX3910 uses gold metalization. Connections to the die should be made with gold wire only. Aluminum bonding is not recommended. Die thickness is typically 8mils. Bondwire inductance between the photodiode and the IN pad can be optimized to obtain best performance. Higher inductance improves bandwidth, while lower bondwire inductance reduces time domain ringing. Bondwires on all other pads should be kept as short as possible to optimize performance. The backside of the MAX3910 die is fully insulated and can be connected to VCC or VEE. 0 -100 -200 -300 -400 -2.25 -1.85 -1.55 -1.05 -0.65 VOSADJ (V) Figure 3. Plot of Offset Adjust Circuit Behavior -0.25 _______________________________________________________________________________________ 7 MAX3910 MONIN Pad LINEAR RANGE Input Capacitance Optical Linear Range Noise and bandwidth are adversely affected by capacitance on the MAX3910’s input node. Use any techniques available to minimize input capacitance. The MAX3910 has high gain and operates in a linear range for inputs not exceeding: I × (r + 1) Linear range = 10log LIN e dBm 2 × ρ (re − 1) Output-Coupling Capacitors The outputs of the MAX3910 can be AC- or DC-coupled. For more information on selecting AC-coupling capacitors, visit Maxim’s website and follow the links to HFAN01.1: Choosing AC-Coupling Capacitors. Applications Information Optical Power Relations where ILIN(mAP-P) is the peak-to-peak linear range. Table 1. Optical Power Relations* PARAMETER SYMBOL PIN-PACKAGE Many MAX3910 specifications relate to the input signal amplitude. When working with fiber optic receivers, the input sometimes is expressed in terms of average optical power and extinction ratio. Average PAVG Extinction re re = P1 / P0 Optical Power of a 1 P1 P1 = 2PAVG Optical power relations are shown in Table 1 for an average mark density of 50% and an average duty cycle of 50%. Optical Power of a 0 P0 P0 = 2PAVG / (re + 1) Optical Modulation Amplitude PIN r −1 PIN = P1 - P0 = 2PAVG e re + 1 Optical Sensitivity Calculation The MAX3910 input-referred RMS noise current (IN) generally determines the receiver sensitivity. To obtain a system bit-error rate of 10-12, the signal-to-noise ratio must be 14.1 or better. The input sensitivity, expressed in average power, can be estimated as: 14.1 × IN × (re + 1) Sensitivity = 10log × 1000 dBm 2 × ρ × (re − 1) where ρ is the photodiode responsivity in A/W and IN is measured in amperes. Input Optical Overload The overload is the largest input that the MAX3910 accepts while meeting specifications. Optical overload can be estimated in terms of average power with the following equation: I × (r + 1) Overload = 10log OL e dBm 2 × ρ (re − 1) where IOL(mAP-P) is the DC overload for the MAX3910. 8 PAVG = (P0 + P1) / 2 re re +1 *Assuming a 50% average mark density. P1 OPTICAL POWER MAX3910 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust PAVG PIN P0 TIME Figure 4. Optical Power Relations _______________________________________________________________________________________ 10.7Gbps Linear Transimpedance Amplifier with Output Offset Adjust PROCESS: BiPOLAR SiGe, SOI CHF (25) VCC (26) MON- (27) MON+ (28) VCC (30) OSADJ (29) VEE1 (32) VEE1 (31) Die Size: 1.6mm ✕ 1.6mm VEE1 (33) VEE1 (1) VCC (24) MONIN (2) N.C. (3) VCC (23) N.C. (4) OUT+ (22) VCC (21) IN (5) 63mil (1.6mm) OUT- (20) FILT (6) VCC (19) N.C. (7) VEE2 (17) VEE1 (16) VEE1 (15) VEE1 (14) VEE1 (12) VEE1 (13) CENTER OF PAD (47µm, 47µm) VCC (18) VEE1(11) VEE1 MONIN N.C. N.C. IN FILT N.C. VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VEE1 VCC VCC OUTVCC OUT+ VCC VCC CHF VCC MONMON+ OSADJ VCC VEE1 VEE1 VEE1 TRANSISTOR COUNT: 1291 VEE1 (10) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 COORDINATES (µm) X Y 38 1259 43 1034 43 908 43 782 43 656 43 530 50 282 47 47 173 47 299 47 425 47 551 47 677 47 803 47 929 47 1055 47 1181 47 1255 267 1255 393 1255 519 1255 645 1255 771 1255 897 1255 1055 1172 1259 1046 1259 920 1259 794 1259 668 1259 542 1259 416 1259 290 1259 164 1259 VEE1 (8) NAME VEE1 (9) PAD Chip Information 63mil (1.6mm) Coordinates are in µm from the lower left corner of the circuit die to the center of the pad. For more information, refer to HFAN-08.0.1: Understanding Bonding Coordinates and Physical Die Size. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3910 Pad Coordinates