Flip Chip FBGA (fcCSP) fcFBGA, fcLGA, fcPoP-MLP, Bare Die fcPoP, fcFBGA Hybrid HIGHLIGHTS •A complete portfolio of high to low-end fcCSP packages for all mobile applications, including fcFBGA, fcLGA, flip chip package-on-package (bare die PoP and molded laser PoP) and hybrid flip chip/wirebond solutions •A leader in the development of a broad range of low cost substrate and process technologies for the cost sensitive mobile market •Ultra low flip chip interconnect parasitics eliminates wire inductance and resistance compared to wirebond interconnect •One piece heat spreader can be added for exceptional thermal performance FEATURES • Body sizes 4 x 4mm through 17 x 17mm • Electroplated Eutectic SnPb, hi-Pb or Pb-free bumps or Cu column • Bumping capability down to 130µm pitch with lead-free solder and pitch down to 40µm with Cu column • Full service wafer bumping with BCB and Polyimide dielectric options for wafer repassivation and redistribution layer (RDL) • Molded underfill (MUF) or Capillary underfill (CUF) options • Uniquely developed fcCuBE MR process supports bump pitches down to 80µm and below, providing a lower cost alternative to TCB • Thermal-Compression Bonding with Non-conductive Paste (TCNCP) available • MUF with solder bump and Cu column qualified and in production • 0.40mm min. package ball (BGA) or pad (LGA) pitch in production • 145µm minimum die solder bump pitch in production • BGA pitch down to 0.35mm qualified and in production • Maximum overall height of 1.40mm (fcLFBGA); 1.20mm (fcTFBGA); 1.00mm (fcVFBGA); 0.65mm (fcLGA) • Conventional 2 to 6 layer through-hole or PPG build-up laminate substrates available; ABF build-up substrates available • Low cost substrate technology options including Embedded Trace Substrate (ETS) in HVM, and Via Under Trace (VUT) qualified, NoClean Flux and Non-PI Bumping qualified or HVM, and others such as large die CUF and Land Side Cap (LSC) with 0.4mm BGA pitch in development • One piece heat spreader option for exceptional thermal performance; fcFBGA-ED-H (1-piece heat spreader) with MUF qualified • Packages assembled in either bare die, exposed die and overmolded strip matrix format, and saw singulated; high density wide strip available www.statschippac.com DESCRIPTION STATS ChipPAC’s fcFBGA packages form a subgroup of the Flip Chip package family of the form factor known as Chip Scale Packages (CSP). STATS ChipPAC offers a complete fcFBGA portfolio of high to low-end leading edge packages for all mobile applications including standard fine pitch fcFBGA packages, hybrid flip chip and fcPoP including Bare Die fcPoP and Molded Laser PoP (fcPoP MLP). STATS ChipPAC’s standard fcFBGA packages offering includes very thin profile packages (fcTFBGA, fcVFBGA, fcWFBGA and fcUFBGA), as well as side-by-side die configurations. All fcFBGA packages are produced on substrates with matrix strip format and use overmolding and saw singulation processes similar to wirebond packages of the same form factors. The fcFBGA is an overmolded package with solder balls, and is available in a high thermal performance package (fcFBGA-H) produced on substrates in matrix strip format with heat spreader. fcFBGA packages are also available in very thin profile hybrid flip chip (flip chip on the bottom and wirebond die on the top) such as fcTFBGASD2 and fcTFBGA-SD3. Hybrid fcFBGA packages are available with Mass Reflow (MR), CUF or MUF, and copper (Cu) pillar and Cu wire. STATS ChipPAC’s fcFBGA offering also includes package-on-package (PoP) solutions in Bare Die and Molded Laser formats. Both fcPoP formats are offered as the bottom PoP package (PoPb) of a stackable flip chip BGA. PoPb is typically an application processor or an integrated baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. Bare Die PoP differs from fcBGA through the inclusion of memory interface (MI) pads on the substrate top side. Molded Laser PoP (MLP) offers aggressive package height reductions or 0.35mm MI pitch, and, with its overmold configuration, provides better warpage performance. MLP-PoP is also offered with an exposed die (ED) which reduces mold cap height and improved warpage performance. Flip Chip FBGA (fcCSP) fcFBGA, fcLGA, fcPoP-MLP, Bare Die fcPoP, fcFBGA Hybrid APPLICATIONS SPECIFICATIONS STATS ChipPAC offers a complete fcFBGA portfolio of high to low-end packages for all mobile applications: Package Thickness 0.65 – 1.4mm Die Thickness 250µm - 80µm Minimum Bump Pitch 130µm, Lead-free solder 40µm, Cu column Marking Laser •Mobile processors for Smart Phones, Tablets and Wearable Electronic (WE) devices including baseband, application processors, and application processors + baseband RELIABILITY •Chipsets for peripheral IC’s driven by demand for high-end Smart Phone functionality, including RFIC, PMIC, Connectivity, Sensors/ MEMS, and Audio CODEC Moisture Sensitivity Level Temperature Cycling High Temperature Storage Unbiased HAST JEDEC Level 3 @ 260°C -55°C/125°C, 1000 cycles (typical) 150°C, 1000 hrs (typical) 130°C, 85% RH, 2 atm, 96 hrs (typical) THERMAL PERFORMANCE ELECTRICAL PERFORMANCE Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and solder ball configuration. Simulation for specific applications should be performed to obtain maximum accuracy. Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the constituents of the signal path. Data below is for a fcLFBGA package, body size 13 x 13mm, 6.0 x 8.0mm die size and frequency of 100MHz. Package Body Size Pin Die Size Thermal Performance (mm) Count (mm) ja θ°C/W fcLFBGA fcLFBGA-H* fcLGA 7x7 14 x 14 13 x 13 5 x 6 191 425 144 71 4.46 x 5.65 4.9 x 4.9 5.5 x 5.5 3.8 x 5.0 33.2 14.0 27.7 35.6 Length Inductance (nH) Capacitance (pF) Resistance (mΩ) Self (short) 0.89 Mutual0.24 Self (long) 1.78 Mutual0.51 Notes: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2. *H/S: 0.3mm formed “Hat” type; 100um TIM1 and 100um lid adhesive: 1.75W/mK. 0.65 0.11 0.73 0.12 18.3 32.5 Note: Net = Total Trace Length + Via + Solder Ball. CROSS-SECTIONS fcFBGA fcPOP Market: Smart Phone & Tablets AP+BB processors and BB; Chipsets (RFIC, PA, XCVR, PMIC, Connectivity, etc) Market: Smart Phones AP Processors (AP, AP+BB) fcVFBGA Very thin profile package fcVFBGA-SS2 Very thin profile, 2 die side by side package fcFBGA-ED-H Fine pitch, exposed die with heat spreader Corporate Office Global Offices HYBRIDS Market: Smart Phones & Wearables BB / Modem; BB + Memory + PMU; MCU/ AP + BT+ Sensors (WE) fcVFBGA-PoP fcVFBGA-Hybrid w/CUF Very thin profile, bare die PoP Very thin profile hybrid Wirebond - Flip Chip fcVFBGA-MLP PoP fcWFBGA-Hybrid Fine Pitch Cu Column Very thin profile, molded laser PoP fcVFBGA MLP PoP-ED Very very thin profile hybrid Wirebond - Flip Chip Very thin profile, molded laser, exposed die PoP fcVFBGA Hybrid-SS2, Cu wire Very thin profile, 2 die side by side, stacked hybrid 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 SWITZERLAND 41-22-929-5658 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. July 2014