IPD Integrated Passive Devices - a Chip Scale Module Package Technology DESCRIPTION WiMAX Balanced Filter GSM Balan & Coupler FEATURES • Embedded RLC components with excellent performance • Resistors to 100,000 ohms • Capacitors range: 0.2pF-100pF • Inductors to 30nH • IPD diplexers, filters for wireless applications • Compact baluns for RF applications • Computerized component generation for fast flawless design (1st run silicon success is typical) • Library RLC components, filters and baluns for GSM, DCS, PCS, GPS, WiMAX and WLAN a/b/g • Full electrical models of all library components • Full foundry services available • Foundry matrix mask space available • Packaging available in QFN, FBGA, FLGA and eWLB formats Chip Scale Module Packaging (CSMP) is an advanced system-inpackage (SiP) solution which features a modular architecture that integrates mixed IC technologies and a wide variety of passive devices (IPD) such as resistors, capacitors, inductors, filters, baluns, transceivers, receivers and interconnects directly onto a silicon substrate. The result is a high performance system level solution, which provides a significant reduction in die size, weight, number of interconnections and system board space requirements, and can be used for many applications. Enabling IPD Technology STATS ChipPAC’s IPD technology is a key enabler of its innovative CSMP offering which features silicon-based passive integration of RLC components. IPDs are a cost effective way to reduce footprint, reduce interconnection complexity, improve component tolerance, yield and reliability. By integrating and fabricating passive devices at the silicon wafer level, STATS ChipPAC is able to fabricate IPDs which are significantly smaller, thinner and with higher performance than standard passive devices. To achieve superior IPD performance, STATS ChipPAC employs a copper metallization process capable of depositing 8 microns or more of copper on a silicon wafer. This results in higher Q components that reduce loss in the RF signal transmission path, thereby increasing battery performance of the wireless system and improving reception. The size of matching circuitry and filters is often reduced by 40%. IPD Component Library STATS ChipPAC’s foundry service includes fully characterized resistor, capacitor, inductor, filter and balun libraries, complete with full electrical models of all library components for packages such as QFN, FBGA, FLGA and eWLB. In addition to standard IPD library solutions, customized IPD designs are also available. Refer to the IPD Products Databook (2nd edition) for a comprehensive list of IPD products that can be integrated into RF SiP solutions. Sample Filter Library APPLICATIONS • RF Power Amplifier Matching/Filters/Couplers • Front End Modules (FEM) • GSM/DCS and CDMA cellular phones • Wireless LAN 802.11 a/b/g and WiMAX systems • 802.11a/b/g and WiMAX filters • GPS Systems • Functional Interposers • Baluns from 750MHz-6GHz • Multi-band RF Transceivers • Miniaturization of RF Systems www.statschippac.com A Comprehensive RF Solution STATS ChipPAC provides the highest level integration of wireless systems. With leading edge technology in CSMP, IPD, eWLB, 3D packaging and a comprehensive RF solutions portfolio, including wafer sort, design, assembly, RF test and supply chain management, STATS ChipPAC offers RF semiconductor companies a complete turnkey solution and distinct competitive advantage in their market. IPD Chip Scale Module Package - Integrated Passive Device RELIABILITY SPECIFICATIONS Die Thickness Gold Wire Marking Packing Options 250mm (nom) 1.0mil Laser mark (black or white) JEDEC tray / tape and reel THERMAL PERFORMANCE, θja (°C/W) Package Body Size (mm) 230 FBGA-CSMP 15 x 15mm (2L) Moisture Sensitivity Level Temperature Cycling UHAST (laminate package) High Temperature Storage Pressure Cooker Test (WLCSMP) Liquid Thermal Shock Die Size (mm) JEDEC Level 1 -65°C/150C, 1000 cycles 130°C, 85% RH, 96 hrs 150°C, 500 hrs 121°C 100% RH, 2 atm, 168 hrs -65°C/150°C, 500 cycles Simulated Values θja, C/W 7.5 x 8.0 24.9 104 fcLGA-CSMP 15 x 15mm (4L) 10.5 x 10.5 23.6 Notes: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-7, JESD51-9) under natural convection as defined in JESD51-2 ELECTRICAL PERFORMANCE Package Body Size (mm) 230 LFBGA-CSMP Frequency SPICE Model or S-Parameter 100MHz or 1.0GHz Values are influenced by final design 15 x 15mm (4L) 100MHz or 1.0GHz Values are influenced by final design 6 x 6mm (1L or 2L) 100MHz or 1.0GHz Values are influenced by final design 15 x 15mm (2L) 104 fcFLGA-CSMP eWLB RDL CROSS-SECTIONS PACKAGE CONFIGURATIONS WLCSMP (Wafer-Level Chip Scale Module Package) Module Size Ball Pitch Ball Diameter IPD Tile FC Die 0201 Passives FBGA-CSMP - LFBGA packages with body sizes up to and including 15 x 15 sq. mm. Refer to STATS ChipPAC’s FBGA datasheet. FLGA-CSMP - FLGA packages with body sizes up to 15 x 15 sq. mm. Refer to STATS ChipPAC’s FLGA datasheet. 10 x 10 x 1.0mm, 38 I/O 0.8mm 0.55mm minimum 10 x 10 x 0.45mm 3x 6x WLCSMP - CSMP package with body size of 10 x 10 sq. mm. eWLB - IPD integrated in eWLB package with body size of 6 x 6 sq. mm or less. Die FBGA-CSMP IPD - Standalone IPDs (balun, diplexer, LPF, BPF, etc.) for RF applications. Refer to STATS ChipPAC’s IPD Product Databook (2nd ed.) for a complete product list. Substrate IPD Si Spacer fcFLGA-CSMP IPD integrated in eWLB with Silicon IC A sample eWLB module containing a CMOS power amplifier chip (on the right) and an IPD chip (on the left). The IPD chip is used for matching and filtering functions. The interconnection between the CMOS chip and the IPD chip is made by RDL through the eWLB process. Silicon die IPD die Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 Global Offices USA 510-979-8000 JAPAN 81-3-3507-5676 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 SWITZERLAND 41-21-8047-200 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. Jan 2014