fcBGA datasheet

Flip Chip BGA
A JCET Company
fcBGA, fcBGA-SiP, fcBGA-H, fcBGA-MPM
HIGHLIGHTS
•Low cost, breakthrough, high performance packages
•Superior thermal solutions
•Package options ranging from bare die, stiffener only,
and one/two piece heat spreader
• ABF buildup to 6-2-6; core thickness down to 200um;
coreless substrate and grounded lid for high electrical
performance
•Green flip chip solution with Pb-free, copper (Cu) column bump and halogen-free material sets
FEATURES
• Body sizes range from 12mm x 12mm to 55mm x 55mm
• Pb-free, Cu column, Eutectic or High Pb bumps (Cu column micro
bumps in development)
• Cu column with Mass Reflow (MR)
• Bump pitch qualified: 130µm for Pb-free; 80µm for Cu column
• 0.8mm BGA pitch
• 40/32/28/20nm Si nodes with Extra/Ultra Low K die electric
• Nitride, Polyimide, PBO wafer passivations qualified & in production • Ni-Au, Ni-Pd-Au, SOP (solder-on-pad), OSP (organic solderable
preservative) and immersion Sn finish
• Bumped wafer thinning down to 100mm for non-molded fcBGA
• 200mm (printed, plated) and 300mm (plated) bumped wafers;
RDL with 200mm and 300mm bumped wafers
• Seamless integration of flip chip, SMT and in-line open/short
testing operations
• F/A metrology tools for rapid diagnostics and debugging, including TDR, CSAM, X-ray, Ion milling and SEM
• All packages qualified to JEDEC specifications and/or custom
requirements based on end applications
APPLICATIONS
STATS ChipPAC offers a complete fcBGA portfolio of high to low-end
packages for the Network, Computing and Consumer markets.
• Networking solutions (ASIC, ASSP, Logic and others) for small cell
base stations, network storage driven by Cloud computing and high
speed/bandwidth Ethernet/network processors
• Computing solutions for DDR4/5 Memory/Datacenter CPU, hybrid/
Tablet APU, Graphics Processing Units (GPU), HDD storage migrating
to flip chip, HDD/memory market
• Consumer solutions for DTVs, STBs , Game Consoles and the IOT
(Smart Wired home)
www.cj-elec.com www.statschippac.com
DESCRIPTION
Flip Chip Ball Grid Array packages (fcBGA) form a subgroup of the
Flip Chip package family. The fcBGA package is the main platform
in this sub-group, which also includes bare die, stiffener only and a
thermally enhanced version with one/two piece heat spreader or lid
(fcBGA-H), System-in-Package (fcBGA-SiP) versions and a package
subsystem meeting the standard BGA footprint that contains multiple
components within the same package (fcBGA-MPM). Options also
include configurations with thin core, Pb-free and copper column
bumps. STATS ChipPAC’s Flip Chip BGA packages are available in ball
counts ranging from 220 to 3000+, body sizes from 12 x 12mm to
55 x 55mm.
STATS ChipPAC offers a complete fcBGA portfolio for the network,
computing and consumer markets. Demand for greater functionality
and significantly higher processing speeds in consumer and networking
devices is driving flip chip technology to provide cost effective, scalable
packages with ultra low K dielectrics, high power integrity, superior
thermal performance and higher resistance to electromigration (EM) in
very large package sizes, with very fine bump pitches and lead-free solder.
Flip Chip interconnection provides the ultimate in miniaturization,
reduced package parasitics and enables new paradigms in the area
of power and ground distribution to the chip not feasible with other
traditional packaging approaches. STATS ChipPAC offers full turnkey
services ranging from design through production, including high speed,
high pin count digital and RF testing.
Flip Chip BGA
A JCET Company
fcBGA, fcBGA-SiP, fcBGA-H, fcBGA-MPM
SPECIFICATIONS
RELIABILITY
Die Thickness Bump Pitch
Marking
Packing Options
Moisture Sensitivity Level
100µm - 760µm
Minimum 125µm area array
Laser
JEDEC tray
JEDEC Level 4 or 3 (peak temp 230°, 245° or 260°)
Temperature Cycling
-55°C/125°C, 1000 cycles (typical)
High Temperature Storage
150°C, 1000 hrs (typical)
Unbiased HAST
130°C, 85% RH, 96 hrs (typical)
THERMAL PERFORMANCE Body Size (mm) Ball Count
31
35
40
40
45
θjc Natural θja (°C/W)
(°C/W)
Convection
1 m/s
Die Size (mm)
792
964
1161
1417
1732
9.6
11.1
12.8
15.1
17.4 1.1
0.8
0.6
0.4
0.3
14.0 / 10.0*
12.5 / 8.9*
11.2 / 8.0*
10.7 / 7.6*
9.0 / 6.5*
11.8 / 6.0*
11.0 / 5.5*
9.4 / 4.8*
8.7 / 4.3*
7.5 / 3.9*
2 m/s
11.0 / 5.7*
10.0 / 5.2*
8.4 / 4.4*
7.7 / 4.0*
6.5 / 3.5*
Notes: *Includes heat sink (0.5” tall, channel design). Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2 or forced
convection defined in JESD51-6.
ELECTRICAL PERFORMANCE
Parametric Data: Sample Embedded Micro-Stripline Configuration
Metal Thickness
Prepreg
Solder Mask
Thickness(d1) Thickness(d2)
Trace
Trace
Width(w) Spacing(s)
Inductance
(nH/mm)
Capacitance
Ind. Trace
Diff. Pair (pF/mm) Lossy Z11@1GHz Lossy Zdiff@1GHz
Lossy Propagation Delay
Even Mode Odd Mode
25µm
0.408
0.109
69.9Ω 84.1Ω 6.10ps/mm 6.54ps/mm
15µm 40µm
35µm 25µm 40µm
0.414
0.097
70.9Ω 100.4Ω 6.12ps/mm 6.39ps/mm
Conductor material = copper
Prepreg material dialetric constant = 3.4@1GHz
Solder mask material dielectric constant = 3.9@1GHz
Parametric Data: Sample Stripline Configuration
Metal Thickness
Prepreg
Thickness(d)
Trace
Width(w)
Trace
Spacing(s)
40µm
25µm
25µm
0.323
0.126
54.6Ω
81.6Ω
6.37ps/mm 6.46ps/mm
50µm
0.329
0.117
55.5Ω
99.0Ω
6.38ps/mm 6.40ps/mm
15µm
Inductance
(nH/mm)
Capacitance
(pF/mm)
Ind. Trace
Diff. Pair
Lossy Z11@1GHz Lossy Zdiff@1GHz
Lossy Propagation Delay
Even Mode
Odd Mode
Conductor material = copper
Prepreg material dialetric constant = 3.4@1GHz
Solder mask material dielectric constant = 3.9@1GHz
CROSS SECTIONS
fcBGA with stiffener
fcBGA-H-SiP with Cu column
fcBGA-MPM-SiP
Corporate Office
Global Offices
10 Ang Mo Kio St. 65, #04-08/09 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823
USA 510-979-8000
CHINA 86-21-5976-5858
KOREA 82-32-340-3114
SWITZERLAND 41-22-929-5658
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Pte. Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes
only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such
information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right
to change the information at any time and without notice.
©Copyright 2016. STATS ChipPAC Pte. Ltd. All rights reserved.
Apr 2016