Bare Die fcPoP Flip Chip Package-on-Package: fcVFBGA-PoPb, fcWFBGA-PoPb HIGHLIGHTS • Stacking fully tested memory and logic packages eliminates known good die (KGD) issues • Package-on-package stacking provides flexibility in mixing and matching IC technologies • Devices can be procured from multiple manufacturing sources • Meets accepted package and board level reliability standards for CSP • Flip Chip enables higher performance, higher density, finer top PoP ball pitch and a smaller/thinner PoP solution FEATURES • CuOSP or Ni/Au on bottom pads of bottom PoP (PoPb) with lead-free ball options • Ni/Au on top memory interface pads of PoPb • Die thickness down to 70µm proven • Supports 0.4mm minimum ball pitch on bottom/BGA pads & as low as 0.4mm pitch on top memory interface pads of PoPb • Capable process with 45nm and 28nm FAB technology in both lead-free and eutectic flip chip bumps • Advanced UF process maximizes allowable die size in package, with 35µm chip gap height • Bottom PoP package thickness of 0.7mm max with 70µm thick flip chip die & 4 layer BU substrate • Optimization of materials to meet warpage requirements during surface mount process • Full in-house electrical, thermal and mechanical simulation and measurement capability • Full in-house package and substrate design capability • Turnkey solution including wafer bumping in both eutectic SnPb & lead-free solder APPLICATIONS • PoPb: Application, baseband or multimedia processor for mobile handset and portable devices • PoPt: Memory to support system and processor functions including DDR, Flash (NAND, NOR), SRAM and combinations thereof TEST SERVICES • Product Engineering support • Probe capability • Program generation/conversion • Drop Ship available www.statschippac.com DESCRIPTION STATS ChipPAC’s Package-on-Package (PoP) family includes a stackable flip chip BGA as the bottom PoP package (PoPb). PoPb is typically an application processor or a baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. PoPt, with memory devices stacked within, is assembled, tested and yielded independently. The two packages are combined by reflowing together (usually performed simultaneously) on the application board to form PoP (Z-interconnection with solder ball). ADVANTAGES PoP has emerged as the preferred approach to integrate memory and logic in many advanced mobile and handheld applications. The bottom logic package and top memory package can be assembled, tested and yielded independently. This business model is preferred by end users as they can leverage their usual suppliers for these device types independently and have the flexibility to match logic processor and memory to support different applications. STATS ChipPAC has always been at the forefront of 3D packaging and stacked die packaging. The wirebonded bottom PoP package was developed and introduced into production years ago. The bottom fcPoP provides the advantage of denser design with larger die size and higher number of IOs within the same PoP package body size / form factor as compared to the wirebonded PoP version. In addition, the use of fcPoP allows for potentially lower PoPb package height, thus reducing the total package stacked height post-SMT process. Improved device electrical performance can also be expected with the fcPoP package as with all other Flip Chip packages in comparison to wirebonded designs. Bare die fcPoP package offers the lowest cost PoP package type and can use down to 0.4mm memory interface (MI) pitch. Bare Die fcPoP Flip Chip Package-on-Package: fcVFBGA-PoPb, fcWFBGA-PoPb SPECIFICATIONS (fcPoP) RELIABILITY Die Thickness FC Bump Pitch FC Bumps* Solder Balls Marking Packing Options Moisture Sensitivity Level JEDEC Level 2A (60% RH/60°C), 120 hrs Temperature Cycling Condition B (-55°C/+125°C, 1000 cycles Temp/Humidity Test 85°C/85% RH, 1000 hrs Highly Accelerated Stress Test 135°C/85% RH, 96 hrs High Temp Storage 150°C, 1000 hrs Minimum 70µm Minimum 150µm (Pb-free) Miminum 80µm/40µm (Cu/SnAg) Pb-free, eutectic Sn/Pb, Cu column Sn/Ag/Cu (Pb-free ball) Laser JEDEC tray or tape & reel *Refer to fcCuBE datasheet for PoP package details using Cu column interconnect. THERMAL PERFORMANCE, θja (°C/W)* Thermal behavior is determined by the exact configuration of the overall structure and the distribution of power dissipation among all of the die. During the package design process, we provide quick-turn thermal feasibility analysis and data as needed to help ensure proper thermal operation. Package Leads 12x12mm fcPoP 14x14mm fcPoP 753 641 Die Size (mm) 7 x 7 x 0.1 8 x 8 x 0.1 Power (W) 2 2 TA (ºC) 25.0 25.0 Airflow (m/s) NC** NC** θja (ºC/W) 23.4 22.5 TJ (ºC) 71.9 70.0 Notes: *Typical bottom fcPoP thermal performance. Data for bottom PoP only without the effect of top PoP package. Substrate 4 layer laminate build-up (1/2/1). Simulation data for package mounted on 4 layer PCB per JEDEC JES51-9 under natural convection. **NC=Natural Convection ELECTRICAL PERFORMANCE The electrical behavior is highly dependent on the package layout and the substrate structures. 3D electrical simulation is used to predict the actual electrical behavior once designs are partially or fully completed. As expected, the electrical performance advantage of using flip chip over wirebond is seen in these packages. CROSS-SECTIONS PACKAGE CONFIGURATIONS Wirebond Bottom fcPoP (PoPb) Bare Die PoP No Flip Chip Interconnect Pb-free Cu/SnAg Body Size BGA Pitch 10x10 ~ 15x15 min 0.4 (mm x mm) (mm) Top Pitch (mm) 0.5 0.4 fcVFBGA-PoPb Pre-Stacked fcPoP (PoPb + PoPt) Pre-stacked PoP: Bare Die PoPb + Memory PoPt TFBGA-PoPt-SD3 + fcVFBGA-PoPb Reference data: fcVFBGA-PoPb < 0.7mm maximum Corporate Office Global Offices 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 USA 510-979-8000 CHINA 86-21-5976-5858 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 SWITZERLAND 41-22-929-5658 The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. Trademark registered in United States. Singapore company registration number 199407932D. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document. STATS ChipPAC reserves the right to change the information at any time and without notice. ©Copyright 2014. STATS ChipPAC Ltd. All rights reserved. May 2014