SSM4957(G)M DUAL P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement D2 Lower gate charge D1 D1 Fast switching characteristics SO-8 -30V BV DSS D2 G1 S1 R DS(ON) 24mΩ ID -7.7A G2 S2 Description D2 D1 Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G2 G1 S2 S1 The SSM4957M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low-voltage applications. This device is available with Pb-free lead finish (second-level interconnect) as SSM4957GM. Absolute Maximum Ratings Symbol Parameter VDS Drain-Source Voltage VGS Gate-Source Voltage ID @ TA=25°C ID @ TA=100°C Total Power Dissipation V V -7.7 A 3 -6.1 A -30 A 2 W 1 PD @ TA=25°C -30 ± 20 Continuous Drain Current Pulsed Drain Current Units 3 Continuous Drain Current IDM Rating Linear Derating Factor 0.016 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C Thermal Data Symbol Rthj-a 10/21/2004 Rev.1.01 Parameter Thermal Resistance Junction-ambient 3 Max. www.SiliconStandard.com Value Unit 62.5 °C/W 1 of 5 SSM4957(G)M Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. -30 - - V - -0.02 - V/°C VGS=-10V, ID=-7A - - 24 mΩ VGS=-4.5V, ID=-5A - - 36 mΩ VDS=VGS, ID=-250uA -1 - -3 V BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA RDS(ON) Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS 2 VDS=-10V, ID=-7A - 12 - S o VDS=-30V, VGS=0V - - -1 uA o Drain-Source Leakage Current (Tj=70 C) VDS=-24V, VGS=0V - - -25 uA Gate-Source Leakage VGS=±20V - - ±100 nA ID=-7A - 27 45 nC Drain-Source Leakage Current (Tj=25 C) IGSS VGS=0V, ID=-250uA Max. Units 2 Qg Total Gate Charge Qgs Gate-Source Charge VDS=-24V - 5 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 18 - nC VDS=-15V - 14 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=-1A - 11 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=-10V - 38 - ns tf Fall Time RD=15Ω - 25 - ns Ciss Input Capacitance VGS=0V - 1670 2670 pF Coss Output Capacitance VDS=-25V - 530 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 435 - pF Min. Typ. IS=-1.7A, VGS=0V - - -1.2 V Source-Drain Diode Symbol VSD Parameter 2 Forward On Voltage 2 Test Conditions Max. Units trr Reverse Recovery Time IS=-7A, VGS=0V, - 35 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 34 - nC Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad. 10/21/2004 Rev.1.01 www.SiliconStandard.com 2 of 5 SSM4957(G)M 120 120 -10V o -10V 100 -ID , Drain Current (A) -ID , Drain Current (A) o T A = 150 C T A = 25 C 100 -7.0V 80 60 -5.0V -4.5V 40 20 80 -7.0V 60 40 -5.0V -4.5V 20 V G =-3.0V V G =-3.0V 0 0 0 1 2 3 4 5 6 7 8 0 -V DS , Drain-to-Source Voltage (V) 2 3 4 5 6 7 -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 48 1.6 ID=-5A T A =25°C ID=-7A V G =-10V 1.4 Normalized R DS(ON) 40 RDS(ON) (mΩ ) 1 32 1.2 1.0 24 0.8 0.6 16 3 5 7 9 -50 11 0 50 100 150 o -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 7 2.0 6 1.5 Normalized -VGS(th) (V) -IS(A) 5 4 T j =150 o C T j =25 o C 3 2 1.0 0.5 1 0.0 0 0 0.2 0.4 0.6 0.8 1 1.2 -50 0 Fig 5. Forward Characteristic of Reverse Diode 10/21/2004 Rev.1.01 50 100 150 T j , Junction Temperature ( o C) -V SD , Source-to-Drain Voltage (V) Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM4957(G)M f=1.0MHz 10000 ID= -7A V DS = - 24 V 10 8 C iss C (pF) -VGS , Gate to Source Voltage (V) 12 6 1000 C oss 4 C rss 2 0 100 0 10 20 30 40 50 60 1 5 9 13 17 21 25 29 -V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1 100 Normalized Thermal Response (Rthja) Duty factor=0.5 10 -ID (A) 1ms 10ms 1 100ms 0.1 1s T A =25 o C Single Pulse DC 0.01 0.2 0.1 0.1 0.05 0.02 0.01 PDM 0.01 t Single Pulse T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135oC/W 0.001 0.1 1 10 100 0.0001 0.001 0.01 -V DS , Drain-to-Source Voltage (V) Fig 9. Maximum Safe Operating Area 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Waveform 10/21/2004 Rev.1.01 Charge Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM4957(G)M Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/21/2004 Rev.1.01 www.SiliconStandard.com 5 of 5