SSM9575M/GM P-CHANNEL ENHANCEMENT-MODE POWER MOSFET Simple drive requirement BV DSS D D Low on-resistance R DS(ON) D D Fast switching characteristics -60V 90mΩ -4A ID G SO-8 S S S Description D Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G S The SSM9575M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. This device is available with Pb-free lead finish (second-level interconnect) as SSM9575GM. Absolute Maximum Ratings Symbol Parameter VDS Drain-Source Voltage VGS Gate-Source Voltage ID @ TA=25°C ID @ TA=100°C Rating Units -60 V ± 25 V 3 -4 A 3 -3.2 A Continuous Drain Current Continuous Drain Current 1 IDM Pulsed Drain Current -20 A PD @ TA=25°C Total Power Dissipation 2.5 W Linear Derating Factor 0.02 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C Thermal Data Symbol Rthj-a 12/02/2004 Rev.2.01 Parameter Thermal Resistance Junction-ambient 3 Max. www.SiliconStandard.com Value Unit 50 °C/W 1 of 5 SSM9575M/GM Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. -60 - - V - -0.04 - V/°C VGS=-10V, ID=-4A - - 90 mΩ VGS=-4.5V, ID=-3A - - 120 mΩ VDS=VGS, ID=-250uA -1 - -3 V BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA RDS(ON) Static Drain-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS 2 VDS=-10V, ID=-4A - 7 - S o VDS=-60V, VGS=0V - - -1 uA o Drain-Source Leakage Current (Tj=70 C) VDS=-48V, VGS=0V - - -25 uA Gate-Source Leakage VGS=±25V - - ±100 nA ID=-4A - 18 28 nC Drain-Source Leakage Current (Tj=25 C) IGSS VGS=0V, ID=-250uA Max. Units 2 Qg Total Gate Charge Qgs Gate-Source Charge VDS=-48V - 5 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 7 - nC VDS=-30V - 12 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=-1A - 5 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=-10V - 68 - ns tf Fall Time RD=30Ω 32 - ns Ciss Input Capacitance VGS=0V - 1745 2790 pF Coss Output Capacitance VDS=-25V - 165 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 125 - pF Min. Typ. IS=-2A, VGS=0V - - -1.2 V Source-Drain Diode Symbol VSD Parameter 2 Forward On Voltage 2 Test Conditions Max. Units trr Reverse Recovery Time IS=-4A, VGS=0V, - 56 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 146 - nC Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 125°C/W when mounted on min. copper pad. 12/02/2004 Rev.2.01 www.SiliconStandard.com 2 of 5 SSM9575M/GM 55 45 -10V -7.0V -5.0V o 50 T A = 25 C 35 40 -ID , Drain Current (A) -ID , Drain Current (A) 45 -4.5V 35 -10V -7.0V -5.0V -4.5V o TA=150 C 40 30 25 20 15 30 25 20 15 10 10 V G = -3.0 V V G = -3.0 V 5 5 0 0 0 3 6 9 12 15 0 3 -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 9 12 15 18 Fig 2. Typical Output Characteristics 2.0 87.5 I D = -4 A V G =-10V 1.8 ID=-3A T A =25°C 1.6 Normalized R DS(ON) 82.5 RDS(ON) (mΩ ) 6 -V DS , Drain-to-Source Voltage (V) 77.5 1.4 1.2 1.0 0.8 72.5 0.6 0.4 67.5 3 5 7 9 -50 11 -V GS , Gate-to-Source Voltage (V) 0 50 100 150 o T j , Junction Temperature ( C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 4 3 3 -VGS(th) (V) -IS(A) 2 2 T j =150 o C T j =25 o C 1 1 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 Fig 5. Forward Characteristic of Reverse Diode 12/02/2004 Rev.2.01 50 100 150 o -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9575M/GM f=1.0MHz 10000 I D = -4A V DS = - 48 V 10 8 C iss C (pF) -VGS , Gate to Source Voltage (V) 12 6 1000 4 2 C oss C rss 100 0 0 10 20 30 1 40 5 9 13 17 21 25 29 -V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 10 -ID (A) 1ms 10ms 1 100ms 0.1 1s T A =25 o C Single Pulse DC 0.2 0.1 0.1 0.05 0.02 0.01 PDM t 0.01 Single Pulse T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W 0.001 0.01 0.1 1 10 100 1000 0.0001 0.001 0.01 -V DS , Drain-to-Source Voltage (V) Fig 9. Maximum Safe Operating Area 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Waveform 12/02/2004 Rev.2.01 Charge Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9575M/GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 12/02/2004 Rev.2.01 www.SiliconStandard.com 5 of 5