SSM9922(G)EO
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Low on-resistance
Capable of 2.5V gate drive
G2
S2
Ideal for DC/DC battery applications
D2
BV DSS
20V
RDS(ON)
15mΩ
6.8A
ID
S2
TSSOP-8
S1
G1
S1
D1
Description
D1
Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, ultra low on-resistance and
cost-effectiveness.
G1
D2
G2
S1
S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM9922GEO.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
VDS
Drain-Source Voltage
20
V
VGS
Gate-Source Voltage
±12
V
3
ID @ TA=25°C
Drain Current , VG S @ 4.5V
6.8
A
ID @ TA=70°C
3
5.4
A
Drain Current , VGS @ 4.5V
1
IDM
Pulsed Drain Current
25
A
PD @ TA=25°C
Total Power Dissipation
1
W
Linear Derating Factor
0.008
W/°C
TSTG
Storage Temperature Range
-55 to 150
°C
TJ
Operating Junction Temperature Range
-55 to 150
°C
Thermal Data
Symbol
Rthj-a
Rev.2.01 12/06/2004
Parameter
Thermal Resistance Junction-ambient
3
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Max.
Value
Unit
125
°C/W
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SSM9922(G)EO
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Typ.
Max. Units
20
-
-
V
BVDSS
Drain-Source Breakdown Voltage
∆ BV DSS/ ∆ Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
-
0.05
-
V/°C
RDS(ON)
Static Drain-Source On-Resistance 2
VGS=4.5V, ID=6A
-
-
15
mΩ
VGS=2.5V, ID=4A
-
-
20
mΩ
VDS=VGS, ID=1mA
0.5
-
1.2
V
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
IDSS
VDS=4.5V, ID=6A
-
22
-
S
o
VDS=20V, VGS=0V
-
-
25
uA
o
Drain-Source Leakage Current (Tj=70 C)
VDS=16V ,VGS=0V
-
-
100
uA
Gate-Source Leakage
VGS=±12V
-
-
±10
uA
ID=6A
-
25
40
nC
Drain-Source Leakage Current (Tj=25 C)
IGSS
VGS=0V, ID=250uA
Min.
2
Qg
Total Gate Charge
Qgs
Gate-Source Charge
VDS=16V
-
3
-
nC
Qgd
Gate-Drain ("Miller") Charge
VGS=4.5V
-
9
-
nC
2
td(on)
Turn-on Delay Time
VDS=15V
-
11
-
ns
tr
Rise Time
ID=1A
-
12
-
ns
td(off)
Turn-off Delay Time
RG=3.3Ω , VGS=4.5V
-
47
-
ns
tf
Fall Time
RD=15Ω
-
23
-
ns
Ciss
Input Capacitance
VGS=0V
-
1730 2770
pF
Coss
Output Capacitance
VDS=20V
-
280
-
pF
Crss
Reverse Transfer Capacitance
f=1.0MHz
-
240
-
pF
Rg
Gate Resistance
f=1.0MHz
-
2.2
-
Ω
Min.
Typ.
IS=0.84A,VGS=0V
-
-
1.2
V
Source-Drain Diode
Symbol
VSD
Parameter
Forward On Voltage
2
2
Test Conditions
Max. Units
trr
Reverse Recovery Time
IS=6A, VGS=0V,
-
24
-
ns
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
-
18
-
nC
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
2
3.Surface mounted on 1 in copper pad of FR4 board ; 208°C/W when mounted on min. copper pad.
Rev.2.01 12/06/2004
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SSM9922(G)EO
50
50
5.0V
4.5V
3.5V
2.5V
T A =25 C
ID , Drain Current (A)
40
40
30
V G =1.8V
20
30
V G =1.8V
20
10
10
0
0
0
1
1
2
2
0
3
V DS , Drain-to-Source Voltage (V)
1
1
2
2
3
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
35
1.6
ID=4A
T A =25°C
ID=6A
V G = 4.5 V
1.4
Normalized R DS(ON)
30
RDS(ON) (mΩ )
5.0V
4.5V
3.5V
2.5V
o
T A = 150 C
ID , Drain Current (A)
o
25
20
1.2
1.0
0.8
15
0.6
10
0
2
4
6
8
10
-50
12
0
50
100
150
T j , Junction Temperature ( o C)
V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
2.0
6
5
Normalized VGS(th) (V)
1.5
IS(A)
4
3
T j =150 o C
2
T j =25 o C
1.0
0.5
1
0
0.0
0
0.2
0.4
0.6
0.8
1
-50
0
Fig 5. Forward Characteristic of
Reverse Diode
Rev.2.01 12/06/2004
50
100
150
T j , Junction Temperature ( o C)
V SD , Source-to-Drain Voltage (V)
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
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SSM9922(G)EO
f=1.0MHz
10000
12
VGS , Gate to Source Voltage (V)
ID=6A
V DS = 10 V
V DS = 12 V
V DS = 16 V
C iss
C (pF)
9
1000
6
3
C oss
C rss
100
0
0
10
20
30
40
50
1
60
5
Q G , Total Gate Charge (nC)
9
13
17
21
25
V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Normalized Thermal Response (Rthja)
Duty factor=0.5
100us
1ms
10
ID (A)
10ms
1
100ms
1s
0.1
T A =25 o C
Single Pulse
DC
0.2
0.1
0.1
0.05
0.02
0.01
PDM
t
0.01
T
Single Pulse
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=208°C/W
0.001
0.0001
0.01
0.1
1
10
0.0010
0.0100
100
Fig 9. Maximum Safe Operating Area
0.1000
1.0000
10.0000
100.0000
t , Pulse Width (s)
V DS , Drain-to-Source Voltage (V)
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
td(on) tr
td(off) tf
Fig 11. Switching Time Waveform
Rev.2.01 12/06/2004
Charge
Q
Fig 12. Gate Charge Waveform
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SSM9922(G)EO
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
Rev.2.01 12/06/2004
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