SY89540U

SY89540U
Precision Low Jitter 4x4 LVDS Crosspoint
Switch with Internal Termination
General Description
The SY89540U is a low-jitter, low skew, high-speed
4x4 crosspoint switch optimized for precision telecom
and enterprise server/storage distribution applications.
The SY89540U guarantees data-rates up to 3.2Gbps
over temperature and voltage.
The SY89540U differential input includes Micrel’s
unique, 3-pin input termination architecture that
directly interfaces to any differential signal (AC or DCcoupled) as small as 100mV (200mVpp) without any
level shifting or termination resistor networks in the
signal path. The LVDS compatible outputs maintain
extremely fast rise/fall times guaranteed to be less
than 120ps.
The SY89540U features a patent-pending isolation
design that significantly improves on channel-tochannel crosstalk performance.
The SY89540U operates from a 2.5V ±5% supply and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY89540U is part of Micrel’s
®
high-speed, Precision Edge product line.
All support documentation can be found on Micrel’s
web site at www.micrel.com.
Typical Performance
Precision Edge
®
Features
• Provides crosspoint switching between any input
pairs to any output pair
• Patent pending, channel-to-channel isolation design
provides superior crosstalk performance
• Guaranteed AC performance over temperature and
voltage:
• DC-to-3.2Gbps throughput
– <480ps propagation delay
– <120ps rise/fall time
– <30ps output-to-output skew
• Ultra-low jitter design:
– 95fs RMS phase jitter (Typ)
– 0.7psRMS crosstalk induced jitter
• Patent pending 50Ω input termination, extended
CMVR, and VT pin accepts DC- and AC-coupled
differential inputs
• 350mV LVDS output swing
• Power supply 2.5V ±5%
• –40°C to +85°C temperature range
• Available in 44-pin (7mm x 7mm) QFN package
• Pb-Free Green package
Applications
• All SONET/SDH channel select applications
• All Fibre Channel multi-channel select applications
• All Gigabit Ethernet multi-channel select
applications
Precision Edge is a registered trademark of Micrel, Inc.
Oct. 1, 2013
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SY89540U
Functional Block Diagram
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SY89540U
Ordering Information(1)
Part Number
Package
Type
Temperature
Range
SY89540UMY
QFN-44
QFN-44
SY89540UMYTR
(2)
Package Marking
Lead
Finish
Industrial
SY89540U with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
Industrial
SY89540U with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electrical only.
2. Tape and Reel ordering option.
Pin Configuration
44-Pin QFN
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Pin Description
Pin Number
Pin Name
Pin Function
17, 15,
10, 8
4, 2
41, 39
IN0, /IN0,
IN1, /IN1,
IN2, /IN2,
IN3, /IN3
Differential Inputs: These input pairs are the differential signal inputs to the
device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin
of a pair internally terminates to a VT pin through 50Ω. Note that these inputs
will default to an indeterminate state if left open. Please refer to the "Input
Interface Applications" section for more details.
16, 9,
3, 40
VT0, VT1,
VT2, VT3
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT pins provide a center-tap to a termination network for
maximum interface flexibility. See "Input Interface Applications" section for more
details.
14,
11,
1,
42
VREF_AC0,
VREF_AC1,
VREF_AC2,
VREF_AC3
Reference Voltage: This output biases to VCC–1.2V. It is used when ACcoupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each
VREF-AC pin with a 0.01F low ESR capacitor. See "Input Interface
Applications" section for more details.
18, 19
SIN0,
SIN1
These single-ended TTL/CMOS-compatible inputs address the data inputs.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and
will default to a logic HIGH state if left open.
38, 37
SOUT0,
SOUT1
These single-ended TTL/CMOS-compatible inputs address the data outputs.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and
will default to logic HIGH state if left open.
5, 7
CONF,
LOAD
These single-ended TTL/CMOS-compatible inputs control the transfer of the
addresses to the internal multiplexers. See "Address Tables" and "Timing
Diagram" sections for more details. Note that these inputs are internally
connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left
open.
Configuration Sequence
1. Load: Loads configuration into buffer, while Configuration Buffer holds
existing switch configuration.
2. Configuration: Loads new configuration into the Configuration Buffer and
updates switch configuration.
Buffer Mode
The SY89540U defaults to buffer mode (IN to Q) if the load and configuration
control signals are not exercised.
23, 24,
26, 27,
29, 30,
32, 33
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
6, 22, 25,
28, 31, 34
VCC
12, 13, 20,
21,35, 36,
43, 44
GND,
Exposed pad
Oct., 1, 2013
Differential Outputs: These LVDS output pairs are the outputs of the device.
Please refer to the truth table below for details. Unused output pairs may be left
open. Each output is designed to drive 350mV into 100Ω across the pair.
Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and
place as close to each VCC pin.
Ground. GND and EPad must both be connected to the same ground.
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SY89540U
The SY89540 can be switched from crosspoint mode
to a 1:4 fanout buffer simply by providing a LOW-toHIGH pulse to the LOAD and CONFIG pins. The input
configuration (SIN0:1) will select the desired input
signal while the output switch will buffer the selected
input signal. To get the same desired input to all four
outputs (1:4), LOAD and CONFIG must be repeated
four times to cover all outputs (i.e., SOUT0:1 must go
through all four output combinations, repeated by
LOAD and CONFIG).
Functional Description
Buffer Mode
SY89540 can be used as a 1:4 fanout buffer. This is
the default mode with LOAD and CONFIG being HIGH
when the device is first powered up. The SIN0 and
SIN1 inputs select the input signal that will be buffered.
Regardless of the output switch selection, the input
signal will be buffered to all four outputs.
Crosspoint Mode
SY89540 can be programmed to take differential input
signals from any input and buffer the signals to one or
more outputs. Prior to configuring SIN and SOUT,
LOAD and CONFIG must be LOW. To program the
desired I/O combination, follow the following
sequence:
1) Select the desired input with the SIN0 and
SIN1 inputs and the output with the SOUT0
and SOUT1.
2) Pulse the LOAD with a positive pulse to load
SIN and SOUT.
3) Pulse the CONFIG pin with a positive pulse to
latched the I/O configuration.
4) This method can be used to create
independent paths between inputs and
outputs. Below is the truth table to create a 4:4
buffer where IN0 -> Q3, IN1 -> Q2, IN2 -> Q1,
and IN3 -> Q0:
Input
SIN1
SIN0
SOUT1
SOUT0
Load
IN0
0
0
1
1
0
IN1
IN2
IN3
0
1
1
1
0
1
1
0
0
1
0
0
Config.
Output
0
Q3
0
Q2
0
Q1
0
Q0
0
0
0
Table 1. 4:4 Buffer Truth Table
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SY89540U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) .......................... –0.5V to +4.0V
Input Voltage (VIN) ..................................–0.5V to VCC
CML Output Voltage (VOUT) .... VCC–1.0V to VCC+5.0V
(3)
Termination Current
Source or sink current on VT .................. ±100mA
Input Current
Source or sink current on IN, /IN .............. ±50mA
VREF-AC Current
Source or sink current on VREF-AC ............... ±2mA
Lead Temperature (soldering, 20sec.) ............. 260°C
Storage Temperature (Ts) ............... –65°C to +150°C
Supply Voltage (VCC) .................. +2.375V to +2.625V
Ambient Temperature (TA) ................ –40°C to +85°C
(4)
Package Thermal Resistance
QFN (JA)
Still-air ............................................................ 23°C/W
QFN (JB)
Junction-to-board ........................................... 12°C/W
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply
VCC = 2.5V
2.375
2.5
2.625
V
ICC
Power Supply Current
No load, max. VCC.
200
280
mA
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
80
100
120
Ω
RIN
Input Resistance
(IN-to-VT, /IN-to-VT)
40
50
60
Ω
VIH
Input HIGH Voltage
(IN, /IN)
1.2
VCC
V
VIL
Input LOW Voltage
(IN, /IN)
0
VIH–0.1
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 1a.
0.1
1.7
V
VDIFF_IN
Differential Input Voltage
|IN, /IN|
See Figure 1b.
0.2
IN-to-VT
Maximum Input Voltage
|IN-to-VT|
VREF-AC
Reference Voltage
VCC–1.3
V
VCC–1.2
1.28
V
VCC–1.1
V
Notes:
1.
Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a
stress rating only and functional operation is not implied for conditions other than those detailed in the operational
sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device
reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Due to limited drive capability use for input of the same package only.
4.
Assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.  JB uses a 4-layer
JA in still-air unless otherwise stated.
5.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been
established.
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SY89540U
LVDS Outputs DC Electrical Characteristics
VCC = 2.5V ±5%, TA = –40°C to +85°C, RL = 100Ω across Q and /Q, unless otherwise noted.
Symbol
Parameter
VOH
Output HIGH Voltage
(Q, /Q)
VOL
Output LOW Voltage
(Q, /Q)
VOUT
Output Voltage Swing
(Q, /Q)
See Figure 1a.
250
350
mV
VDIFF_OU
Differential Output Voltage Swing
|Q – /Q|
See Figure 1b.
500
700
mV
VOCM
Output Common Mode Voltage
(Q, /Q)
See Figure 4b.
1.125
1.275
V
VOCM
Change in Common Mode Voltage
(Q, /Q)
See Figure 4b.
–50
+50
mV
Max
Units
VCC
V
0.8
V
30
µA
T
Condition
Min
Typ
Max
Units
1.475
V
0.925
V
LVTTL/CMOS DC Electrical Characteristics
VCC = 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
Oct., 1, 2013
Condition
Min
2.0
–125
–300
VIL = 0V
7
Typ
µA
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SY89540U
AC Electrical Characteristics(7)
VCC = 2.5V ±5%, TA = –40°C to +85°C, RL = 100Ω across each output pair, unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
fMAX
Maximum Operating Frequency
NRZ Data
3.2
4
Gbps
tPD
Propagation Delay
Clock, VOUT ≥200mV
4
GHz
IN-to-Q
280
CONFIG-to-Q
350
tPD
Tempco
tS
380
Max
480
Ω
800
160
Set-up Time
SIN-to-LOAD
SOUT-to-LOAD
LOAD-to-CONFIG
CONFIG-to-LOAD
Units
fs/°C
800
800
800
950
ps
th
Hold Time
LOAD-to-SIN, LOAD-to-SOUT
800
ps
tPW
Minimum LOAD and CONFIG
Pulse Width
800
ps
tSKEW
Output-to-Output Skew
Part-to-Part Skew
Note 8
Note 9
tJITTER
RMS Phase Jitter
Output = 622MHz
30
150
95
ps
ps
fs
Integration Range 12kHz – 20MHz
tr , t r
Crosstalk-Induced Jitter
Note 10
Rise/Fall Times
At full output swing (20% to 80%)
40
80
0.7
psRMS
120
ps
Notes:
7.
High frequency AC-parameters are guaranteed by design and characterization.
8.
Output to output skew is measured between two different outputs under identical transitions. Input voltage swing is
100mV.
9.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew
of the edges at the respective inputs.
10. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is
measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to
each other at the inputs.
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SY89540U
Single-Ended and Differential Swing
Figure 1b. Differential Voltage Swing
Figure 1a. Single-Ended Voltage Swing
Timing Diagram
Figure 2. Timing Diagram
Truth Tables
Input Select Address Table
Output Select Address Table
SIN1
SIN0
Input
SOUT1
SOUT0
Output
0
0
IN0
0
0
Q0
0
1
IN1
0
1
Q1
1
0
IN2
1
0
Q2
1
1
IN3
1
1
Q3
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SY89540U
Typical Operating Characteristics
VCC = 2.5, VIN = 100mV, at 25°C.
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Functional Characteristics
VCC = 2.5, VIN = 100mV, at 25°C.
Clock Pattern
Data Pattern
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Input and Output Stage Internal
Termination
Output Stage Internal Termination
On a nominal 1.25V common mode above ground,
LVDS specifies a small swing of 350mV, typical. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as
a function of data input, is kept to a minimum to
keep EMI low.
Figure 3. Simplified Differential Input Stage
Figure 4a. LVDS Differential Measurement
Figure 4b. LVDS Common Mode Measurement
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Input Interface Applications
Figure 5a. LVPECL Interface
(DC-Coupled)
Figure 5b. LVPECL Interface
(AC0Coupled)
Figure 5d. CML Interface
(AC-Coupled)
Figure 5e. LVDS Interface
Figure 5c. CML Interface
(DC-Coupled)
Related Product and Support Documentation
Part Number
Function
Datasheet Link
SY58540U
Ultra Precision 4x4 CML Crosspoint Switch
w/Internal I/O Termination
http:///www.micrel.com/product-info/products/sy89540u.shtml
HBW Solutions
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
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SY89540U
Package Information
44-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended
for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a
significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a
Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
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