THAN0078_Rev.1.1_E Application Note THAN0078_Rev.1.1_E THC63LVD823(B)/THC63LVD824A Application Note Mode settings, System Diagram and PCB Design Guide Copyright©2010 THine Electronics, Inc. 1/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 1.Mode Settings THC63LVD823(B) MODE1 Input mode H: Single L: Dual MODE0 Output mode H: Single L: Dual DDRN DDR H or Hi-Z: DDR off L: DDR on O/E Output Enable Output Disable(Hi-Z) H H * L Output Enable(Fig2-1,3-1) H H * H Output Disable(Hi-Z) H L * L Output Enable/DDR off(Fig2-2,3-4) H L H or Hi-Z H Output Enable/DDR on(Fig2-3,3-4) H L L H Output Disable(Hi-Z) L H * L Output Enable(Fig2-4,3-2) L H * H Output Disable(Hi-Z) L L * L Output Enable(Fig2-5,3-5) L L * H Input/Output Single In/ Single Out Single In/ Dual Out Dual In/ Single Out Dual In/ Dual Out Option - THC63LVD824A MODE1 Output mode Input/Output Single In/ Dual Out Dual In/ Dual Out Copyright©2010 THine Electronics, Inc. Option L: Dual MODE0 Input mode H: Single L: Dual Output Enable(Fig2-6,3-1) L H Output Enable(Fig2-7,3-5) L L 2/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 2.Signal Flow for Each Setting THC63LVD823(B) Single In / Single Out CLK Frequency f Data Rate f Hi-z Or H or L Fix R1[7:0] G1[7:0] B1[7:0] Hysnc Vsync DE CLKIN CLK TA1+/Frequency TB1+/f TC1+/TD1+/Data Rate TCLK1+/f R2[7:0] G2[7:0] B2[7:0] TA2+/TB2+/TC2/TD2+/TCLK2+/- Hi-z Fig2-1 Single In / Dual Out DDR off R1[7:0] G1[7:0] B1[7:0] Hysnc1 Vsync DATA Rate DE f CLKIN CLK Frequency f Hi-z Or H or L Fix Single In / Dual Out DDR on CLK TA1+/Frequency TB1+/f/2 TC1+/TD1+/DATA Rate TCLK1+/f/2 CLK TA2+/Frequency TB2+/f/2 TC2/TD2+/DATA Rate TCLK2+/f/2 R2[7:0] G2[7:0] B2[7:0] R1[7:0] G1[7:0] B1[7:0] Hysnc Vsync DATA Rate DE f CLKIN CLK Frequency f/2 Hi-z Or H or L Fix CLK TA1+/Frequency TB1+/f/2 TC1+/TD1+/DATA Rate TCLK1+/f/2 CLK TA2+/Frequency TB2+/f/2 TC2+/TD2+/DATA Rate TCLK2+/f/2 R2[7:0] G2[7:0] B2[7:0] =TCLK1+/- =TCLK1+/- Fig2-2 Fig2-3 Dual In / Single Out Dual In / Dual Out R1[7:0] CLK G1[7:0] Frequency B1[7:0] f Hysnc Vsync Data Rate DE f CLKIN CLK TA1+/Frequency TB1+/2f TC1+/TD1+/Data Rate TCLK1+/2f R2[7:0] Data Rate G2[7:0] f B2[7:0] TA2+/TB2+/TC2+/TD2+/TCLK2+/- Hi-z R1[7:0] CLK Frequency G1[7:0] B1[7:0] f Hysnc Data Rate Vsync DE f CLKIN CLK TA1+/Frequency TB1+/f TC1+/TD1+/Data Rate TCLK1+/f R2[7:0] Data Rate G2[7:0] f B2[7:0] CLK TA2+/Frequency TB2+/f TC2+/TD2+/Data Rate TCLK2+/f =TCLK1+/- Fig2-4 Fig2-5 Single In / Dual Out Dual In / Dual Out THC63LVD824A R1[7:0] CLK G1[7:0] Frequency B1[7:0] f Hysnc Vsync Data Rate DE f CLKOUT CLK RA1+/Frequency RB1+/2f RC1+/RD1+/Data Rate RCLK1+/2f Hi-z Or H or L Fix RA2+/RB2+/RC2+/RD2+/RCLK2+/- R2[7:0] G2[7:0] B2[7:0] Data Rate f CLK RA1+/Frequency RB1+/f RC1+/RD1+/Data Rate RCLK1+/f R1[7:0] CLK G1[7:0] Frequency B1[7:0] f Hysnc Vsync Data Rate DE f CLKOUT CLK RA2+/Frequency RB2+/f RC2+/RD2+/Data Rate RCLK2+/f R2[7:0] G2[7:0] B2[7:0] Data Rate f Synchronous to RCLK1+/- Fig2-6 Copyright©2010 THine Electronics, Inc. Fig2-7 3/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 3.TTL DATA Timing Diagram Following are THC63LVD823(B) TTL data input timing example for SXGA+(1400 x 1050). HSYNC DE DotCLK R1x/G1x/B1x #1 #3 #5 #7 1395 #1397 #1399 R2x/G2x/B2x #2 #4 #6 #8 1396 #1398 #1400 #1 #2 #1399 #1400 TFT Panel (1400 x 1050) Note: 1) R1x MSB R17 R16 R15 R14 R13 R12 R11 LSB R10 G1x G17 G16 G15 G14 G13 G12 G11 G10 B1x B17 B16 B15 B14 B13 B12 B11 B10 R2x R27 R26 R25 R24 R23 R22 R21 R20 G2x G27 G26 G25 G24 G23 G22 G21 G20 B2x B27 B26 B25 B24 B23 B22 B21 B20 2) For single and dual link applications, min. pulse width of HSYNC/VSYNC/DE are 2pixels. Copyright©2010 THine Electronics, Inc. 4/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 1) Single Link(1) Example : THC63LVD823(B) : Falling edge / 8bit / Single in(TTL)-Single out(LVDS) THC63LVD824A : Falling edge / 8bit / Single in(LVDS)-Dual out(TTL) / Output driverbility Low VCC VCC F.Bead F.Bead THC63LVD823(B) THC63LVD824A LVCC VCC GND LVDS VCC 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF LGND VCC PVCC *1 JP RS 0.01uF PGND PLL VCC 0.1uF 0.001uF ohm twist 0.1uF 0.001uF R17 - R10 8 G17 - G10 8 B17 - B10 8 RA1- TA1- CLKIN ohm RA1+ HSYNC VSYNC DE 8 8 8 TB1- /PDWN OPEN RB1+ /PDWN R17 - R10 8 G17 - G10 8 B17 - B10 8 ohm RC1+ TC1+ RCLK1- TCLK1- ohm RCLK1+ TCLK1+ TD1- ohm TA2- OPEN OPEN RA2- TA2+ OPEN OPEN RA2+ TB2- OPEN OPEN RB2- TB2+ OPEN OPEN RB2+ TC2- OPEN OPEN RC2- TC2+ OPEN OPEN RC2+ TCLK2- OPEN OPEN RCLK2- TCLK2+ OPEN OPEN RCLK2+ TD2- OPEN OPEN RD2- TD2+ OPEN OPEN RD2+ MAP DDRN PRBS N/C HSYNC VSYNC DE R27 - R20 8 G27 - G20 8 B27 - B20 8 RD1RD1+ TD1+ VCC *2 MAP CLKOUT RC1- TC1- R27 - R20 G27 - G20 B27 - B20 RB1ohm TB1+ R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE MODE1 MODE0 R/F DRVSEL pair Cable or PCB trace MODE1 MODE0 OE R/F 0.1uF 0.001uF LVDS GND PLL GND TA1+ CLKIN (25~112MHz) /PDWN VCC GND CLKOUT (12.5~56MHz) /PDWN R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE R17 - R10 G17 - G10 B17 - B10 *3 PCB(Transmitter) *1 : If RS pin tied to VCC, LVDS swing is 350mV. If RS pin tied to GND, LVDS swing is 200mV. *2: Refer to datasheet Copyright©2010 THine Electronics, Inc. GND GND PCB(Receiver) Fig3-1 *3: Connect each PCB GND 5/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 2) Single Link(2) Example : THC63LVD823(B) : Falling edge / 8bit / Dual in(TTL)-Single out(LVDS) THC63LVD824A : Falling edge / 8bit / Single in(LVDS)-Dual out(TTL) / Output driverbility Low VCC VCC F.Bead F.Bead THC63LVD823(B) THC63LVD824A LVCC VCC GND 0.1uF 0.001uF 0.1uF 0.001uF VCC PVCC JP RS 0.01uF CLKIN (12.5~56MHz) /PDWN 8 R17 - R10 8 G17 - G10 8 B17 - B10 PGND MODE1 MODE0 OE R/F /PDWN 8 R27 - R20 8 G27 - G20 8 B27 - B20 0.1uF 0.001uF ohm twist 0.1uF 0.001uF MODE1 MODE0 R/F DRVSEL RA1- ohm TA1+ RA1+ TB1- RB1- CLKOUT RB1+ /PDWN CLKOUT (12.5~56MHz) /PDWN R17 - R10 8 G17 - G10 8 B17 - B10 8 R17 - R10 G17 - G10 B17 - B10 ohm RC1- TC1- ohm RC1+ TC1+ RCLK1- TCLK1- ohm RCLK1+ TCLK1+ TD1- ohm TA2- OPEN OPEN RA2- TA2+ OPEN OPEN RA2+ TB2- OPEN OPEN RB2- TB2+ OPEN OPEN RB2+ TC2- OPEN OPEN RC2- TC2+ OPEN OPEN RC2+ TCLK2- OPEN OPEN RCLK2- TCLK2+ OPEN OPEN RCLK2+ TD2- OPEN OPEN RD2- TD2+ OPEN OPEN RD2+ MAP DDRN PRBS N/C HSYNC VSYNC DE R27 - R20 8 G27 - G20 8 B27 - B20 8 RD1RD1+ TD1+ VCC OPEN PLL VCC TB1+ R27 - R20 G27 - G20 B27 - B20 0.1uF 0.001uF LVDS GND PLL GND TA1- CLKIN HSYNC VSYNC DE VCC GND pair Cable or PCB trace R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE MAP 0.1uF 0.001uF LGND *1 *2 LVDS VCC HSYNC VSYNC DE R27 - R20 G27 - G20 B27 - B20 *3 PCB(Transmitter) *1 : If RS pin tied to VCC, LVDS swing is 350mV. If RS pin tied to GND, LVDS swing is 200mV. *2: Refer to datasheet Copyright©2010 THine Electronics, Inc. GND GND PCB(Receiver) Fig3-2 *3: Connect each PCB GND 6/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 3) Single Link(3) Example : THC63LVD823(B) : Falling edge / 6bit / Dual in(TTL)-Single out(LVDS) THC63LVD824A : Falling edge / 6bit / Single in(LVDS)-Dual out(TTL) / Output driverbility Low VCC VCC F.Bead F.Bead THC63LVD823(B) THC63LVD824A LVCC VCC GND LVDS VCC 0.1uF 0.001uF 0.1uF 0.001uF 0.1uF 0.001uF LGND VCC PVCC *1 JP RS 0.01uF PGND MODE1 MODE0 OE R/F PLL VCC 0.1uF ohm twist 0.001uF pair Cable or PCB trace 0.1uF 0.001uF TA1- 6 R17 - R12 6 G17 - G12 B17 - B12 6 RA1- TA1+ RA1+ HSYNC VSYNC DE HSYNC VSYNC DE 6 R27 - R22 6 G27 - G22 B27 - B22 6 2 2 2 2 2 2 TC1TC1+ CLKOUT RC1- /PDWN CLKOUT (12.5~56MHz) /PDWN R17 - R12 6 G17 - G12 6 B17 - B12 6 R17 - R12 G17 - G12 B17 - B12 RC1+ TCLK1- RCLK1ohm TCLK1+ TD1TD1+ RCLK1+ VCC OPEN RD1- ohm OPEN ohm TA2- OPEN TA2+ OPEN OPEN TB2- OPEN OPEN TB2+ OPEN OPEN TC2- OPEN OPEN TC2+ OPEN OPEN TCLK2- OPEN OPEN OPEN OPEN OPEN OPEN RD2- OPEN OPEN RD2+ R11 - R10 G11 - G10 B11 - B10 R21 - R20 G21 - G20 B21 - B20 TCLK2+ TD2TD2+ OPEN HSYNC VSYNC DE HSYNC VSYNC DE R27 - R22 6 G27 - G22 6 B27 - B22 6 RD1+ ohm VCC OPEN RB1+ ohm R27 - R22 G27 - G22 B27 - B22 MAP DDRN PRBS N/C RB1ohm TB1+ /PDWN R17 - R12 G17 - G12 B17 - B12 MODE1 MODE0 R/F DRVSEL ohm CLKIN 0.1uF 0.001uF LVDS GND PLL GND TB1CLKIN (12.5~56MHz) /PDWN VCC GND R27 - R22 G27 - G22 B27 - B22 2 OPEN R11 - R10 G11 - G10 2 OPEN 2 B11 - B10 OPEN R21 - R20 2 OPEN G21 - G20 2 OPEN B21 - B20 2 OPEN RA2RA2+ RB2RB2+ RC2RC2+ RCLK2RCLK2+ *2 PCB(Transmitter) *1 : If RS pin tied to VCC, LVDS swing is 350mV. If RS pin tied to GND, LVDS swing is 200mV. Copyright©2010 THine Electronics, Inc. GND GND PCB(Receiver) Fig3-3 *2: Connect each PCB GND 7/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 4) Dual Link(1) Example : THC63LVD823(B) : Falling edge/ 8bit / Single in(TTL)-Dual out(LVDS) / DDR Off or On THC63LVD824A : Falling edge / 8bit / Dual in(LVDS)-Dual out(TTL) / Output driverbility Low Note1: tDEINT = tTCIP*2n (n=integer) Note2: tDEINT >= 4*tTCIP Note3: tDEH >= 2k*tTCIP, tDEL >= 2m*tTCIP (k,m = integer) (tDEINT = DE Period, tTCIP = CLKIN Period, tDEH = DE High Time, tDEL = DE Low Time ) *2 VCC VCC F.Bead F.Bead THC63LVD823(B) THC63LVD824A LVCC VCC GND LGND 0.1uF 0.001uF LVDS VCC 0.1uF 0.001uF 0.1uF 0.001uF VCC *1 RS 0.01uF 0.1uF 0.001uF LVDS GND PLL VCC PVCC JP VCC GND PLL GND PGND MODE1 MODE0 OE R/F 0.1uF 0.001uF ohm twist pair Cable or PCB trace 0.1uF 0.001uF MODE1 MODE0 R/F DRVSEL RA1- TA1ohm *4 CLKIN CLKIN /PDWN /PDWN 8 R17 - R10 8 G17 - G10 8 B17 - B10 HSYNC VSYNC DE 8 8 8 RA1+ TB1- RB1- CLKOUT RB1+ /PDWN *4 ohm TB1+ R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE TA1+ ohm RC1+ TC1+ ohm RCLK1+ TCLK1+ R27 - R20 G27 - G20 B27 - B20 ohm RD1+ TD1+ HSYNC VSYNC DE R27 - R20 8 G27 - G20 8 B27 - B20 8 RD1- TD1- R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE RCLK1- TCLK1- /PDWN R17 - R10 8 G17 - G10 8 B17 - B10 8 RC1- TC1- CLKOUT R17 - R10 G17 - G10 B17 - B10 RA2- TA2ohm RA2+ TA2+ RB2- TB2ohm RB2+ TB2+ *2 MAP DDRN OPEN MAP DDRN PRBS N/C RC2- TC2ohm RC2+ TC2+ RCLK2- TCLK2ohm RCLK2+ TCLK2+ RD2- TD2ohm RD2+ TD2+ *3 PCB(Transmitter) *1 : If RS pin tied to VCC, LVDS swing is 350mV. If RS pin tied to GND, LVDS swing is 200mV. *2: Refer to datasheet Copyright©2010 THine Electronics, Inc. GND *3: Connect each PCB GND 8/13 *4 Fig3-4 PCB(Receiver) GND DDR off on CLKIN 50~150MHz 25~75MHz CLKOUT 25~75MHz 12.5~37.5MHz THine Electronics, Inc. THAN0078_Rev.1.1_E 5) Dual Link(2) Example : THC63LVD823(B): Falling edge / 8bit / Dual in(TTL)-Dual out(LVDS) THC63LVD824A : Falling edge / 8bit / Dual in(LVDS)-Dual out(TTL) / Output driverbility Low VCC VCC F.Bead F.Bead THC63LVD823(B) THC63LVD824A LVCC LVDS VCC VCC GND 0.1uF 0.001uF LGND 0.1uF 0.001uF 0.1uF 0.001uF VCC *1 RS 0.01uF 0.1uF 0.001uF LVDS GND PLL VCC PVCC JP VCC GND PLL GND PGND MODE1 MODE0 OE R/F 0.1uF 0.001uF 0.1uF 0.001uF ohm twist pair Cable or PCB trace MODE1 MODE0 R/F DRVSEL RA1- TA1ohm CLKIN (25~85MHz) /PDWN CLKIN R17 - R10 8 G17 - G10 8 B17 - B10 8 R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE R27 - R20 8 G27 - G20 8 B27 - B20 8 RA1+ TB1- RB1- CLKOUT RB1+ /PDWN ohm /PDWN HSYNC VSYNC DE TA1+ TB1+ R17 - R10 8 G17 - G10 8 B17 - B10 8 RC1- TC1ohm RC1+ TC1+ RCLK1- TCLK1ohm RCLK1+ TCLK1+ R27 - R20 G27 - G20 B27 - B20 8 R27 - R20 G27 - G20 8 B27 - B20 8 RD1- TD1ohm RD1+ TD1+ HSYNC VSYNC DE CLKOUT (25~85MHz) /PDWN R17 - R10 G17 - G10 B17 - B10 HSYNC VSYNC DE R27 - R20 G27 - G20 B27 - B20 RA2- TA2ohm RA2+ TA2+ RB2- TB2ohm VCC *2 MAP OPEN RB2+ TB2+ MAP DDRN PRBS N/C RC2- TC2ohm RC2+ TC2+ RCLK2- TCLK2ohm RCLK2+ TCLK2+ RD2- TD2ohm RD2+ TD2+ *3 PCB(Transmitter) *1 : If RS pin tied to VCC, LVDS swing is 350mV. If RS pin tied to GND, LVDS swing is 200mV. *2: Refer to datasheet Copyright©2010 THine Electronics, Inc. GND GND PCB(Receiver) Fig3-5 *3: Connect each PCB GND 9/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 4. Note 1)Output Control THC63LVD823(B) /PDWN OE Input(TTL) Output(LVDS) L L Open or Hi-z Hi-z L L Input CLK Hi-z L H Open or Hi-z Hi-z L H Input CLK Hi-z H L Open or Hi-z Hi-z H L Input CLK Hi-z H H Open or Hi-z Hi-z H H Input CLK *1 Data, CLK Out THC63LVD824A /PDWN Input(LVDS) Output(TTL) L Open or Hi-z All Low L Input CLK All Low H Open or Hi-z Unstable H Input CLK *1 *2 Data *2, CLK Out *1 With in the range of Recommended Operating Conditions. Refer to Recommended Operating Conditions on data sheet. Without the range, the Output(TTL) may unfixed Data, CLK Out. *2 Open or Hi-z Input Data channel outputs unfixed Data(TTL). 2)Power On Sequence Power on THC63LVD823(B) after THC63LVD824A. 3)Cable Connection and Disconnection Don’t connect and disconnect the LVDS cable , when the power is supplied to the system. 4)GND Connection Connect the each GND of the PCB which THC63LVD823(B) and THC63LVD824A on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 5)Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVD823B THC63LVD824A TCLKTHC63LVD824A Copyright©2010 THine Electronics, Inc. 10/13 THine Electronics, Inc. THAN0078_Rev.1.1_E 6)Asynchronous use Asynchronous use such as following systems are not recommended. CLKOUT DATA IC TCLK+ THC63LVD823B CLKOUT CLKOUT CLKOUT TCLK- CLKOUT THC63LVD824A DATA IC TCLKTCLK+ THC63LVD823B TCLK- CLKOUT THC63LVD824A DATA IC TCLK+ TCLK- IC TCLK- TCLK+ Copyright©2010 THine Electronics, Inc. DATA TCLK+ THC63LVD823B CLKOUT IC DATA THC63LVD824A TCLK- CLKOUT DATA DATA LVDS-Rx TCLK- TCLK+ LVDS-Tx DATA IC DATA IC TCLK+ LVDS-Tx DATA IC TCLKTCLK+ THC63LVD823B DATA CLKOUT LVDS-Rx THC63LVD824A 11/13 DATA THine Electronics, Inc. THAN0078_Rev.1.1_E 5. PCB Design Guide Line General Guideline • Use 4 layer PCB (minimum). • Locate by-pass capacitors adjacent to the device pins as close as possible. • Make the loop minimum which is consist of Power line and Gnd line. LVDS Traces • Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be well balanced.(Keep all these differential impedance and the length of media as same as possible.). • • • • • Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See following figure. Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as much as possible. Avoid 90 degree bends. Minimize the number of VIA on LVDS traces. Match impedance of PCB trace, connector, media (cable) and termination to minimize reflections (emissions) for cabled applications (typically 100ohm differential mode characteristic impedance). • Place Terminal Resister adjacent to the Receiver. GND S1 >2 x S1 +Signal -Signal Copyright©2010 THine Electronics, Inc. 12/13 +Signal -Signal THine Electronics, Inc. THAN0078_Rev.1.1_E Attentions and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. E-mail:[email protected] Copyright©2010 THine Electronics, Inc. 13/13 THine Electronics, Inc.