ETC THC63LVD823

THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
Features
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
• Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
• Supports Single Link, Dual-in (TTL)/Single-out
•
•
•
•
•
•
•
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT
LVDS OUTPUT
GREEN1
BLUE1
8
8
8
8
TA1 +/PARALLEL TO SERIAL
1st DATA
8
MUX
RED1
8
HSYNC
VSYNC
DE
TB1 +/TC1 +/-
1st Link
TD1 +/TCLK1 +/(25 to 135MHz)
RED2
2nd DATA
GREEN2
BLUE2
PARALLEL TO SERIAL
TA2 +/8
8
8
TRANSMITTER CLOCK IN
(25 to 85MHz)
TB2 +/TC2 +/-
2nd Link
TD2 +/TCLK2 +/(25 to 85MHz)
PLL
R/F
/PDWN
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD823 _Rev2.0
B14
B13
B12
GND
VCC
B11
B10
G17
G16
G15
G14
G13
G12
G11
G10
R17
R16
R15
R14
GND
VCC
R13
R12
R11
R10
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Pin Out
50
LVDS GND
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TA1TA1+
TB1TB1+
LVDS VCC
TC1TC1+
TCLK1TCLK1+
TD1TD1+
LVDS GND
TA2TA2+
TB2TB2+
LVDS VCC
TC2TC2+
TCLK2TCLK2+
TD2TD2+
LVDS GND
B25
VCC
GND
B26
B27
HSYNC
VSYNC
DE
CLKIN
R/F
RS
TEST1
TEST2
MODE1
MODE0
OE
6/8
/PDWN
TEST3
TEST4
TEST5
PLL GND
PLL VCC
PLL GND
B24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
B16
B17
R20
R21
R22
R23
R24
R25
R26
R27
VCC
GND
G20
G21
G22
G23
G24
G25
G26
G27
B20
B21
B22
B23
1
B15
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Description
Pin Name
Pin #
Type
Description
TA1+, TA1-
48, 49
LVDS OUT
TB1+, TB1-
46, 47
LVDS OUT
TC1+, TC1-
43, 44
LVDS OUT
TD1+, TD1-
39, 40
LVDS OUT
TCLK1+, TCLK1-
41, 42
LVDS OUT
TA2+, TA2-
36, 37
LVDS OUT
TB2+, TB2-
34, 35
LVDS OUT
TC2+, TC2-
31, 32
LVDS OUT
TD2+, TD2-
27, 28
LVDS OUT
TCLK2+, TCLK2-
29, 30
LVDS OUT
R17 ~ R10
60, 59, 58, 57,
54, 53, 52, 51
IN
G17 ~ G10
68, 67, 66, 65,
64, 63, 62, 61
IN
B17 ~ B10
78, 77, 76, 75,
74, 73, 70, 69
IN
R27 ~ R20
86, 85, 84, 83,
82, 81, 80, 79
IN
G27 ~ G20
96, 95, 94, 93,
92, 91, 90, 89
IN
B27 ~ B20
6, 5, 2, 1, 100,
99, 98, 97
IN
DE
9
IN
Data Enable Input.
VSYNC
8
IN
Vsync Input.
HSYNC
7
IN
Hsync Input.
CLKIN
10
IN
Clock Input.
TEST1, TEST5
13, 22
OUT
TEST3, TEST4
20, 21
IN
Test Pins, must be L for normal operation.
TEST2
14
IN
Test Pins, must be H for normal operation.
/PDWN
19
IN
6/8
18
IN
OE
17
IN
The 1st Link. The 1st pixel output data when Dual Link.
LVDS Clock Out for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Out for 2nd Link.
The 1st Pixel Data Inputs.
The 2nd Pixel Data Inputs.
Test Pins.
H: Normal operation,
L: Power down (all outputs are Hi-Z)
6bit/8bit color select.
H: 6bit (TDx+/- are GND), L: 8bit.
Output enable.
H: Output enable, L: Output disable (all outputs are Hi-Z)
Pixel Data Mode.
MODE1, MODE0
15, 16
IN
RS
12
IN
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
MODE1
L
L
H
MODE0
L
H
H
Mode
Dual Link (Dual-in/Dual-out)
Single Link (Dual-in/Single-out)
Single Link (Single-in/Single-out)
LVDS swing range select.
H: Normal range, L: Reduced range.
3
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Name
Pin #
Type
Description
R/F
11
IN
VCC
3, 55, 71, 87
Power
Power Supply Pins for TTL inputs, output and digital
circuitry.
GND
4, 56, 72, 88
Ground
Ground Pins for TTL inputs, outputs and digital circuitry.
LVDS VCC
33, 45
Power
Power Supply Pins for LVDS Outputs.
LVDS GND
26, 38, 50
Ground
Ground Pins for LVDS Outputs.
PLL VCC
24
Power
Power Supply for PLL circuitry.
PLL GND
23, 25
Ground
Ground Pin for PLL circuitry.
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Absolute Maximum Ratings 1
Supply Voltage (VCC)
-0.3V ~ +4.0V
CMOS/TTL Input Voltage
-0.3V ~ (VCC + 0.3V)
CMOS/TTL Output Voltage
-0.3V ~ (VCC + 0.3V)
LVDS Driver Output Voltage
-0.3V ~ (VCC + 0.3V)
Output Current
-30mA ~ 30mA
Junction Temperature
+125 °C
Storage Temperature Range
-55 °C ~ +125 °C
Lead Temperature (Soldering, 4sec)
+260 °C
Maximum Power Dissipation @+25 °C
1.0W
Electrical Characteristics
CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
IINC
Input Current
0V ≤ VIN ≤ V CC
± 10
µA
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics”
specify conditions for device operation.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
LVDS Transmitter DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
VOD
∆VOD
VOC
Parameter
Conditions
Differential Output Voltage
RL=100Ω
Min.
Typ.
Max.
Normal
swing
250
350
450
mV
Reduced
swing
100
200
300
mV
35
mV
Change in VOD between
complementary output states
Common Mode Voltage
RL=100Ω
∆VOC
Change in VOC between
complementary output states
IOS
Output Short Circuit Current
IOZ
Output TRI-State current
Units
1.125
1.25
1.375
V
35
mV
VOUT=0V, RL=100Ω
-24
mA
/PDWN=0V, VOUT=0V to
VCC
± 10
µA
Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
Parameter
Condition(*)
VESA SXGA ( 60Hz )
Transmitter Supply
ITCCG
CLKIN=54MHz
VESA UXGA ( 60Hz )
CLKIN=81MHz
ITCCW
CLKIN=54MHz
VESA UXGA ( 60Hz )
CLKIN=81MHz
ITCCS
Transmitter Power Down
Supply Current
50
58
mA
78
89
mA
53
61
mA
86
99
mA
10
µA
MODE<1:0>=LH
RL=100Ω,CL=5pF
MODE<1:0>=LL
RL=100Ω,CL=5pF
MODE<1:0>=LH
RL=100Ω,CL=5pF
VCC=3.3V
Current
(Double Checker Pattern)
Units
VCC=3.3V
VESA SXGA ( 60Hz )
Transmitter Supply
Max.
VCC=3.3V
Current
(256 Gray Scale Pattern)
Typ.
MODE<1:0>=LL
RL=100Ω,CL=5pF
VCC=3.3
/PDWN = L
(*) VESA is a trademark of the Video Electronics Standards Association.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
256 Gray Scale Pattern
CLKIN
Rx0/Gx0/Bx0
Rx1/Gx1/Bx1
Rx2/Gx2/Bx2
Rx3/Gx3/Bx3
Rx4/Gx4/Bx4
Rx5/Gx5/Bx5
Rx6/Gx6/Bx6
Rx7/Gx7/Bx7
x=1,2
DE
Double Checker Pattern
CLKIN
R1n/G1n/B1n
R2n/G2n/B2n
n=0~7
DE
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70 °C
Symbol
Parameter
Min.
Typ.
Max.
Units
tTCIT
CLK IN Transition time
tTCIP
CLK IN Period
tTCH
CLK IN High Time
0.35tTCIP
tTCL
CLK IN Low Time
0.35tTCIP
tTS
TTL Data Setup to CLK IN
2.5
ns
tTH
TTL Data Hold from CKL IN
0.0
ns
5.0
ns
40.0
ns
0.5tTCIP
0.65tTCIP
ns
0.5tTCIP
0.65tTCIP
ns
11.76
Dual Link
11.76
40.0
ns
Single Link
7.4
20.0
ns
tTCOP
CLK OUT Period
tLVT
LVDS Transition Time
tTOP1
Output Data Position0 (tTCOP = 7.4ns)
-0.15
0.0
+0.15
ns
tTOP0
Output Data Position1 (tTCOP = 7.4ns)
t TCOP
-------------– 0.15
7
tTCOP
-------------7
t TCOP
-------------+ 0.15
7
ns
tTOP6
Output Data Position2 (tTCOP = 7.4ns)
t TCOP
2 -------------– 0.15
7
tTCOP
2 -------------7
tTCOP
2 -------------+ 0.15
7
ns
tTOP5
Output Data Position3 (tTCOP = 7.4ns)
t TCOP
3 -------------– 0.15
7
tTCOP
3 -------------7
tTCOP
3 -------------+ 0.15
7
ns
tTOP4
Output Data Position4 (tTCOP = 7.4ns)
t TCOP
4 -------------– 0.15
7
tTCOP
4 -------------7
tTCOP
4 -------------+ 0.15
7
ns
tTOP3
Output Data Position5 (tTCOP = 7.4ns)
t TCOP
5 -------------– 0.15
7
tTCOP
5 -------------7
tTCOP
5 -------------+ 0.15
7
ns
tTOP2
Output Data Position6 (tTCOP = 7.4ns)
t TCOP
6 -------------– 0.15
7
tTCOP
6 -------------7
tTCOP
6 -------------+ 0.15
7
ns
tTPLL
Phase Lock Loop Set
10.0
ms
tOE
OE High to Data Valid
tCK12
0.5
ns
50
ns
Skew Time between TCLK1+ and
TCLK2+
AC Timing Diagrams
TTL Input
0.5
90%
90%
CLK IN
10%
10%
tTCIT
LVDS Output
Vdiff=(TA+)-(TA-)
Vdiff
5pF
tTCIT
80%
80%
TA+
ns
20%
20%
100Ω
TAtLVT
LVDS Output Load
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
7
tLVT
THine Electronics, Inc.
THC63LVD823 _Rev2.0
AC Timing Diagrams
TTL Inputs
tTCIP
CLK IN
tTCH
2.0V
2.0V
tTCL
R/F = L
2.0V
0.8V
Hsync
Vsync
DE
Rxn
0.8V
R/F = H
tTH
tTS
2.0V
2.0V
0.8V
0.8V
Gxn
Bxn
x = 1,2
n = 0~7
Phase Lock Loop Set Time
VCC
3.0V
CLKIN
2.0V
/PDWN
tTPLL
Vdiff=0V
TCLKx+/-
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Power Up Sequence
Power Up Sequence must be Sequence1 or Sequence2.
1)Sequence1
tPW
VCC
PVCC
LVCC
VCC
VCC/2
GND
tPD
VCC
PD
VCC/2
GND
1)
2)
tPW < 10msec
tPD > tPW
2)Sequence2
VCC
PVCC
LVCC
VCC
3.0V
GND
VCC
PD
GND
GND
PD pin must be High after VCC voltage is 3.0V.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
AC Timing Diagrams
LVDS Outputs
tTOP2
tTOP3
tTOP4
tTOP5
tTOP6
tTOP0
tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
TCLKx+
Tyx1
Tyx0
Tyx6
Tyx5
Vdiff = 0V
x = 1,2
y = A,B,C,D
Tyx4
Tyx3
Tyx2
Tyx1
Vdiff = 0V
tTCOP
TCLK1+
Vdiff = 0V
tCK12
TCLK2+
Vdiff = 0V
Note:
Vdiff = (Tyx+) - (Tyx-) , (TCLKx+) - (TCLKx-)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pixel Map Table for Single/Dual Link
1st Pixel Data
TFT Panel Data
24Bit
LSB R10
18Bit
-
2nd Pixel Data
823 TTL Input Pin
TFT Panel Data
R10
R11
-
R11
R21
-
R21
R12
R10
R12
R22
R20
R22
R13
R11
R13
R23
R21
R23
R14
R12
R14
R24
R22
R24
R15
R13
R15
R25
R23
R25
R16
R14
R16
R26
R24
R26
MSB
R17
R15
R17
MSB
R27
R25
R27
LSB
G10
-
G10
LSB
G20
-
G20
G11
-
G11
G21
-
G21
G12
G10
G12
G22
G20
G22
G13
G11
G13
G23
G21
G23
G14
G12
G14
G24
G22
G24
G15
G13
G15
G25
G23
G25
G16
G14
G16
G26
G24
G26
G17
G15
G17
MSB
G27
G25
G27
LSB
MSB
LSB
MSB
18Bit
-
823 TTL Input Pin
24Bit
LSB R20
R20
B10
-
B10
B20
-
B20
B11
-
B11
B21
-
B21
B12
B10
B12
B22
B20
B22
B13
B11
B13
B23
B21
B23
B14
B12
B14
B24
B22
B24
B15
B13
B15
B25
B23
B25
B16
B14
B16
B26
B24
B26
B17
B15
B17
B27
B25
B27
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
MSB
11
THine Electronics, Inc.
THC63LVD823 _Rev2.0
823 TTL Data Input Timing for Single/Dual Link
Example : SXGA+(1400 x 1050)
HSYNC
DE
CLKIN
R1x/G1x/B1x
#1
#3
#5
#7
1395 #1397 #1399
R2x/G2x/B2x
#2
#4
#6
#8
1396 #1398 #1400
#1
#2
n = 0~7
#1399 #1400
TFT Panel
(1400 x 1050)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
TTL Data Inputs Timing Diagrams in Dual Link
(Dual-in / Dual-out Mode)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
R16’
R15’
R14’
R13’
R12’
G12
R17
R16
R15
R14
R13
R12
G12’’
TB1+/-
G17’
G16’
G15’
G14’
G13’
B13
B12
G17
G16
G15
G14
G13
B13’’
TC1+/-
HSYNC’
B17’
B16’
B15’
B14’
DE
B17
B16
B15
B14
DE’’
TD1+/-
B10’
G11’
G10’
R11’
R10’
L
B11
B10
G11
G10
R11
R10
L’’
TA2+/-
R26’
R25’
R24’
R23’
R22’
G22
R27
R26
R25
R24
R23
R22
G22’’
TB2+/-
G27’
G26’
G25’
G24’
G23’
B23
B22
G27
G26
G25
G24
G23
B23’’
TC2+/-
HSYNC’
B27’
B26’
B25’
B24’
DE
VSYNC HSYNC
B27
B26
B25
B24
DE’’
TD2+/-
B20’
G21’
G20’
R21’
R20’
L
B21
G21
G20
R21
R20
L’’
VSYNC HSYNC
TCLK2+
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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B20
THine Electronics, Inc.
THC63LVD823 _Rev2.0
TTL Data Inputs Timing Diagrams in Single Link
(Dual-in / Single-out Mode)
Previous Cycle
(2nd Pixel Data)
Current Cycle
(1st Pixel Data)
TCLK1+
TA1+/-
R26’
R25’
R24’
R23’
R22’
G12
R17
R16
R15
R14
R13
R12
G22’’
TB1+/-
G27’
G26’
G25’
G24’
G23’
B13
B12
G17
G16
G15
G14
G13
B23’’
TC1+/-
HSYNC’
B27’
B26’
B25’
B24’
DE
B17
B16
B15
B14
DE’’
TD1+/-
B20’
G21’
G20’
R21’
R20’
L
G11
G10
R11
R10
L’’
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
VSYNC HSYNC
B11
14
B10
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Package
INDEX ∆
100
76
PIN No.1
75
16.0SQ TYP
14.0SQ TYP
0.5TYP
0.22
25
51
50
1.2MAX
1.00TYP
26
UNIT:mm
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice.
2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention
when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to
them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found.
3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other
persons are strictly prohibited without our permission.
4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVD823 use, except
for those directly related to THC63LVD823’s structure, manufacture or functions. THC63LVD823 is designed on
the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that
require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people’s lives, etc.). In addition, when using THC63LVD823 for traffic signals, safety devices and control/safety units
in transportation equipment, etc., appropriate measures should be taken.
5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very
slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care
should be taken to provide sufficient redundancy and fail-safe design.
6. No radiation-hardened design is incorporated in THC63LVD823.
7. Judgment on whether THC63LVD823 comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user’s responsibility.
8. This technical document was provisionally created during development of THC63LVD823, so there is a possibility
of differences between it and the product’s final specifications. When designing circuits using THC63LVD823, be
sure to refer to the final technical documents.
THine Electronics, Inc.
Wakamatsu Bldg, 6F
3-3-6, Nihombashi-Honcho,
Chuo-ku, Tokyo, 103-0023 Japan
Tel: 81-3-3270-0666
Fax: 81-3-3270-0688
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THine Electronics, Inc.