BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 1024×8 bit electrically erasable PROM BR24L08-W / BR24L08F-W / BR24L08FJ-W / BR24L08FV-W / BR24L08FVM-W The BR24L08-W series is 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗ I C BUS is a registered trademark of Philips. 2 zApplications General purpose zFeatures 1) 1024 registers × 8 bits serial architecture. 2) Single power supply (1.8V to 5.5V). 3) Two wire serial interface. 4) Self-timed write cycle with automatic erase. 5) 16byte Page Write mode. 6) Low power consumption. Write (5V) : 1.5mA (Typ.) Read (5V) : 0.2mA (Typ.) Standby (5V) : 0.1µA (Typ.) 7) DATA security Write protect feature (WP pin). Inhibit to WRITE at low VCC. 8) Small package - - - DIP8 / SOP8 / SOP-J8 / SSOP-B8 / MSOP-8 9) High reliability EEPROM with Double-Cell structure. 10) High reliability fine pattern CMOS technology. 11) Endurance : 1,000,000 erase / write cycles 12) Data retention : 40 years 13) Filtered inputs in SCL•SDA for noise suppression. 14) Initial data FFh in all address. zAbsolute maximum ratings (Ta=25°C) Parameter Supply voltage Power dissipation Symbol Limits VCC −0.3 to +6.5 Pd Unit V 800(DIP8) ∗1 450(SOP8) ∗2 450(SOP-J8) ∗2 300(SSOP-B8) ∗3 310(MSOP8) ∗4 mW Storage temperature Tstg −65 to +125 °C Operating temperature Topr −40 to +85 °C Terminal voltage ∗1 ∗2 ∗3 ∗4 − −0.3 to VCC+0.3 V Reduced by 8.0mW for each increase in Ta of 1°C over 25°C. Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. Reduced by 3.1mW for each increase in Ta of 1°C over 25°C. 1/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zRecommended operating conditions (Ta=25°C) Symbol Limits Unit Supply voltage Parameter VCC 1.8 to 5.5 V Input voltage VIN 0 to VCC V zDC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V) Parameter "HIGH" input volatge 1 Symbol Min. Typ. Max. Unit VIH1 0.7VCC − − V Conditions 2.5V≤VCC≤5.5V "LOW" input volatge 1 VIL1 − − 0.3VCC V 2.5V≤VCC≤5.5V "HIGH" input volatge 2 VIH2 0.8VCC − − V 1.8V≤VCC<2.5V "LOW" input volatge 2 VIL2 − − 0.2VCC V 1.8V≤VCC<2.5V "LOW" output volatge 1 VOL1 − − 0.4 V IOL=3.0mA, 2.5V≤VCC≤5.5V, (SDA) "LOW" output volatge 2 VOL2 − − 0.2 V IOL=0.7mA, 1.8V≤VCC≤5.5V, (SDA) Input leakage current ILI −1 − 1 µA VIN=0V to VCC Output leakage current ILO −1 − 1 µA VOUT=0V to VCC ICC1 − − 2.0 mA VCC=5.5V, fSCL=400kHz, tWR=5ms, Byte Write, Page Write ICC2 − − 0.5 mA VCC=5.5V, fSCL=400kHz Random Read, Current Read, Sequential Read ISB − − 2.0 µA VCC=5.5V, SDA•SCL=VCC, A0, A1, A2=GND, WP=GND Operating current Standby current This product is not designed for protection against radioactive rays. 2/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zDimension 9.3±0.3 5 6.5±0.3 2.54 0.5±0.1 4 0.3Min. 1 1.27 0.4±0.1 0.15±0.1 0.1 0° ~ 15° Fig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L08-W) Fig.1(b) PHYSICAL DIMENSION (Units : mm) SOP8 (BR24L08F-W) 3.0±0.2 4.9±0.2 0.2±0.1 1.27 0.42±0.1 0.1 1.15±0.1 0.1 1 2 3 4 8 5 1 4 6.4±0.3 4.4±0.2 6.0±0.3 3.9±0.2 0.45Min. 8 7 6 5 1.375±0.1 0.175 5 6.2±0.3 4.4±0.2 0.51Min. 0.3±0.1 1.5±0.1 0.11 4 7.62 3.2±0.2 3.4±0.3 1 5.0±0.2 8 0.3Min. 8 (0.52) Fig.1(c) PHYSICAL DIMENSION (Units : mm) SOP-J8 (BR24L08FJ-W) 0.15±0.1 0.1 0.22±0.1 0.65 Fig.1(d) PHYSICAL DIMENSION (Units : mm) SSOP-B8 (BR24L08FV-W) 5 1 4 0.29±0.15 0.6±0.2 8 2.8±0.1 4.0±0.2 2.9±0.1 +0.05 0.145−0.03 0.9Max. 0.75±0.05 0.08±0.05 0.475 +0.05 0.22−0.04 0.65 0.08 M 0.08 S Fig.1(e) PHYSICAL DIMENSION (Units : mm) MSOP8 (BR24L08FVM-W) 3/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zBlock diagram A0 1 32kbit EEPROM array 2 A2 3 VCC 7 WP 6 SCL 5 SDA 8bit 10bit A1 8 Address decoder Data register Slave word address register 10bit START STOP Control logic ACK GND 4 High voltage generator Vcc level detect Fig.2 BLOCK DIAGRAM zPin configuration VCC WP SCL SDA 8 7 6 5 BR24L08-W BR24L08F-W BR24L08FJ-W BR24L08FV-W BR24L08FVM-W 1 2 3 4 A0 A1 A2 GND Fig.3 PIN LAYOUT zPin name Pin name I/O VCC − Power supply Function GND − Ground (0V) A0, A1 − Out of use A2 IN Slave address set SCL IN Serial clock input SDA IN / OUT WP IN Slave and word address, serial data input, serial data output ∗1 Write protect input ∗1 An open drain output requires a pull-up resistor. 4/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=1.8 to 5.5V) Parameter Symbol Fast-mode 2.5V ≤ Vcc ≤ 5.5V Min. Typ. Max. Standard-mode 1.8V ≤ Vcc ≤ 5.5V Min. Typ. Max. Unit Clock frequency fSCL − − 400 − − 100 kHz Data clock "HIGH" period tHIGH 0.6 − − 4.0 − − µs tLOW 1.2 − − 4.7 − − µs tR − − 0.3 − − 1.0 µs Data clock "LOW" period SDA and SCL rise time ∗1 SDA and SCL fall time ∗1 tF − − 0.3 − − 0.3 µs tHD:STA 0.6 − − 4.0 − − µs Start condition setup time tSU:STA 0.6 − − 4.7 − − µs Input data hold time tHD:DAT 0 − − 0 − − ns Input data setup time tSU:DAT 100 − − 250 − − ns tPD 0.1 − 0.9 0.2 − 3.5 µs Start condition hold time Output data delay time tDH 0.1 − − 0.2 − − µs tSU:STO 0.6 − − 4.7 − − µs Bus free time tBUF 1.2 − − 4.7 − − µs Write cycle time tWR − − 5 − − 5 ms Output data hold time Stop condition setup time Noise spike width (SDA and SCL) WP hold time tl − − 0.1 − − 0.1 µs tHD:WP 0 − − 0 − − ns WP setup time tSU:WP 0.1 − − 0.1 − − µs WP high period tHIGH:WP 1.0 − − 1.0 − − µs ∗1 Not 100% tested. 5/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zSynchronous data timing tR tF tHIGH SCL tHD : STA tSU : DAT tLOW tHD : DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU : STA tHD : STA tSU : STO SDA START BIT STOP BIT Fig.4 SYNCHRONOUS DATA TIMING •SDA data is latched into the chip at the rising edge of SCL clock. •Output data toggles at the falling edge of SCL clock. zWrite cycle timing SCL SDA D0 ACK tWR WRITE DATA (n) STOP CONDITION START CONDITION Fig.5 WRITE CYCLE TIMING 6/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zWP timing SCL DATA (1) SDA D1 DATA (n) D0 ACK ACK tWR STOP BIT WP tSU : WP tHD : WP Fig.6(a) WP TIMING OF THE WRITE OPERATION SCL DATA (1) SDA D1 DATA (n) D0 ACK ACK tHIGH : WP WP Fig.6(b) WP TIMING OF THE WRITE CANCEL OPERATION •For the WRITE operation, WP must be “LOW” during the period of time from the rising edge of the clock which takes in D0 of first byte until the end of tWR. ( See Fig.6 (a) ) During this period, WRITE operation is canceled by setting WP “HIGH”. ( See Fig.6 (b) ) •In the case of setting WP “HIGH” during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed. Please write correct data again in the case. 7/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zDevice operation 1) Start condition (Recognition of start bit) • All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. • The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.4 SYNCHRONOUS DATA TIMING) 2) Stop condition (Recognition of stop bit) • All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. (See Fig.4 SYNCHRONOUS DATA TIMING) 3) Notice about write command • In the case that stop condition is not executed in WRITE mode, transferred data will not be written in a memory. 4) Device addressing • Following a START condition, the master output the slave address to be accessed. • The most significant four bits of the slave address are the “device type identifier”, for this device it is fixed as “1010”. • The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2 input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin. Using this address scheme, up to two devices may be connected to the bus. • The next two bits (P1, P0) are used by the master to select t four 256 word page of memory. P1, P0 set to “0” “0” - - - - - - 1page (000 to 0FF) P1, P0 set to “0” “1” - - - - - - 2page (100 to 1FF) P1, P0 set to “1” “0” - - - - - - 3page (200 to 2FF) P1, P0 set to “1” “1” - - - - - - 4page (300 to 3FF) • The last bit of the stream (R/W - - - READ / WRITE) determines the operation to be performed. When set to “1”, a read operation is selected ; when set to “0”, a write operation is selected. R / W set to “0” - - - - - - WRITE (including word address input of Random Read) R / W set to “1” - - - - - - READ 1010 A2 P1 P0 R/W 5) Write protect (WP) When WP pin set to VCC (H level), write protect is set for 1024 words (all address). When WP pin set to GND (L level), enable to write 1024 words (all address). Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected. 8/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 6) Acknowledge • Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is µ-COM. When outputting the data in the read operation, it is this device.) • During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been received. (When inputting the slave address in the write or read operation, receiver is this device. When outputting the data in the read operation, it is µ-COM.) • The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). • In the WRITE mode, the device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word (word address and write data). • In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an Acknowledge. • If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. (See Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER) START CONDITION (START BIT) SCL (From µ−COM) 1 8 9 SDA (µ−COM OUTPUT DATA) SDA (IC OUTPUT DATA) Acknowledge Signal (ACK Signal) Fig.7 ACKNOWLEDGE RESPONSE FROM RECEIVER 9/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zByte write S T A R T SDA LINE W R I T E SLAVE ADDRESS WORD ADDRESS WA 7 1 0 1 0 A2 P1 P0 DATA WA 0 D7 D0 A C K R A / C W K S T O P A C K WP Fig.8 BYTE WRITE CYCLE TIMING • By using this command, the data is programmed into the indicated word address. • When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. zPage write S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS (n) WA 7 1 0 1 0 A2 P1 P0 R A / C WK DATA (n) WA 0 D7 S T O P DATA (n+15) D0 A C K D0 A C K A C K WP Fig.9 PAGE WRITE CYCLE TIMING • This device is capable of sixteen byte Page Write operation. • When two or more byte data are inputted, the four low order address bits are internally incremented by one after the receipt of each word. The six higher order bits of the address (P1, P0, WA7 to WA4) remain constant. • If the master transmits more than sixteen words, prior to generating the STOP condition, the address counter will “roll over”, and the previous transmitted data will be overwritten. 10/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zCurrent read S T A R T SDA LINE SLAVE ADDRESS 1 0 1 R E A D S T O P DATA 0 A2 P1 P0 D7 D0 R A / C W K A C K Fig.10 CURRENT READ CYCLE TIMING • In case that the previous operation is Random or Current Read (which includes Sequential Read respectively), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If the last command is Byte or Page Write, the internal address counter stays at the last address (n). Thus Current Read outputs the data of the word address (n). • If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to transmit the data. [ It can transmit all data (8kbit 1024word) ] • If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with “High” always, then input stop condition. zRandom read S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS(n) WA 7 1 0 1 0 A2P1P0 R A / C W K S T A R T WA 0 SLAVE ADDRESS R E A D 1 0 1 0 A2A1PS A C K S T O P DATA(n) D7 R A / C W K D0 A C K Fig.11 RANDOM READ CYCLE TIMING • Random read operation allows the master to access any memory location indicated word address. • If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to transmit the data. [ It can transmit all data (8kbit 1024word) ] • If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with “High” always, then input stop condition. 11/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zSequential read S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 P1 P0 DATA(n) D7 R A / C W K S T O P DATA(n+x) D0 D7 A C K A C K D0 A C K Fig.12 SEQUENTIAL READ CYCLE TIMING (Current Read) • If an Acknowledge is detected, and no STOP condition is generated by the master (µ-COM), the device will continue to transmit the data. [ It can transmit all data (8kbit 1024word) ] • If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to the standby mode. • The Sequential Read operation can be performed with both Current Read and Random Read. Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read. So the device transmits the next data, Read is not terminated. In the case of terminating Read, input Acknowledge with “High” always, then input stop condition. 12/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs zApplication 1) WP effective timing WP is fixed to “H” or “L” usually. But in case of controlling WP to cancel the write command, please pay attention to [ WP effective timing ] as follows. During write command input, write command is canceled by controlling WP “H” within the WP cancellation effective period. The period from the start condition to the rising edge of the clock which take in D0 of the data (the first byte of the data for Page Write) is the cancellation invalid period. WP input is don’t care during the period. Setup time for rising edge of the SCL which takes in D0 must be more than 100ns. The period from the rising edge of SCL which takes in D0 to the end of internal write cycle (tWR) is the cancellation effective period. In case of setting WP to “H” during tWR, WRITE operation is stopped in the middle and the data of accessing address is not guaranteed, so that write correct data again please. It is not necessary waiting tWR (5msmax.) after stopping command by WP, because the device is stand by state. · The rising edge of the clock which take in D0 SCL SDA SCL D1 D0 ACK SDA AN ENLARGEMENT SDA S T A R T SLAVE ADDRESS A C K L WORD ADDRESS A C K L D7 D6 · The rising edge of SDA D0 ACK AN ENLARGEMENT D5 D4 WP cancellation invalid period D3 D2 D1 D0 A C K L DATA A C K L A C K L S T O P tWR WP cancellation effective period Stop of the write operation No data will be written Data is not guaranteed WP Fig.13 WP EFFECTIVE TIMING 13/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 2) Software reset Please execute software reset in case that the device is an unexpected state after power up and / or the command input need to be reset. There are some kinds of software reset. Here we show three types of example as follows. During dummy clock, please release SDA bus (tied to VCC by pull up resistor). During that time, the device may pull the SDA line LOW for Acknowledge or outputting or read data. If the master controls the SDA line HIGH, it will conflict with the device output LOW then it makes a current overload. It may cause instantaneous power down and may damage the device. DUMMY CLOCK × 14 SCL 1 2 13 START × 2 14 COMMAND COMMAND SDA Fig.14-(a) DUMMY CLOCK × 14 + START + START DUMMY CLOCK × 9 START SCL 1 2 8 START 9 COMMAND COMMAND SDA Fig.14-(b) START+ DUMMY CLOCK × 9 + START START × 9 SCL 1 2 3 7 8 9 COMMAND COMMAND SDA Fig.14-(c) START × 9 ∗ COMMAND starts with start condition. 14/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 3) Acknowledge polling Since the device ignore all input commands during the internal write cycle, no ACK will be returned. When the master send the next command after the write command, if the device returns the ACK, it means that the program is completed. If no ACK id returned, it means that the device is still busy. By using Acknowledge polling, the waiting time is minimized less than tWR=5ms. In case of operating Write or Current Read right after Write, first, send the slave address (R / W is “HIGH” or “LOW” respectively). After the device returns the ACK, continue word address input or data output respectively. During the internal write cycle, no ACK will be returned. (ACK=HIGH) THE FIRST WRITE COMMAND S T A R T WRITE COMMAND S T A R T S T O P S T A R T A C K H SLAVE ADDRESS SLAVE ADDRESS A C K H ••• tWR THE SECOND WRITE COMMAND ••• S T A R T SLAVE ADDRESS A C K H S T A R T SLAVE ADDRESS A C K L WORD ADDRESS A C K L DATA A C K L S T O P tWR After the internal write cycle is completed ACK will be returned (ACK=LOW). Then input next Word Address and data. Fig.15 SUCCESSIVE WRITE OPERATION BY ACKNOWLEDGE POLLING 15/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 4) Command cancellation by start and stop condition During a command input, it is canceled by the successive inputs of start condition and stop condition. (Fig.4) But during ACK or data output, the device may output the SDA line LOW. In such cases, operation of start and stop condition is impossible, so that the reset can’t work. Execute the software reset in the cases. (See Page14) Operating the command cancel by start and stop condition during the command of Random Read or Sequential Read or Current Read, internal address counter is not confirmed. Therefore operation of Current Read after this in not valid. Operate a Random Read in this case. SCL SDA 1 0 1 0 START CONDITION STOP CONDITION Fig.16 COMMAND CANCELLATION BY START AND STOP CONDITION DURING THE INPUT OF SLAVE ADDRESS 16/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 5) Notes for power supply VCC rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of P.O.R. and LVCC. In the case of power up, keep the following conditions to ensure functions of P.O.R and LVCC. (1) It is necessary to be “SDA=‘H’ ” and “SCL=’L’ or ‘H’ ”. (2) Follow the recommended conditions of tR, tOFF, Vbot for the function of P.O.R. durning power up. tR VCC Recommended conditions of tR, tOFF, Vbot tOFF Vbot tR tOFF Vbot Below 10ms Above 10ms Below 0.3V Below 100ms Above 10ms Below 0.2V 0 VCC rising wave from (3) Prevent SDA and SCL from being “Hi-Z”. In case that condition 1. and / or 2. cannot be met, take following actions. A) Unable to keep condition 1. (SDA is “LOW” during power up.) →Control SDA, SCL to be “HIGH” as figure below. VCC tLOW SCL SDA After VCC becomes stable After VCC becomes stable tDH tSU:DAT a) SCL="H" and SDA="L" tSU:DAT b) SCL="L" and SDA="L" B) Unable to keep condition 2. → After power becomes stable, execute software reset. (See Page14 ) C) Unable to keep condition 1 and 2. → Follow the instruction A first, then the instruction B. • LVCC circuit LVCC circuit inhibit write operation at low voltage, and prevent an inadvertent write. Below the LVCC voltage (Typ.=1.2V), write operation is inhibited. 17/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 6) I / O circuit • Pull up resister of SDA pin The pull up resister is needed because SDA is NMOS open drain. Decide the value of this resister (RPU) properly, by considering VIL, IL characteristics of a controller which control the device and VOH, IOL characteristics of the device. If large RPU is chosen, clock frequency need to be slow. In case of small RPU, the operating current increases. • Maximum of RPU Maximum of RPU is determined by following factor. c SDA rise time determined by RPU and the capacitance of bus line (CBUS) must be less than TR. And the other timing must keep the conditions of AC spec. d When SDA bus is HIGH, the voltage A of SDA bus determined by a total input leak (IL) of the all devices connected to the bus and RPU must be enough higher than input HIGH level of a controller and the device, including noise margin 0.2VCC. VCC − ILRPU − 0.2VCC ≥ VIH MICRO COMPUTER RPU ≤ BR24LXX 0.8VCC − VIH IL RPU IL Examples : When VCC=3V IL=10µA VIH=0.7VCC A SDA PIN IL THE CAPACITANCE OF BUS LINE (CBUS) According to 2 RPU ≤ 0.8×3−0.7×3 10×10−6 ≤ 300 [kΩ] 18/25 Memory ICs BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W • The minimum value RPU The minimum value of RPU is determined by following factors. c Meet the condition that VOLMAX=0.4V, IOLMAX=3mA when the device output low on SDA line. VCC − VOL ≤ IOL RPU RPU ≥ VCC − VOL IOL d VOLMAX (=0.4V) must be lower than the input LOW level of the controller and the EEPROM including recommended noise margin (0.1VCC). VOLMAX ≤ VIL − 0.1VCC Examples : VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC According to 1 RPU ≥ 3−0.4 3×10−3 ≥ 867 [Ω] and VOL =0.4[V] VIL =0.3×3 =0.9[V] so that condition 2 is met • Pull up resister of SCL pin In the case that SCL is controlled by CMOS output, the pull up resister of SCL is not needed. But in the case that there is a timing at which SCL is Hi-Z, connect SCL to VCC with pull up resister. Several ∼ several dozen kΩ is recommended as a pull up resister, which is considered with the driving ability of the output port of the controller. 7) Connections of A0, A1, A2, WP pin • Connections of device address pin (A0, A1, A2) The state of device address PIN are compared with the device address send by the master, then one of the devices which are connected to the identical bus is selected. Pull up or down these pins, or connect them to VCC or GND. Pins which is not used as device address (N.C. PIN) may be either HIGH, LOW, and Hi-Z. The type of the device which have N.C. PIN BR24L16 / F / FJ / FV / FVM-W BR24L08 / F / FJ / FV / FVM-W BR24L04 / F / FJ / FV / FVM-W A0, A1, A2 A0, A1 A0 • Connections of WP pin The WP input allows or inhibits write operations. When WP is HIGH, only READ is available and WRITE to any address is inhibited. Both Read and Write are available when WP is LOW. In the case that the device is used as a ROM, it is recommended that WP is pulled up or connected to VCC. In the case that both READ and WRITE are operated, WP pin must be pulled down or connected to GND or controlled. 19/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 8) Notes for noise on VCC • About bypass capacitor Noise and surges on power line may cause the abnormal function. It is recommended that the bypass capacitors (0.1µF) are attached on the VCC and GND line beside the device. The attachment of bypass capacitors on the board near by connector is also recommended. IC capacitor 0.01 to 0.1µF PRINT BASE GND VCC capacitor 10 to 100µF 9) The notice about the connection of controller • About RS The open drain interface is recommended for SDA port in I2C BUS. But, in the case that Tri-state CMOS interface is applied to SDA, insert a series resister RS between SDA pin of the device and a pull up resister RPU. It limits the current from PMOS of controller to NMOS of EEPROM. RS also protects SDA pin from surges. Therefore, RS is able to be used though SDA port is open drain. RPU RS CONTROLLER SDA PIN EEPROM ACK SCL SDA "H" OUTPUT OF CONTROLLER "L" OUTPUT OF EEPROM The "H" output of controller and the "L" output of EEPROM may cause current overload to SDA line. 20/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs • The maximum value of RS The maximum value of RS is determined by following factors. c SDA rise time determined by RPU and the capacitance of bus line (CBUS ) of SDA must be less than tR. And the other timing must also keep the conditions of the AC timing. d When the device outputs LOW on SDA line, the voltage of the bus A determined by RPU and RS must be lower than the inputs LOW level of the controller, including recommended noise margin (0.1VCC). (VCC−VOL) × RS + VOL+0.1VCC ≤ VIL RPU+RS RS ≤ VIL−VOL−0.1VCC × RPU 1.1VCC−VIL Examples : When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ According to 2 RS ≤ 0.3×3−0.4−0.1×3 × 20×103 1.1×3−0.3×3 ≤ 1.67 [kΩ] VCC RPU A RS VOL CAPACITANCE OF BUS LINE (CBUS) VIL CONTROLLER EEPROM • The minimum value of RS The minimum value of RS is determined by the current overload due to the conflict on the bus. The current overload may cause noise on the power line and instantaneous power down. The following conditions must be met, where Ι is the maximum permissible current. The maximum permissible current depends on VCC line impedance and so on. It need to be less than 10mA for EEPROM. VCC ≤Ι RS RS ≥ VCC Ι Examples : When VCC=3V, Ι=10mA RPU RS "L" OUTPUT RS ≥ 3 10×10−3 ≥ 300 [Ω] MAXIMUM CURRENT Ι "H" OUTPUT CONTROLLER EEPROM 21/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 6 5 5 4 SPEC 3 2 Ta=85°C Ta=−40°C Ta=25°C 1 1 L OUTPUT VOLTAGE : VOL (V) 6 L INPUT VOLTAGE : VIL (V) H INPUT VOLTAGE : VIH (V) 10) The special character DATA The following characteristic data are typ. value. 4 Ta=85°C Ta=−40°C Ta=25°C 3 2 1 SPEC 0 0 1 3 2 4 5 0 0 6 SUPPLY VOLTAGE : VCC (V) 2 3 4 5 0.6 Ta=25°C 0.4 Ta=85°C SPEC 0.2 Ta=−40°C 0 0 6 SUPPLY VOLTAGE : VCC (V) Fig.17 High input voltage VIH (A0,A1,A2,SCL,SDA,WP) SPEC 0.4 Ta=25°C Ta=85°C 0.2 4 5 6 1.2 SPEC OUTPUT LEAK CURRENT : ILO (µA) INPUT LEAK CURRENT : ILI (µA) 0.6 3 2 Fig.19 Low output voltage VOL−IOL (VCC=1.8V) 1.2 0.8 1 L OUTPUT CURRENT : IOL (mA) Fig.18 Low input voltage VIL (A2,SCL,SDA,WP) 1 L OUTPUT VOLTAGE : VOL (V) 1 0.8 1 0.8 0.6 0.4 Ta=85°C Ta=25°C Ta=−40°C 0.2 SPEC 1 0.8 0.6 0.4 Ta=85°C Ta=25°C Ta=−40°C 0.2 Ta=−40°C 1 3 2 4 5 0 0 6 Fig.20 Low output voltage VOL−IOL (VCC=2.5V) CURRENT CONSUMPTION AT READING : ICC2 (mA) CURRENT CONSUMPTION AT WRITING : ICC1 (mA) 4 5 0 0 6 fSCL=400kHz DATA=AAh 1.5 Ta=25°C Ta=85°C 1 Ta=−40°C 0.5 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.23 Write operating current ICC1 (fSCL=400kHz) 6 3 4 5 6 2.5 0.5 fSCL=400kHz DATA=AAh 0.3 Ta=25°C Ta=85°C 0.2 0.1 0 0 2 Fig.22 Output leakage current ILO(SDA) SPEC 0.4 1 SUPPLY VOLTAGE : VCC (V) 0.6 SPEC 0 0 3 Fig.21 Input leakage current ILI (A2,SCL,WP) 2.5 2 2 1 SUPPLY VOLTAGE : VCC (V) L OUTPUT CURRENT : IOL (mA) CURRENT CONSUMPTION AT WRITING : ICC1 (mA) 0 0 Ta=−40°C 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.24 Read operating current ICC2 (fSCL=400kHz) 6 SPEC 2 fSCL=100kHz DATA=AAh 1.5 Ta=25°C Ta=85°C 1 Ta=−40°C 0.5 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig.25 Write operating current ICC1 (fSCL=100kHz) 22/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 10000 2.5 SPEC 0.5 fSCL=100kHz DATA=AAh 0.3 Ta=25°C Ta=85°C 0.2 0.1 2 1.5 1 0.5 Ta=−40°C 0 0 1 3 2 4 Ta=85°C 5 0 0 6 1 SUPPLY VOLTAGE : VCC (V) 4 5 DATA CLK L TIME : tLOW (µs) SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 1 SPEC1 2 3 4 5 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 SPEC1 1 0 0 6 SUPPLY VOLTAGE : VCC (V) Fig.29 Data clock "H" period tHIGH 6 INPUT DATA HOLD TIME : tHD:DAT (ns) SPEC2 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 SPEC1 1 0 0 2 3 4 5 Ta=−40°C Ta=25°C Ta=85°C 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.32 Start condition setup time tSU:STA 6 6 3 4 5 6 5 SPEC2 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 1 0 0 Ta=−40°C Ta=25°C Ta=85°C 1 SPEC1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.30 Data clock "L" period tLOW Fig.31 Start condition hold time tHD:STA 6 50 SPEC1,2 0 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE −50 −100 Ta=85°C Ta=25°C Ta=−40°C −150 −200 0 2 SUPPLY VOLTAGE : VCC (V) 50 5 4 Ta=85°C Ta=25°C Ta=−40°C 1 1 Fig.28 Clock frequency fSCL INPUT DATA HOLD TIME : tHD:DAT (ns) 0 0 10 SUPPLY VOLTAGE : VCC (V) SPEC2 SPEC2 4 1 SPEC2 1 0 6 5 Ta=−40°C Ta=25°C Ta=85°C SPEC1 100 Fig.27 Standby current ISB 5 DATA CLK H TIME : tHIGH (µs) 3 2 1000 SUPPLY VOLTAGE : VCC (V) Fig.26 Read operating current ICC2 (fSCL=100kHz) START CONDITION SET UP TIME : tSU:STA (µs) Ta=25°C Ta=−40°C START CONDITION HOLD TIME : tHD:STA (µs) 0.4 Ta=85°C Ta=25°C Ta=−40°C SPEC SCL FREQUENCY : fSCL (kHz) STANDBY CURRENT : ISB (µA) CURRENT CONSUMPTION AT READING : ICC2 (mA) 0.6 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.33 Input data hold time tHD:DAT(HIGH) 6 SPEC1,2 0 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE −50 Ta=85°C −100 −150 Ta=25°C −200 0 1 Ta=−40°C 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig.34 Input data hold time tHD:DAT(LOW) 23/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W SPEC2 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE SPEC1 100 0 Ta=85°C Ta=25°C Ta=−40°C −100 1 2 3 4 5 6 SPEC2 200 SPEC1 100 −200 0 2 3 4 5 Fig.35 Input data setup time tSU:DAT(HIGH) Fig.36 Input data setup time tSU:DAT(LOW) OUTPUT DATA HOLD TIME : tDH (µs) SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 2 Ta=−40°C Ta=25°C Ta=85°C SPEC1 1 SPEC2 SPEC1 1 2 3 4 5 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 2 Ta=85°C Ta=25°C Ta=−40°C SPEC1 1 SPEC2 SPEC1 1 2 3 4 5 Fig.37 Output data delay time tPD0 SPEC2 3 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 2 Ta=85°C Ta=25°C Ta=−40°C SPEC1 1 SPEC2 SPEC1 1 2 3 4 5 SPEC2 3 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 2 Ta=−40°C Ta=25°C Ta=85°C SPEC2 0 0 6 SPEC1 1 SPEC1 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) Fig.38 Output data delay time tPD1 Fig.39 Output data hold time tDH0 Fig.40 Output data hold time tDH1 5 5 SPEC2 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 Ta=85°C Ta=25°C Ta=−40°C 1 SPEC1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.41 Stop condition setup time tSU:STO 6 6 SUPPLY VOLTAGE : VCC (V) 4 0 0 6 SPEC2 3 0 0 6 4 BUS OPEN TIME BEFORE TRANSMISSION : tBUF (µs) OUTPUT DATA DELAY TIME : tPD (µs) STOP CONDITION SET UP TIME : tSU:STO (µs) 1 Ta=−40°C SUPPLY VOLTAGE : VCC (V) SPEC2 0 0 Ta=25°C −100 SUPPLY VOLTAGE : VCC (V) 3 1 Ta=85°C 0 4 0 0 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE OUTPUT DATA HOLD TIME : tDH (µs) −200 0 4 4 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 3 2 SPEC1 1 0 0 6 6 SPEC2 Ta=−40°C Ta=25°C Ta=85°C 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.42 BUS free time tBUF 6 INTERNAL WRITING CYCLE TIME : tWR (ms) 200 300 OUTPUT DATA DELAY TIME : tPD (µs) 300 INPUT DATA SET UP TIME : tSU:DAT (ns) INPUT DATA SET UP TIME : tSU:DAT (ns) Memory ICs SPEC1,2 5 Ta=−40°C 4 Ta=25°C 3 Ta=85°C 2 1 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig.43 Write cycle time tWR 24/25 BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 0.6 0.5 Ta=−40°C 0.4 Ta=25°C 0.3 Ta=85°C 0.2 0.1 SPEC1,2 0 0 1 2 3 4 5 0.5 0.4 0.3 Ta=−40°C 0.2 Ta=25°C Ta=85°C 0.1 SPEC1,2 0 0 6 1 2 3 4 5 Ta=−40°C 0.3 Ta=85°C 0.2 0.1 SPEC1,2 0 0 6 Ta=25°C 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.44 Noise spike width tI (SCL H) Fig.45 Noise spike width tI (SCL L) Fig.46 Noise spike width tI (SDA H) 0.2 0.4 Ta=−40°C Ta=25°C Ta=85°C 0.2 0.1 SPEC1,2 0 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE −0.2 Ta=85°C −0.4 1 2 3 4 Ta=−40°C Ta=25°C SPEC1,2 5 6 −0.6 0 6 1.2 WP EFFECTIVE TIME : tHIGH:WP (µs) WP SET UP TIME : tSU:WP (µs) 0.5 0 0 0.4 SUPPLY VOLTAGE : VCC (V) SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0.3 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0.5 SUPPLY VOLTAGE : VCC (V) 0.6 NOISE REDUCTION EFFECTIVE TIME : tI (SDA L) (µs) 0.6 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE NOISE REDUCTION EFFECTIVE TIME : tI (SDA H) (µs) SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE NOISE REDUCTION EFFECTIVE TIME : tI (SCL L) (µs) NOISE REDUCTION EFFECTIVE TIME : tI (SCL H) (µs) 0.6 1 2 3 4 5 6 1 SPEC1,2 0.8 SPEC1 : FAST-MODE SPEC2 : STANDARD-MODE 0.6 0.4 Ta=−40°C Ta=25°C Ta=85°C 0.2 0 0 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) Fig.47 Noise spike width tI (SDA L) Fig.48 WP setup time tSU:WP Fig.49 WP high period tHIGH:WP 6 25/25